diff options
Diffstat (limited to 'drivers/gpu/drm/amd')
173 files changed, 292967 insertions, 5061 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 61360e27715f..26682454a446 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -5,15 +5,23 @@ config DRM_AMDGPU_SI Choose this option if you want to enable experimental support for SI asics. + SI is already supported in radeon. Experimental support for SI + in amdgpu will be disabled by default and is still provided by + radeon. Use module options to override this: + + radeon.si_support=0 amdgpu.si_support=1 + config DRM_AMDGPU_CIK bool "Enable amdgpu support for CIK parts" depends on DRM_AMDGPU help - Choose this option if you want to enable experimental support - for CIK asics. + Choose this option if you want to enable support for CIK asics. + + CIK is already supported in radeon. Support for CIK in amdgpu + will be disabled by default and is still provided by radeon. + Use module options to override this: - CIK is already supported in radeon. CIK support in amdgpu - is for experimentation and testing. + radeon.cik_support=0 amdgpu.cik_support=1 config DRM_AMDGPU_USERPTR bool "Always enable userptr write support" diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 660786aba7d2..faea6349228f 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -4,7 +4,7 @@ FULL_AMD_PATH=$(src)/.. -ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \ +ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ -I$(FULL_AMD_PATH)/amdgpu \ -I$(FULL_AMD_PATH)/scheduler \ @@ -24,7 +24,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ - amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o + amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \ + amdgpu_queue_mgr.o # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ @@ -34,7 +35,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o amdgpu-y += \ - vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o + vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o # add GMC block amdgpu-y += \ @@ -54,7 +55,8 @@ amdgpu-y += \ # add PSP block amdgpu-y += \ amdgpu_psp.o \ - psp_v3_1.o + psp_v3_1.o \ + psp_v10_0.o # add SMC block amdgpu-y += \ @@ -92,6 +94,11 @@ amdgpu-y += \ vce_v3_0.o \ vce_v4_0.o +# add VCN block +amdgpu-y += \ + amdgpu_vcn.o \ + vcn_v1_0.o + # add amdkfd interfaces amdgpu-y += \ amdgpu_amdkfd.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 833c3c16501a..ff7bf1a9f967 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -36,16 +36,18 @@ #include <linux/hashtable.h> #include <linux/dma-fence.h> -#include <ttm/ttm_bo_api.h> -#include <ttm/ttm_bo_driver.h> -#include <ttm/ttm_placement.h> -#include <ttm/ttm_module.h> -#include <ttm/ttm_execbuf_util.h> +#include <drm/ttm/ttm_bo_api.h> +#include <drm/ttm/ttm_bo_driver.h> +#include <drm/ttm/ttm_placement.h> +#include <drm/ttm/ttm_module.h> +#include <drm/ttm/ttm_execbuf_util.h> #include <drm/drmP.h> #include <drm/drm_gem.h> #include <drm/amdgpu_drm.h> +#include <kgd_kfd_interface.h> + #include "amd_shared.h" #include "amdgpu_mode.h" #include "amdgpu_ih.h" @@ -62,6 +64,7 @@ #include "amdgpu_acp.h" #include "amdgpu_uvd.h" #include "amdgpu_vce.h" +#include "amdgpu_vcn.h" #include "gpu_scheduler.h" #include "amdgpu_virt.h" @@ -92,6 +95,7 @@ extern int amdgpu_vm_size; extern int amdgpu_vm_block_size; extern int amdgpu_vm_fault_stop; extern int amdgpu_vm_debug; +extern int amdgpu_vm_update_mode; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_no_evict; @@ -109,6 +113,15 @@ extern int amdgpu_prim_buf_per_se; extern int amdgpu_pos_buf_per_se; extern int amdgpu_cntl_sb_buf_per_se; extern int amdgpu_param_buf_per_se; +extern int amdgpu_job_hang_limit; +extern int amdgpu_lbpw; + +#ifdef CONFIG_DRM_AMDGPU_SI +extern int amdgpu_si_support; +#endif +#ifdef CONFIG_DRM_AMDGPU_CIK +extern int amdgpu_cik_support; +#endif #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 @@ -305,8 +318,8 @@ struct amdgpu_gart_funcs { /* set pte flags based per asic */ uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, uint32_t flags); - /* adjust mc addr in fb for APU case */ - u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); + /* get the pde for a given mc addr */ + u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); uint32_t (*get_invalidate_req)(unsigned int vm_id); }; @@ -554,7 +567,7 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev); void amdgpu_gart_fini(struct amdgpu_device *adev); -void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, +int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int pages); int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, struct page **pagelist, @@ -602,6 +615,7 @@ struct amdgpu_mc { uint32_t srbm_soft_reset; struct amdgpu_mode_mc_save save; bool prt_warning; + uint64_t stolen_size; /* apertures */ u64 shared_aperture_start; u64 shared_aperture_end; @@ -772,6 +786,29 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, struct dma_fence **f); /* + * Queue manager + */ +struct amdgpu_queue_mapper { + int hw_ip; + struct mutex lock; + /* protected by lock */ + struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; +}; + +struct amdgpu_queue_mgr { + struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; +}; + +int amdgpu_queue_mgr_init(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr); +int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr); +int amdgpu_queue_mgr_map(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr, + int hw_ip, int instance, int ring, + struct amdgpu_ring **out_ring); + +/* * context related structures */ @@ -784,6 +821,7 @@ struct amdgpu_ctx_ring { struct amdgpu_ctx { struct kref refcount; struct amdgpu_device *adev; + struct amdgpu_queue_mgr queue_mgr; unsigned reset_counter; spinlock_t ring_lock; struct dma_fence **fences; @@ -822,6 +860,7 @@ struct amdgpu_fpriv { struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; + u32 vram_lost_counter; }; /* @@ -830,6 +869,8 @@ struct amdgpu_fpriv { struct amdgpu_bo_list { struct mutex lock; + struct rcu_head rhead; + struct kref refcount; struct amdgpu_bo *gds_obj; struct amdgpu_bo *gws_obj; struct amdgpu_bo *oa_obj; @@ -893,20 +934,26 @@ struct amdgpu_rlc { u32 *register_restore; }; +#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES + struct amdgpu_mec { struct amdgpu_bo *hpd_eop_obj; u64 hpd_eop_gpu_addr; struct amdgpu_bo *mec_fw_obj; u64 mec_fw_gpu_addr; - u32 num_pipe; u32 num_mec; - u32 num_queue; + u32 num_pipe_per_mec; + u32 num_queue_per_pipe; void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; + + /* These are the resources for which amdgpu takes ownership */ + DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); }; struct amdgpu_kiq { u64 eop_gpu_addr; struct amdgpu_bo *eop_obj; + struct mutex ring_mutex; struct amdgpu_ring ring; struct amdgpu_irq_src irq; }; @@ -981,9 +1028,15 @@ struct amdgpu_gfx_config { }; struct amdgpu_cu_info { - uint32_t number; /* total active CU number */ - uint32_t ao_cu_mask; + uint32_t max_waves_per_simd; uint32_t wave_front_size; + uint32_t max_scratch_slots_per_cu; + uint32_t lds_size; + + /* total active CU number */ + uint32_t number; + uint32_t ao_cu_mask; + uint32_t ao_cu_bitmap[4][4]; uint32_t bitmap[4][4]; }; @@ -1061,6 +1114,8 @@ struct amdgpu_gfx { uint32_t grbm_soft_reset; uint32_t srbm_soft_reset; bool in_reset; + /* s3/s4 mask */ + bool in_suspend; /* NGG */ struct amdgpu_ngg ngg; }; @@ -1109,12 +1164,14 @@ struct amdgpu_cs_parser { /* user fence */ struct amdgpu_bo_list_entry uf_entry; + + unsigned num_post_dep_syncobjs; + struct drm_syncobj **post_dep_syncobjs; }; #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ -#define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */ struct amdgpu_job { struct amd_sched_job base; @@ -1122,6 +1179,8 @@ struct amdgpu_job { struct amdgpu_vm *vm; struct amdgpu_ring *ring; struct amdgpu_sync sync; + struct amdgpu_sync dep_sync; + struct amdgpu_sync sched_sync; struct amdgpu_ib *ibs; struct dma_fence *fence; /* the hw fence */ uint32_t preamble_status; @@ -1129,7 +1188,6 @@ struct amdgpu_job { void *owner; uint64_t fence_ctx; /* the fence_context this job uses */ bool vm_needs_flush; - bool need_pipeline_sync; unsigned vm_id; uint64_t vm_pd_addr; uint32_t gds_base, gds_size; @@ -1221,6 +1279,9 @@ struct amdgpu_firmware { const struct amdgpu_psp_funcs *funcs; struct amdgpu_bo *rbuf; struct mutex mutex; + + /* gpu info firmware data pointer */ + const struct firmware *gpu_info_fw; }; /* @@ -1296,7 +1357,6 @@ struct amdgpu_smumgr { */ struct amdgpu_allowed_register_entry { uint32_t reg_offset; - bool untouched; bool grbm_indexed; }; @@ -1424,6 +1484,7 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); +#define AMDGPU_RESET_MAGIC_NUM 64 struct amdgpu_device { struct device *dev; struct drm_device *ddev; @@ -1523,7 +1584,9 @@ struct amdgpu_device { atomic64_t gtt_usage; atomic64_t num_bytes_moved; atomic64_t num_evictions; + atomic64_t num_vram_cpu_page_faults; atomic_t gpu_reset_counter; + atomic_t vram_lost_counter; /* data for buffer migration throttling */ struct { @@ -1570,11 +1633,18 @@ struct amdgpu_device { /* sdma */ struct amdgpu_sdma sdma; - /* uvd */ - struct amdgpu_uvd uvd; + union { + struct { + /* uvd */ + struct amdgpu_uvd uvd; + + /* vce */ + struct amdgpu_vce vce; + }; - /* vce */ - struct amdgpu_vce vce; + /* vcn */ + struct amdgpu_vcn vcn; + }; /* firmwares */ struct amdgpu_firmware firmware; @@ -1598,6 +1668,9 @@ struct amdgpu_device { /* amdkfd interface */ struct kfd_dev *kfd; + /* delayed work_func for deferring clockgating during resume */ + struct delayed_work late_init_work; + struct amdgpu_virt virt; /* link all shadow bo */ @@ -1606,9 +1679,13 @@ struct amdgpu_device { /* link all gtt */ spinlock_t gtt_list_lock; struct list_head gtt_list; + /* keep an lru list of rings by HW IP */ + struct list_head ring_lru_list; + spinlock_t ring_lru_list_lock; /* record hw reset is performed */ bool has_hw_reset; + u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; }; @@ -1617,7 +1694,6 @@ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) return container_of(bdev, struct amdgpu_device, mman.bdev); } -bool amdgpu_device_is_px(struct drm_device *dev); int amdgpu_device_init(struct amdgpu_device *adev, struct drm_device *ddev, struct pci_dev *pdev, @@ -1733,30 +1809,31 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *sr unsigned occupied, chunk1, chunk2; void *dst; - if (ring->count_dw < count_dw) { + if (unlikely(ring->count_dw < count_dw)) { DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); - } else { - occupied = ring->wptr & ring->buf_mask; - dst = (void *)&ring->ring[occupied]; - chunk1 = ring->buf_mask + 1 - occupied; - chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; - chunk2 = count_dw - chunk1; - chunk1 <<= 2; - chunk2 <<= 2; - - if (chunk1) - memcpy(dst, src, chunk1); - - if (chunk2) { - src += chunk1; - dst = (void *)ring->ring; - memcpy(dst, src, chunk2); - } - - ring->wptr += count_dw; - ring->wptr &= ring->ptr_mask; - ring->count_dw -= count_dw; + return; + } + + occupied = ring->wptr & ring->buf_mask; + dst = (void *)&ring->ring[occupied]; + chunk1 = ring->buf_mask + 1 - occupied; + chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; + chunk2 = count_dw - chunk1; + chunk1 <<= 2; + chunk2 <<= 2; + + if (chunk1) + memcpy(dst, src, chunk1); + + if (chunk2) { + src += chunk1; + dst = (void *)ring->ring; + memcpy(dst, src, chunk2); } + + ring->wptr += count_dw; + ring->wptr &= ring->ptr_mask; + ring->count_dw -= count_dw; } static inline struct amdgpu_sdma_instance * @@ -1792,6 +1869,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) +#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) @@ -1813,6 +1891,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) +#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) @@ -1848,10 +1927,6 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev); void amdgpu_update_display_priority(struct amdgpu_device *adev); -int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); -int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, - u32 ip_instance, u32 ring, - struct amdgpu_ring **out_ring); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); @@ -1900,6 +1975,8 @@ static inline bool amdgpu_has_atpx(void) { return false; } extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; extern const int amdgpu_max_kms_ioctl; +bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv); int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); void amdgpu_driver_unload_kms(struct drm_device *dev); void amdgpu_driver_lastclose_kms(struct drm_device *dev); @@ -1912,10 +1989,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags); long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index dba8a5b25e66..5f8ada1d872b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -24,6 +24,7 @@ #include "amd_shared.h" #include <drm/drmP.h> #include "amdgpu.h" +#include "amdgpu_gfx.h" #include <linux/module.h> const struct kfd2kgd_calls *kfd2kgd; @@ -60,9 +61,9 @@ int amdgpu_amdkfd_init(void) return ret; } -bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev) +bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev) { - switch (rdev->asic_type) { + switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_KAVERI: kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions(); @@ -86,59 +87,83 @@ void amdgpu_amdkfd_fini(void) } } -void amdgpu_amdkfd_device_probe(struct amdgpu_device *rdev) +void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) { if (kgd2kfd) - rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, - rdev->pdev, kfd2kgd); + adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, + adev->pdev, kfd2kgd); } -void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev) +void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) { - if (rdev->kfd) { + int i; + int last_valid_bit; + if (adev->kfd) { struct kgd2kfd_shared_resources gpu_resources = { .compute_vmid_bitmap = 0xFF00, - - .first_compute_pipe = 1, - .compute_pipe_count = 4 - 1, + .num_mec = adev->gfx.mec.num_mec, + .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, + .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe }; - amdgpu_doorbell_get_kfd_info(rdev, + /* this is going to have a few of the MSBs set that we need to + * clear */ + bitmap_complement(gpu_resources.queue_bitmap, + adev->gfx.mec.queue_bitmap, + KGD_MAX_QUEUES); + + /* remove the KIQ bit as well */ + if (adev->gfx.kiq.ring.ready) + clear_bit(amdgpu_gfx_queue_to_bit(adev, + adev->gfx.kiq.ring.me - 1, + adev->gfx.kiq.ring.pipe, + adev->gfx.kiq.ring.queue), + gpu_resources.queue_bitmap); + + /* According to linux/bitmap.h we shouldn't use bitmap_clear if + * nbits is not compile time constant */ + last_valid_bit = adev->gfx.mec.num_mec + * adev->gfx.mec.num_pipe_per_mec + * adev->gfx.mec.num_queue_per_pipe; + for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) + clear_bit(i, gpu_resources.queue_bitmap); + + amdgpu_doorbell_get_kfd_info(adev, &gpu_resources.doorbell_physical_address, &gpu_resources.doorbell_aperture_size, &gpu_resources.doorbell_start_offset); - kgd2kfd->device_init(rdev->kfd, &gpu_resources); + kgd2kfd->device_init(adev->kfd, &gpu_resources); } } -void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev) +void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) { - if (rdev->kfd) { - kgd2kfd->device_exit(rdev->kfd); - rdev->kfd = NULL; + if (adev->kfd) { + kgd2kfd->device_exit(adev->kfd); + adev->kfd = NULL; } } -void amdgpu_amdkfd_interrupt(struct amdgpu_device *rdev, +void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, const void *ih_ring_entry) { - if (rdev->kfd) - kgd2kfd->interrupt(rdev->kfd, ih_ring_entry); + if (adev->kfd) + kgd2kfd->interrupt(adev->kfd, ih_ring_entry); } -void amdgpu_amdkfd_suspend(struct amdgpu_device *rdev) +void amdgpu_amdkfd_suspend(struct amdgpu_device *adev) { - if (rdev->kfd) - kgd2kfd->suspend(rdev->kfd); + if (adev->kfd) + kgd2kfd->suspend(adev->kfd); } -int amdgpu_amdkfd_resume(struct amdgpu_device *rdev) +int amdgpu_amdkfd_resume(struct amdgpu_device *adev) { int r = 0; - if (rdev->kfd) - r = kgd2kfd->resume(rdev->kfd); + if (adev->kfd) + r = kgd2kfd->resume(adev->kfd); return r; } @@ -147,7 +172,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, void **mem_obj, uint64_t *gpu_addr, void **cpu_ptr) { - struct amdgpu_device *rdev = (struct amdgpu_device *)kgd; + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct kgd_mem **mem = (struct kgd_mem **) mem_obj; int r; @@ -159,10 +184,10 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, if ((*mem) == NULL) return -ENOMEM; - r = amdgpu_bo_create(rdev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, &(*mem)->bo); if (r) { - dev_err(rdev->dev, + dev_err(adev->dev, "failed to allocate BO for amdkfd (%d)\n", r); return r; } @@ -170,21 +195,21 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, /* map the buffer */ r = amdgpu_bo_reserve((*mem)->bo, true); if (r) { - dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r); + dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); goto allocate_mem_reserve_bo_failed; } r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT, &(*mem)->gpu_addr); if (r) { - dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r); + dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); goto allocate_mem_pin_bo_failed; } *gpu_addr = (*mem)->gpu_addr; r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr); if (r) { - dev_err(rdev->dev, + dev_err(adev->dev, "(%d) failed to map bo to kernel for amdkfd\n", r); goto allocate_mem_kmap_bo_failed; } @@ -220,27 +245,27 @@ void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) uint64_t get_vmem_size(struct kgd_dev *kgd) { - struct amdgpu_device *rdev = + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; BUG_ON(kgd == NULL); - return rdev->mc.real_vram_size; + return adev->mc.real_vram_size; } uint64_t get_gpu_clock_counter(struct kgd_dev *kgd) { - struct amdgpu_device *rdev = (struct amdgpu_device *)kgd; + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; - if (rdev->gfx.funcs->get_gpu_clock_counter) - return rdev->gfx.funcs->get_gpu_clock_counter(rdev); + if (adev->gfx.funcs->get_gpu_clock_counter) + return adev->gfx.funcs->get_gpu_clock_counter(adev); return 0; } uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) { - struct amdgpu_device *rdev = (struct amdgpu_device *)kgd; + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; /* The sclk is in quantas of 10kHz */ - return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; + return adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index de530f68d4e3..73f83a10ae14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -39,15 +39,15 @@ struct kgd_mem { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); -bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev); +bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev); -void amdgpu_amdkfd_suspend(struct amdgpu_device *rdev); -int amdgpu_amdkfd_resume(struct amdgpu_device *rdev); -void amdgpu_amdkfd_interrupt(struct amdgpu_device *rdev, +void amdgpu_amdkfd_suspend(struct amdgpu_device *adev); +int amdgpu_amdkfd_resume(struct amdgpu_device *adev); +void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, const void *ih_ring_entry); -void amdgpu_amdkfd_device_probe(struct amdgpu_device *rdev); -void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev); -void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev); +void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); +void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); +void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev); struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void); struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 1a0a5f7cccbc..5254562fd0f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -29,6 +29,7 @@ #include "cikd.h" #include "cik_sdma.h" #include "amdgpu_ucode.h" +#include "gfx_v7_0.h" #include "gca/gfx_7_2_d.h" #include "gca/gfx_7_2_enum.h" #include "gca/gfx_7_2_sh_mask.h" @@ -38,8 +39,6 @@ #include "gmc/gmc_7_1_sh_mask.h" #include "cik_structs.h" -#define CIK_PIPE_PER_MEC (4) - enum { MAX_TRAPID = 8, /* 3 bits in the bitfield. */ MAX_WATCH_ADDRESSES = 4 @@ -185,8 +184,10 @@ static void unlock_srbm(struct kgd_dev *kgd) static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t queue_id) { - uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1; - uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); + struct amdgpu_device *adev = get_amdgpu_device(kgd); + + uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); } @@ -243,18 +244,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr) { - struct amdgpu_device *adev = get_amdgpu_device(kgd); - - uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1; - uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); - - lock_srbm(kgd, mec, pipe, 0, 0); - WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8)); - WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8)); - WREG32(mmCP_HPD_EOP_VMID, 0); - WREG32(mmCP_HPD_EOP_CONTROL, hpd_size); - unlock_srbm(kgd); - + /* amdgpu owns the per-pipe state */ return 0; } @@ -264,8 +254,8 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t mec; uint32_t pipe; - mec = (pipe_id / CIK_PIPE_PER_MEC) + 1; - pipe = (pipe_id % CIK_PIPE_PER_MEC); + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, 0, 0); @@ -309,55 +299,11 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, m = get_mqd(mqd); is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); - - acquire_queue(kgd, pipe_id, queue_id); - WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo); - WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi); - WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control); - - WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo); - WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi); - WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); - - WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control); - WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo); - WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi); - - WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr); - - WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state); - WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd); - WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type); - - WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo); - WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi); - WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo); - WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi); - - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - m->cp_hqd_pq_rptr_report_addr_hi); - - WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr); - - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo); - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi); - - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control); - - WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid); - - WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum); - - WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority); - WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority); - - WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr); - if (is_wptr_shadow_valid) - WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow); + m->cp_hqd_pq_wptr = wptr_shadow; - WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active); + acquire_queue(kgd, pipe_id, queue_id); + gfx_v7_0_mqd_commit(adev, m); release_queue(kgd); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 6697612239c2..133d06671e46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -28,6 +28,7 @@ #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "amdgpu_ucode.h" +#include "gfx_v8_0.h" #include "gca/gfx_8_0_sh_mask.h" #include "gca/gfx_8_0_d.h" #include "gca/gfx_8_0_enum.h" @@ -38,8 +39,6 @@ #include "vi_structs.h" #include "vid.h" -#define VI_PIPE_PER_MEC (4) - struct cik_sdma_rlc_registers; /* @@ -146,8 +145,10 @@ static void unlock_srbm(struct kgd_dev *kgd) static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t queue_id) { - uint32_t mec = (++pipe_id / VI_PIPE_PER_MEC) + 1; - uint32_t pipe = (pipe_id % VI_PIPE_PER_MEC); + struct amdgpu_device *adev = get_amdgpu_device(kgd); + + uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); } @@ -205,6 +206,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr) { + /* amdgpu owns the per-pipe state */ return 0; } @@ -214,8 +216,8 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t mec; uint32_t pipe; - mec = (++pipe_id / VI_PIPE_PER_MEC) + 1; - pipe = (pipe_id % VI_PIPE_PER_MEC); + mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, 0, 0); @@ -251,53 +253,11 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, m = get_mqd(mqd); valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr)); - acquire_queue(kgd, pipe_id, queue_id); - - WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control); - WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo); - WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi); - - WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid); - WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state); - WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority); - WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority); - WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum); - WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo); - WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - m->cp_hqd_pq_rptr_report_addr_hi); - - if (valid_wptr > 0) - WREG32(mmCP_HQD_PQ_WPTR, shadow_wptr); - - WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control); - - WREG32(mmCP_HQD_EOP_BASE_ADDR, m->cp_hqd_eop_base_addr_lo); - WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, m->cp_hqd_eop_base_addr_hi); - WREG32(mmCP_HQD_EOP_CONTROL, m->cp_hqd_eop_control); - WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); - WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); - WREG32(mmCP_HQD_EOP_EVENTS, m->cp_hqd_eop_done_events); - - WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, m->cp_hqd_ctx_save_base_addr_lo); - WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, m->cp_hqd_ctx_save_base_addr_hi); - WREG32(mmCP_HQD_CTX_SAVE_CONTROL, m->cp_hqd_ctx_save_control); - WREG32(mmCP_HQD_CNTL_STACK_OFFSET, m->cp_hqd_cntl_stack_offset); - WREG32(mmCP_HQD_CNTL_STACK_SIZE, m->cp_hqd_cntl_stack_size); - WREG32(mmCP_HQD_WG_STATE_OFFSET, m->cp_hqd_wg_state_offset); - WREG32(mmCP_HQD_CTX_SAVE_SIZE, m->cp_hqd_ctx_save_size); - - WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control); - - WREG32(mmCP_HQD_DEQUEUE_REQUEST, m->cp_hqd_dequeue_request); - WREG32(mmCP_HQD_ERROR, m->cp_hqd_error); - WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); - WREG32(mmCP_HQD_EOP_DONES, m->cp_hqd_eop_dones); - - WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active); + if (valid_wptr == 0) + m->cp_hqd_pq_wptr = shadow_wptr; + acquire_queue(kgd, pipe_id, queue_id); + gfx_v8_0_mqd_commit(adev, mqd); release_queue(kgd); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index a6649874e6ce..f621ee115c98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -35,33 +35,59 @@ #define AMDGPU_BO_LIST_MAX_PRIORITY 32u #define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1) -static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv, - struct amdgpu_bo_list **result, +static int amdgpu_bo_list_set(struct amdgpu_device *adev, + struct drm_file *filp, + struct amdgpu_bo_list *list, + struct drm_amdgpu_bo_list_entry *info, + unsigned num_entries); + +static void amdgpu_bo_list_release_rcu(struct kref *ref) +{ + unsigned i; + struct amdgpu_bo_list *list = container_of(ref, struct amdgpu_bo_list, + refcount); + + for (i = 0; i < list->num_entries; ++i) + amdgpu_bo_unref(&list->array[i].robj); + + mutex_destroy(&list->lock); + kvfree(list->array); + kfree_rcu(list, rhead); +} + +static int amdgpu_bo_list_create(struct amdgpu_device *adev, + struct drm_file *filp, + struct drm_amdgpu_bo_list_entry *info, + unsigned num_entries, int *id) { int r; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_bo_list *list; - *result = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL); - if (!*result) + list = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL); + if (!list) return -ENOMEM; + /* initialize bo list*/ + mutex_init(&list->lock); + kref_init(&list->refcount); + r = amdgpu_bo_list_set(adev, filp, list, info, num_entries); + if (r) { + kfree(list); + return r; + } + + /* idr alloc should be called only after initialization of bo list. */ mutex_lock(&fpriv->bo_list_lock); - r = idr_alloc(&fpriv->bo_list_handles, *result, - 1, 0, GFP_KERNEL); + r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL); + mutex_unlock(&fpriv->bo_list_lock); if (r < 0) { - mutex_unlock(&fpriv->bo_list_lock); - kfree(*result); + kfree(list); return r; } *id = r; - mutex_init(&(*result)->lock); - (*result)->num_entries = 0; - (*result)->array = NULL; - - mutex_lock(&(*result)->lock); - mutex_unlock(&fpriv->bo_list_lock); - return 0; } @@ -71,13 +97,9 @@ static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id) mutex_lock(&fpriv->bo_list_lock); list = idr_remove(&fpriv->bo_list_handles, id); - if (list) { - /* Another user may have a reference to this list still */ - mutex_lock(&list->lock); - mutex_unlock(&list->lock); - amdgpu_bo_list_free(list); - } mutex_unlock(&fpriv->bo_list_lock); + if (list) + kref_put(&list->refcount, amdgpu_bo_list_release_rcu); } static int amdgpu_bo_list_set(struct amdgpu_device *adev, @@ -96,7 +118,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, int r; unsigned long total_size = 0; - array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry)); + array = kvmalloc_array(num_entries, sizeof(struct amdgpu_bo_list_entry), GFP_KERNEL); if (!array) return -ENOMEM; memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry)); @@ -148,7 +170,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, for (i = 0; i < list->num_entries; ++i) amdgpu_bo_unref(&list->array[i].robj); - drm_free_large(list->array); + kvfree(list->array); list->gds_obj = gds_obj; list->gws_obj = gws_obj; @@ -163,7 +185,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, error_free: while (i--) amdgpu_bo_unref(&array[i].robj); - drm_free_large(array); + kvfree(array); return r; } @@ -172,11 +194,17 @@ amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id) { struct amdgpu_bo_list *result; - mutex_lock(&fpriv->bo_list_lock); + rcu_read_lock(); result = idr_find(&fpriv->bo_list_handles, id); - if (result) - mutex_lock(&result->lock); - mutex_unlock(&fpriv->bo_list_lock); + + if (result) { + if (kref_get_unless_zero(&result->refcount)) + mutex_lock(&result->lock); + else + result = NULL; + } + rcu_read_unlock(); + return result; } @@ -214,6 +242,7 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, void amdgpu_bo_list_put(struct amdgpu_bo_list *list) { mutex_unlock(&list->lock); + kref_put(&list->refcount, amdgpu_bo_list_release_rcu); } void amdgpu_bo_list_free(struct amdgpu_bo_list *list) @@ -224,7 +253,7 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list) amdgpu_bo_unref(&list->array[i].robj); mutex_destroy(&list->lock); - drm_free_large(list->array); + kvfree(list->array); kfree(list); } @@ -244,8 +273,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, int r; - info = drm_malloc_ab(args->in.bo_number, - sizeof(struct drm_amdgpu_bo_list_entry)); + info = kvmalloc_array(args->in.bo_number, + sizeof(struct drm_amdgpu_bo_list_entry), GFP_KERNEL); if (!info) return -ENOMEM; @@ -273,16 +302,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, switch (args->in.operation) { case AMDGPU_BO_LIST_OP_CREATE: - r = amdgpu_bo_list_create(fpriv, &list, &handle); + r = amdgpu_bo_list_create(adev, filp, info, args->in.bo_number, + &handle); if (r) goto error_free; - - r = amdgpu_bo_list_set(adev, filp, list, info, - args->in.bo_number); - amdgpu_bo_list_put(list); - if (r) - goto error_free; - break; case AMDGPU_BO_LIST_OP_DESTROY: @@ -311,11 +334,11 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, memset(args, 0, sizeof(*args)); args->out.list_handle = handle; - drm_free_large(info); + kvfree(info); return 0; error_free: - drm_free_large(info); + kvfree(info); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index c6dba1eaefbd..c0a806280257 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -838,6 +838,12 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, return -EINVAL; mode_info = info->mode_info; + if (mode_info) { + /* if the displays are off, vblank time is max */ + mode_info->vblank_time_us = 0xffffffff; + /* always set the reference clock */ + mode_info->ref_clock = adev->clock.spll.reference_freq; + } if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { list_for_each_entry(crtc, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4e6b9501ab0a..5599c01b265d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -27,81 +27,10 @@ #include <linux/pagemap.h> #include <drm/drmP.h> #include <drm/amdgpu_drm.h> +#include <drm/drm_syncobj.h> #include "amdgpu.h" #include "amdgpu_trace.h" -int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, - u32 ip_instance, u32 ring, - struct amdgpu_ring **out_ring) -{ - /* Right now all IPs have only one instance - multiple rings. */ - if (ip_instance != 0) { - DRM_ERROR("invalid ip instance: %d\n", ip_instance); - return -EINVAL; - } - - switch (ip_type) { - default: - DRM_ERROR("unknown ip type: %d\n", ip_type); - return -EINVAL; - case AMDGPU_HW_IP_GFX: - if (ring < adev->gfx.num_gfx_rings) { - *out_ring = &adev->gfx.gfx_ring[ring]; - } else { - DRM_ERROR("only %d gfx rings are supported now\n", - adev->gfx.num_gfx_rings); - return -EINVAL; - } - break; - case AMDGPU_HW_IP_COMPUTE: - if (ring < adev->gfx.num_compute_rings) { - *out_ring = &adev->gfx.compute_ring[ring]; - } else { - DRM_ERROR("only %d compute rings are supported now\n", - adev->gfx.num_compute_rings); - return -EINVAL; - } - break; - case AMDGPU_HW_IP_DMA: - if (ring < adev->sdma.num_instances) { - *out_ring = &adev->sdma.instance[ring].ring; - } else { - DRM_ERROR("only %d SDMA rings are supported\n", - adev->sdma.num_instances); - return -EINVAL; - } - break; - case AMDGPU_HW_IP_UVD: - *out_ring = &adev->uvd.ring; - break; - case AMDGPU_HW_IP_VCE: - if (ring < adev->vce.num_rings){ - *out_ring = &adev->vce.ring[ring]; - } else { - DRM_ERROR("only %d VCE rings are supported\n", adev->vce.num_rings); - return -EINVAL; - } - break; - case AMDGPU_HW_IP_UVD_ENC: - if (ring < adev->uvd.num_enc_rings){ - *out_ring = &adev->uvd.ring_enc[ring]; - } else { - DRM_ERROR("only %d UVD ENC rings are supported\n", - adev->uvd.num_enc_rings); - return -EINVAL; - } - break; - } - - if (!(*out_ring && (*out_ring)->adev)) { - DRM_ERROR("Ring %d is not initialized on IP %d\n", - ring, ip_type); - return -EINVAL; - } - - return 0; -} - static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, struct drm_amdgpu_cs_chunk_fence *data, uint32_t *offset) @@ -135,7 +64,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, return 0; } -int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) +static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) { struct amdgpu_fpriv *fpriv = p->filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -194,7 +123,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) size = p->chunks[i].length_dw; cdata = (void __user *)(uintptr_t)user_chunk.chunk_data; - p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); + p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); if (p->chunks[i].kdata == NULL) { ret = -ENOMEM; i--; @@ -226,6 +155,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) break; case AMDGPU_CHUNK_ID_DEPENDENCIES: + case AMDGPU_CHUNK_ID_SYNCOBJ_IN: + case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: break; default: @@ -247,7 +178,7 @@ free_all_kdata: i = p->nchunks - 1; free_partial_kdata: for (; i >= 0; i--) - drm_free_large(p->chunks[i].kdata); + kvfree(p->chunks[i].kdata); kfree(p->chunks); p->chunks = NULL; p->nchunks = 0; @@ -505,7 +436,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, return r; if (binding_userptr) { - drm_free_large(lobj->user_pages); + kvfree(lobj->user_pages); lobj->user_pages = NULL; } } @@ -566,12 +497,12 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, &e->user_invalidated) && e->user_pages) { /* We acquired a page array, but somebody - * invalidated it. Free it an try again + * invalidated it. Free it and try again */ release_pages(e->user_pages, e->robj->tbo.ttm->num_pages, false); - drm_free_large(e->user_pages); + kvfree(e->user_pages); e->user_pages = NULL; } @@ -597,12 +528,13 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } - /* Fill the page arrays for all useptrs. */ + /* Fill the page arrays for all userptrs. */ list_for_each_entry(e, &need_pages, tv.head) { struct ttm_tt *ttm = e->robj->tbo.ttm; - e->user_pages = drm_calloc_large(ttm->num_pages, - sizeof(struct page*)); + e->user_pages = kvmalloc_array(ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); if (!e->user_pages) { r = -ENOMEM; DRM_ERROR("calloc failure in %s\n", __func__); @@ -612,7 +544,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); if (r) { DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); - drm_free_large(e->user_pages); + kvfree(e->user_pages); e->user_pages = NULL; goto error_free_pages; } @@ -708,7 +640,7 @@ error_free_pages: release_pages(e->user_pages, e->robj->tbo.ttm->num_pages, false); - drm_free_large(e->user_pages); + kvfree(e->user_pages); } } @@ -753,6 +685,11 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo ttm_eu_backoff_reservation(&parser->ticket, &parser->validated); } + + for (i = 0; i < parser->num_post_dep_syncobjs; i++) + drm_syncobj_put(parser->post_dep_syncobjs[i]); + kfree(parser->post_dep_syncobjs); + dma_fence_put(parser->fence); if (parser->ctx) @@ -761,7 +698,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo amdgpu_bo_list_put(parser->bo_list); for (i = 0; i < parser->nchunks; i++) - drm_free_large(parser->chunks[i].kdata); + kvfree(parser->chunks[i].kdata); kfree(parser->chunks); if (parser->job) amdgpu_job_free(parser->job); @@ -916,9 +853,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, return -EINVAL; } - r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, - chunk_ib->ip_instance, chunk_ib->ring, - &ring); + r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type, + chunk_ib->ip_instance, chunk_ib->ring, &ring); if (r) return r; @@ -995,62 +931,148 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, return 0; } -static int amdgpu_cs_dependencies(struct amdgpu_device *adev, - struct amdgpu_cs_parser *p) +static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, + struct amdgpu_cs_chunk *chunk) { struct amdgpu_fpriv *fpriv = p->filp->driver_priv; - int i, j, r; - - for (i = 0; i < p->nchunks; ++i) { - struct drm_amdgpu_cs_chunk_dep *deps; - struct amdgpu_cs_chunk *chunk; - unsigned num_deps; + unsigned num_deps; + int i, r; + struct drm_amdgpu_cs_chunk_dep *deps; - chunk = &p->chunks[i]; + deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; + num_deps = chunk->length_dw * 4 / + sizeof(struct drm_amdgpu_cs_chunk_dep); - if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) - continue; + for (i = 0; i < num_deps; ++i) { + struct amdgpu_ring *ring; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; - deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; - num_deps = chunk->length_dw * 4 / - sizeof(struct drm_amdgpu_cs_chunk_dep); + ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id); + if (ctx == NULL) + return -EINVAL; - for (j = 0; j < num_deps; ++j) { - struct amdgpu_ring *ring; - struct amdgpu_ctx *ctx; - struct dma_fence *fence; + r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr, + deps[i].ip_type, + deps[i].ip_instance, + deps[i].ring, &ring); + if (r) { + amdgpu_ctx_put(ctx); + return r; + } - r = amdgpu_cs_get_ring(adev, deps[j].ip_type, - deps[j].ip_instance, - deps[j].ring, &ring); + fence = amdgpu_ctx_get_fence(ctx, ring, + deps[i].handle); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + amdgpu_ctx_put(ctx); + return r; + } else if (fence) { + r = amdgpu_sync_fence(p->adev, &p->job->sync, + fence); + dma_fence_put(fence); + amdgpu_ctx_put(ctx); if (r) return r; + } + } + return 0; +} - ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); - if (ctx == NULL) - return -EINVAL; +static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, + uint32_t handle) +{ + int r; + struct dma_fence *fence; + r = drm_syncobj_fence_get(p->filp, handle, &fence); + if (r) + return r; - fence = amdgpu_ctx_get_fence(ctx, ring, - deps[j].handle); - if (IS_ERR(fence)) { - r = PTR_ERR(fence); - amdgpu_ctx_put(ctx); - return r; + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence); + dma_fence_put(fence); - } else if (fence) { - r = amdgpu_sync_fence(adev, &p->job->sync, - fence); - dma_fence_put(fence); - amdgpu_ctx_put(ctx); - if (r) - return r; - } + return r; +} + +static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p, + struct amdgpu_cs_chunk *chunk) +{ + unsigned num_deps; + int i, r; + struct drm_amdgpu_cs_chunk_sem *deps; + + deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; + num_deps = chunk->length_dw * 4 / + sizeof(struct drm_amdgpu_cs_chunk_sem); + + for (i = 0; i < num_deps; ++i) { + r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle); + if (r) + return r; + } + return 0; +} + +static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p, + struct amdgpu_cs_chunk *chunk) +{ + unsigned num_deps; + int i; + struct drm_amdgpu_cs_chunk_sem *deps; + deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; + num_deps = chunk->length_dw * 4 / + sizeof(struct drm_amdgpu_cs_chunk_sem); + + p->post_dep_syncobjs = kmalloc_array(num_deps, + sizeof(struct drm_syncobj *), + GFP_KERNEL); + p->num_post_dep_syncobjs = 0; + + for (i = 0; i < num_deps; ++i) { + p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle); + if (!p->post_dep_syncobjs[i]) + return -EINVAL; + p->num_post_dep_syncobjs++; + } + return 0; +} + +static int amdgpu_cs_dependencies(struct amdgpu_device *adev, + struct amdgpu_cs_parser *p) +{ + int i, r; + + for (i = 0; i < p->nchunks; ++i) { + struct amdgpu_cs_chunk *chunk; + + chunk = &p->chunks[i]; + + if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) { + r = amdgpu_cs_process_fence_dep(p, chunk); + if (r) + return r; + } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) { + r = amdgpu_cs_process_syncobj_in_dep(p, chunk); + if (r) + return r; + } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) { + r = amdgpu_cs_process_syncobj_out_dep(p, chunk); + if (r) + return r; } } return 0; } +static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) +{ + int i; + + for (i = 0; i < p->num_post_dep_syncobjs; ++i) + drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence); +} + static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) { @@ -1071,6 +1093,9 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job->owner = p->filp; job->fence_ctx = entity->fence_context; p->fence = dma_fence_get(&job->base.s_fence->finished); + + amdgpu_cs_post_dependencies(p); + cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); job->uf_sequence = cs->out.handle; amdgpu_job_free_resources(job); @@ -1078,13 +1103,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, trace_amdgpu_cs_ioctl(job); amd_sched_entity_push_job(&job->base); - return 0; } int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; union drm_amdgpu_cs *cs = data; struct amdgpu_cs_parser parser = {}; bool reserved_buffers = false; @@ -1092,6 +1117,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (!adev->accel_working) return -EBUSY; + if (amdgpu_kms_vram_lost(adev, fpriv)) + return -ENODEV; parser.adev = adev; parser.filp = filp; @@ -1153,21 +1180,28 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, { union drm_amdgpu_wait_cs *wait = data; struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); struct amdgpu_ring *ring = NULL; struct amdgpu_ctx *ctx; struct dma_fence *fence; long r; - r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, - wait->in.ring, &ring); - if (r) - return r; + if (amdgpu_kms_vram_lost(adev, fpriv)) + return -ENODEV; ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); if (ctx == NULL) return -EINVAL; + r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, + wait->in.ip_type, wait->in.ip_instance, + wait->in.ring, &ring); + if (r) { + amdgpu_ctx_put(ctx); + return r; + } + fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); if (IS_ERR(fence)) r = PTR_ERR(fence); @@ -1203,15 +1237,17 @@ static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, struct dma_fence *fence; int r; - r = amdgpu_cs_get_ring(adev, user->ip_type, user->ip_instance, - user->ring, &ring); - if (r) - return ERR_PTR(r); - ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id); if (ctx == NULL) return ERR_PTR(-EINVAL); + r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type, + user->ip_instance, user->ring, &ring); + if (r) { + amdgpu_ctx_put(ctx); + return ERR_PTR(r); + } + fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no); amdgpu_ctx_put(ctx); @@ -1332,12 +1368,15 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; union drm_amdgpu_wait_fences *wait = data; uint32_t fence_count = wait->in.fence_count; struct drm_amdgpu_fence *fences_user; struct drm_amdgpu_fence *fences; int r; + if (amdgpu_kms_vram_lost(adev, fpriv)) + return -ENODEV; /* Get the fences from userspace */ fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 90d1ac8a80f8..a11e44340b23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -52,12 +52,20 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) struct amd_sched_rq *rq; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; + + if (ring == &adev->gfx.kiq.ring) + continue; + r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, rq, amdgpu_sched_jobs); if (r) goto failed; } + r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr); + if (r) + goto failed; + return 0; failed: @@ -86,6 +94,8 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) for (i = 0; i < adev->num_rings; i++) amd_sched_entity_fini(&adev->rings[i]->sched, &ctx->rings[i].entity); + + amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr); } static int amdgpu_ctx_alloc(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bbac5d5d1fcf..4a8fc15467cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -54,8 +54,14 @@ #include <linux/pci.h> #include <linux/firmware.h> +MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); +MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); + +#define AMDGPU_RESUME_MS 2000 + static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); +static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); static const char *amdgpu_asic_name[] = { "TAHITI", @@ -77,6 +83,7 @@ static const char *amdgpu_asic_name[] = { "POLARIS11", "POLARIS12", "VEGA10", + "RAVEN", "LAST", }; @@ -478,9 +485,8 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, /* * amdgpu_wb_*() - * Writeback is the the method by which the the GPU updates special pages - * in memory with the status of certain GPU events (fences, ring pointers, - * etc.). + * Writeback is the method by which the GPU updates special pages in memory + * with the status of certain GPU events (fences, ring pointers,etc.). */ /** @@ -506,7 +512,7 @@ static void amdgpu_wb_fini(struct amdgpu_device *adev) * * @adev: amdgpu_device pointer * - * Disables Writeback and frees the Writeback memory (all asics). + * Initializes writeback and allocates writeback memory (all asics). * Used at driver startup. * Returns 0 on success or an -error on failure. */ @@ -614,7 +620,7 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) * @mc: memory controller structure holding memory informations * @base: base address at which to put VRAM * - * Function will place try to place VRAM at base address provided + * Function will try to place VRAM at base address provided * as parameter (which is so far either PCI aperture address or * for IGP TOM base address). * @@ -636,7 +642,7 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) * ones) * * Note: IGP TOM addr should be the same as the aperture addr, we don't - * explicitly check for that thought. + * explicitly check for that though. * * FIXME: when reducing VRAM size align new size on power of 2. */ @@ -1067,6 +1073,10 @@ def_value: static void amdgpu_check_vm_size(struct amdgpu_device *adev) { + /* no need to check the default value */ + if (amdgpu_vm_size == -1) + return; + if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", amdgpu_vm_size); @@ -1338,6 +1348,9 @@ int amdgpu_ip_block_add(struct amdgpu_device *adev, if (!ip_block_version) return -EINVAL; + DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, + ip_block_version->funcs->name); + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; return 0; @@ -1388,6 +1401,104 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) } } +static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + const struct gpu_info_firmware_header_v1_0 *hdr; + + adev->firmware.gpu_info_fw = NULL; + + switch (adev->asic_type) { + case CHIP_TOPAZ: + case CHIP_TONGA: + case CHIP_FIJI: + case CHIP_POLARIS11: + case CHIP_POLARIS10: + case CHIP_POLARIS12: + case CHIP_CARRIZO: + case CHIP_STONEY: +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_VERDE: + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_OLAND: + case CHIP_HAINAN: +#endif +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: +#endif + default: + return 0; + case CHIP_VEGA10: + chip_name = "vega10"; + break; + case CHIP_RAVEN: + chip_name = "raven"; + break; + } + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); + err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); + if (err) { + dev_err(adev->dev, + "Failed to load gpu_info firmware \"%s\"\n", + fw_name); + goto out; + } + err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); + if (err) { + dev_err(adev->dev, + "Failed to validate gpu_info firmware \"%s\"\n", + fw_name); + goto out; + } + + hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; + amdgpu_ucode_print_gpu_info_hdr(&hdr->header); + + switch (hdr->version_major) { + case 1: + { + const struct gpu_info_firmware_v1_0 *gpu_info_fw = + (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); + adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); + adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); + adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); + adev->gfx.config.max_texture_channel_caches = + le32_to_cpu(gpu_info_fw->gc_num_tccs); + adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); + adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); + adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); + adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); + adev->gfx.config.double_offchip_lds_buf = + le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); + adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); + adev->gfx.cu_info.max_waves_per_simd = + le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); + adev->gfx.cu_info.max_scratch_slots_per_cu = + le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); + adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); + break; + } + default: + dev_err(adev->dev, + "Unsupported gpu_info table %d\n", hdr->header.ucode_version); + err = -EINVAL; + goto out; + } +out: + return err; +} + static int amdgpu_early_init(struct amdgpu_device *adev) { int i, r; @@ -1440,8 +1551,12 @@ static int amdgpu_early_init(struct amdgpu_device *adev) return r; break; #endif - case CHIP_VEGA10: - adev->family = AMDGPU_FAMILY_AI; + case CHIP_VEGA10: + case CHIP_RAVEN: + if (adev->asic_type == CHIP_RAVEN) + adev->family = AMDGPU_FAMILY_RV; + else + adev->family = AMDGPU_FAMILY_AI; r = soc15_set_ip_blocks(adev); if (r) @@ -1452,6 +1567,10 @@ static int amdgpu_early_init(struct amdgpu_device *adev) return -EINVAL; } + r = amdgpu_device_parse_gpu_info_fw(adev); + if (r) + return r; + if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_request_full_gpu(adev, true); if (r) @@ -1460,7 +1579,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) for (i = 0; i < adev->num_ip_blocks; i++) { if ((amdgpu_ip_block_mask & (1 << i)) == 0) { - DRM_ERROR("disabled ip block: %d\n", i); + DRM_ERROR("disabled ip block: %d <%s>\n", + i, adev->ip_blocks[i].version->funcs->name); adev->ip_blocks[i].status.valid = false; } else { if (adev->ip_blocks[i].version->funcs->early_init) { @@ -1548,22 +1668,24 @@ static int amdgpu_init(struct amdgpu_device *adev) return 0; } -static int amdgpu_late_init(struct amdgpu_device *adev) +static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) +{ + memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); +} + +static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) +{ + return !!memcmp(adev->gart.ptr, adev->reset_magic, + AMDGPU_RESET_MAGIC_NUM); +} + +static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) { int i = 0, r; for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].version->funcs->late_init) { - r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); - if (r) { - DRM_ERROR("late_init of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - return r; - } - adev->ip_blocks[i].status.late_initialized = true; - } /* skip CG for VCE/UVD, it's handled specially */ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { @@ -1577,6 +1699,31 @@ static int amdgpu_late_init(struct amdgpu_device *adev) } } } + return 0; +} + +static int amdgpu_late_init(struct amdgpu_device *adev) +{ + int i = 0, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (adev->ip_blocks[i].version->funcs->late_init) { + r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); + if (r) { + DRM_ERROR("late_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } + adev->ip_blocks[i].status.late_initialized = true; + } + } + + mod_delayed_work(system_wq, &adev->late_init_work, + msecs_to_jiffies(AMDGPU_RESUME_MS)); + + amdgpu_fill_reset_magic(adev); return 0; } @@ -1668,6 +1815,13 @@ static int amdgpu_fini(struct amdgpu_device *adev) return 0; } +static void amdgpu_late_init_func_handler(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, late_init_work.work); + amdgpu_late_set_cg_state(adev); +} + int amdgpu_suspend(struct amdgpu_device *adev) { int i, r; @@ -1713,19 +1867,25 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) { int i, r; - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; + static enum amd_ip_block_type ip_order[] = { + AMD_IP_BLOCK_TYPE_GMC, + AMD_IP_BLOCK_TYPE_COMMON, + AMD_IP_BLOCK_TYPE_IH, + }; - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) - r = adev->ip_blocks[i].version->funcs->hw_init(adev); + for (i = 0; i < ARRAY_SIZE(ip_order); i++) { + int j; + struct amdgpu_ip_block *block; - if (r) { - DRM_ERROR("resume of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - return r; + for (j = 0; j < adev->num_ip_blocks; j++) { + block = &adev->ip_blocks[j]; + + if (block->version->type != ip_order[i] || + !block->status.valid) + continue; + + r = block->version->funcs->hw_init(adev); + DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); } } @@ -1736,33 +1896,67 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) { int i, r; + static enum amd_ip_block_type ip_order[] = { + AMD_IP_BLOCK_TYPE_SMC, + AMD_IP_BLOCK_TYPE_DCE, + AMD_IP_BLOCK_TYPE_GFX, + AMD_IP_BLOCK_TYPE_SDMA, + AMD_IP_BLOCK_TYPE_VCE, + }; + + for (i = 0; i < ARRAY_SIZE(ip_order); i++) { + int j; + struct amdgpu_ip_block *block; + + for (j = 0; j < adev->num_ip_blocks; j++) { + block = &adev->ip_blocks[j]; + + if (block->version->type != ip_order[i] || + !block->status.valid) + continue; + + r = block->version->funcs->hw_init(adev); + DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); + } + } + + return 0; +} + +static int amdgpu_resume_phase1(struct amdgpu_device *adev) +{ + int i, r; + for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) - continue; - - r = adev->ip_blocks[i].version->funcs->hw_init(adev); - if (r) { - DRM_ERROR("resume of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - return r; + adev->ip_blocks[i].version->type == + AMD_IP_BLOCK_TYPE_IH) { + r = adev->ip_blocks[i].version->funcs->resume(adev); + if (r) { + DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } } } return 0; } -static int amdgpu_resume(struct amdgpu_device *adev) +static int amdgpu_resume_phase2(struct amdgpu_device *adev) { int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) + continue; r = adev->ip_blocks[i].version->funcs->resume(adev); if (r) { DRM_ERROR("resume of IP block <%s> failed %d\n", @@ -1774,6 +1968,18 @@ static int amdgpu_resume(struct amdgpu_device *adev) return 0; } +static int amdgpu_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_resume_phase1(adev); + if (r) + return r; + r = amdgpu_resume_phase2(adev); + + return r; +} + static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) { if (adev->is_atom_fw) { @@ -1856,8 +2062,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_check_arguments(adev); - /* Registers mapping */ - /* TODO: block userspace mapping of io register */ spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->smc_idx_lock); spin_lock_init(&adev->pcie_idx_lock); @@ -1873,6 +2077,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->gtt_list); spin_lock_init(&adev->gtt_list_lock); + INIT_LIST_HEAD(&adev->ring_lru_list); + spin_lock_init(&adev->ring_lru_list_lock); + + INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); + + /* Registers mapping */ + /* TODO: block userspace mapping of io register */ if (adev->asic_type >= CHIP_BONAIRE) { adev->rmmio_base = pci_resource_start(adev->pdev, 5); adev->rmmio_size = pci_resource_len(adev->pdev, 5); @@ -1985,6 +2196,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->accel_working = true; + amdgpu_vm_check_compute_bug(adev); + /* Initialize the buffer migration limit. */ if (amdgpu_moverate >= 0) max_MBps = amdgpu_moverate; @@ -2013,6 +2226,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) DRM_ERROR("registering register debugfs failed (%d).\n", r); + r = amdgpu_debugfs_test_ib_ring_init(adev); + if (r) + DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); + r = amdgpu_debugfs_firmware_init(adev); if (r) DRM_ERROR("registering firmware debugfs failed (%d).\n", r); @@ -2069,7 +2286,12 @@ void amdgpu_device_fini(struct amdgpu_device *adev) amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); r = amdgpu_fini(adev); + if (adev->firmware.gpu_info_fw) { + release_firmware(adev->firmware.gpu_info_fw); + adev->firmware.gpu_info_fw = NULL; + } adev->accel_working = false; + cancel_delayed_work_sync(&adev->late_init_work); /* free i2c buses */ amdgpu_i2c_fini(adev); amdgpu_atombios_fini(adev); @@ -2454,16 +2676,15 @@ err: * amdgpu_sriov_gpu_reset - reset the asic * * @adev: amdgpu device pointer - * @voluntary: if this reset is requested by guest. - * (true means by guest and false means by HYPERVISOR ) + * @job: which job trigger hang * * Attempt the reset the GPU if it has hung (all asics). * for SRIOV case. * Returns 0 for success or an error on failure. */ -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) +int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) { - int i, r = 0; + int i, j, r = 0; int resched; struct amdgpu_bo *bo, *tmp; struct amdgpu_ring *ring; @@ -2476,22 +2697,39 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); - /* block scheduler */ - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - ring = adev->rings[i]; + /* we start from the ring trigger GPU hang */ + j = job ? job->ring->idx : 0; + /* block scheduler */ + for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { + ring = adev->rings[i % AMDGPU_MAX_RINGS]; if (!ring || !ring->sched.thread) continue; kthread_park(ring->sched.thread); + + if (job && j != i) + continue; + + /* here give the last chance to check if job removed from mirror-list + * since we already pay some time on kthread_park */ + if (job && list_empty(&job->base.node)) { + kthread_unpark(ring->sched.thread); + goto give_up_reset; + } + + if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) + amd_sched_job_kickout(&job->base); + + /* only do job_reset on the hang ring if @job not NULL */ amd_sched_hw_job_reset(&ring->sched); - } - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(adev); + /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ + amdgpu_fence_driver_force_completion_ring(ring); + } /* request to take full control of GPU before re-initialization */ - if (voluntary) + if (job) amdgpu_virt_reset_gpu(adev); else amdgpu_virt_request_full_gpu(adev, true); @@ -2541,20 +2779,28 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) } dma_fence_put(fence); - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_ring *ring = adev->rings[i]; + for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { + ring = adev->rings[i % AMDGPU_MAX_RINGS]; if (!ring || !ring->sched.thread) continue; + if (job && j != i) { + kthread_unpark(ring->sched.thread); + continue; + } + amd_sched_job_recovery(&ring->sched); kthread_unpark(ring->sched.thread); } drm_helper_resume_force_mode(adev->ddev); +give_up_reset: ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); if (r) { /* bad news, how to tell it to userspace ? */ dev_info(adev->dev, "GPU reset failed\n"); + } else { + dev_info(adev->dev, "GPU reset successed!\n"); } adev->gfx.in_reset = false; @@ -2574,10 +2820,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) { int i, r; int resched; - bool need_full_reset; - - if (amdgpu_sriov_vf(adev)) - return amdgpu_sriov_gpu_reset(adev, true); + bool need_full_reset, vram_lost = false; if (!amdgpu_check_soft_reset(adev)) { DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); @@ -2637,16 +2880,27 @@ retry: if (!r) { dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); - r = amdgpu_resume(adev); + r = amdgpu_resume_phase1(adev); + if (r) + goto out; + vram_lost = amdgpu_check_vram_lost(adev); + if (vram_lost) { + DRM_ERROR("VRAM is lost!\n"); + atomic_inc(&adev->vram_lost_counter); + } + r = amdgpu_ttm_recover_gart(adev); + if (r) + goto out; + r = amdgpu_resume_phase2(adev); + if (r) + goto out; + if (vram_lost) + amdgpu_fill_reset_magic(adev); } } +out: if (!r) { amdgpu_irq_gpu_reset_resume_helper(adev); - if (need_full_reset && amdgpu_need_backup(adev)) { - r = amdgpu_ttm_recover_gart(adev); - if (r) - DRM_ERROR("gart recovery failed!!!\n"); - } r = amdgpu_ib_ring_tests(adev); if (r) { dev_err(adev->dev, "ib ring test failed (%d).\n", r); @@ -2708,10 +2962,11 @@ retry: drm_helper_resume_force_mode(adev->ddev); ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); - if (r) { + if (r) /* bad news, how to tell it to userspace ? */ dev_info(adev->dev, "GPU reset failed\n"); - } + else + dev_info(adev->dev, "GPU reset successed!\n"); return r; } @@ -3495,11 +3750,60 @@ static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) } } +static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + int r = 0, i; + + /* hold on the scheduler */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + kthread_park(ring->sched.thread); + } + + seq_printf(m, "run ib test:\n"); + r = amdgpu_ib_ring_tests(adev); + if (r) + seq_printf(m, "ib ring tests failed (%d).\n", r); + else + seq_printf(m, "ib ring tests passed.\n"); + + /* go on the scheduler */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + kthread_unpark(ring->sched.thread); + } + + return 0; +} + +static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { + {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} +}; + +static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) +{ + return amdgpu_debugfs_add_files(adev, + amdgpu_debugfs_test_ib_ring_list, 1); +} + int amdgpu_debugfs_init(struct drm_minor *minor) { return 0; } #else +static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) +{ + return 0; +} static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) { return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 38e9b0d3659a..1cb52fd19060 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -22,7 +22,7 @@ * Authors: Alex Deucher */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_i2c.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ab6b0d0febab..b59f37c83fa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -39,7 +39,7 @@ #include <linux/module.h> #include <linux/pm_runtime.h> #include <linux/vga_switcheroo.h> -#include "drm_crtc_helper.h" +#include <drm/drm_crtc_helper.h> #include "amdgpu.h" #include "amdgpu_irq.h" @@ -65,9 +65,12 @@ * - 3.13.0 - Add PRT support * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality * - 3.15.0 - Export more gpu info for gfx9 + * - 3.16.0 - Add reserved vmid support + * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. + * - 3.18.0 - Export gpu always on cu bitmap */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 15 +#define KMS_DRIVER_MINOR 18 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; @@ -92,7 +95,8 @@ int amdgpu_vm_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; -int amdgpu_vram_page_split = 1024; +int amdgpu_vram_page_split = 512; +int amdgpu_vm_update_mode = -1; int amdgpu_exp_hw_support = 0; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; @@ -110,6 +114,8 @@ int amdgpu_prim_buf_per_se = 0; int amdgpu_pos_buf_per_se = 0; int amdgpu_cntl_sb_buf_per_se = 0; int amdgpu_param_buf_per_se = 0; +int amdgpu_job_hang_limit = 0; +int amdgpu_lbpw = -1; MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -177,6 +183,9 @@ module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); +MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); +module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); + MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); @@ -232,6 +241,38 @@ module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); +MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); +module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); + +MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); +module_param_named(lbpw, amdgpu_lbpw, int, 0444); + +#ifdef CONFIG_DRM_AMDGPU_SI + +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) +int amdgpu_si_support = 0; +MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); +#else +int amdgpu_si_support = 1; +MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); +#endif + +module_param_named(si_support, amdgpu_si_support, int, 0444); +#endif + +#ifdef CONFIG_DRM_AMDGPU_CIK + +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) +int amdgpu_cik_support = 0; +MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); +#else +int amdgpu_cik_support = 1; +MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); +#endif + +module_param_named(cik_support, amdgpu_cik_support, int, 0444); +#endif + static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_SI @@ -461,6 +502,9 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + /* Raven */ + {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, + {0, 0, 0} }; @@ -492,6 +536,7 @@ static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) static int amdgpu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { + struct drm_device *dev; unsigned long flags = ent->driver_data; int ret; @@ -514,7 +559,29 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, if (ret) return ret; - return drm_get_pci_dev(pdev, ent, &kms_driver); + dev = drm_dev_alloc(&kms_driver, &pdev->dev); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + ret = pci_enable_device(pdev); + if (ret) + goto err_free; + + dev->pdev = pdev; + + pci_set_drvdata(pdev, dev); + + ret = drm_dev_register(dev, ent->driver_data); + if (ret) + goto err_pci; + + return 0; + +err_pci: + pci_disable_device(pdev); +err_free: + drm_dev_unref(dev); + return ret; } static void @@ -522,7 +589,8 @@ amdgpu_pci_remove(struct pci_dev *pdev) { struct drm_device *dev = pci_get_drvdata(pdev); - drm_put_dev(dev); + drm_dev_unregister(dev); + drm_dev_unref(dev); } static void @@ -716,11 +784,21 @@ static const struct file_operations amdgpu_driver_kms_fops = { #endif }; +static bool +amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, + stime, etime, mode); +} + static struct drm_driver kms_driver = { .driver_features = DRIVER_USE_AGP | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | - DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, + DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, .load = amdgpu_driver_load_kms, .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, @@ -730,8 +808,8 @@ static struct drm_driver kms_driver = { .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, - .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, - .get_scanout_position = amdgpu_get_crtc_scanoutpos, + .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, + .get_scanout_position = amdgpu_get_crtc_scanout_position, #if defined(CONFIG_DEBUG_FS) .debugfs_init = amdgpu_debugfs_init, #endif @@ -808,7 +886,7 @@ static int __init amdgpu_init(void) driver->num_ioctls = amdgpu_max_kms_ioctl; amdgpu_register_atpx_handler(); /* let modprobe override vga console setting */ - return drm_pci_init(driver, pdriver); + return pci_register_driver(pdriver); error_sched: amdgpu_fence_slab_fini(); @@ -823,7 +901,7 @@ error_sync: static void __exit amdgpu_exit(void) { amdgpu_amdkfd_fini(); - drm_pci_exit(driver, pdriver); + pci_unregister_driver(pdriver); amdgpu_unregister_atpx_handler(); amdgpu_sync_fini(); amd_sched_fence_slab_fini(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 7b60fb79c3a6..333bad749067 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -541,6 +541,12 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) } } +void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring) +{ + if (ring) + amdgpu_fence_write(ring, ring->fence_drv.sync_seq); +} + /* * Common fence implementation */ @@ -660,11 +666,17 @@ static const struct drm_info_list amdgpu_debugfs_fence_list[] = { {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} }; + +static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { + {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, +}; #endif int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) + if (amdgpu_sriov_vf(adev)) + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); #else return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 902e6015abca..a57abc1a25fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -224,8 +224,9 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) * * Unbinds the requested pages from the gart page table and * replaces them with the dummy page (all asics). + * Returns 0 for success, -EINVAL for failure. */ -void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, +int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int pages) { unsigned t; @@ -237,7 +238,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, if (!adev->gart.ready) { WARN(1, "trying to unbind memory from uninitialized GART !\n"); - return; + return -EINVAL; } t = offset / AMDGPU_GPU_PAGE_SIZE; @@ -258,6 +259,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, } mb(); amdgpu_gart_flush_gpu_tlb(adev, 0); + return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 94cb91cf93eb..621f739103a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -219,16 +219,6 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, ttm_eu_backoff_reservation(&ticket, &list); } -static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) -{ - if (r == -EDEADLK) { - r = amdgpu_gpu_reset(adev); - if (!r) - r = -EAGAIN; - } - return r; -} - /* * GEM ioctls. */ @@ -249,20 +239,17 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_CREATE_CPU_GTT_USWC | AMDGPU_GEM_CREATE_VRAM_CLEARED| AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) { - r = -EINVAL; - goto error_unlock; - } + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) + return -EINVAL; + /* reject invalid gem domains */ if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | - AMDGPU_GEM_DOMAIN_OA)) { - r = -EINVAL; - goto error_unlock; - } + AMDGPU_GEM_DOMAIN_OA)) + return -EINVAL; /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | @@ -274,10 +261,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, size = size << AMDGPU_GWS_SHIFT; else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) size = size << AMDGPU_OA_SHIFT; - else { - r = -EINVAL; - goto error_unlock; - } + else + return -EINVAL; } size = roundup(size, PAGE_SIZE); @@ -286,21 +271,17 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, args->in.domain_flags, kernel, &gobj); if (r) - goto error_unlock; + return r; r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ drm_gem_object_unreference_unlocked(gobj); if (r) - goto error_unlock; + return r; memset(args, 0, sizeof(*args)); args->out.handle = handle; return 0; - -error_unlock: - r = amdgpu_gem_handle_lockup(adev, r); - return r; } int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, @@ -334,7 +315,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_DOMAIN_CPU, 0, 0, &gobj); if (r) - goto handle_lockup; + return r; bo = gem_to_amdgpu_bo(gobj); bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT; @@ -374,7 +355,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, /* drop reference from allocate - handle holds it now */ drm_gem_object_unreference_unlocked(gobj); if (r) - goto handle_lockup; + return r; args->handle = handle; return 0; @@ -388,9 +369,6 @@ unlock_mmap_sem: release_object: drm_gem_object_unreference_unlocked(gobj); -handle_lockup: - r = amdgpu_gem_handle_lockup(adev, r); - return r; } @@ -456,7 +434,6 @@ unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { - struct amdgpu_device *adev = dev->dev_private; union drm_amdgpu_gem_wait_idle *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; @@ -484,7 +461,6 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, r = ret; drm_gem_object_unreference_unlocked(gobj); - r = amdgpu_gem_handle_lockup(adev, r); return r; } @@ -593,9 +569,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, uint64_t va_flags; int r = 0; - if (!adev->vm_manager.enabled) - return -ENOTTY; - if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { dev_err(&dev->pdev->dev, "va_address 0x%lX is in reserved area 0x%X\n", @@ -621,6 +594,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->operation); return -EINVAL; } + if ((args->operation == AMDGPU_VA_OP_MAP) || + (args->operation == AMDGPU_VA_OP_REPLACE)) { + if (amdgpu_kms_vram_lost(adev, fpriv)) + return -ENODEV; + } INIT_LIST_HEAD(&list); if ((args->operation != AMDGPU_VA_OP_CLEAR) && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 19943356cca7..e26108aad3fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -108,3 +108,209 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s p = next + 1; } } + +void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) +{ + int i, queue, pipe, mec; + + /* policy for amdgpu compute queue ownership */ + for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { + queue = i % adev->gfx.mec.num_queue_per_pipe; + pipe = (i / adev->gfx.mec.num_queue_per_pipe) + % adev->gfx.mec.num_pipe_per_mec; + mec = (i / adev->gfx.mec.num_queue_per_pipe) + / adev->gfx.mec.num_pipe_per_mec; + + /* we've run out of HW */ + if (mec >= adev->gfx.mec.num_mec) + break; + + if (adev->gfx.mec.num_mec > 1) { + /* policy: amdgpu owns the first two queues of the first MEC */ + if (mec == 0 && queue < 2) + set_bit(i, adev->gfx.mec.queue_bitmap); + } else { + /* policy: amdgpu owns all queues in the first pipe */ + if (mec == 0 && pipe == 0) + set_bit(i, adev->gfx.mec.queue_bitmap); + } + } + + /* update the number of active compute rings */ + adev->gfx.num_compute_rings = + bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + + /* If you hit this case and edited the policy, you probably just + * need to increase AMDGPU_MAX_COMPUTE_RINGS */ + if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) + adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; +} + +static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, + struct amdgpu_ring *ring) +{ + int queue_bit; + int mec, pipe, queue; + + queue_bit = adev->gfx.mec.num_mec + * adev->gfx.mec.num_pipe_per_mec + * adev->gfx.mec.num_queue_per_pipe; + + while (queue_bit-- >= 0) { + if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) + continue; + + amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue); + + /* Using pipes 2/3 from MEC 2 seems cause problems */ + if (mec == 1 && pipe > 1) + continue; + + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + return 0; + } + + dev_err(adev->dev, "Failed to find a queue for KIQ\n"); + return -EINVAL; +} + +int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + int r = 0; + + mutex_init(&kiq->ring_mutex); + + r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); + if (r) + return r; + + ring->adev = NULL; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_KIQ; + + r = amdgpu_gfx_kiq_acquire(adev, ring); + if (r) + return r; + + ring->eop_gpu_addr = kiq->eop_gpu_addr; + sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); + r = amdgpu_ring_init(adev, ring, 1024, + irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); + if (r) + dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); + + return r; +} + +void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq) +{ + amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); + amdgpu_ring_fini(ring); +} + +void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + + amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); +} + +int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, + unsigned hpd_size) +{ + int r; + u32 *hpd; + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + + r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, + &kiq->eop_gpu_addr, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); + return r; + } + + memset(hpd, 0, hpd_size); + + r = amdgpu_bo_reserve(kiq->eop_obj, true); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); + amdgpu_bo_kunmap(kiq->eop_obj); + amdgpu_bo_unreserve(kiq->eop_obj); + + return 0; +} + +/* create MQD for each compute queue */ +int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, + unsigned mqd_size) +{ + struct amdgpu_ring *ring = NULL; + int r, i; + + /* create MQD for KIQ */ + ring = &adev->gfx.kiq.ring; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, &ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /* prepare MQD backup */ + adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); + if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) + dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); + } + + /* create MQD for each KCQ */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, &ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /* prepare MQD backup */ + adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); + if (!adev->gfx.mec.mqd_backup[i]) + dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); + } + } + + return 0; +} + +void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int i; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + kfree(adev->gfx.mec.mqd_backup[i]); + amdgpu_bo_free_kernel(&ring->mqd_obj, + &ring->mqd_gpu_addr, + &ring->mqd_ptr); + } + + ring = &adev->gfx.kiq.ring; + kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); + amdgpu_bo_free_kernel(&ring->mqd_obj, + &ring->mqd_gpu_addr, + &ring->mqd_ptr); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index e02044086445..1f279050d334 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -30,4 +30,64 @@ void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh); +void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); + +int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq); + +void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq); + +void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); +int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, + unsigned hpd_size); + +int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, + unsigned mqd_size); +void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev); + +/** + * amdgpu_gfx_create_bitmask - create a bitmask + * + * @bit_width: length of the mask + * + * create a variable length bit mask. + * Returns the bitmask. + */ +static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) +{ + return (u32)((1ULL << bit_width) - 1); +} + +static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, + int mec, int pipe, int queue) +{ + int bit = 0; + + bit += mec * adev->gfx.mec.num_pipe_per_mec + * adev->gfx.mec.num_queue_per_pipe; + bit += pipe * adev->gfx.mec.num_queue_per_pipe; + bit += queue; + + return bit; +} + +static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit, + int *mec, int *pipe, int *queue) +{ + *queue = bit % adev->gfx.mec.num_queue_per_pipe; + *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) + % adev->gfx.mec.num_pipe_per_mec; + *mec = (bit / adev->gfx.mec.num_queue_per_pipe) + / adev->gfx.mec.num_pipe_per_mec; + +} +static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, + int mec, int pipe, int queue) +{ + return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue), + adev->gfx.mec.queue_bitmap); +} + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 6e4ae0d983c2..f774b3f497d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -121,6 +121,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib *ib = &ibs[0]; + struct dma_fence *tmp = NULL; bool skip_preamble, need_ctx_switch; unsigned patch_offset = ~0; struct amdgpu_vm *vm; @@ -160,8 +161,16 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, dev_err(adev->dev, "scheduling IB failed (%d).\n", r); return r; } - if (ring->funcs->emit_pipeline_sync && job && job->need_pipeline_sync) + + if (ring->funcs->emit_pipeline_sync && job && + ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || + amdgpu_vm_need_pipeline_sync(ring, job))) { amdgpu_ring_emit_pipeline_sync(ring); + dma_fence_put(tmp); + } + + if (ring->funcs->insert_start) + ring->funcs->insert_start(ring); if (vm) { r = amdgpu_vm_flush(ring, job); @@ -188,8 +197,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, status |= AMDGPU_HAVE_CTX_SWITCH; status |= job->preamble_status; - if (vm) - status |= AMDGPU_VM_DOMAIN; amdgpu_ring_emit_cntxcntl(ring, status); } @@ -208,6 +215,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, need_ctx_switch = false; } + if (ring->funcs->emit_tmz) + amdgpu_ring_emit_tmz(ring, false); + if (ring->funcs->emit_hdp_invalidate #ifdef CONFIG_X86_64 && !(adev->flags & AMD_IS_APU) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index a3da1a122fc8..3de8e74e5b3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -62,8 +62,9 @@ enum amdgpu_ih_clientid AMDGPU_IH_CLIENTID_MP0 = 0x1e, AMDGPU_IH_CLIENTID_MP1 = 0x1f, - AMDGPU_IH_CLIENTID_MAX + AMDGPU_IH_CLIENTID_MAX, + AMDGPU_IH_CLIENTID_VCN = AMDGPU_IH_CLIENTID_UVD }; #define AMDGPU_IH_CLIENTID_LEGACY 0 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index a6b7e367a860..62da6c5c6095 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -83,7 +83,8 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) struct amdgpu_device *adev = container_of(work, struct amdgpu_device, reset_work); - amdgpu_gpu_reset(adev); + if (!amdgpu_sriov_vf(adev)) + amdgpu_gpu_reset(adev); } /* Disable *all* interrupts */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 7570f2439a11..3d641e10e6b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -36,7 +36,11 @@ static void amdgpu_job_timedout(struct amd_sched_job *s_job) job->base.sched->name, atomic_read(&job->ring->fence_drv.last_seq), job->ring->fence_drv.sync_seq); - amdgpu_gpu_reset(job->adev); + + if (amdgpu_sriov_vf(job->adev)) + amdgpu_sriov_gpu_reset(job->adev, job); + else + amdgpu_gpu_reset(job->adev); } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, @@ -57,9 +61,10 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, (*job)->vm = vm; (*job)->ibs = (void *)&(*job)[1]; (*job)->num_ibs = num_ibs; - (*job)->need_pipeline_sync = false; amdgpu_sync_create(&(*job)->sync); + amdgpu_sync_create(&(*job)->dep_sync); + amdgpu_sync_create(&(*job)->sched_sync); return 0; } @@ -98,6 +103,8 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job) dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); + amdgpu_sync_free(&job->dep_sync); + amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -107,6 +114,8 @@ void amdgpu_job_free(struct amdgpu_job *job) dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); + amdgpu_sync_free(&job->dep_sync); + amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -138,11 +147,18 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; - struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync); + struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync); + int r; + if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) { + r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence); + if (r) + DRM_ERROR("Error adding fence to sync (%d)\n", r); + } + if (!fence) + fence = amdgpu_sync_get_fence(&job->sync); while (fence == NULL && vm && !job->vm_id) { struct amdgpu_ring *ring = job->ring; - int r; r = amdgpu_vm_grab_id(vm, ring, &job->sync, &job->base.s_fence->finished, @@ -153,9 +169,6 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) fence = amdgpu_sync_get_fence(&job->sync); } - if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) - job->need_pipeline_sync = true; - return fence; } @@ -163,6 +176,7 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) { struct dma_fence *fence = NULL; struct amdgpu_job *job; + struct amdgpu_fpriv *fpriv = NULL; int r; if (!sched_job) { @@ -174,10 +188,16 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); trace_amdgpu_sched_run_job(job); - r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence); - if (r) - DRM_ERROR("Error scheduling IBs (%d)\n", r); - + if (job->vm) + fpriv = container_of(job->vm, struct amdgpu_fpriv, vm); + /* skip ib schedule when vram is lost */ + if (fpriv && amdgpu_kms_vram_lost(job->adev, fpriv)) + DRM_ERROR("Skip scheduling IBs!\n"); + else { + r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence); + if (r) + DRM_ERROR("Error scheduling IBs (%d)\n", r); + } /* if gpu reset, hw fence will be replaced here */ dma_fence_put(job->fence); job->fence = dma_fence_get(fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 96c341670782..b0b23101d1c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -87,6 +87,41 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) struct amdgpu_device *adev; int r, acpi_status; +#ifdef CONFIG_DRM_AMDGPU_SI + if (!amdgpu_si_support) { + switch (flags & AMD_ASIC_MASK) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + case CHIP_HAINAN: + dev_info(dev->dev, + "SI support provided by radeon.\n"); + dev_info(dev->dev, + "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" + ); + return -ENODEV; + } + } +#endif +#ifdef CONFIG_DRM_AMDGPU_CIK + if (!amdgpu_cik_support) { + switch (flags & AMD_ASIC_MASK) { + case CHIP_KAVERI: + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KABINI: + case CHIP_MULLINS: + dev_info(dev->dev, + "CIK support provided by radeon.\n"); + dev_info(dev->dev, + "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" + ); + return -ENODEV; + } + } +#endif + adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); if (adev == NULL) { return -ENOMEM; @@ -235,6 +270,7 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_amdgpu_info *info = data; struct amdgpu_mode_info *minfo = &adev->mode_info; void __user *out = (void __user *)(uintptr_t)info->return_pointer; @@ -247,6 +283,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file if (!info->return_size || !info->return_pointer) return -EINVAL; + if (amdgpu_kms_vram_lost(adev, fpriv)) + return -ENODEV; switch (info->query) { case AMDGPU_INFO_ACCEL_WORKING: @@ -319,6 +357,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ib_size_alignment = 1; break; + case AMDGPU_HW_IP_VCN_DEC: + type = AMD_IP_BLOCK_TYPE_VCN; + ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 16; + break; + case AMDGPU_HW_IP_VCN_ENC: + type = AMD_IP_BLOCK_TYPE_VCN; + for (i = 0; i < adev->vcn.num_enc_rings; i++) + ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 1; + break; default: return -EINVAL; } @@ -361,6 +412,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file case AMDGPU_HW_IP_UVD_ENC: type = AMD_IP_BLOCK_TYPE_UVD; break; + case AMDGPU_HW_IP_VCN_DEC: + case AMDGPU_HW_IP_VCN_ENC: + type = AMD_IP_BLOCK_TYPE_VCN; + break; default: return -EINVAL; } @@ -397,6 +452,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file case AMDGPU_INFO_NUM_EVICTIONS: ui64 = atomic64_read(&adev->num_evictions); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: + ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VRAM_USAGE: ui64 = atomic64_read(&adev->vram_usage); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; @@ -536,6 +594,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.cu_active_number = adev->gfx.cu_info.number; dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; dev_info.ce_ram_size = adev->gfx.ce_ram_size; + memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], + sizeof(adev->gfx.cu_info.ao_cu_bitmap)); memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], sizeof(adev->gfx.cu_info.bitmap)); dev_info.vram_type = adev->mc.vram_type; @@ -730,6 +790,12 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev) vga_switcheroo_process_delayed_switch(); } +bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv) +{ + return fpriv->vram_lost_counter != atomic_read(&adev->vram_lost_counter); +} + /** * amdgpu_driver_open_kms - drm callback for open * @@ -757,7 +823,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto out_suspend; } - r = amdgpu_vm_init(adev, &fpriv->vm); + r = amdgpu_vm_init(adev, &fpriv->vm, + AMDGPU_VM_CONTEXT_GFX); if (r) { kfree(fpriv); goto out_suspend; @@ -782,6 +849,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); + fpriv->vram_lost_counter = atomic_read(&adev->vram_lost_counter); file_priv->driver_priv = fpriv; out_suspend: @@ -814,8 +882,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); - amdgpu_uvd_free_handles(adev, file_priv); - amdgpu_vce_free_handles(adev, file_priv); + if (adev->asic_type != CHIP_RAVEN) { + amdgpu_uvd_free_handles(adev, file_priv); + amdgpu_vce_free_handles(adev, file_priv); + } amdgpu_vm_bo_rmv(adev, fpriv->prt_va); @@ -945,50 +1015,10 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) amdgpu_irq_put(adev, &adev->crtc_irq, idx); } -/** - * amdgpu_get_vblank_timestamp_kms - get vblank timestamp - * - * @dev: drm dev pointer - * @crtc: crtc to get the timestamp for - * @max_error: max error - * @vblank_time: time value - * @flags: flags passed to the driver - * - * Gets the timestamp on the requested crtc based on the - * scanout position. (all asics). - * Returns postive status flags on success, negative error on failure. - */ -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags) -{ - struct drm_crtc *crtc; - struct amdgpu_device *adev = dev->dev_private; - - if (pipe >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %u\n", pipe); - return -EINVAL; - } - - /* Get associated drm_crtc: */ - crtc = &adev->mode_info.crtcs[pipe]->base; - if (!crtc) { - /* This can occur on driver load if some component fails to - * initialize completely and driver is unloaded */ - DRM_ERROR("Uninitialized crtc %d\n", pipe); - return -EINVAL; - } - - /* Helper routine in DRM core does all the work: */ - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - &crtc->hwmode); -} - const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), /* KMS */ DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index dbd10618ec20..43a9d3aec6c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -534,6 +534,9 @@ struct amdgpu_framebuffer { ((em) == ATOM_ENCODER_MODE_DP_MST)) /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ +#define DRM_SCANOUTPOS_VALID (1 << 0) +#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) +#define DRM_SCANOUTPOS_ACCURATE (1 << 2) #define USE_REAL_VBLANKSTART (1 << 30) #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 365883d7948d..8ee69652be8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -960,6 +960,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) return -EINVAL; /* hurrah the memory is not visible ! */ + atomic64_inc(&adev->num_vram_cpu_page_faults); amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; for (i = 0; i < abo->placement.num_placement; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index f5ae871aa11c..b7e1c026c0c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -72,6 +72,7 @@ static int amdgpu_pp_early_init(void *handle) case CHIP_CARRIZO: case CHIP_STONEY: case CHIP_VEGA10: + case CHIP_RAVEN: adev->pp_enabled = true; if (amdgpu_create_pp_handle(adev)) return -EINVAL; @@ -187,6 +188,9 @@ static int amdgpu_pp_hw_fini(void *handle) int ret = 0; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->pp_enabled && adev->pm.dpm_enabled) + amdgpu_pm_sysfs_fini(adev); + if (adev->powerplay.ip_funcs->hw_fini) ret = adev->powerplay.ip_funcs->hw_fini( adev->powerplay.pp_handle); @@ -205,10 +209,9 @@ static void amdgpu_pp_late_fini(void *handle) adev->powerplay.ip_funcs->late_fini( adev->powerplay.pp_handle); - if (adev->pp_enabled && adev->pm.dpm_enabled) - amdgpu_pm_sysfs_fini(adev); - amd_powerplay_destroy(adev->powerplay.pp_handle); + if (adev->pp_enabled) + amd_powerplay_destroy(adev->powerplay.pp_handle); } static int amdgpu_pp_suspend(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index ac5e92e5d59d..4083be61b328 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -24,12 +24,13 @@ */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_psp.h" #include "amdgpu_ucode.h" #include "soc15_common.h" #include "psp_v3_1.h" +#include "psp_v10_0.h" static void psp_set_funcs(struct amdgpu_device *adev); @@ -61,6 +62,12 @@ static int psp_sw_init(void *handle) psp->compare_sram_data = psp_v3_1_compare_sram_data; psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; break; + case CHIP_RAVEN: + psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf; + psp->ring_init = psp_v10_0_ring_init; + psp->cmd_submit = psp_v10_0_cmd_submit; + psp->compare_sram_data = psp_v10_0_compare_sram_data; + break; default: return -EINVAL; } @@ -145,8 +152,8 @@ static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, uint64_t tmr_mc, uint32_t size) { cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; - cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc; - cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32); + cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); + cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); cmd->cmd.cmd_setup_tmr.buf_size = size; } @@ -230,6 +237,13 @@ static int psp_asd_load(struct psp_context *psp) int ret; struct psp_gfx_cmd_resp *cmd; + /* If PSP version doesn't match ASD version, asd loading will be failed. + * add workaround to bypass it for sriov now. + * TODO: add version check to make it common + */ + if (amdgpu_sriov_vf(psp->adev)) + return 0; + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); if (!cmd) return -ENOMEM; @@ -319,14 +333,11 @@ static int psp_load_fw(struct amdgpu_device *adev) { int ret; struct psp_context *psp = &adev->psp; - struct psp_gfx_cmd_resp *cmd; - cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); - if (!cmd) + psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); + if (!psp->cmd) return -ENOMEM; - psp->cmd = cmd; - ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, AMDGPU_GEM_DOMAIN_GTT, &psp->fw_pri_bo, @@ -365,8 +376,6 @@ static int psp_load_fw(struct amdgpu_device *adev) if (ret) goto failed_mem; - kfree(cmd); - return 0; failed_mem: @@ -376,7 +385,8 @@ failed_mem1: amdgpu_bo_free_kernel(&psp->fw_pri_bo, &psp->fw_pri_mc_addr, &psp->fw_pri_buf); failed: - kfree(cmd); + kfree(psp->cmd); + psp->cmd = NULL; return ret; } @@ -436,6 +446,9 @@ static int psp_hw_fini(void *handle) amdgpu_bo_free_kernel(&psp->fence_buf_bo, &psp->fence_buf_mc_addr, &psp->fence_buf); + kfree(psp->cmd); + psp->cmd = NULL; + return 0; } @@ -542,3 +555,12 @@ const struct amdgpu_ip_block_version psp_v3_1_ip_block = .rev = 0, .funcs = &psp_ip_funcs, }; + +const struct amdgpu_ip_block_version psp_v10_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_PSP, + .major = 10, + .minor = 0, + .rev = 0, + .funcs = &psp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 0301e4e0b297..1a1c8b469f93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -138,4 +138,6 @@ extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t field_val, uint32_t mask, bool check_changed); +extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c new file mode 100644 index 000000000000..befc09b68543 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c @@ -0,0 +1,299 @@ +/* + * Copyright 2017 Valve Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Andres Rodriguez + */ + +#include "amdgpu.h" +#include "amdgpu_ring.h" + +static int amdgpu_queue_mapper_init(struct amdgpu_queue_mapper *mapper, + int hw_ip) +{ + if (!mapper) + return -EINVAL; + + if (hw_ip > AMDGPU_MAX_IP_NUM) + return -EINVAL; + + mapper->hw_ip = hw_ip; + mutex_init(&mapper->lock); + + memset(mapper->queue_map, 0, sizeof(mapper->queue_map)); + + return 0; +} + +static struct amdgpu_ring *amdgpu_get_cached_map(struct amdgpu_queue_mapper *mapper, + int ring) +{ + return mapper->queue_map[ring]; +} + +static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper, + int ring, struct amdgpu_ring *pring) +{ + if (WARN_ON(mapper->queue_map[ring])) { + DRM_ERROR("Un-expected ring re-map\n"); + return -EINVAL; + } + + mapper->queue_map[ring] = pring; + + return 0; +} + +static int amdgpu_identity_map(struct amdgpu_device *adev, + struct amdgpu_queue_mapper *mapper, + int ring, + struct amdgpu_ring **out_ring) +{ + switch (mapper->hw_ip) { + case AMDGPU_HW_IP_GFX: + *out_ring = &adev->gfx.gfx_ring[ring]; + break; + case AMDGPU_HW_IP_COMPUTE: + *out_ring = &adev->gfx.compute_ring[ring]; + break; + case AMDGPU_HW_IP_DMA: + *out_ring = &adev->sdma.instance[ring].ring; + break; + case AMDGPU_HW_IP_UVD: + *out_ring = &adev->uvd.ring; + break; + case AMDGPU_HW_IP_VCE: + *out_ring = &adev->vce.ring[ring]; + break; + case AMDGPU_HW_IP_UVD_ENC: + *out_ring = &adev->uvd.ring_enc[ring]; + break; + case AMDGPU_HW_IP_VCN_DEC: + *out_ring = &adev->vcn.ring_dec; + break; + case AMDGPU_HW_IP_VCN_ENC: + *out_ring = &adev->vcn.ring_enc[ring]; + break; + default: + *out_ring = NULL; + DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip); + return -EINVAL; + } + + return amdgpu_update_cached_map(mapper, ring, *out_ring); +} + +static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip) +{ + switch (hw_ip) { + case AMDGPU_HW_IP_GFX: + return AMDGPU_RING_TYPE_GFX; + case AMDGPU_HW_IP_COMPUTE: + return AMDGPU_RING_TYPE_COMPUTE; + case AMDGPU_HW_IP_DMA: + return AMDGPU_RING_TYPE_SDMA; + case AMDGPU_HW_IP_UVD: + return AMDGPU_RING_TYPE_UVD; + case AMDGPU_HW_IP_VCE: + return AMDGPU_RING_TYPE_VCE; + default: + DRM_ERROR("Invalid HW IP specified %d\n", hw_ip); + return -1; + } +} + +static int amdgpu_lru_map(struct amdgpu_device *adev, + struct amdgpu_queue_mapper *mapper, + int user_ring, + struct amdgpu_ring **out_ring) +{ + int r, i, j; + int ring_type = amdgpu_hw_ip_to_ring_type(mapper->hw_ip); + int ring_blacklist[AMDGPU_MAX_RINGS]; + struct amdgpu_ring *ring; + + /* 0 is a valid ring index, so initialize to -1 */ + memset(ring_blacklist, 0xff, sizeof(ring_blacklist)); + + for (i = 0, j = 0; i < AMDGPU_MAX_RINGS; i++) { + ring = mapper->queue_map[i]; + if (ring) + ring_blacklist[j++] = ring->idx; + } + + r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist, + j, out_ring); + if (r) + return r; + + return amdgpu_update_cached_map(mapper, user_ring, *out_ring); +} + +/** + * amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct + * + * @adev: amdgpu_device pointer + * @mgr: amdgpu_queue_mgr structure holding queue information + * + * Initialize the the selected @mgr (all asics). + * + * Returns 0 on success, error on failure. + */ +int amdgpu_queue_mgr_init(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr) +{ + int i, r; + + if (!adev || !mgr) + return -EINVAL; + + memset(mgr, 0, sizeof(*mgr)); + + for (i = 0; i < AMDGPU_MAX_IP_NUM; ++i) { + r = amdgpu_queue_mapper_init(&mgr->mapper[i], i); + if (r) + return r; + } + + return 0; +} + +/** + * amdgpu_queue_mgr_fini - de-initialize an amdgpu_queue_mgr struct + * + * @adev: amdgpu_device pointer + * @mgr: amdgpu_queue_mgr structure holding queue information + * + * De-initialize the the selected @mgr (all asics). + * + * Returns 0 on success, error on failure. + */ +int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr) +{ + return 0; +} + +/** + * amdgpu_queue_mgr_map - Map a userspace ring id to an amdgpu_ring + * + * @adev: amdgpu_device pointer + * @mgr: amdgpu_queue_mgr structure holding queue information + * @hw_ip: HW IP enum + * @instance: HW instance + * @ring: user ring id + * @our_ring: pointer to mapped amdgpu_ring + * + * Map a userspace ring id to an appropriate kernel ring. Different + * policies are configurable at a HW IP level. + * + * Returns 0 on success, error on failure. + */ +int amdgpu_queue_mgr_map(struct amdgpu_device *adev, + struct amdgpu_queue_mgr *mgr, + int hw_ip, int instance, int ring, + struct amdgpu_ring **out_ring) +{ + int r, ip_num_rings; + struct amdgpu_queue_mapper *mapper = &mgr->mapper[hw_ip]; + + if (!adev || !mgr || !out_ring) + return -EINVAL; + + if (hw_ip >= AMDGPU_MAX_IP_NUM) + return -EINVAL; + + if (ring >= AMDGPU_MAX_RINGS) + return -EINVAL; + + /* Right now all IPs have only one instance - multiple rings. */ + if (instance != 0) { + DRM_ERROR("invalid ip instance: %d\n", instance); + return -EINVAL; + } + + switch (hw_ip) { + case AMDGPU_HW_IP_GFX: + ip_num_rings = adev->gfx.num_gfx_rings; + break; + case AMDGPU_HW_IP_COMPUTE: + ip_num_rings = adev->gfx.num_compute_rings; + break; + case AMDGPU_HW_IP_DMA: + ip_num_rings = adev->sdma.num_instances; + break; + case AMDGPU_HW_IP_UVD: + ip_num_rings = 1; + break; + case AMDGPU_HW_IP_VCE: + ip_num_rings = adev->vce.num_rings; + break; + case AMDGPU_HW_IP_UVD_ENC: + ip_num_rings = adev->uvd.num_enc_rings; + break; + case AMDGPU_HW_IP_VCN_DEC: + ip_num_rings = 1; + break; + case AMDGPU_HW_IP_VCN_ENC: + ip_num_rings = adev->vcn.num_enc_rings; + break; + default: + DRM_ERROR("unknown ip type: %d\n", hw_ip); + return -EINVAL; + } + + if (ring >= ip_num_rings) { + DRM_ERROR("Ring index:%d exceeds maximum:%d for ip:%d\n", + ring, ip_num_rings, hw_ip); + return -EINVAL; + } + + mutex_lock(&mapper->lock); + + *out_ring = amdgpu_get_cached_map(mapper, ring); + if (*out_ring) { + /* cache hit */ + r = 0; + goto out_unlock; + } + + switch (mapper->hw_ip) { + case AMDGPU_HW_IP_GFX: + case AMDGPU_HW_IP_UVD: + case AMDGPU_HW_IP_VCE: + case AMDGPU_HW_IP_UVD_ENC: + case AMDGPU_HW_IP_VCN_DEC: + case AMDGPU_HW_IP_VCN_ENC: + r = amdgpu_identity_map(adev, mapper, ring, out_ring); + break; + case AMDGPU_HW_IP_DMA: + case AMDGPU_HW_IP_COMPUTE: + r = amdgpu_lru_map(adev, mapper, ring, out_ring); + break; + default: + *out_ring = NULL; + r = -EINVAL; + DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip); + } + +out_unlock: + mutex_unlock(&mapper->lock); + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 6a85db0c0bc3..75165e07b1cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -135,6 +135,8 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) if (ring->funcs->end_use) ring->funcs->end_use(ring); + + amdgpu_ring_lru_touch(ring->adev, ring); } /** @@ -253,10 +255,13 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, } ring->max_dw = max_dw; + INIT_LIST_HEAD(&ring->lru_list); + amdgpu_ring_lru_touch(adev, ring); if (amdgpu_debugfs_ring_init(adev, ring)) { DRM_ERROR("Failed to register debugfs file for rings !\n"); } + return 0; } @@ -294,6 +299,84 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) ring->adev->rings[ring->idx] = NULL; } +static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev, + struct amdgpu_ring *ring) +{ + /* list_move_tail handles the case where ring isn't part of the list */ + list_move_tail(&ring->lru_list, &adev->ring_lru_list); +} + +static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring, + int *blacklist, int num_blacklist) +{ + int i; + + for (i = 0; i < num_blacklist; i++) { + if (ring->idx == blacklist[i]) + return true; + } + + return false; +} + +/** + * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block + * + * @adev: amdgpu_device pointer + * @type: amdgpu_ring_type enum + * @blacklist: blacklisted ring ids array + * @num_blacklist: number of entries in @blacklist + * @ring: output ring + * + * Retrieve the amdgpu_ring structure for the least recently used ring of + * a specific IP block (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist, + int num_blacklist, struct amdgpu_ring **ring) +{ + struct amdgpu_ring *entry; + + /* List is sorted in LRU order, find first entry corresponding + * to the desired HW IP */ + *ring = NULL; + spin_lock(&adev->ring_lru_list_lock); + list_for_each_entry(entry, &adev->ring_lru_list, lru_list) { + if (entry->funcs->type != type) + continue; + + if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist)) + continue; + + *ring = entry; + amdgpu_ring_lru_touch_locked(adev, *ring); + break; + } + spin_unlock(&adev->ring_lru_list_lock); + + if (!*ring) { + DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type); + return -EINVAL; + } + + return 0; +} + +/** + * amdgpu_ring_lru_touch - mark a ring as recently being used + * + * @adev: amdgpu_device pointer + * @ring: ring to touch + * + * Move @ring to the tail of the lru list + */ +void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ + spin_lock(&adev->ring_lru_list_lock); + amdgpu_ring_lru_touch_locked(adev, ring); + spin_unlock(&adev->ring_lru_list_lock); +} + /* * Debugfs info */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 944443c5b90a..bc8dec992f73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -47,7 +47,9 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_UVD, AMDGPU_RING_TYPE_VCE, AMDGPU_RING_TYPE_KIQ, - AMDGPU_RING_TYPE_UVD_ENC + AMDGPU_RING_TYPE_UVD_ENC, + AMDGPU_RING_TYPE_VCN_DEC, + AMDGPU_RING_TYPE_VCN_ENC }; struct amdgpu_device; @@ -76,6 +78,7 @@ struct amdgpu_fence_driver { int amdgpu_fence_driver_init(struct amdgpu_device *adev); void amdgpu_fence_driver_fini(struct amdgpu_device *adev); void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); +void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, unsigned num_hw_submission); @@ -130,6 +133,7 @@ struct amdgpu_ring_funcs { int (*test_ib)(struct amdgpu_ring *ring, long timeout); /* insert NOP packets */ void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); + void (*insert_start)(struct amdgpu_ring *ring); void (*insert_end)(struct amdgpu_ring *ring); /* pad the indirect buffer to the necessary number of dw */ void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); @@ -142,6 +146,7 @@ struct amdgpu_ring_funcs { void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); + void (*emit_tmz)(struct amdgpu_ring *ring, bool start); }; struct amdgpu_ring { @@ -149,6 +154,7 @@ struct amdgpu_ring { const struct amdgpu_ring_funcs *funcs; struct amdgpu_fence_driver fence_drv; struct amd_gpu_scheduler sched; + struct list_head lru_list; struct amdgpu_bo *ring_obj; volatile uint32_t *ring; @@ -180,6 +186,7 @@ struct amdgpu_ring { u64 cond_exe_gpu_addr; volatile u32 *cond_exe_cpu_addr; unsigned vm_inv_eng; + bool has_compute_vm_bug; #if defined(CONFIG_DEBUG_FS) struct dentry *ent; #endif @@ -194,6 +201,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned ring_size, struct amdgpu_irq_src *irq_src, unsigned irq_type); void amdgpu_ring_fini(struct amdgpu_ring *ring); +int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist, + int num_blacklist, struct amdgpu_ring **ring); +void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring); static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) { int i = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index ed814e6d0207..a6899180b265 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -298,6 +298,25 @@ struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) return NULL; } +int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr) +{ + struct amdgpu_sync_entry *e; + struct hlist_node *tmp; + int i, r; + + hash_for_each_safe(sync->fences, i, tmp, e, node) { + r = dma_fence_wait(e->fence, intr); + if (r) + return r; + + hash_del(&e->node); + dma_fence_put(e->fence); + kmem_cache_free(amdgpu_sync_slab, e); + } + + return 0; +} + /** * amdgpu_sync_free - free the sync object * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h index 605be266e07f..dc7687993317 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -49,6 +49,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring); struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); +int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr); void amdgpu_sync_free(struct amdgpu_sync *sync); int amdgpu_sync_init(void); void amdgpu_sync_fini(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5db0230e45c6..c9b131b13ef7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -29,11 +29,11 @@ * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> * Dave Airlie */ -#include <ttm/ttm_bo_api.h> -#include <ttm/ttm_bo_driver.h> -#include <ttm/ttm_placement.h> -#include <ttm/ttm_module.h> -#include <ttm/ttm_page_alloc.h> +#include <drm/ttm/ttm_bo_api.h> +#include <drm/ttm/ttm_bo_driver.h> +#include <drm/ttm/ttm_placement.h> +#include <drm/ttm/ttm_module.h> +#include <drm/ttm/ttm_page_alloc.h> #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include <linux/seq_file.h> @@ -745,6 +745,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) return r; } + spin_lock(>t->adev->gtt_list_lock); flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, @@ -753,12 +754,13 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) if (r) { DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages, gtt->offset); - return r; + goto error_gart_bind; } - spin_lock(>t->adev->gtt_list_lock); + list_add_tail(>t->list, >t->adev->gtt_list); +error_gart_bind: spin_unlock(>t->adev->gtt_list_lock); - return 0; + return r; } int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) @@ -789,6 +791,7 @@ int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) { struct amdgpu_ttm_tt *gtt = (void *)ttm; + int r; if (gtt->userptr) amdgpu_ttm_tt_unpin_userptr(ttm); @@ -797,14 +800,17 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) return 0; /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ - if (gtt->adev->gart.ready) - amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); - spin_lock(>t->adev->gtt_list_lock); + r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); + if (r) { + DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", + gtt->ttm.ttm.num_pages, gtt->offset); + goto error_unbind; + } list_del_init(>t->list); +error_unbind: spin_unlock(>t->adev->gtt_list_lock); - - return 0; + return r; } static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) @@ -1115,7 +1121,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) /* Change the size here instead of the init above so only lpfn is affected */ amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); - r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, + r = amdgpu_bo_create(adev, adev->mc.stolen_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, @@ -1462,6 +1468,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, if (size & 0x3 || *pos & 0x3) return -EINVAL; + if (*pos >= adev->mc.mc_vram_size) + return -ENXIO; + while (size) { unsigned long flags; uint32_t value; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index dfd1c98efa7c..4f50eeb65855 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -197,6 +197,27 @@ void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) } } +void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("GPU_INFO\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = + container_of(hdr, struct gpu_info_firmware_header_v1_0, header); + + DRM_DEBUG("version_major: %u\n", + le16_to_cpu(gpu_info_hdr->version_major)); + DRM_DEBUG("version_minor: %u\n", + le16_to_cpu(gpu_info_hdr->version_minor)); + } else { + DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); + } +} + int amdgpu_ucode_validate(const struct firmware *fw) { const struct common_firmware_header *hdr = @@ -253,6 +274,15 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; + case CHIP_RAVEN: +#if 0 + if (!load_type) + return AMDGPU_FW_LOAD_DIRECT; + else + return AMDGPU_FW_LOAD_PSP; +#else + return AMDGPU_FW_LOAD_DIRECT; +#endif default: DRM_ERROR("Unknow firmware load type\n"); } @@ -349,7 +379,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - 0, NULL, NULL, bo); + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, bo); if (err) { dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); goto failed; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 758f03a1770d..30b5500dc152 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -113,6 +113,32 @@ struct sdma_firmware_header_v1_1 { uint32_t digest_size; }; +/* gpu info payload */ +struct gpu_info_firmware_v1_0 { + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; +}; + +/* version_major=1, version_minor=0 */ +struct gpu_info_firmware_header_v1_0 { + struct common_firmware_header header; + uint16_t version_major; /* version */ + uint16_t version_minor; /* version */ +}; + /* header is fixed size */ union amdgpu_firmware_header { struct common_firmware_header common; @@ -124,6 +150,7 @@ union amdgpu_firmware_header { struct rlc_firmware_header_v2_0 rlc_v2_0; struct sdma_firmware_header_v1_0 sdma; struct sdma_firmware_header_v1_1 sdma_v1_1; + struct gpu_info_firmware_header_v1_0 gpu_info; uint8_t raw[0x100]; }; @@ -184,6 +211,7 @@ void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); +void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); int amdgpu_ucode_validate(const struct firmware *fw); bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, uint16_t hdr_major, uint16_t hdr_minor); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 735c38d7db0d..b692ad402252 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -165,35 +165,14 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | (binary_id << 8)); - /* allocate firmware, stack and heap BO */ - - r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &adev->vce.vcpu_bo); + r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo, + &adev->vce.gpu_addr, &adev->vce.cpu_addr); if (r) { dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r); return r; } - r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); - if (r) { - amdgpu_bo_unref(&adev->vce.vcpu_bo); - dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); - return r; - } - - r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, - &adev->vce.gpu_addr); - amdgpu_bo_unreserve(adev->vce.vcpu_bo); - if (r) { - amdgpu_bo_unref(&adev->vce.vcpu_bo); - dev_err(adev->dev, "(%d) VCE bo pin failed\n", r); - return r; - } - - ring = &adev->vce.ring[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vce.entity, @@ -230,7 +209,8 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev) amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity); - amdgpu_bo_unref(&adev->vce.vcpu_bo); + amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr, + (void **)&adev->vce.cpu_addr); for (i = 0; i < adev->vce.num_rings; i++) amdgpu_ring_fini(&adev->vce.ring[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 0a7f18c461e4..5ce54cde472d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -33,6 +33,8 @@ struct amdgpu_vce { struct amdgpu_bo *vcpu_bo; uint64_t gpu_addr; + void *cpu_addr; + void *saved_bo; unsigned fw_version; unsigned fb_version; atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c new file mode 100644 index 000000000000..09190fadd228 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -0,0 +1,654 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +#include <linux/firmware.h> +#include <linux/module.h> +#include <drm/drmP.h> +#include <drm/drm.h> + +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_vcn.h" +#include "soc15d.h" +#include "soc15_common.h" + +#include "vega10/soc15ip.h" +#include "raven1/VCN/vcn_1_0_offset.h" + +/* 1 second timeout */ +#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) + +/* Firmware Names */ +#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" + +MODULE_FIRMWARE(FIRMWARE_RAVEN); + +static void amdgpu_vcn_idle_work_handler(struct work_struct *work); + +int amdgpu_vcn_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + struct amd_sched_rq *rq; + unsigned long bo_size; + const char *fw_name; + const struct common_firmware_header *hdr; + unsigned version_major, version_minor, family_id; + int r; + + INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); + + switch (adev->asic_type) { + case CHIP_RAVEN: + fw_name = FIRMWARE_RAVEN; + break; + default: + return -EINVAL; + } + + r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); + if (r) { + dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", + fw_name); + return r; + } + + r = amdgpu_ucode_validate(adev->vcn.fw); + if (r) { + dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", + fw_name); + release_firmware(adev->vcn.fw); + adev->vcn.fw = NULL; + return r; + } + + hdr = (const struct common_firmware_header *)adev->vcn.fw->data; + family_id = le32_to_cpu(hdr->ucode_version) & 0xff; + version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; + version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; + DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", + version_major, version_minor, family_id); + + + bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) + + AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE + + AMDGPU_VCN_SESSION_SIZE * 40; + r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, + &adev->vcn.gpu_addr, &adev->vcn.cpu_addr); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); + return r; + } + + ring = &adev->vcn.ring_dec; + rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; + r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, + rq, amdgpu_sched_jobs); + if (r != 0) { + DRM_ERROR("Failed setting up VCN dec run queue.\n"); + return r; + } + + ring = &adev->vcn.ring_enc[0]; + rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; + r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, + rq, amdgpu_sched_jobs); + if (r != 0) { + DRM_ERROR("Failed setting up VCN enc run queue.\n"); + return r; + } + + return 0; +} + +int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) +{ + int i; + + kfree(adev->vcn.saved_bo); + + amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec); + + amd_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc); + + amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo, + &adev->vcn.gpu_addr, + (void **)&adev->vcn.cpu_addr); + + amdgpu_ring_fini(&adev->vcn.ring_dec); + + for (i = 0; i < adev->vcn.num_enc_rings; ++i) + amdgpu_ring_fini(&adev->vcn.ring_enc[i]); + + release_firmware(adev->vcn.fw); + + return 0; +} + +int amdgpu_vcn_suspend(struct amdgpu_device *adev) +{ + unsigned size; + void *ptr; + + if (adev->vcn.vcpu_bo == NULL) + return 0; + + cancel_delayed_work_sync(&adev->vcn.idle_work); + + size = amdgpu_bo_size(adev->vcn.vcpu_bo); + ptr = adev->vcn.cpu_addr; + + adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL); + if (!adev->vcn.saved_bo) + return -ENOMEM; + + memcpy_fromio(adev->vcn.saved_bo, ptr, size); + + return 0; +} + +int amdgpu_vcn_resume(struct amdgpu_device *adev) +{ + unsigned size; + void *ptr; + + if (adev->vcn.vcpu_bo == NULL) + return -EINVAL; + + size = amdgpu_bo_size(adev->vcn.vcpu_bo); + ptr = adev->vcn.cpu_addr; + + if (adev->vcn.saved_bo != NULL) { + memcpy_toio(ptr, adev->vcn.saved_bo, size); + kfree(adev->vcn.saved_bo); + adev->vcn.saved_bo = NULL; + } else { + const struct common_firmware_header *hdr; + unsigned offset; + + hdr = (const struct common_firmware_header *)adev->vcn.fw->data; + offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, + le32_to_cpu(hdr->ucode_size_bytes)); + size -= le32_to_cpu(hdr->ucode_size_bytes); + ptr += le32_to_cpu(hdr->ucode_size_bytes); + memset_io(ptr, 0, size); + } + + return 0; +} + +static void amdgpu_vcn_idle_work_handler(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, vcn.idle_work.work); + unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec); + + if (fences == 0) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_uvd(adev, false); + } else { + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + } + } else { + schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); + } +} + +void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); + + if (set_clocks) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_uvd(adev, true); + } else { + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + } + } +} + +void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) +{ + schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); +} + +int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t tmp = 0; + unsigned i; + int r; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD); + r = amdgpu_ring_alloc(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_commit(ring); + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID)); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + return r; +} + +static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, + bool direct, struct dma_fence **fence) +{ + struct ttm_validate_buffer tv; + struct ww_acquire_ctx ticket; + struct list_head head; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + struct dma_fence *f = NULL; + struct amdgpu_device *adev = ring->adev; + uint64_t addr; + int i, r; + + memset(&tv, 0, sizeof(tv)); + tv.bo = &bo->tbo; + + INIT_LIST_HEAD(&head); + list_add(&tv.head, &head); + + r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); + if (r) + return r; + + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + if (r) + goto err; + + r = amdgpu_job_alloc_with_ib(adev, 64, &job); + if (r) + goto err; + + ib = &job->ibs[0]; + addr = amdgpu_bo_gpu_offset(bo); + ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0); + ib->ptr[1] = addr; + ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0); + ib->ptr[3] = addr >> 32; + ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0); + ib->ptr[5] = 0; + for (i = 6; i < 16; i += 2) { + ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0); + ib->ptr[i+1] = 0; + } + ib->length_dw = 16; + + if (direct) { + r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + job->fence = dma_fence_get(f); + if (r) + goto err_free; + + amdgpu_job_free(job); + } else { + r = amdgpu_job_submit(job, ring, &adev->vcn.entity_dec, + AMDGPU_FENCE_OWNER_UNDEFINED, &f); + if (r) + goto err_free; + } + + ttm_eu_fence_buffer_objects(&ticket, &head, f); + + if (fence) + *fence = dma_fence_get(f); + amdgpu_bo_unref(&bo); + dma_fence_put(f); + + return 0; + +err_free: + amdgpu_job_free(job); + +err: + ttm_eu_backoff_reservation(&ticket, &head); + return r; +} + +static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct dma_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_bo *bo; + uint32_t *msg; + int r, i; + + r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, &bo); + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (r) { + amdgpu_bo_unref(&bo); + return r; + } + + r = amdgpu_bo_kmap(bo, (void **)&msg); + if (r) { + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + return r; + } + + msg[0] = cpu_to_le32(0x00000028); + msg[1] = cpu_to_le32(0x00000038); + msg[2] = cpu_to_le32(0x00000001); + msg[3] = cpu_to_le32(0x00000000); + msg[4] = cpu_to_le32(handle); + msg[5] = cpu_to_le32(0x00000000); + msg[6] = cpu_to_le32(0x00000001); + msg[7] = cpu_to_le32(0x00000028); + msg[8] = cpu_to_le32(0x00000010); + msg[9] = cpu_to_le32(0x00000000); + msg[10] = cpu_to_le32(0x00000007); + msg[11] = cpu_to_le32(0x00000000); + msg[12] = cpu_to_le32(0x00000780); + msg[13] = cpu_to_le32(0x00000440); + for (i = 14; i < 1024; ++i) + msg[i] = cpu_to_le32(0x0); + + amdgpu_bo_kunmap(bo); + amdgpu_bo_unreserve(bo); + + return amdgpu_vcn_dec_send_msg(ring, bo, true, fence); +} + +static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + bool direct, struct dma_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_bo *bo; + uint32_t *msg; + int r, i; + + r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, &bo); + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (r) { + amdgpu_bo_unref(&bo); + return r; + } + + r = amdgpu_bo_kmap(bo, (void **)&msg); + if (r) { + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + return r; + } + + msg[0] = cpu_to_le32(0x00000028); + msg[1] = cpu_to_le32(0x00000018); + msg[2] = cpu_to_le32(0x00000000); + msg[3] = cpu_to_le32(0x00000002); + msg[4] = cpu_to_le32(handle); + msg[5] = cpu_to_le32(0x00000000); + for (i = 6; i < 1024; ++i) + msg[i] = cpu_to_le32(0x0); + + amdgpu_bo_kunmap(bo); + amdgpu_bo_unreserve(bo); + + return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence); +} + +int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct dma_fence *fence; + long r; + + r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); + goto error; + } + + r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, true, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); + goto error; + } + + r = dma_fence_wait_timeout(fence, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out.\n"); + r = -ETIMEDOUT; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + } else { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + r = 0; + } + + dma_fence_put(fence); + +error: + return r; +} + +int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t rptr = amdgpu_ring_get_rptr(ring); + unsigned i; + int r; + + r = amdgpu_ring_alloc(ring, 16); + if (r) { + DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, VCN_ENC_CMD_END); + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + if (amdgpu_ring_get_rptr(ring) != rptr) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed\n", + ring->idx); + r = -ETIMEDOUT; + } + + return r; +} + +static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct dma_fence **fence) +{ + const unsigned ib_size_dw = 16; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + struct dma_fence *f = NULL; + uint64_t dummy; + int i, r; + + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); + if (r) + return r; + + ib = &job->ibs[0]; + dummy = ib->gpu_addr + 1024; + + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = upper_32_bits(dummy); + ib->ptr[ib->length_dw++] = dummy; + ib->ptr[ib->length_dw++] = 0x0000000b; + + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ + + for (i = ib->length_dw; i < ib_size_dw; ++i) + ib->ptr[i] = 0x0; + + r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + job->fence = dma_fence_get(f); + if (r) + goto err; + + amdgpu_job_free(job); + if (fence) + *fence = dma_fence_get(f); + dma_fence_put(f); + + return 0; + +err: + amdgpu_job_free(job); + return r; +} + +static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + struct dma_fence **fence) +{ + const unsigned ib_size_dw = 16; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + struct dma_fence *f = NULL; + uint64_t dummy; + int i, r; + + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); + if (r) + return r; + + ib = &job->ibs[0]; + dummy = ib->gpu_addr + 1024; + + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = upper_32_bits(dummy); + ib->ptr[ib->length_dw++] = dummy; + ib->ptr[ib->length_dw++] = 0x0000000b; + + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ + + for (i = ib->length_dw; i < ib_size_dw; ++i) + ib->ptr[i] = 0x0; + + r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + job->fence = dma_fence_get(f); + if (r) + goto err; + + amdgpu_job_free(job); + if (fence) + *fence = dma_fence_get(f); + dma_fence_put(f); + + return 0; + +err: + amdgpu_job_free(job); + return r; +} + +int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct dma_fence *fence = NULL; + long r; + + r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); + goto error; + } + + r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); + goto error; + } + + r = dma_fence_wait_timeout(fence, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out.\n"); + r = -ETIMEDOUT; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + } else { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + r = 0; + } +error: + dma_fence_put(fence); + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h new file mode 100644 index 000000000000..d50ba0657854 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -0,0 +1,77 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_VCN_H__ +#define __AMDGPU_VCN_H__ + +#define AMDGPU_VCN_STACK_SIZE (200*1024) +#define AMDGPU_VCN_HEAP_SIZE (256*1024) +#define AMDGPU_VCN_SESSION_SIZE (50*1024) +#define AMDGPU_VCN_FIRMWARE_OFFSET 256 +#define AMDGPU_VCN_MAX_ENC_RINGS 3 + +#define VCN_DEC_CMD_FENCE 0x00000000 +#define VCN_DEC_CMD_TRAP 0x00000001 +#define VCN_DEC_CMD_WRITE_REG 0x00000004 +#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 +#define VCN_DEC_CMD_PACKET_START 0x0000000a +#define VCN_DEC_CMD_PACKET_END 0x0000000b + +#define VCN_ENC_CMD_NO_OP 0x00000000 +#define VCN_ENC_CMD_END 0x00000001 +#define VCN_ENC_CMD_IB 0x00000002 +#define VCN_ENC_CMD_FENCE 0x00000003 +#define VCN_ENC_CMD_TRAP 0x00000004 +#define VCN_ENC_CMD_REG_WRITE 0x0000000b +#define VCN_ENC_CMD_REG_WAIT 0x0000000c + +struct amdgpu_vcn { + struct amdgpu_bo *vcpu_bo; + void *cpu_addr; + uint64_t gpu_addr; + unsigned fw_version; + void *saved_bo; + struct delayed_work idle_work; + const struct firmware *fw; /* VCN firmware */ + struct amdgpu_ring ring_dec; + struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; + struct amdgpu_irq_src irq; + struct amd_sched_entity entity_dec; + struct amd_sched_entity entity_enc; + unsigned num_enc_rings; +}; + +int amdgpu_vcn_sw_init(struct amdgpu_device *adev); +int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); +int amdgpu_vcn_suspend(struct amdgpu_device *adev); +int amdgpu_vcn_resume(struct amdgpu_device *adev); +void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); +void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); + +int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); +int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); + +int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); +int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 6bf5cea294f2..8a081e162d13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -22,6 +22,7 @@ */ #include "amdgpu.h" +#define MAX_KIQ_REG_WAIT 100000 int amdgpu_allocate_static_csa(struct amdgpu_device *adev) { @@ -105,8 +106,9 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) /* enable virtual display */ adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; + adev->cg_flags = 0; + adev->pg_flags = 0; - mutex_init(&adev->virt.lock_kiq); mutex_init(&adev->virt.lock_reset); } @@ -120,17 +122,19 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) BUG_ON(!ring->funcs->emit_rreg); - mutex_lock(&adev->virt.lock_kiq); + mutex_lock(&kiq->ring_mutex); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_rreg(ring, reg); amdgpu_fence_emit(ring, &f); amdgpu_ring_commit(ring); - mutex_unlock(&adev->virt.lock_kiq); + mutex_unlock(&kiq->ring_mutex); - r = dma_fence_wait(f, false); - if (r) - DRM_ERROR("wait for kiq fence error: %ld.\n", r); + r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT)); dma_fence_put(f); + if (r < 1) { + DRM_ERROR("wait for kiq fence error: %ld.\n", r); + return ~0; + } val = adev->wb.wb[adev->virt.reg_val_offs]; @@ -146,15 +150,15 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) BUG_ON(!ring->funcs->emit_wreg); - mutex_lock(&adev->virt.lock_kiq); + mutex_lock(&kiq->ring_mutex); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_wreg(ring, reg, v); amdgpu_fence_emit(ring, &f); amdgpu_ring_commit(ring); - mutex_unlock(&adev->virt.lock_kiq); + mutex_unlock(&kiq->ring_mutex); - r = dma_fence_wait(f, false); - if (r) + r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT)); + if (r < 1) DRM_ERROR("wait for kiq fence error: %ld.\n", r); dma_fence_put(f); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index a8ed162cc0bc..9e1062edb76e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -52,7 +52,6 @@ struct amdgpu_virt { uint64_t csa_vmid0_addr; bool chained_ib_support; uint32_t reg_val_offs; - struct mutex lock_kiq; struct mutex lock_reset; struct amdgpu_irq_src ack_irq; struct amdgpu_irq_src rcv_irq; @@ -97,7 +96,7 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary); +int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8ecf82c5fe74..5795f81369f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -79,6 +79,12 @@ struct amdgpu_pte_update_params { uint64_t flags); /* indicate update pt or its shadow */ bool shadow; + /* The next two are used during VM update by CPU + * DMA addresses to use for mapping + * Kernel pointer of PD/PT BO that needs to be updated + */ + dma_addr_t *pages_addr; + void *kptr; }; /* Helper to disable partial resident texture feature from a fence callback */ @@ -275,12 +281,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, adev->vm_manager.block_size; unsigned pt_idx, from, to; int r; + u64 flags; if (!parent->entries) { unsigned num_entries = amdgpu_vm_num_entries(adev, level); - parent->entries = drm_calloc_large(num_entries, - sizeof(struct amdgpu_vm_pt)); + parent->entries = kvmalloc_array(num_entries, + sizeof(struct amdgpu_vm_pt), + GFP_KERNEL | __GFP_ZERO); if (!parent->entries) return -ENOMEM; memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); @@ -299,6 +307,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, saddr = saddr & ((1 << shift) - 1); eaddr = eaddr & ((1 << shift) - 1); + flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + if (vm->use_cpu_for_update) + flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + else + flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_SHADOW); + /* walk over the address space and allocate the page tables */ for (pt_idx = from; pt_idx <= to; ++pt_idx) { struct reservation_object *resv = vm->root.bo->tbo.resv; @@ -310,10 +326,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, amdgpu_vm_bo_size(adev, level), AMDGPU_GPU_PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED, + flags, NULL, resv, &pt); if (r) return r; @@ -391,6 +404,71 @@ static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, atomic_read(&adev->gpu_reset_counter); } +static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) +{ + return !!vm->reserved_vmid[vmhub]; +} + +/* idr_mgr->lock must be held */ +static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, + struct amdgpu_ring *ring, + struct amdgpu_sync *sync, + struct dma_fence *fence, + struct amdgpu_job *job) +{ + struct amdgpu_device *adev = ring->adev; + unsigned vmhub = ring->funcs->vmhub; + uint64_t fence_context = adev->fence_context + ring->idx; + struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; + struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; + struct dma_fence *updates = sync->last_vm_update; + int r = 0; + struct dma_fence *flushed, *tmp; + bool needs_flush = false; + + flushed = id->flushed_updates; + if ((amdgpu_vm_had_gpu_reset(adev, id)) || + (atomic64_read(&id->owner) != vm->client_id) || + (job->vm_pd_addr != id->pd_gpu_addr) || + (updates && (!flushed || updates->context != flushed->context || + dma_fence_is_later(updates, flushed))) || + (!id->last_flush || (id->last_flush->context != fence_context && + !dma_fence_is_signaled(id->last_flush)))) { + needs_flush = true; + /* to prevent one context starved by another context */ + id->pd_gpu_addr = 0; + tmp = amdgpu_sync_peek_fence(&id->active, ring); + if (tmp) { + r = amdgpu_sync_fence(adev, sync, tmp); + return r; + } + } + + /* Good we can use this VMID. Remember this submission as + * user of the VMID. + */ + r = amdgpu_sync_fence(ring->adev, &id->active, fence); + if (r) + goto out; + + if (updates && (!flushed || updates->context != flushed->context || + dma_fence_is_later(updates, flushed))) { + dma_fence_put(id->flushed_updates); + id->flushed_updates = dma_fence_get(updates); + } + id->pd_gpu_addr = job->vm_pd_addr; + atomic64_set(&id->owner, vm->client_id); + job->vm_needs_flush = needs_flush; + if (needs_flush) { + dma_fence_put(id->last_flush); + id->last_flush = NULL; + } + job->vm_id = id - id_mgr->ids; + trace_amdgpu_vm_grab_id(vm, ring, job); +out: + return r; +} + /** * amdgpu_vm_grab_id - allocate the next free VMID * @@ -415,12 +493,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, unsigned i; int r = 0; + mutex_lock(&id_mgr->lock); + if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { + r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); + mutex_unlock(&id_mgr->lock); + return r; + } fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); - if (!fences) + if (!fences) { + mutex_unlock(&id_mgr->lock); return -ENOMEM; - - mutex_lock(&id_mgr->lock); - + } /* Check if we have an idle VMID */ i = 0; list_for_each_entry(idle, &id_mgr->ids_lru, list) { @@ -521,7 +604,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, id->pd_gpu_addr = job->vm_pd_addr; dma_fence_put(id->flushed_updates); id->flushed_updates = dma_fence_get(updates); - id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); atomic64_set(&id->owner, vm->client_id); needs_flush: @@ -540,40 +622,118 @@ error: return r; } -static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) +static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + unsigned vmhub) +{ + struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; + + mutex_lock(&id_mgr->lock); + if (vm->reserved_vmid[vmhub]) { + list_add(&vm->reserved_vmid[vmhub]->list, + &id_mgr->ids_lru); + vm->reserved_vmid[vmhub] = NULL; + atomic_dec(&id_mgr->reserved_vmid_num); + } + mutex_unlock(&id_mgr->lock); +} + +static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + unsigned vmhub) +{ + struct amdgpu_vm_id_manager *id_mgr; + struct amdgpu_vm_id *idle; + int r = 0; + + id_mgr = &adev->vm_manager.id_mgr[vmhub]; + mutex_lock(&id_mgr->lock); + if (vm->reserved_vmid[vmhub]) + goto unlock; + if (atomic_inc_return(&id_mgr->reserved_vmid_num) > + AMDGPU_VM_MAX_RESERVED_VMID) { + DRM_ERROR("Over limitation of reserved vmid\n"); + atomic_dec(&id_mgr->reserved_vmid_num); + r = -EINVAL; + goto unlock; + } + /* Select the first entry VMID */ + idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); + list_del_init(&idle->list); + vm->reserved_vmid[vmhub] = idle; + mutex_unlock(&id_mgr->lock); + + return 0; +unlock: + mutex_unlock(&id_mgr->lock); + return r; +} + +/** + * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug + * + * @adev: amdgpu_device pointer + */ +void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) { - struct amdgpu_device *adev = ring->adev; const struct amdgpu_ip_block *ip_block; + bool has_compute_vm_bug; + struct amdgpu_ring *ring; + int i; - if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) - /* only compute rings */ - return false; + has_compute_vm_bug = false; ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); - if (!ip_block) - return false; + if (ip_block) { + /* Compute has a VM bug for GFX version < 7. + Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ + if (ip_block->version->major <= 7) + has_compute_vm_bug = true; + else if (ip_block->version->major == 8) + if (adev->gfx.mec_fw_version < 673) + has_compute_vm_bug = true; + } - if (ip_block->version->major <= 7) { - /* gfx7 has no workaround */ - return true; - } else if (ip_block->version->major == 8) { - if (adev->gfx.mec_fw_version >= 673) - /* gfx8 is fixed in MEC firmware 673 */ - return false; + for (i = 0; i < adev->num_rings; i++) { + ring = adev->rings[i]; + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) + /* only compute rings */ + ring->has_compute_vm_bug = has_compute_vm_bug; else - return true; + ring->has_compute_vm_bug = false; } - return false; } -static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) +bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, + struct amdgpu_job *job) { - u64 addr = mc_addr; + struct amdgpu_device *adev = ring->adev; + unsigned vmhub = ring->funcs->vmhub; + struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; + struct amdgpu_vm_id *id; + bool gds_switch_needed; + bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; + + if (job->vm_id == 0) + return false; + id = &id_mgr->ids[job->vm_id]; + gds_switch_needed = ring->funcs->emit_gds_switch && ( + id->gds_base != job->gds_base || + id->gds_size != job->gds_size || + id->gws_base != job->gws_base || + id->gws_size != job->gws_size || + id->oa_base != job->oa_base || + id->oa_size != job->oa_size); - if (adev->gart.gart_funcs->adjust_mc_addr) - addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr); + if (amdgpu_vm_had_gpu_reset(adev, id)) + return true; - return addr; + return vm_flush_needed || gds_switch_needed; +} + +static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) +{ + return (adev->mc.real_vram_size == adev->mc.visible_vram_size); } /** @@ -598,8 +758,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) id->gws_size != job->gws_size || id->oa_base != job->oa_base || id->oa_size != job->oa_size); - bool vm_flush_needed = job->vm_needs_flush || - amdgpu_vm_ring_has_compute_vm_bug(ring); + bool vm_flush_needed = job->vm_needs_flush; unsigned patch_offset = 0; int r; @@ -614,15 +773,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) if (ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring); - if (ring->funcs->emit_pipeline_sync && !job->need_pipeline_sync) - amdgpu_ring_emit_pipeline_sync(ring); - if (ring->funcs->emit_vm_flush && vm_flush_needed) { - u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); struct dma_fence *fence; - trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr); - amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); + trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); + amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); r = amdgpu_fence_emit(ring, &fence); if (r) @@ -631,6 +786,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) mutex_lock(&id_mgr->lock); dma_fence_put(id->last_flush); id->last_flush = fence; + id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); mutex_unlock(&id_mgr->lock); } @@ -805,6 +961,53 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) return result; } +/** + * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU + * + * @params: see amdgpu_pte_update_params definition + * @pe: kmap addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: hw access flags + * + * Write count number of PT/PD entries directly. + */ +static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint64_t flags) +{ + unsigned int i; + uint64_t value; + + for (i = 0; i < count; i++) { + value = params->pages_addr ? + amdgpu_vm_map_gart(params->pages_addr, addr) : + addr; + amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, + i, value, flags); + addr += incr; + } + + /* Flush HDP */ + mb(); + amdgpu_gart_flush_gpu_tlb(params->adev, 0); +} + +static int amdgpu_vm_bo_wait(struct amdgpu_device *adev, struct amdgpu_bo *bo) +{ + struct amdgpu_sync sync; + int r; + + amdgpu_sync_create(&sync); + amdgpu_sync_resv(adev, &sync, bo->tbo.resv, AMDGPU_FENCE_OWNER_VM); + r = amdgpu_sync_wait(&sync, true); + amdgpu_sync_free(&sync); + + return r; +} + /* * amdgpu_vm_update_level - update a single level in the hierarchy * @@ -821,11 +1024,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, unsigned level) { struct amdgpu_bo *shadow; - struct amdgpu_ring *ring; - uint64_t pd_addr, shadow_addr; + struct amdgpu_ring *ring = NULL; + uint64_t pd_addr, shadow_addr = 0; uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; - unsigned count = 0, pt_idx, ndw; + unsigned count = 0, pt_idx, ndw = 0; struct amdgpu_job *job; struct amdgpu_pte_update_params params; struct dma_fence *fence = NULL; @@ -834,34 +1037,54 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, if (!parent->entries) return 0; - ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - /* padding, etc. */ - ndw = 64; + memset(¶ms, 0, sizeof(params)); + params.adev = adev; + shadow = parent->bo->shadow; - /* assume the worst case */ - ndw += parent->last_entry_used * 6; + WARN_ON(vm->use_cpu_for_update && shadow); + if (vm->use_cpu_for_update && !shadow) { + r = amdgpu_bo_kmap(parent->bo, (void **)&pd_addr); + if (r) + return r; + r = amdgpu_vm_bo_wait(adev, parent->bo); + if (unlikely(r)) { + amdgpu_bo_kunmap(parent->bo); + return r; + } + params.func = amdgpu_vm_cpu_set_ptes; + } else { + if (shadow) { + r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + if (r) + return r; + } + ring = container_of(vm->entity.sched, struct amdgpu_ring, + sched); - pd_addr = amdgpu_bo_gpu_offset(parent->bo); + /* padding, etc. */ + ndw = 64; - shadow = parent->bo->shadow; - if (shadow) { - r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + /* assume the worst case */ + ndw += parent->last_entry_used * 6; + + pd_addr = amdgpu_bo_gpu_offset(parent->bo); + + if (shadow) { + shadow_addr = amdgpu_bo_gpu_offset(shadow); + ndw *= 2; + } else { + shadow_addr = 0; + } + + r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); if (r) return r; - shadow_addr = amdgpu_bo_gpu_offset(shadow); - ndw *= 2; - } else { - shadow_addr = 0; - } - r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); - if (r) - return r; + params.ib = &job->ibs[0]; + params.func = amdgpu_vm_do_set_ptes; + } - memset(¶ms, 0, sizeof(params)); - params.adev = adev; - params.ib = &job->ibs[0]; /* walk over the address space and update the directory */ for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { @@ -881,6 +1104,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, } pt = amdgpu_bo_gpu_offset(bo); + pt = amdgpu_gart_get_vm_pde(adev, pt); if (parent->entries[pt_idx].addr == pt) continue; @@ -892,19 +1116,16 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { if (count) { - uint64_t pt_addr = - amdgpu_vm_adjust_mc_addr(adev, last_pt); - if (shadow) - amdgpu_vm_do_set_ptes(¶ms, - last_shadow, - pt_addr, count, - incr, - AMDGPU_PTE_VALID); - - amdgpu_vm_do_set_ptes(¶ms, last_pde, - pt_addr, count, incr, - AMDGPU_PTE_VALID); + params.func(¶ms, + last_shadow, + last_pt, count, + incr, + AMDGPU_PTE_VALID); + + params.func(¶ms, last_pde, + last_pt, count, incr, + AMDGPU_PTE_VALID); } count = 1; @@ -917,17 +1138,17 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, } if (count) { - uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); - if (vm->root.bo->shadow) - amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, - count, incr, AMDGPU_PTE_VALID); + params.func(¶ms, last_shadow, last_pt, + count, incr, AMDGPU_PTE_VALID); - amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr, - count, incr, AMDGPU_PTE_VALID); + params.func(¶ms, last_pde, last_pt, + count, incr, AMDGPU_PTE_VALID); } - if (params.ib->length_dw == 0) { + if (params.func == amdgpu_vm_cpu_set_ptes) + amdgpu_bo_kunmap(parent->bo); + else if (params.ib->length_dw == 0) { amdgpu_job_free(job); } else { amdgpu_ring_pad_ib(ring, params.ib); @@ -971,6 +1192,32 @@ error_free: } /* + * amdgpu_vm_invalidate_level - mark all PD levels as invalid + * + * @parent: parent PD + * + * Mark all PD level as invalid after an error. + */ +static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) +{ + unsigned pt_idx; + + /* + * Recurse into the subdirectories. This recursion is harmless because + * we only have a maximum of 5 layers. + */ + for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { + struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; + + if (!entry->bo) + continue; + + entry->addr = ~0ULL; + amdgpu_vm_invalidate_level(entry); + } +} + +/* * amdgpu_vm_update_directories - make sure that all directories are valid * * @adev: amdgpu_device pointer @@ -982,7 +1229,13 @@ error_free: int amdgpu_vm_update_directories(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - return amdgpu_vm_update_level(adev, vm, &vm->root, 0); + int r; + + r = amdgpu_vm_update_level(adev, vm, &vm->root, 0); + if (r) + amdgpu_vm_invalidate_level(&vm->root); + + return r; } /** @@ -1022,58 +1275,37 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, * @flags: mapping flags * * Update the page tables in the range @start - @end. + * Returns 0 for success, -EINVAL for failure. */ -static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, +static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, uint64_t start, uint64_t end, uint64_t dst, uint64_t flags) { struct amdgpu_device *adev = params->adev; const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; - uint64_t cur_pe_start, cur_nptes, cur_dst; - uint64_t addr; /* next GPU address to be updated */ + uint64_t addr, pe_start; struct amdgpu_bo *pt; - unsigned nptes; /* next number of ptes to be updated */ - uint64_t next_pe_start; - - /* initialize the variables */ - addr = start; - pt = amdgpu_vm_get_pt(params, addr); - if (!pt) { - pr_err("PT not found, aborting update_ptes\n"); - return; - } - - if (params->shadow) { - if (!pt->shadow) - return; - pt = pt->shadow; - } - if ((addr & ~mask) == (end & ~mask)) - nptes = end - addr; - else - nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); - - cur_pe_start = amdgpu_bo_gpu_offset(pt); - cur_pe_start += (addr & mask) * 8; - cur_nptes = nptes; - cur_dst = dst; + unsigned nptes; + int r; + bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); - /* for next ptb*/ - addr += nptes; - dst += nptes * AMDGPU_GPU_PAGE_SIZE; /* walk over the address space and update the page tables */ - while (addr < end) { + for (addr = start; addr < end; addr += nptes) { pt = amdgpu_vm_get_pt(params, addr); if (!pt) { pr_err("PT not found, aborting update_ptes\n"); - return; + return -EINVAL; } if (params->shadow) { + if (WARN_ONCE(use_cpu_update, + "CPU VM update doesn't suuport shadow pages")) + return 0; + if (!pt->shadow) - return; + return 0; pt = pt->shadow; } @@ -1082,32 +1314,25 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, else nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); - next_pe_start = amdgpu_bo_gpu_offset(pt); - next_pe_start += (addr & mask) * 8; + if (use_cpu_update) { + r = amdgpu_bo_kmap(pt, (void *)&pe_start); + if (r) + return r; + } else + pe_start = amdgpu_bo_gpu_offset(pt); - if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && - ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { - /* The next ptb is consecutive to current ptb. - * Don't call the update function now. - * Will update two ptbs together in future. - */ - cur_nptes += nptes; - } else { - params->func(params, cur_pe_start, cur_dst, cur_nptes, - AMDGPU_GPU_PAGE_SIZE, flags); + pe_start += (addr & mask) * 8; - cur_pe_start = next_pe_start; - cur_nptes = nptes; - cur_dst = dst; - } + params->func(params, pe_start, dst, nptes, + AMDGPU_GPU_PAGE_SIZE, flags); - /* for next ptb*/ - addr += nptes; dst += nptes * AMDGPU_GPU_PAGE_SIZE; + + if (use_cpu_update) + amdgpu_bo_kunmap(pt); } - params->func(params, cur_pe_start, cur_dst, cur_nptes, - AMDGPU_GPU_PAGE_SIZE, flags); + return 0; } /* @@ -1119,11 +1344,14 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, * @end: last PTE to handle * @dst: addr those PTEs should point to * @flags: hw mapping flags + * Returns 0 for success, -EINVAL for failure. */ -static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, +static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, uint64_t start, uint64_t end, uint64_t dst, uint64_t flags) { + int r; + /** * The MC L1 TLB supports variable sized pages, based on a fragment * field in the PTE. When this field is set to a non-zero value, page @@ -1152,28 +1380,30 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, /* system pages are non continuously */ if (params->src || !(flags & AMDGPU_PTE_VALID) || - (frag_start >= frag_end)) { - - amdgpu_vm_update_ptes(params, start, end, dst, flags); - return; - } + (frag_start >= frag_end)) + return amdgpu_vm_update_ptes(params, start, end, dst, flags); /* handle the 4K area at the beginning */ if (start != frag_start) { - amdgpu_vm_update_ptes(params, start, frag_start, - dst, flags); + r = amdgpu_vm_update_ptes(params, start, frag_start, + dst, flags); + if (r) + return r; dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; } /* handle the area in the middle */ - amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, - flags | frag_flags); + r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, + flags | frag_flags); + if (r) + return r; /* handle the 4K area at the end */ if (frag_end != end) { dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; - amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); + r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); } + return r; } /** @@ -1215,6 +1445,25 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, params.vm = vm; params.src = src; + if (vm->use_cpu_for_update) { + /* params.src is used as flag to indicate system Memory */ + if (pages_addr) + params.src = ~0; + + /* Wait for PT BOs to be free. PTs share the same resv. object + * as the root PD BO + */ + r = amdgpu_vm_bo_wait(adev, vm->root.bo); + if (unlikely(r)) + return r; + + params.func = amdgpu_vm_cpu_set_ptes; + params.pages_addr = pages_addr; + params.shadow = false; + return amdgpu_vm_frag_ptes(¶ms, start, last + 1, + addr, flags); + } + ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); /* sync to everything on unmapping */ @@ -1294,9 +1543,13 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, goto error_free; params.shadow = true; - amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); + r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); + if (r) + goto error_free; params.shadow = false; - amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); + r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); + if (r) + goto error_free; amdgpu_ring_pad_ib(ring, params.ib); WARN_ON(params.ib->length_dw > ndw); @@ -2137,20 +2390,25 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) * * @adev: amdgpu_device pointer * @vm: requested vm + * @vm_context: Indicates if it GFX or Compute context * * Init @vm fields. */ -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + int vm_context) { const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT(adev) * 8); unsigned ring_instance; struct amdgpu_ring *ring; struct amd_sched_rq *rq; - int r; + int r, i; + u64 flags; vm->va = RB_ROOT; vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); + for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) + vm->reserved_vmid[i] = NULL; spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->invalidated); INIT_LIST_HEAD(&vm->cleared); @@ -2167,14 +2425,29 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) return r; + if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & + AMDGPU_VM_USE_CPU_FOR_COMPUTE); + else + vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & + AMDGPU_VM_USE_CPU_FOR_GFX); + DRM_DEBUG_DRIVER("VM update mode is %s\n", + vm->use_cpu_for_update ? "CPU" : "SDMA"); + WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), + "CPU update of VM recommended only for large BAR system\n"); vm->last_dir_update = NULL; + flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + if (vm->use_cpu_for_update) + flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + else + flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_SHADOW); + r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED, + flags, NULL, NULL, &vm->root.bo); if (r) goto error_free_sched_entity; @@ -2219,7 +2492,7 @@ static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) for (i = 0; i <= level->last_entry_used; i++) amdgpu_vm_free_levels(&level->entries[i]); - drm_free_large(level->entries); + kvfree(level->entries); } /** @@ -2235,6 +2508,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_bo_va_mapping *mapping, *tmp; bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; + int i; amd_sched_entity_fini(vm->entity.sched, &vm->entity); @@ -2258,6 +2532,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_vm_free_levels(&vm->root); dma_fence_put(vm->last_dir_update); + for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) + amdgpu_vm_free_reserved_vmid(adev, vm, i); } /** @@ -2277,6 +2553,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) mutex_init(&id_mgr->lock); INIT_LIST_HEAD(&id_mgr->ids_lru); + atomic_set(&id_mgr->reserved_vmid_num, 0); /* skip over VMID 0, since it is the system VM */ for (j = 1; j < id_mgr->num_ids; ++j) { @@ -2295,6 +2572,23 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) atomic64_set(&adev->vm_manager.client_counter, 0); spin_lock_init(&adev->vm_manager.prt_lock); atomic_set(&adev->vm_manager.num_prt_users, 0); + + /* If not overridden by the user, by default, only in large BAR systems + * Compute VM tables will be updated by CPU + */ +#ifdef CONFIG_X86_64 + if (amdgpu_vm_update_mode == -1) { + if (amdgpu_vm_is_large_bar(adev)) + adev->vm_manager.vm_update_mode = + AMDGPU_VM_USE_CPU_FOR_COMPUTE; + else + adev->vm_manager.vm_update_mode = 0; + } else + adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; +#else + adev->vm_manager.vm_update_mode = 0; +#endif + } /** @@ -2322,3 +2616,28 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) } } } + +int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +{ + union drm_amdgpu_vm *args = data; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + int r; + + switch (args->in.op) { + case AMDGPU_VM_OP_RESERVE_VMID: + /* current, we only have requirement to reserve vmid from gfxhub */ + r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, + AMDGPU_GFXHUB); + if (r) + return r; + break; + case AMDGPU_VM_OP_UNRESERVE_VMID: + amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); + break; + default: + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index e1d951ece433..936f158bc5ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -84,6 +84,16 @@ struct amdgpu_bo_list_entry; /* hardcode that limit for now */ #define AMDGPU_VA_RESERVED_SIZE (8 << 20) +/* max vmids dedicated for process */ +#define AMDGPU_VM_MAX_RESERVED_VMID 1 + +#define AMDGPU_VM_CONTEXT_GFX 0 +#define AMDGPU_VM_CONTEXT_COMPUTE 1 + +/* See vm_update_mode */ +#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) +#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) + struct amdgpu_vm_pt { struct amdgpu_bo *bo; @@ -123,8 +133,13 @@ struct amdgpu_vm { /* client id */ u64 client_id; + /* dedicated to vm */ + struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; /* each VM will map on CSA */ struct amdgpu_bo_va *csa_bo_va; + + /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ + bool use_cpu_for_update; }; struct amdgpu_vm_id { @@ -152,6 +167,7 @@ struct amdgpu_vm_id_manager { unsigned num_ids; struct list_head ids_lru; struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; + atomic_t reserved_vmid_num; }; struct amdgpu_vm_manager { @@ -168,8 +184,6 @@ struct amdgpu_vm_manager { uint32_t block_size; /* vram base address for page table entry */ u64 vram_base_offset; - /* is vm enabled? */ - bool enabled; /* vm pte handling */ const struct amdgpu_vm_pte_funcs *vm_pte_funcs; struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; @@ -181,11 +195,18 @@ struct amdgpu_vm_manager { /* partial resident texture handling */ spinlock_t prt_lock; atomic_t num_prt_users; + + /* controls how VM page tables are updated for Graphics and Compute. + * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU + * BIT1[= 0] Compute updated by SDMA [= 1] by CPU + */ + int vm_update_mode; }; void amdgpu_vm_manager_init(struct amdgpu_device *adev); void amdgpu_vm_manager_fini(struct amdgpu_device *adev); -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + int vm_context); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, @@ -239,5 +260,9 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); +int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, + struct amdgpu_job *job); +void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index ec93714e4524..cb508a211b2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -22,7 +22,7 @@ */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_ucode.h" diff --git a/drivers/gpu/drm/amd/amdgpu/ci_smc.c b/drivers/gpu/drm/amd/amdgpu/ci_smc.c index 7eb9069db8e3..b8ba51e045b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_smc.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_smc.c @@ -23,7 +23,7 @@ */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "cikd.h" #include "ppsmc.h" diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 9d33e5641419..37a499ab30eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -24,7 +24,7 @@ #include <linux/firmware.h> #include <linux/slab.h> #include <linux/module.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -964,62 +964,62 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, } static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { - {mmGRBM_STATUS, false}, - {mmGB_ADDR_CONFIG, false}, - {mmMC_ARB_RAMCFG, false}, - {mmGB_TILE_MODE0, false}, - {mmGB_TILE_MODE1, false}, - {mmGB_TILE_MODE2, false}, - {mmGB_TILE_MODE3, false}, - {mmGB_TILE_MODE4, false}, - {mmGB_TILE_MODE5, false}, - {mmGB_TILE_MODE6, false}, - {mmGB_TILE_MODE7, false}, - {mmGB_TILE_MODE8, false}, - {mmGB_TILE_MODE9, false}, - {mmGB_TILE_MODE10, false}, - {mmGB_TILE_MODE11, false}, - {mmGB_TILE_MODE12, false}, - {mmGB_TILE_MODE13, false}, - {mmGB_TILE_MODE14, false}, - {mmGB_TILE_MODE15, false}, - {mmGB_TILE_MODE16, false}, - {mmGB_TILE_MODE17, false}, - {mmGB_TILE_MODE18, false}, - {mmGB_TILE_MODE19, false}, - {mmGB_TILE_MODE20, false}, - {mmGB_TILE_MODE21, false}, - {mmGB_TILE_MODE22, false}, - {mmGB_TILE_MODE23, false}, - {mmGB_TILE_MODE24, false}, - {mmGB_TILE_MODE25, false}, - {mmGB_TILE_MODE26, false}, - {mmGB_TILE_MODE27, false}, - {mmGB_TILE_MODE28, false}, - {mmGB_TILE_MODE29, false}, - {mmGB_TILE_MODE30, false}, - {mmGB_TILE_MODE31, false}, - {mmGB_MACROTILE_MODE0, false}, - {mmGB_MACROTILE_MODE1, false}, - {mmGB_MACROTILE_MODE2, false}, - {mmGB_MACROTILE_MODE3, false}, - {mmGB_MACROTILE_MODE4, false}, - {mmGB_MACROTILE_MODE5, false}, - {mmGB_MACROTILE_MODE6, false}, - {mmGB_MACROTILE_MODE7, false}, - {mmGB_MACROTILE_MODE8, false}, - {mmGB_MACROTILE_MODE9, false}, - {mmGB_MACROTILE_MODE10, false}, - {mmGB_MACROTILE_MODE11, false}, - {mmGB_MACROTILE_MODE12, false}, - {mmGB_MACROTILE_MODE13, false}, - {mmGB_MACROTILE_MODE14, false}, - {mmGB_MACROTILE_MODE15, false}, - {mmCC_RB_BACKEND_DISABLE, false, true}, - {mmGC_USER_RB_BACKEND_DISABLE, false, true}, - {mmGB_BACKEND_MAP, false, false}, - {mmPA_SC_RASTER_CONFIG, false, true}, - {mmPA_SC_RASTER_CONFIG_1, false, true}, + {mmGRBM_STATUS}, + {mmGB_ADDR_CONFIG}, + {mmMC_ARB_RAMCFG}, + {mmGB_TILE_MODE0}, + {mmGB_TILE_MODE1}, + {mmGB_TILE_MODE2}, + {mmGB_TILE_MODE3}, + {mmGB_TILE_MODE4}, + {mmGB_TILE_MODE5}, + {mmGB_TILE_MODE6}, + {mmGB_TILE_MODE7}, + {mmGB_TILE_MODE8}, + {mmGB_TILE_MODE9}, + {mmGB_TILE_MODE10}, + {mmGB_TILE_MODE11}, + {mmGB_TILE_MODE12}, + {mmGB_TILE_MODE13}, + {mmGB_TILE_MODE14}, + {mmGB_TILE_MODE15}, + {mmGB_TILE_MODE16}, + {mmGB_TILE_MODE17}, + {mmGB_TILE_MODE18}, + {mmGB_TILE_MODE19}, + {mmGB_TILE_MODE20}, + {mmGB_TILE_MODE21}, + {mmGB_TILE_MODE22}, + {mmGB_TILE_MODE23}, + {mmGB_TILE_MODE24}, + {mmGB_TILE_MODE25}, + {mmGB_TILE_MODE26}, + {mmGB_TILE_MODE27}, + {mmGB_TILE_MODE28}, + {mmGB_TILE_MODE29}, + {mmGB_TILE_MODE30}, + {mmGB_TILE_MODE31}, + {mmGB_MACROTILE_MODE0}, + {mmGB_MACROTILE_MODE1}, + {mmGB_MACROTILE_MODE2}, + {mmGB_MACROTILE_MODE3}, + {mmGB_MACROTILE_MODE4}, + {mmGB_MACROTILE_MODE5}, + {mmGB_MACROTILE_MODE6}, + {mmGB_MACROTILE_MODE7}, + {mmGB_MACROTILE_MODE8}, + {mmGB_MACROTILE_MODE9}, + {mmGB_MACROTILE_MODE10}, + {mmGB_MACROTILE_MODE11}, + {mmGB_MACROTILE_MODE12}, + {mmGB_MACROTILE_MODE13}, + {mmGB_MACROTILE_MODE14}, + {mmGB_MACROTILE_MODE15}, + {mmCC_RB_BACKEND_DISABLE, true}, + {mmGC_USER_RB_BACKEND_DISABLE, true}, + {mmGB_BACKEND_MAP, false}, + {mmPA_SC_RASTER_CONFIG, true}, + {mmPA_SC_RASTER_CONFIG_1, true}, }; static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, @@ -1050,11 +1050,10 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num, if (reg_offset != cik_allowed_read_registers[i].reg_offset) continue; - if (!cik_allowed_read_registers[i].untouched) - *value = cik_allowed_read_registers[i].grbm_indexed ? - cik_read_indexed_register(adev, se_num, - sh_num, reg_offset) : - RREG32(reg_offset); + *value = cik_allowed_read_registers[i].grbm_indexed ? + cik_read_indexed_register(adev, se_num, + sh_num, reg_offset) : + RREG32(reg_offset); return 0; } return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index c57c3f18af01..b8918432c572 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "cikd.h" diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index a5f294ebff5c..0c1209cdd1cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "vid.h" diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 5dffa27afa45..9f78c03a2e31 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_i2c.h" diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 47bbc87f96d2..4bcf01dc567a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_i2c.h" diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index d8c9a959493e..fd134a4629d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_i2c.h" @@ -118,14 +118,27 @@ static const struct { static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, u32 block_offset, u32 reg) { - DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n"); - return 0; + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + + return r; } static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, u32 block_offset, u32 reg, u32 v) { - DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n"); + unsigned long flags; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, + reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); } static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) @@ -501,21 +514,16 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) { - int num_crtc = 0; - switch (adev->asic_type) { case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: - num_crtc = 6; - break; + return 6; case CHIP_OLAND: - num_crtc = 2; - break; + return 2; default: - num_crtc = 0; + return 0; } - return num_crtc; } void dce_v6_0_disable_dce(struct amdgpu_device *adev) @@ -1225,17 +1233,17 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); } } -/* + static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) { int i; - u32 offset, tmp; + u32 tmp; for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - offset = adev->mode_info.audio.pin[i].offset; - tmp = RREG32_AUDIO_ENDPT(offset, - AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); - if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) + tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); + if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, + PORT_CONNECTIVITY)) adev->mode_info.audio.pin[i].connected = false; else adev->mode_info.audio.pin[i].connected = true; @@ -1257,45 +1265,206 @@ static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *ade return NULL; } -static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder) +static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) { struct amdgpu_device *adev = encoder->dev->dev_private; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - u32 offset; if (!dig || !dig->afmt || !dig->afmt->pin) return; - offset = dig->afmt->offset; - - WREG32(AFMT_AUDIO_SRC_CONTROL + offset, - AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); - + WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, + REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, + dig->afmt->pin->id)); } static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, struct drm_display_mode *mode) { - DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n"); + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + int interlace = 0; + u32 tmp; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + interlace = 1; + + if (connector->latency_present[interlace]) { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, connector->video_latency[interlace]); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, connector->audio_latency[interlace]); + } else { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, 0); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, 0); + } + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); } static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) { - DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n"); + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u8 *sadb = NULL; + int sad_count; + u32 tmp; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); + if (sad_count < 0) { + DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); + sad_count = 0; + } + + /* program the speaker allocation */ + tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + HDMI_CONNECTION, 0); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + DP_CONNECTION, 0); + + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + DP_CONNECTION, 1); + else + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + HDMI_CONNECTION, 1); + + if (sad_count) + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, sadb[0]); + else + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, 5); /* stereo */ + + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); + + kfree(sadb); } static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) { - DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n"); + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + struct cea_sad *sads; + int i, sad_count; + + static const u16 eld_reg_to_type[][2] = { + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, + }; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); + if (sad_count <= 0) { + DRM_ERROR("Couldn't read SADs: %d\n", sad_count); + return; + } + + for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { + u32 tmp = 0; + u8 stereo_freqs = 0; + int max_channels = -1; + int j; + + for (j = 0; j < sad_count; j++) { + struct cea_sad *sad = &sads[j]; + + if (sad->format == eld_reg_to_type[i][1]) { + if (sad->channels > max_channels) { + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + MAX_CHANNELS, sad->channels); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + DESCRIPTOR_BYTE_2, sad->byte2); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES, sad->freq); + max_channels = sad->channels; + } + + if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) + stereo_freqs |= sad->freq; + else + break; + } + } + + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); + } + + kfree(sads); } -*/ + static void dce_v6_0_audio_enable(struct amdgpu_device *adev, struct amdgpu_audio_pin *pin, bool enable) { - DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n"); + if (!pin) + return; + + WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); } static const u32 pin_offsets[7] = @@ -1311,42 +1480,372 @@ static const u32 pin_offsets[7] = static int dce_v6_0_audio_init(struct amdgpu_device *adev) { + int i; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + switch (adev->asic_type) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + default: + adev->mode_info.audio.num_pins = 6; + break; + case CHIP_OLAND: + adev->mode_info.audio.num_pins = 2; + break; + } + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].offset = pin_offsets[i]; + adev->mode_info.audio.pin[i].id = i; + dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + return 0; } static void dce_v6_0_audio_fini(struct amdgpu_device *adev) { + int i; + if (!amdgpu_audio) + return; + + if (!adev->mode_info.audio.enabled) + return; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) + dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + + adev->mode_info.audio.enabled = false; } -/* -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) { - DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n"); + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); } -*/ -/* - * build a HDMI Video Info Frame - */ -/* -static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, - void *buffer, size_t size) + +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, + uint32_t clock, int bpc) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, + bpc > 8 ? 0 : 1); + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); +} + +static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, + struct drm_display_mode *mode) { - DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n"); + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct hdmi_avi_infoframe frame; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + uint8_t *payload = buffer + 3; + uint8_t *header = buffer; + ssize_t err; + u32 tmp; + + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + if (err < 0) { + DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); + return; + } + + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (err < 0) { + DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); + return; + } + + WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, + payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); + WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, + payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); + WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, + payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); + WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, + payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + /* anything other than 0 */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, + HDMI_AUDIO_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); } static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) { - DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n"); + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); + u32 tmp; + + /* + * Two dtos: generally use dto0 for hdmi, dto1 for dp. + * Express [24MHz / target pixel clock] as an exact rational + * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ + tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); + if (em == ATOM_ENCODER_MODE_HDMI) { + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO_SEL, 0); + } else if (ENCODER_MODE_IS_DP(em)) { + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, + DCCG_AUDIO_DTO_SEL, 1); + } + WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); + if (em == ATOM_ENCODER_MODE_HDMI) { + WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); + WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); + } else if (ENCODER_MODE_IS_DP(em)) { + WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); + WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); + } } -*/ -/* - * update the info frames with the data from the current display mode - */ + +static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); + WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); + WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); + WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); + WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); + WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); +} + +static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmHDMI_GC + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); + WREG32(mmHDMI_GC + dig->afmt->offset, tmp); +} + +static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + if (enable) { + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + } else { + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + } +} + +static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + if (enable) { + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); + WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); + + tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); + WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); + } else { + WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); + } +} + static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) { - DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n"); + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); + int bpc = 8; + + if (!dig || !dig->afmt) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (!dig->afmt->enabled) + return; + + dig->afmt->pin = dce_v6_0_audio_get_pin(adev); + if (!dig->afmt->pin) + return; + + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + bpc = amdgpu_crtc->bpc; + } + + /* disable audio before setting up hw */ + dce_v6_0_audio_enable(adev, dig->afmt->pin, false); + + dce_v6_0_audio_set_mute(encoder, true); + dce_v6_0_audio_write_speaker_allocation(encoder); + dce_v6_0_audio_write_sad_regs(encoder); + dce_v6_0_audio_write_latency_fields(encoder, mode); + if (em == ATOM_ENCODER_MODE_HDMI) { + dce_v6_0_audio_set_dto(encoder, mode->clock); + dce_v6_0_audio_set_vbi_packet(encoder); + dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); + } else if (ENCODER_MODE_IS_DP(em)) { + dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); + } + dce_v6_0_audio_set_packet(encoder); + dce_v6_0_audio_select_pin(encoder); + dce_v6_0_audio_set_avi_infoframe(encoder, mode); + dce_v6_0_audio_set_mute(encoder, false); + if (em == ATOM_ENCODER_MODE_HDMI) { + dce_v6_0_audio_hdmi_enable(encoder, 1); + } else if (ENCODER_MODE_IS_DP(em)) { + dce_v6_0_audio_dp_enable(encoder, 1); + } + + /* enable audio after setting up hw */ + dce_v6_0_audio_enable(adev, dig->afmt->pin, true); } static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) @@ -1362,6 +1861,7 @@ static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) /* Silent, r600_hdmi_enable will raise WARN for us */ if (enable && dig->afmt->enabled) return; + if (!enable && !dig->afmt->enabled) return; @@ -2756,6 +3256,7 @@ dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); amdgpu_encoder->pixel_clock = adjusted_mode->clock; @@ -2765,7 +3266,7 @@ dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, /* set scaler clears this on some chips */ dce_v6_0_set_interleave(encoder->crtc, mode); - if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { + if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { dce_v6_0_afmt_enable(encoder, true); dce_v6_0_afmt_setmode(encoder, adjusted_mode); } @@ -2827,11 +3328,12 @@ static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig; + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); if (amdgpu_atombios_encoder_is_digital(encoder)) { - if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) + if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) dce_v6_0_afmt_enable(encoder, false); dig = amdgpu_encoder->enc_priv; dig->dig_encoder = -1; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index db30c6ba563a..a9e869554627 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_i2c.h" diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index f1b479b6ac98..90bb08309a53 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_i2c.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index a125f9d44577..5173ca1fd159 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -393,8 +393,11 @@ out: static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) { - const u32 num_tile_mode_states = 32; - u32 reg_offset, gb_tile_moden, split_equal_to_row_size; + const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); + u32 reg_offset, split_equal_to_row_size, *tilemode; + + memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); + tilemode = adev->gfx.config.tile_mode_array; switch (adev->gfx.config.mem_row_size_in_kb) { case 1: @@ -410,887 +413,680 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) } if (adev->asic_type == CHIP_VERDE) { - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { - switch (reg_offset) { - case 0: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 1: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 2: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 3: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 4: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16)); - break; - case 5: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 6: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 7: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 8: - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); - break; - case 9: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16)); - break; - case 10: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 11: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 12: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 13: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16)); - break; - case 14: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 15: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 16: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 17: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 18: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P4_8x16)); - break; - case 19: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 20: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 21: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 22: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 23: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 24: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 25: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 26: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 27: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 28: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 29: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 30: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - default: - continue; - } - adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); - } - } else if (adev->asic_type == CHIP_OLAND || - adev->asic_type == CHIP_HAINAN) { - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { - switch (reg_offset) { - case 0: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 1: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 2: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 3: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 4: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2)); - break; - case 5: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 6: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 7: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 8: - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); - break; - case 9: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2)); - break; - case 10: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 11: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 12: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 13: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2)); - break; - case 14: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 15: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 16: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 17: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 18: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P2)); - break; - case 19: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | - PIPE_CONFIG(ADDR_SURF_P2) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 20: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P2) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 21: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 22: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 23: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 24: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_8_BANK)); - break; - case 25: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 26: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 27: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 28: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 29: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 30: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P2) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - default: - continue; - } - adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); - } + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); + tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); + } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2); + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2); + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2); + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2); + tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK); + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { - switch (reg_offset) { - case 0: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 1: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 2: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 3: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 4: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); - break; - case 5: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 6: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 7: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 8: - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); - break; - case 9: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); - break; - case 10: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 11: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 12: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 13: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); - break; - case 14: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 15: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 16: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK)); - break; - case 17: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 18: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_1D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); - break; - case 19: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 20: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THICK) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_16_BANK) | - TILE_SPLIT(split_equal_to_row_size)); - break; - case 21: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 22: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_4_BANK)); - break; - case 23: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 24: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 25: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 26: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 27: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 28: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 29: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - case 30: - gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | - ARRAY_MODE(ARRAY_2D_TILED_THIN1) | - PIPE_CONFIG(ADDR_SURF_P4_8x16) | - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | - NUM_BANKS(ADDR_SURF_2_BANK)); - break; - default: - continue; - } - adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); - } - } else{ - + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK); + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); + tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK) | + TILE_SPLIT(split_equal_to_row_size); + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK); + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_2_BANK); + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); + } else { DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); } - } static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, @@ -1318,11 +1114,6 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, WREG32(mmGRBM_GFX_INDEX, data); } -static u32 gfx_v6_0_create_bitmask(u32 bit_width) -{ - return (u32)(((u64)1 << bit_width) - 1); -} - static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) { u32 data, mask; @@ -1332,8 +1123,8 @@ static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); - mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/ - adev->gfx.config.max_sh_per_se); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ + adev->gfx.config.max_sh_per_se); return ~data & mask; } @@ -1399,11 +1190,10 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; - if (!se_mask[idx]) { + if (!se_mask[idx]) raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; - } else { + else raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; - } } pkr0_mask &= rb_mask; @@ -1411,11 +1201,10 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; - if (!pkr0_mask) { + if (!pkr0_mask) raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; - } else { + else raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; - } } if (rb_per_se >= 2) { @@ -1427,13 +1216,12 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, if (!rb0_mask || !rb1_mask) { raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; - if (!rb0_mask) { + if (!rb0_mask) raster_config_se |= RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; - } else { + else raster_config_se |= RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; - } } if (rb_per_se > 2) { @@ -1444,13 +1232,12 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, if (!rb0_mask || !rb1_mask) { raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; - if (!rb0_mask) { + if (!rb0_mask) raster_config_se |= RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; - } else { + else raster_config_se |= RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; - } } } } @@ -1479,8 +1266,9 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); data = gfx_v6_0_get_rb_active_bitmap(adev); - active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * - rb_bitmap_width_per_sh); + active_rbs |= data << + ((i * adev->gfx.config.max_sh_per_se + j) * + rb_bitmap_width_per_sh); } } gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -1494,13 +1282,12 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) gfx_v6_0_raster_config(adev, &raster_config); if (!adev->gfx.config.backend_enable_mask || - adev->gfx.config.num_rbs >= num_rb_pipes) { + adev->gfx.config.num_rbs >= num_rb_pipes) WREG32(mmPA_SC_RASTER_CONFIG, raster_config); - } else { + else gfx_v6_0_write_harvested_raster_configs(adev, raster_config, adev->gfx.config.backend_enable_mask, num_rb_pipes); - } /* cache the values for userspace */ for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { @@ -1517,11 +1304,6 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); } -/* -static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev) -{ -} -*/ static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap) @@ -1544,7 +1326,7 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); - mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; } @@ -1688,7 +1470,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); - mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); + adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); + mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; adev->gfx.config.mem_max_burst_length_bytes = 256; @@ -3719,6 +3502,12 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; unsigned disable_masks[4 * 2]; + u32 ao_cu_num; + + if (adev->flags & AMD_IS_APU) + ao_cu_num = 2; + else + ao_cu_num = adev->gfx.config.max_cu_per_sh; memset(cu_info, 0, sizeof(*cu_info)); @@ -3737,16 +3526,18 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) bitmap = gfx_v6_0_get_cu_enabled(adev); cu_info->bitmap[i][j] = bitmap; - for (k = 0; k < 16; k++) { + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { if (bitmap & mask) { - if (counter < 2) + if (counter < ao_cu_num) ao_bitmap |= mask; counter ++; } mask <<= 1; } active_cu_number += counter; - ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + if (i < 2 && j < 2) + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + cu_info->ao_cu_bitmap[i][j] = ao_bitmap; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index ee2f2139e2eb..37b45e4403d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -21,12 +21,13 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "amdgpu_gfx.h" #include "cikd.h" #include "cik.h" +#include "cik_structs.h" #include "atom.h" #include "amdgpu_ucode.h" #include "clearstate_ci.h" @@ -48,7 +49,7 @@ #include "oss/oss_2_0_sh_mask.h" #define GFX7_NUM_GFX_RINGS 1 -#define GFX7_NUM_COMPUTE_RINGS 8 +#define GFX7_MEC_HPD_SIZE 2048 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); @@ -1607,19 +1608,6 @@ static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, } /** - * gfx_v7_0_create_bitmask - create a bitmask - * - * @bit_width: length of the mask - * - * create a variable length bit mask (CIK). - * Returns the bitmask. - */ -static u32 gfx_v7_0_create_bitmask(u32 bit_width) -{ - return (u32)((1ULL << bit_width) - 1); -} - -/** * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs * * @adev: amdgpu_device pointer @@ -1637,8 +1625,8 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; - mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / - adev->gfx.config.max_sh_per_se); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se); return (~data) & mask; } @@ -1837,7 +1825,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) /** * gmc_v7_0_init_compute_vmid - gart enable * - * @rdev: amdgpu_device pointer + * @adev: amdgpu_device pointer * * Initialize compute vmid sh_mem registers * @@ -2821,26 +2809,23 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) } } -#define MEC_HPD_SIZE 2048 - static int gfx_v7_0_mec_init(struct amdgpu_device *adev) { int r; u32 *hpd; + size_t mec_hpd_size; - /* - * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total - * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total - * Nonetheless, we assign only 1 pipe because all other pipes will - * be handled by KFD - */ - adev->gfx.mec.num_mec = 1; - adev->gfx.mec.num_pipe = 1; - adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + + /* take ownership of the relevant compute queues */ + amdgpu_gfx_compute_queue_acquire(adev); + /* allocate space for ALL pipes (even the ones we don't own) */ + mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec + * GFX7_MEC_HPD_SIZE * 2; if (adev->gfx.mec.hpd_eop_obj == NULL) { r = amdgpu_bo_create(adev, - adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, + mec_hpd_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, &adev->gfx.mec.hpd_eop_obj); @@ -2870,7 +2855,7 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) } /* clear memory. Not sure if this is required or not */ - memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); + memset(hpd, 0, mec_hpd_size); amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); @@ -2917,275 +2902,296 @@ struct hqd_registers u32 cp_mqd_control; }; -struct bonaire_mqd +static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, + int mec, int pipe) { - u32 header; - u32 dispatch_initiator; - u32 dimensions[3]; - u32 start_idx[3]; - u32 num_threads[3]; - u32 pipeline_stat_enable; - u32 perf_counter_enable; - u32 pgm[2]; - u32 tba[2]; - u32 tma[2]; - u32 pgm_rsrc[2]; - u32 vmid; - u32 resource_limits; - u32 static_thread_mgmt01[2]; - u32 tmp_ring_size; - u32 static_thread_mgmt23[2]; - u32 restart[3]; - u32 thread_trace_enable; - u32 reserved1; - u32 user_data[16]; - u32 vgtcs_invoke_count[2]; - struct hqd_registers queue_state; - u32 dequeue_cntr; - u32 interrupt_queue[64]; -}; - -/** - * gfx_v7_0_cp_compute_resume - setup the compute queue registers - * - * @adev: amdgpu_device pointer - * - * Program the compute queues and test them to make sure they - * are working. - * Returns 0 for success, error for failure. - */ -static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) -{ - int r, i, j; - u32 tmp; - bool use_doorbell = true; - u64 hqd_gpu_addr; - u64 mqd_gpu_addr; u64 eop_gpu_addr; - u64 wb_gpu_addr; - u32 *buf; - struct bonaire_mqd *mqd; - struct amdgpu_ring *ring; - - /* fix up chicken bits */ - tmp = RREG32(mmCP_CPF_DEBUG); - tmp |= (1 << 23); - WREG32(mmCP_CPF_DEBUG, tmp); + u32 tmp; + size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) + * GFX7_MEC_HPD_SIZE * 2; - /* init the pipes */ mutex_lock(&adev->srbm_mutex); - for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { - int me = (i < 4) ? 1 : 2; - int pipe = (i < 4) ? i : (i - 4); + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); + cik_srbm_select(adev, mec + 1, pipe, 0, 0); - cik_srbm_select(adev, me, pipe, 0, 0); + /* write the EOP addr */ + WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); + WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); - /* write the EOP addr */ - WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); - WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); + /* set the VMID assigned */ + WREG32(mmCP_HPD_EOP_VMID, 0); - /* set the VMID assigned */ - WREG32(mmCP_HPD_EOP_VMID, 0); + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(mmCP_HPD_EOP_CONTROL); + tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; + tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); + WREG32(mmCP_HPD_EOP_CONTROL, tmp); - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32(mmCP_HPD_EOP_CONTROL); - tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; - tmp |= order_base_2(MEC_HPD_SIZE / 8); - WREG32(mmCP_HPD_EOP_CONTROL, tmp); - } cik_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); +} - /* init the queues. Just two for now. */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; +static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) +{ + int i; - if (ring->mqd_obj == NULL) { - r = amdgpu_bo_create(adev, - sizeof(struct bonaire_mqd), - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &ring->mqd_obj); - if (r) { - dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); - return r; - } + /* disable the queue if it's active */ + if (RREG32(mmCP_HQD_ACTIVE) & 1) { + WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); } - r = amdgpu_bo_reserve(ring->mqd_obj, false); - if (unlikely(r != 0)) { - gfx_v7_0_cp_compute_fini(adev); - return r; - } - r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, - &mqd_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); - gfx_v7_0_cp_compute_fini(adev); - return r; - } - r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); - if (r) { - dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); - gfx_v7_0_cp_compute_fini(adev); - return r; - } + if (i == adev->usec_timeout) + return -ETIMEDOUT; - /* init the mqd struct */ - memset(buf, 0, sizeof(struct bonaire_mqd)); + WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); + WREG32(mmCP_HQD_PQ_RPTR, 0); + WREG32(mmCP_HQD_PQ_WPTR, 0); + } - mqd = (struct bonaire_mqd *)buf; - mqd->header = 0xC0310800; - mqd->static_thread_mgmt01[0] = 0xffffffff; - mqd->static_thread_mgmt01[1] = 0xffffffff; - mqd->static_thread_mgmt23[0] = 0xffffffff; - mqd->static_thread_mgmt23[1] = 0xffffffff; + return 0; +} - mutex_lock(&adev->srbm_mutex); - cik_srbm_select(adev, ring->me, - ring->pipe, - ring->queue, 0); +static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, + struct cik_mqd *mqd, + uint64_t mqd_gpu_addr, + struct amdgpu_ring *ring) +{ + u64 hqd_gpu_addr; + u64 wb_gpu_addr; - /* disable wptr polling */ - tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); - tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; - WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); + /* init the mqd struct */ + memset(mqd, 0, sizeof(struct cik_mqd)); - /* enable doorbell? */ - mqd->queue_state.cp_hqd_pq_doorbell_control = - RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); - if (use_doorbell) - mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; - else - mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, - mqd->queue_state.cp_hqd_pq_doorbell_control); - - /* disable the queue if it's active */ - mqd->queue_state.cp_hqd_dequeue_request = 0; - mqd->queue_state.cp_hqd_pq_rptr = 0; - mqd->queue_state.cp_hqd_pq_wptr= 0; - if (RREG32(mmCP_HQD_ACTIVE) & 1) { - WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); - for (j = 0; j < adev->usec_timeout; j++) { - if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) - break; - udelay(1); - } - WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); - WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); - WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); - } + mqd->header = 0xC0310800; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; - /* set the pointer to the MQD */ - mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; - mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); - WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); - WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); - /* set MQD vmid to 0 */ - mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); - mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; - WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); - - /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ - hqd_gpu_addr = ring->gpu_addr >> 8; - mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; - mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); - WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); - WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); - - /* set up the HQD, this is similar to CP_RB0_CNTL */ - mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); - mqd->queue_state.cp_hqd_pq_control &= - ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | - CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); - - mqd->queue_state.cp_hqd_pq_control |= - order_base_2(ring->ring_size / 8); - mqd->queue_state.cp_hqd_pq_control |= - (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); + /* enable doorbell? */ + mqd->cp_hqd_pq_doorbell_control = + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + if (ring->use_doorbell) + mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + else + mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + + /* set MQD vmid to 0 */ + mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); + mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); + mqd->cp_hqd_pq_control &= + ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | + CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); + + mqd->cp_hqd_pq_control |= + order_base_2(ring->ring_size / 8); + mqd->cp_hqd_pq_control |= + (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); #ifdef __BIG_ENDIAN - mqd->queue_state.cp_hqd_pq_control |= - 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; + mqd->cp_hqd_pq_control |= + 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; #endif - mqd->queue_state.cp_hqd_pq_control &= - ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | + mqd->cp_hqd_pq_control &= + ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); - mqd->queue_state.cp_hqd_pq_control |= - CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | - CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ - WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); - - /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; - mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, - mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); - - /* set the wb address wether it's enabled or not */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; - mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = - upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, - mqd->queue_state.cp_hqd_pq_rptr_report_addr); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); - - /* enable the doorbell if requested */ - if (use_doorbell) { - mqd->queue_state.cp_hqd_pq_doorbell_control = - RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); - mqd->queue_state.cp_hqd_pq_doorbell_control &= - ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; - mqd->queue_state.cp_hqd_pq_doorbell_control |= - (ring->doorbell_index << - CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); - mqd->queue_state.cp_hqd_pq_doorbell_control |= - CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; - mqd->queue_state.cp_hqd_pq_doorbell_control &= - ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | - CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); + mqd->cp_hqd_pq_control |= + CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | + CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ - } else { - mqd->queue_state.cp_hqd_pq_doorbell_control = 0; + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + + /* set the wb address wether it's enabled or not */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + + /* enable the doorbell if requested */ + if (ring->use_doorbell) { + mqd->cp_hqd_pq_doorbell_control = + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + mqd->cp_hqd_pq_doorbell_control &= + ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; + mqd->cp_hqd_pq_doorbell_control |= + (ring->doorbell_index << + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); + mqd->cp_hqd_pq_doorbell_control |= + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + mqd->cp_hqd_pq_doorbell_control &= + ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); + + } else { + mqd->cp_hqd_pq_doorbell_control = 0; + } + + /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + ring->wptr = 0; + mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); + mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + + /* set the vmid for the queue */ + mqd->cp_hqd_vmid = 0; + + /* defaults */ + mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); + mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); + mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); + mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); + mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); + mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); + mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); + mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); + mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); + mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); + mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); + mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); + mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); + mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); + + /* activate the queue */ + mqd->cp_hqd_active = 1; +} + +int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) +{ + uint32_t tmp; + uint32_t mqd_reg; + uint32_t *mqd_data; + + /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ + mqd_data = &mqd->cp_mqd_base_addr_lo; + + /* disable wptr polling */ + tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); + tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); + WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); + + /* program all HQD registers */ + for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) + WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); + + /* activate the HQD */ + for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) + WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); + + return 0; +} + +static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) +{ + int r; + u64 mqd_gpu_addr; + struct cik_mqd *mqd; + struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; + + if (ring->mqd_obj == NULL) { + r = amdgpu_bo_create(adev, + sizeof(struct cik_mqd), + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, + &ring->mqd_obj); + if (r) { + dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); + return r; } - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, - mqd->queue_state.cp_hqd_pq_doorbell_control); + } + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto out; - /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ - ring->wptr = 0; - mqd->queue_state.cp_hqd_pq_wptr = lower_32_bits(ring->wptr); - WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); - mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, + &mqd_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); + goto out_unreserve; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd); + if (r) { + dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); + goto out_unreserve; + } - /* set the vmid for the queue */ - mqd->queue_state.cp_hqd_vmid = 0; - WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); + mutex_lock(&adev->srbm_mutex); + cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - /* activate the queue */ - mqd->queue_state.cp_hqd_active = 1; - WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); + gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); + gfx_v7_0_mqd_deactivate(adev); + gfx_v7_0_mqd_commit(adev, mqd); - cik_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); - amdgpu_bo_kunmap(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); + amdgpu_bo_kunmap(ring->mqd_obj); +out_unreserve: + amdgpu_bo_unreserve(ring->mqd_obj); +out: + return 0; +} - ring->ready = true; +/** + * gfx_v7_0_cp_compute_resume - setup the compute queue registers + * + * @adev: amdgpu_device pointer + * + * Program the compute queues and test them to make sure they + * are working. + * Returns 0 for success, error for failure. + */ +static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) +{ + int r, i, j; + u32 tmp; + struct amdgpu_ring *ring; + + /* fix up chicken bits */ + tmp = RREG32(mmCP_CPF_DEBUG); + tmp |= (1 << 23); + WREG32(mmCP_CPF_DEBUG, tmp); + + /* init all pipes (even the ones we don't own) */ + for (i = 0; i < adev->gfx.mec.num_mec; i++) + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) + gfx_v7_0_compute_pipe_init(adev, i, j); + + /* init the queues */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + r = gfx_v7_0_compute_queue_init(adev, i); + if (r) { + gfx_v7_0_cp_compute_fini(adev); + return r; + } } gfx_v7_0_cp_compute_enable(adev, true); for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; - + ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) ring->ready = false; @@ -3797,6 +3803,9 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) gfx_v7_0_update_rlc(adev, tmp); data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + if (orig != data) + WREG32(mmRLC_CGCG_CGLS_CTRL, data); + } else { gfx_v7_0_enable_gui_idle_interrupt(adev, false); @@ -3806,11 +3815,11 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) RREG32(mmCB_CGTT_SCLK_CTRL); data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); - } - - if (orig != data) - WREG32(mmRLC_CGCG_CGLS_CTRL, data); + if (orig != data) + WREG32(mmRLC_CGCG_CGLS_CTRL, data); + gfx_v7_0_enable_gui_idle_interrupt(adev, true); + } } static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) @@ -4089,7 +4098,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; - mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); return (~data) & mask; } @@ -4470,7 +4479,7 @@ static int gfx_v7_0_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; - adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; + adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; adev->gfx.funcs = &gfx_v7_0_gfx_funcs; adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; gfx_v7_0_set_ring_funcs(adev); @@ -4662,11 +4671,57 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.gb_addr_config = gb_addr_config; } +static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, + int mec, int pipe, int queue) +{ + int r; + unsigned irq_type; + struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; + + /* mec0 is me1 */ + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; + sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); + + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + + ring->pipe; + + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024, + &adev->gfx.eop_irq, irq_type); + if (r) + return r; + + + return 0; +} + static int gfx_v7_0_sw_init(void *handle) { struct amdgpu_ring *ring; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int i, r; + int i, j, k, r, ring_id; + + switch (adev->asic_type) { + case CHIP_KAVERI: + adev->gfx.mec.num_mec = 2; + break; + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KABINI: + case CHIP_MULLINS: + default: + adev->gfx.mec.num_mec = 1; + break; + } + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 8; /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); @@ -4716,29 +4771,23 @@ static int gfx_v7_0_sw_init(void *handle) return r; } - /* set up the compute queues */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - unsigned irq_type; - - /* max 32 queues per MEC */ - if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { - DRM_ERROR("Too many (%d) compute rings!\n", i); - break; + /* set up the compute queues - allocate horizontally across pipes */ + ring_id = 0; + for (i = 0; i < adev->gfx.mec.num_mec; ++i) { + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { + if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) + continue; + + r = gfx_v7_0_compute_ring_init(adev, + ring_id, + i, k, j); + if (r) + return r; + + ring_id++; + } } - ring = &adev->gfx.compute_ring[i]; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; - ring->me = 1; /* first MEC */ - ring->pipe = i / 8; - ring->queue = i % 8; - sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); - irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; - /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024, - &adev->gfx.eop_irq, irq_type); - if (r) - return r; } /* reserve GDS, GWS and OA resource for gfx */ @@ -4969,8 +5018,8 @@ static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, u32 mec_int_cntl, mec_int_cntl_reg; /* - * amdgpu controls only pipe 0 of MEC1. That's why this function only - * handles the setting of interrupts for this specific pipe. All other + * amdgpu controls only the first MEC. That's why this function only + * handles the setting of interrupts for this specific MEC. All other * pipes' interrupts are set by amdkfd. */ @@ -4979,6 +5028,15 @@ static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, case 0: mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; break; + case 1: + mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; + break; + case 2: + mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; + break; + case 3: + mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; + break; default: DRM_DEBUG("invalid pipe %d\n", pipe); return; @@ -5336,6 +5394,12 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; unsigned disable_masks[4 * 2]; + u32 ao_cu_num; + + if (adev->flags & AMD_IS_APU) + ao_cu_num = 2; + else + ao_cu_num = adev->gfx.config.max_cu_per_sh; memset(cu_info, 0, sizeof(*cu_info)); @@ -5354,16 +5418,18 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) bitmap = gfx_v7_0_get_cu_active_bitmap(adev); cu_info->bitmap[i][j] = bitmap; - for (k = 0; k < 16; k ++) { + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { if (bitmap & mask) { - if (counter < 2) + if (counter < ao_cu_num) ao_bitmap |= mask; counter ++; } mask <<= 1; } active_cu_number += counter; - ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + if (i < 2 && j < 2) + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + cu_info->ao_cu_bitmap[i][j] = ao_bitmap; } } gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h index 2f5164cc0e53..6fb9c1524691 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h @@ -29,4 +29,9 @@ extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block; extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block; extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block; +struct amdgpu_device; +struct cik_mqd; + +int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 758d636a6f52..aa5a50f5eac8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -21,7 +21,7 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_gfx.h" #include "vi.h" @@ -40,7 +40,6 @@ #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" - #include "gca/gfx_8_0_d.h" #include "gca/gfx_8_0_enum.h" #include "gca/gfx_8_0_sh_mask.h" @@ -52,7 +51,7 @@ #include "smu/smu_7_1_3_d.h" #define GFX8_NUM_GFX_RINGS 1 -#define GFX8_NUM_COMPUTE_RINGS 8 +#define GFX8_MEC_HPD_SIZE 2048 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 @@ -657,10 +656,8 @@ static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); -static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t addr); -static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t addr); -static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev); -static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev); +static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring); +static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring); static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) { @@ -859,7 +856,8 @@ err1: } -static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) { +static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) +{ release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -941,12 +939,6 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); - /* chain ib ucode isn't formal released, just disable it by far - * TODO: when ucod ready we should use ucode version to judge if - * chain-ib support or not. - */ - adev->virt.chained_ib_support = false; - adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); @@ -960,6 +952,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + /* + * Support for MCBP/Virtualization in combination with chained IBs is + * formal released on feature version #46 + */ + if (adev->gfx.ce_feature_version >= 46 && + adev->gfx.pfp_feature_version >= 46) { + adev->virt.chained_ib_support = true; + DRM_INFO("Chained IB support enabled!\n"); + } else + adev->virt.chained_ib_support = false; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); if (err) @@ -1373,64 +1376,22 @@ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) } } -static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev, - struct amdgpu_ring *ring, - struct amdgpu_irq_src *irq) -{ - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - int r = 0; - - r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); - if (r) - return r; - - ring->adev = NULL; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_KIQ; - if (adev->gfx.mec2_fw) { - ring->me = 2; - ring->pipe = 0; - } else { - ring->me = 1; - ring->pipe = 1; - } - - ring->queue = 0; - ring->eop_gpu_addr = kiq->eop_gpu_addr; - sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); - r = amdgpu_ring_init(adev, ring, 1024, - irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); - if (r) - dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); - - return r; -} -static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring, - struct amdgpu_irq_src *irq) -{ - amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); - amdgpu_ring_fini(ring); -} - -#define MEC_HPD_SIZE 2048 - static int gfx_v8_0_mec_init(struct amdgpu_device *adev) { int r; u32 *hpd; + size_t mec_hpd_size; - /* - * we assign only 1 pipe because all other pipes will - * be handled by KFD - */ - adev->gfx.mec.num_mec = 1; - adev->gfx.mec.num_pipe = 1; - adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + + /* take ownership of the relevant compute queues */ + amdgpu_gfx_compute_queue_acquire(adev); + + mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; if (adev->gfx.mec.hpd_eop_obj == NULL) { r = amdgpu_bo_create(adev, - adev->gfx.mec.num_queue * MEC_HPD_SIZE, + mec_hpd_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, &adev->gfx.mec.hpd_eop_obj); @@ -1459,7 +1420,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) return r; } - memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE); + memset(hpd, 0, mec_hpd_size); amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); @@ -1467,38 +1428,6 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) return 0; } -static void gfx_v8_0_kiq_fini(struct amdgpu_device *adev) -{ - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - - amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); -} - -static int gfx_v8_0_kiq_init(struct amdgpu_device *adev) -{ - int r; - u32 *hpd; - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - - r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, - &kiq->eop_gpu_addr, (void **)&hpd); - if (r) { - dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); - return r; - } - - memset(hpd, 0, MEC_HPD_SIZE); - - r = amdgpu_bo_reserve(kiq->eop_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); - amdgpu_bo_kunmap(kiq->eop_obj); - amdgpu_bo_unreserve(kiq->eop_obj); - - return 0; -} - static const u32 vgpr_init_compute_shader[] = { 0x7e000209, 0x7e020208, @@ -1907,46 +1836,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_tile_pipes = 2; adev->gfx.config.max_sh_per_se = 1; adev->gfx.config.max_backends_per_se = 2; - - switch (adev->pdev->revision) { - case 0xc4: - case 0x84: - case 0xc8: - case 0xcc: - case 0xe1: - case 0xe3: - /* B10 */ - adev->gfx.config.max_cu_per_sh = 8; - break; - case 0xc5: - case 0x81: - case 0x85: - case 0xc9: - case 0xcd: - case 0xe2: - case 0xe4: - /* B8 */ - adev->gfx.config.max_cu_per_sh = 6; - break; - case 0xc6: - case 0xca: - case 0xce: - case 0x88: - case 0xe6: - /* B6 */ - adev->gfx.config.max_cu_per_sh = 6; - break; - case 0xc7: - case 0x87: - case 0xcb: - case 0xe5: - case 0x89: - default: - /* B4 */ - adev->gfx.config.max_cu_per_sh = 4; - break; - } - + adev->gfx.config.max_cu_per_sh = 8; adev->gfx.config.max_texture_channel_caches = 2; adev->gfx.config.max_gprs = 256; adev->gfx.config.max_gs_threads = 32; @@ -1963,35 +1853,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_tile_pipes = 2; adev->gfx.config.max_sh_per_se = 1; adev->gfx.config.max_backends_per_se = 1; - - switch (adev->pdev->revision) { - case 0x80: - case 0x81: - case 0xc0: - case 0xc1: - case 0xc2: - case 0xc4: - case 0xc8: - case 0xc9: - case 0xd6: - case 0xda: - case 0xe9: - case 0xea: - adev->gfx.config.max_cu_per_sh = 3; - break; - case 0x83: - case 0xd0: - case 0xd1: - case 0xd2: - case 0xd4: - case 0xdb: - case 0xe1: - case 0xe2: - default: - adev->gfx.config.max_cu_per_sh = 2; - break; - } - + adev->gfx.config.max_cu_per_sh = 3; adev->gfx.config.max_texture_channel_caches = 2; adev->gfx.config.max_gprs = 256; adev->gfx.config.max_gs_threads = 16; @@ -2083,13 +1945,67 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) return 0; } +static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, + int mec, int pipe, int queue) +{ + int r; + unsigned irq_type; + struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; + + ring = &adev->gfx.compute_ring[ring_id]; + + /* mec0 is me1 */ + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + + (ring_id * GFX8_MEC_HPD_SIZE); + sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); + + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + + ring->pipe; + + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024, + &adev->gfx.eop_irq, irq_type); + if (r) + return r; + + + return 0; +} + static int gfx_v8_0_sw_init(void *handle) { - int i, r; + int i, j, k, r, ring_id; struct amdgpu_ring *ring; struct amdgpu_kiq *kiq; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + switch (adev->asic_type) { + case CHIP_FIJI: + case CHIP_TONGA: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + case CHIP_POLARIS10: + case CHIP_CARRIZO: + adev->gfx.mec.num_mec = 2; + break; + case CHIP_TOPAZ: + case CHIP_STONEY: + default: + adev->gfx.mec.num_mec = 1; + break; + } + + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 8; + /* KIQ event */ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq); if (r) @@ -2151,49 +2067,41 @@ static int gfx_v8_0_sw_init(void *handle) return r; } - /* set up the compute queues */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - unsigned irq_type; - /* max 32 queues per MEC */ - if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { - DRM_ERROR("Too many (%d) compute rings!\n", i); - break; + /* set up the compute queues - allocate horizontally across pipes */ + ring_id = 0; + for (i = 0; i < adev->gfx.mec.num_mec; ++i) { + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { + if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) + continue; + + r = gfx_v8_0_compute_ring_init(adev, + ring_id, + i, k, j); + if (r) + return r; + + ring_id++; + } } - ring = &adev->gfx.compute_ring[i]; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; - ring->me = 1; /* first MEC */ - ring->pipe = i / 8; - ring->queue = i % 8; - ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); - sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); - irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; - /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, - irq_type); - if (r) - return r; } - if (amdgpu_sriov_vf(adev)) { - r = gfx_v8_0_kiq_init(adev); - if (r) { - DRM_ERROR("Failed to init KIQ BOs!\n"); - return r; - } + r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE); + if (r) { + DRM_ERROR("Failed to init KIQ BOs!\n"); + return r; + } - kiq = &adev->gfx.kiq; - r = gfx_v8_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); - if (r) - return r; + kiq = &adev->gfx.kiq; + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); + if (r) + return r; - /* create MQD for all compute queues as wel as KIQ for SRIOV case */ - r = gfx_v8_0_compute_mqd_sw_init(adev); - if (r) - return r; - } + /* create MQD for all compute queues as well as KIQ for SRIOV case */ + r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation)); + if (r) + return r; /* reserve GDS, GWS and OA resource for gfx */ r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, @@ -2237,11 +2145,9 @@ static int gfx_v8_0_sw_fini(void *handle) for (i = 0; i < adev->gfx.num_compute_rings; i++) amdgpu_ring_fini(&adev->gfx.compute_ring[i]); - if (amdgpu_sriov_vf(adev)) { - gfx_v8_0_compute_mqd_sw_fini(adev); - gfx_v8_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); - gfx_v8_0_kiq_fini(adev); - } + amdgpu_gfx_compute_mqd_sw_fini(adev); + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); + amdgpu_gfx_kiq_fini(adev); gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); @@ -3594,11 +3500,6 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, WREG32(mmGRBM_GFX_INDEX, data); } -static u32 gfx_v8_0_create_bitmask(u32 bit_width) -{ - return (u32)((1ULL << bit_width) - 1); -} - static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) { u32 data, mask; @@ -3608,8 +3509,8 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); - mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se / - adev->gfx.config.max_sh_per_se); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se); return (~data) & mask; } @@ -3823,7 +3724,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) /** * gfx_v8_0_init_compute_vmid - gart enable * - * @rdev: amdgpu_device pointer + * @adev: amdgpu_device pointer * * Initialize compute vmid sh_mem registers * @@ -4481,6 +4382,39 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) return 0; } +static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ + u32 tmp; + /* no gfx doorbells on iceland */ + if (adev->asic_type == CHIP_TOPAZ) + return; + + tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); + + if (ring->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_EN, 1); + } else { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); + } + + WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); + + if (adev->flags & AMD_IS_APU) + return; + + tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, + DOORBELL_RANGE_LOWER, + AMDGPU_DOORBELL_GFX_RING0); + WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); + + WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, + CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); +} static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) { @@ -4528,34 +4462,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmCP_RB0_BASE, rb_addr); WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); - /* no gfx doorbells on iceland */ - if (adev->asic_type != CHIP_TOPAZ) { - tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); - if (ring->use_doorbell) { - tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, - DOORBELL_OFFSET, ring->doorbell_index); - tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, - DOORBELL_HIT, 0); - tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, - DOORBELL_EN, 1); - } else { - tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, - DOORBELL_EN, 0); - } - WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); - - if (adev->asic_type == CHIP_TONGA) { - tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, - DOORBELL_RANGE_LOWER, - AMDGPU_DOORBELL_GFX_RING0); - WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); - - WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, - CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); - } - - } - + gfx_v8_0_set_cpg_door_bell(adev, ring); /* start the ring */ amdgpu_ring_clear_ring(ring); gfx_v8_0_cp_gfx_start(adev); @@ -4628,29 +4535,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) return 0; } -static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) -{ - int i, r; - - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - - if (ring->mqd_obj) { - r = amdgpu_bo_reserve(ring->mqd_obj, false); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); - - amdgpu_bo_unpin(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); - - amdgpu_bo_unref(&ring->mqd_obj); - ring->mqd_obj = NULL; - ring->mqd_ptr = NULL; - ring->mqd_gpu_addr = 0; - } - } -} - /* KIQ functions */ static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring) { @@ -4666,45 +4550,111 @@ static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring) WREG32(mmRLC_CP_SCHEDULERS, tmp); } -static void gfx_v8_0_kiq_enable(struct amdgpu_ring *ring) +static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) { - amdgpu_ring_alloc(ring, 8); + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t scratch, tmp = 0; + uint64_t queue_mask = 0; + int r, i; + + for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { + if (!test_bit(i, adev->gfx.mec.queue_bitmap)) + continue; + + /* This situation may be hit in the future if a new HW + * generation exposes more than 64 queues. If so, the + * definition of queue_mask needs updating */ + if (WARN_ON(i > (sizeof(queue_mask)*8))) { + DRM_ERROR("Invalid KCQ enabled: %d\n", i); + break; + } + + queue_mask |= (1ull << i); + } + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("Failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + + r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11); + if (r) { + DRM_ERROR("Failed to lock KIQ (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } /* set resources */ - amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); - amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ - amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ - amdgpu_ring_write(ring, 0); /* queue mask hi */ - amdgpu_ring_write(ring, 0); /* gws mask lo */ - amdgpu_ring_write(ring, 0); /* gws mask hi */ - amdgpu_ring_write(ring, 0); /* oac mask */ - amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ - amdgpu_ring_commit(ring); - udelay(50); + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); + amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ + amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ + amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* oac mask */ + amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); + uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + + /* map queues */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); + /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ + amdgpu_ring_write(kiq_ring, + PACKET3_MAP_QUEUES_NUM_QUEUES(1)); + amdgpu_ring_write(kiq_ring, + PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) | + PACKET3_MAP_QUEUES_QUEUE(ring->queue) | + PACKET3_MAP_QUEUES_PIPE(ring->pipe) | + PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */ + amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); + } + /* write to scratch for completion */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(kiq_ring, 0xDEADBEEF); + amdgpu_ring_commit(kiq_ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i >= adev->usec_timeout) { + DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + + return r; } -static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring, - struct amdgpu_ring *ring) +static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) { - struct amdgpu_device *adev = kiq_ring->adev; - uint64_t mqd_addr, wptr_addr; + int i, r = 0; - mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); - wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - amdgpu_ring_alloc(kiq_ring, 8); + if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { + WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) + break; + udelay(1); + } + if (i == adev->usec_timeout) + r = -ETIMEDOUT; + } + WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); + WREG32(mmCP_HQD_PQ_RPTR, 0); + WREG32(mmCP_HQD_PQ_WPTR, 0); - amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); - /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ - amdgpu_ring_write(kiq_ring, 0x21010000); - amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2) | - (ring->queue << 26) | - (ring->pipe << 29) | - ((ring->me == 1 ? 0 : 1) << 31)); /* doorbell */ - amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); - amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); - amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); - amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); - amdgpu_ring_commit(kiq_ring); - udelay(50); + return r; } static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) @@ -4721,7 +4671,12 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) mqd->compute_static_thread_mgmt_se2 = 0xffffffff; mqd->compute_static_thread_mgmt_se3 = 0xffffffff; mqd->compute_misc_reserved = 0x00000003; - + if (!(adev->flags & AMD_IS_APU)) { + mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); + mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); + } eop_base_addr = ring->eop_gpu_addr >> 8; mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); @@ -4729,7 +4684,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ tmp = RREG32(mmCP_HQD_EOP_CONTROL); tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, - (order_base_2(MEC_HPD_SIZE / 4) - 1)); + (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1)); mqd->cp_hqd_eop_control = tmp; @@ -4741,11 +4696,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) mqd->cp_hqd_pq_doorbell_control = tmp; - /* disable the queue if it's active */ - mqd->cp_hqd_dequeue_request = 0; - mqd->cp_hqd_pq_rptr = 0; - mqd->cp_hqd_pq_wptr = 0; - /* set the pointer to the MQD */ mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); @@ -4815,149 +4765,160 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); mqd->cp_hqd_persistent_state = tmp; + /* set MTYPE */ + tmp = RREG32(mmCP_HQD_IB_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); + tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3); + mqd->cp_hqd_ib_control = tmp; + + tmp = RREG32(mmCP_HQD_IQ_TIMER); + tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3); + mqd->cp_hqd_iq_timer = tmp; + + tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3); + mqd->cp_hqd_ctx_save_control = tmp; + + /* defaults */ + mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR); + mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR); + mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); + mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO); + mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI); + mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET); + mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE); + mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); + mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE); + mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS); + mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR); + mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM); + mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES); + /* activate the queue */ mqd->cp_hqd_active = 1; return 0; } -static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring) +int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, + struct vi_mqd *mqd) { - struct amdgpu_device *adev = ring->adev; - struct vi_mqd *mqd = ring->mqd_ptr; - int j; + uint32_t mqd_reg; + uint32_t *mqd_data; + + /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */ + mqd_data = &mqd->cp_mqd_base_addr_lo; /* disable wptr polling */ WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); - WREG32(mmCP_HQD_EOP_BASE_ADDR, mqd->cp_hqd_eop_base_addr_lo); - WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, mqd->cp_hqd_eop_base_addr_hi); + /* program all HQD registers */ + for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++) + WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - WREG32(mmCP_HQD_EOP_CONTROL, mqd->cp_hqd_eop_control); - - /* enable doorbell? */ - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control); - - /* disable the queue if it's active */ - if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { - WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); - for (j = 0; j < adev->usec_timeout; j++) { - if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) - break; - udelay(1); - } - WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); - WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); - WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); + /* Tonga errata: EOP RPTR/WPTR should be left unmodified. + * This is safe since EOP RPTR==WPTR for any inactive HQD + * on ASICs that do not support context-save. + * EOP writes/reads can start anywhere in the ring. + */ + if (adev->asic_type != CHIP_TONGA) { + WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr); + WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr); + WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem); } - /* set the pointer to the MQD */ - WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); - WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); - - /* set MQD vmid to 0 */ - WREG32(mmCP_MQD_CONTROL, mqd->cp_mqd_control); + for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++) + WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); - /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ - WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); - WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); + /* activate the HQD */ + for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) + WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); - /* set up the HQD, this is similar to CP_RB0_CNTL */ - WREG32(mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); - - /* set the wb address whether it's enabled or not */ - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, - mqd->cp_hqd_pq_rptr_report_addr_lo); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - mqd->cp_hqd_pq_rptr_report_addr_hi); - - /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo); - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi); - - /* enable the doorbell if requested */ - if (ring->use_doorbell) { - if ((adev->asic_type == CHIP_CARRIZO) || - (adev->asic_type == CHIP_FIJI) || - (adev->asic_type == CHIP_STONEY)) { - WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, - AMDGPU_DOORBELL_KIQ << 2); - WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, - AMDGPU_DOORBELL_MEC_RING7 << 2); - } - } - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control); + return 0; +} - /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ - WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); +static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct vi_mqd *mqd = ring->mqd_ptr; + int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; - /* set the vmid for the queue */ - WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); + gfx_v8_0_kiq_setting(ring); - WREG32(mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); + if (adev->gfx.in_reset) { /* for GPU_RESET case */ + /* reset MQD to a clean status */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); - /* activate the queue */ - WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); + /* reset ring buffer */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_mqd_commit(adev, mqd); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } else { + memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); + ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_mqd_init(ring); + gfx_v8_0_mqd_commit(adev, mqd); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); - if (ring->use_doorbell) - WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); + } return 0; } -static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) +static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct vi_mqd *mqd = ring->mqd_ptr; - bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); - int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; + int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (is_kiq) { - gfx_v8_0_kiq_setting(&kiq->ring); - } else { - mqd_idx = ring - &adev->gfx.compute_ring[0]; - } - - if (!adev->gfx.in_reset) { - memset((void *)mqd, 0, sizeof(*mqd)); + if (!adev->gfx.in_reset && !adev->gfx.in_suspend) { + memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); + ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; mutex_lock(&adev->srbm_mutex); vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v8_0_mqd_init(ring); - if (is_kiq) - gfx_v8_0_kiq_init_register(ring); vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); - } else { /* for GPU_RESET case */ + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); + } else if (adev->gfx.in_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); - + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); /* reset ring buffer */ ring->wptr = 0; amdgpu_ring_clear_ring(ring); - - if (is_kiq) { - mutex_lock(&adev->srbm_mutex); - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v8_0_kiq_init_register(ring); - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - } + } else { + amdgpu_ring_clear_ring(ring); } - - if (is_kiq) - gfx_v8_0_kiq_enable(ring); - else - gfx_v8_0_map_queue_enable(&kiq->ring, ring); - return 0; } +static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev) +{ + if (adev->asic_type > CHIP_TONGA) { + WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); + WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2); + } + /* enable doorbells */ + WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); +} + static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) { struct amdgpu_ring *ring = NULL; @@ -4981,13 +4942,6 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) if (r) goto done; - ring->ready = true; - r = amdgpu_ring_test_ring(ring); - if (r) { - ring->ready = false; - goto done; - } - for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; @@ -4996,272 +4950,41 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); if (!r) { - r = gfx_v8_0_kiq_init_queue(ring); + r = gfx_v8_0_kcq_init_queue(ring); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } amdgpu_bo_unreserve(ring->mqd_obj); if (r) goto done; - - ring->ready = true; - r = amdgpu_ring_test_ring(ring); - if (r) - ring->ready = false; } -done: - return r; -} - -static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) -{ - int r, i, j; - u32 tmp; - bool use_doorbell = true; - u64 hqd_gpu_addr; - u64 mqd_gpu_addr; - u64 eop_gpu_addr; - u64 wb_gpu_addr; - u32 *buf; - struct vi_mqd *mqd; - - /* init the queues. */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - - if (ring->mqd_obj == NULL) { - r = amdgpu_bo_create(adev, - sizeof(struct vi_mqd), - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, - NULL, &ring->mqd_obj); - if (r) { - dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(ring->mqd_obj, false); - if (unlikely(r != 0)) { - gfx_v8_0_cp_compute_fini(adev); - return r; - } - r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, - &mqd_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); - gfx_v8_0_cp_compute_fini(adev); - return r; - } - r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); - if (r) { - dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); - gfx_v8_0_cp_compute_fini(adev); - return r; - } - - /* init the mqd struct */ - memset(buf, 0, sizeof(struct vi_mqd)); - - mqd = (struct vi_mqd *)buf; - mqd->header = 0xC0310800; - mqd->compute_pipelinestat_enable = 0x00000001; - mqd->compute_static_thread_mgmt_se0 = 0xffffffff; - mqd->compute_static_thread_mgmt_se1 = 0xffffffff; - mqd->compute_static_thread_mgmt_se2 = 0xffffffff; - mqd->compute_static_thread_mgmt_se3 = 0xffffffff; - mqd->compute_misc_reserved = 0x00000003; - - mutex_lock(&adev->srbm_mutex); - vi_srbm_select(adev, ring->me, - ring->pipe, - ring->queue, 0); - - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); - eop_gpu_addr >>= 8; - - /* write the EOP addr */ - WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); - WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); - - /* set the VMID assigned */ - WREG32(mmCP_HQD_VMID, 0); - - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32(mmCP_HQD_EOP_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, - (order_base_2(MEC_HPD_SIZE / 4) - 1)); - WREG32(mmCP_HQD_EOP_CONTROL, tmp); - - /* disable wptr polling */ - tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); - tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); - WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); - - mqd->cp_hqd_eop_base_addr_lo = - RREG32(mmCP_HQD_EOP_BASE_ADDR); - mqd->cp_hqd_eop_base_addr_hi = - RREG32(mmCP_HQD_EOP_BASE_ADDR_HI); - - /* enable doorbell? */ - tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); - if (use_doorbell) { - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - } else { - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); - } - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); - mqd->cp_hqd_pq_doorbell_control = tmp; - - /* disable the queue if it's active */ - mqd->cp_hqd_dequeue_request = 0; - mqd->cp_hqd_pq_rptr = 0; - mqd->cp_hqd_pq_wptr= 0; - if (RREG32(mmCP_HQD_ACTIVE) & 1) { - WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); - for (j = 0; j < adev->usec_timeout; j++) { - if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) - break; - udelay(1); - } - WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); - WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); - WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); - } - - /* set the pointer to the MQD */ - mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; - mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); - WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); - WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); - - /* set MQD vmid to 0 */ - tmp = RREG32(mmCP_MQD_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); - WREG32(mmCP_MQD_CONTROL, tmp); - mqd->cp_mqd_control = tmp; - - /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ - hqd_gpu_addr = ring->gpu_addr >> 8; - mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; - mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); - WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); - WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); - - /* set up the HQD, this is similar to CP_RB0_CNTL */ - tmp = RREG32(mmCP_HQD_PQ_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, - (order_base_2(ring->ring_size / 4) - 1)); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); -#ifdef __BIG_ENDIAN - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); -#endif - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); - WREG32(mmCP_HQD_PQ_CONTROL, tmp); - mqd->cp_hqd_pq_control = tmp; - - /* set the wb address wether it's enabled or not */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; - mqd->cp_hqd_pq_rptr_report_addr_hi = - upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, - mqd->cp_hqd_pq_rptr_report_addr_lo); - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - mqd->cp_hqd_pq_rptr_report_addr_hi); - - /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; - mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo); - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, - mqd->cp_hqd_pq_wptr_poll_addr_hi); - - /* enable the doorbell if requested */ - if (use_doorbell) { - if ((adev->asic_type == CHIP_CARRIZO) || - (adev->asic_type == CHIP_FIJI) || - (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_POLARIS11) || - (adev->asic_type == CHIP_POLARIS10) || - (adev->asic_type == CHIP_POLARIS12)) { - WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, - AMDGPU_DOORBELL_KIQ << 2); - WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, - AMDGPU_DOORBELL_MEC_RING7 << 2); - } - tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, - DOORBELL_OFFSET, ring->doorbell_index); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); - mqd->cp_hqd_pq_doorbell_control = tmp; - - } else { - mqd->cp_hqd_pq_doorbell_control = 0; - } - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, - mqd->cp_hqd_pq_doorbell_control); + gfx_v8_0_set_mec_doorbell_range(adev); - /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ - ring->wptr = 0; - mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); - WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); - mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); - - /* set the vmid for the queue */ - mqd->cp_hqd_vmid = 0; - WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); - - tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); - tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); - WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); - mqd->cp_hqd_persistent_state = tmp; - if (adev->asic_type == CHIP_STONEY || - adev->asic_type == CHIP_POLARIS11 || - adev->asic_type == CHIP_POLARIS10 || - adev->asic_type == CHIP_POLARIS12) { - tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL); - tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1); - WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp); - } - - /* activate the queue */ - mqd->cp_hqd_active = 1; - WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); - - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - - amdgpu_bo_kunmap(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); - } + r = gfx_v8_0_kiq_kcq_enable(adev); + if (r) + goto done; - if (use_doorbell) { - tmp = RREG32(mmCP_PQ_STATUS); - tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); - WREG32(mmCP_PQ_STATUS, tmp); + /* Test KIQ */ + ring = &adev->gfx.kiq.ring; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; } - gfx_v8_0_cp_compute_enable(adev, true); - + /* Test KCQs */ for (i = 0; i < adev->gfx.num_compute_rings; i++) { - struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - + ring = &adev->gfx.compute_ring[i]; ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) ring->ready = false; } - return 0; +done: + return r; } static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) @@ -5314,10 +5037,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) if (r) return r; - if (amdgpu_sriov_vf(adev)) - r = gfx_v8_0_kiq_resume(adev); - else - r = gfx_v8_0_cp_compute_resume(adev); + r = gfx_v8_0_kiq_resume(adev); if (r) return r; @@ -5361,7 +5081,6 @@ static int gfx_v8_0_hw_fini(void *handle) } gfx_v8_0_cp_enable(adev, false); gfx_v8_0_rlc_stop(adev); - gfx_v8_0_cp_compute_fini(adev); amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); @@ -5372,15 +5091,18 @@ static int gfx_v8_0_hw_fini(void *handle) static int gfx_v8_0_suspend(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - + adev->gfx.in_suspend = true; return gfx_v8_0_hw_fini(adev); } static int gfx_v8_0_resume(void *handle) { + int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - return gfx_v8_0_hw_init(adev); + r = gfx_v8_0_hw_init(adev); + adev->gfx.in_suspend = false; + return r; } static bool gfx_v8_0_is_idle(void *handle) @@ -5469,25 +5191,6 @@ static bool gfx_v8_0_check_soft_reset(void *handle) } } -static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev, - struct amdgpu_ring *ring) -{ - int i; - - mutex_lock(&adev->srbm_mutex); - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { - WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, 2); - for (i = 0; i < adev->usec_timeout; i++) { - if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) - break; - udelay(1); - } - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); -} - static int gfx_v8_0_pre_soft_reset(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -5517,7 +5220,11 @@ static int gfx_v8_0_pre_soft_reset(void *handle) for (i = 0; i < adev->gfx.num_compute_rings; i++) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - gfx_v8_0_inactive_hqd(adev, ring); + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_deactivate_hqd(adev, 2); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); } /* Disable MEC parsing/prefetching */ gfx_v8_0_cp_compute_enable(adev, false); @@ -5588,18 +5295,6 @@ static int gfx_v8_0_soft_reset(void *handle) return 0; } -static void gfx_v8_0_init_hqd(struct amdgpu_device *adev, - struct amdgpu_ring *ring) -{ - mutex_lock(&adev->srbm_mutex); - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); - WREG32(mmCP_HQD_PQ_RPTR, 0); - WREG32(mmCP_HQD_PQ_WPTR, 0); - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); -} - static int gfx_v8_0_post_soft_reset(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -5625,9 +5320,13 @@ static int gfx_v8_0_post_soft_reset(void *handle) for (i = 0; i < adev->gfx.num_compute_rings; i++) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - gfx_v8_0_init_hqd(adev, ring); + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_deactivate_hqd(adev, 2); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); } - gfx_v8_0_cp_compute_resume(adev); + gfx_v8_0_kiq_resume(adev); } gfx_v8_0_rlc_start(adev); @@ -5773,7 +5472,7 @@ static int gfx_v8_0_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; - adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; + adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; adev->gfx.funcs = &gfx_v8_0_gfx_funcs; gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); @@ -6265,6 +5964,8 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); if (temp != data) WREG32(mmRLC_CGCG_CGLS_CTRL, data); + /* enable interrupts again for PG */ + gfx_v8_0_enable_gui_idle_interrupt(adev, true); } gfx_v8_0_wait_for_rlc_serdes(adev); @@ -6568,9 +6269,13 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |= ib->length_dw | (vm_id << 24); - if (amdgpu_sriov_vf(ring->adev) && ib->flags & AMDGPU_IB_FLAG_PREEMPT) + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { control |= INDIRECT_BUFFER_PRE_ENB(1); + if (!(ib->flags & AMDGPU_IB_FLAG_CE)) + gfx_v8_0_ring_emit_de_meta(ring); + } + amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, #ifdef __BIG_ENDIAN @@ -6753,8 +6458,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) uint32_t dw2 = 0; if (amdgpu_sriov_vf(ring->adev)) - gfx_v8_0_ring_emit_ce_meta_init(ring, - (flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr); + gfx_v8_0_ring_emit_ce_meta(ring); dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { @@ -6780,10 +6484,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); amdgpu_ring_write(ring, dw2); amdgpu_ring_write(ring, 0); - - if (amdgpu_sriov_vf(ring->adev)) - gfx_v8_0_ring_emit_de_meta_init(ring, - (flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr); } static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) @@ -6813,7 +6513,6 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne ring->ring[offset] = (ring->ring_size >> 2) - offset + cur; } - static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) { struct amdgpu_device *adev = ring->adev; @@ -6851,15 +6550,27 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) { + u32 mec_int_cntl, mec_int_cntl_reg; + /* - * amdgpu controls only pipe 0 of MEC1. That's why this function only - * handles the setting of interrupts for this specific pipe. All other + * amdgpu controls only the first MEC. That's why this function only + * handles the setting of interrupts for this specific MEC. All other * pipes' interrupts are set by amdkfd. */ if (me == 1) { switch (pipe) { case 0: + mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; + break; + case 1: + mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; + break; + case 2: + mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; + break; + case 3: + mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; break; default: DRM_DEBUG("invalid pipe %d\n", pipe); @@ -6870,8 +6581,20 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, return; } - WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE, - state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + default: + break; + } } static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, @@ -6992,8 +6715,6 @@ static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev, { struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); - BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ); - switch (type) { case AMDGPU_CP_KIQ_IRQ_DRIVER0: WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE, @@ -7023,8 +6744,6 @@ static int gfx_v8_0_kiq_irq(struct amdgpu_device *adev, u8 me_id, pipe_id, queue_id; struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); - BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ); - me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; queue_id = (entry->ring_id & 0x70) >> 4; @@ -7257,7 +6976,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); - mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; } @@ -7268,9 +6987,15 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; unsigned disable_masks[4 * 2]; + u32 ao_cu_num; memset(cu_info, 0, sizeof(*cu_info)); + if (adev->flags & AMD_IS_APU) + ao_cu_num = 2; + else + ao_cu_num = adev->gfx.config.max_cu_per_sh; + amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); @@ -7286,16 +7011,18 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) bitmap = gfx_v8_0_get_cu_active_bitmap(adev); cu_info->bitmap[i][j] = bitmap; - for (k = 0; k < 16; k ++) { + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { if (bitmap & mask) { - if (counter < 2) + if (counter < ao_cu_num) ao_bitmap |= mask; counter ++; } mask <<= 1; } active_cu_number += counter; - ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + if (i < 2 && j < 2) + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + cu_info->ao_cu_bitmap[i][j] = ao_bitmap; } } gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -7323,7 +7050,7 @@ const struct amdgpu_ip_block_version gfx_v8_1_ip_block = .funcs = &gfx_v8_0_ip_funcs, }; -static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t csa_addr) +static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring) { uint64_t ce_payload_addr; int cnt_ce; @@ -7333,10 +7060,12 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c } ce_payload = {}; if (ring->adev->virt.chained_ib_support) { - ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); + ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 + + offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2; } else { - ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, ce_payload); + ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 + + offsetof(struct vi_gfx_meta_data, ce_payload); cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2; } @@ -7350,15 +7079,16 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2); } -static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t csa_addr) +static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring) { - uint64_t de_payload_addr, gds_addr; + uint64_t de_payload_addr, gds_addr, csa_addr; int cnt_de; static union { struct vi_de_ib_state regular; struct vi_de_ib_state_chained_ib chained; } de_payload = {}; + csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; gds_addr = csa_addr + 4096; if (ring->adev->virt.chained_ib_support) { de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr); @@ -7381,68 +7111,3 @@ static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t c amdgpu_ring_write(ring, upper_32_bits(de_payload_addr)); amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2); } - -/* create MQD for each compute queue */ -static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev) -{ - struct amdgpu_ring *ring = NULL; - int r, i; - - /* create MQD for KIQ */ - ring = &adev->gfx.kiq.ring; - if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, sizeof(struct vi_mqd), PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, - &ring->mqd_gpu_addr, &ring->mqd_ptr); - if (r) { - dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); - return r; - } - - /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct vi_mqd), GFP_KERNEL); - if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) - dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); - } - - /* create MQD for each KCQ */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, sizeof(struct vi_mqd), PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, - &ring->mqd_gpu_addr, &ring->mqd_ptr); - if (r) { - dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); - return r; - } - - /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct vi_mqd), GFP_KERNEL); - if (!adev->gfx.mec.mqd_backup[i]) - dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); - } - } - - return 0; -} - -static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev) -{ - struct amdgpu_ring *ring = NULL; - int i; - - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - kfree(adev->gfx.mec.mqd_backup[i]); - amdgpu_bo_free_kernel(&ring->mqd_obj, - &ring->mqd_gpu_addr, - &ring->mqd_ptr); - } - - ring = &adev->gfx.kiq.ring; - kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); - amdgpu_bo_free_kernel(&ring->mqd_obj, - &ring->mqd_gpu_addr, - &ring->mqd_ptr); -} diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h index 788cc3ab584b..ec3f11fa986c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h @@ -27,4 +27,9 @@ extern const struct amdgpu_ip_block_version gfx_v8_0_ip_block; extern const struct amdgpu_ip_block_version gfx_v8_1_ip_block; +struct amdgpu_device; +struct vi_mqd; + +int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, struct vi_mqd *mqd); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 0c16b7563b73..3a0b69b09ed6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -21,7 +21,7 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_gfx.h" #include "soc15.h" @@ -38,8 +38,17 @@ #include "v9_structs.h" #define GFX9_NUM_GFX_RINGS 1 -#define GFX9_NUM_COMPUTE_RINGS 8 -#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000 +#define GFX9_MEC_HPD_SIZE 2048 +#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L +#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L +#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34 + +#define mmPWR_MISC_CNTL_STATUS 0x0183 +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); @@ -48,6 +57,13 @@ MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); +MODULE_FIRMWARE("amdgpu/raven_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven_me.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); + static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), @@ -86,14 +102,27 @@ static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = static const u32 golden_settings_gc_9_0[] = { - SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400, + SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, + SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107, SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, - SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff + SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, + SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff, + SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 }; static const u32 golden_settings_gc_9_0_vg10[] = @@ -104,11 +133,47 @@ static const u32 golden_settings_gc_9_0_vg10[] = SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, - SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800, - SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007 + SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800 +}; + +static const u32 golden_settings_gc_9_1[] = +{ + SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104, + SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, + SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, + SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120, + SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, + SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff, + SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 +}; + +static const u32 golden_settings_gc_9_1_rv1[] = +{ + SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, + SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042, + SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000, + SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, + SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 }; #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 +#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); @@ -118,6 +183,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) { @@ -130,6 +196,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_gc_9_0_vg10, (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); break; + case CHIP_RAVEN: + amdgpu_program_register_sequence(adev, + golden_settings_gc_9_1, + (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); + amdgpu_program_register_sequence(adev, + golden_settings_gc_9_1_rv1, + (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); + break; default: break; } @@ -284,6 +358,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; const struct gfx_firmware_header_v1_0 *cp_hdr; + const struct rlc_firmware_header_v2_0 *rlc_hdr; + unsigned int *tmp = NULL; + unsigned int i = 0; DRM_DEBUG("\n"); @@ -291,6 +368,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) case CHIP_VEGA10: chip_name = "vega10"; break; + case CHIP_RAVEN: + chip_name = "raven"; + break; default: BUG(); } @@ -333,9 +413,46 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); - cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; - adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); - adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); + adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); + adev->gfx.rlc.save_and_restore_offset = + le32_to_cpu(rlc_hdr->save_and_restore_offset); + adev->gfx.rlc.clear_state_descriptor_offset = + le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); + adev->gfx.rlc.avail_scratch_ram_locations = + le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); + adev->gfx.rlc.reg_restore_list_size = + le32_to_cpu(rlc_hdr->reg_restore_list_size); + adev->gfx.rlc.reg_list_format_start = + le32_to_cpu(rlc_hdr->reg_list_format_start); + adev->gfx.rlc.reg_list_format_separate_start = + le32_to_cpu(rlc_hdr->reg_list_format_separate_start); + adev->gfx.rlc.starting_offsets_start = + le32_to_cpu(rlc_hdr->starting_offsets_start); + adev->gfx.rlc.reg_list_format_size_bytes = + le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); + adev->gfx.rlc.reg_list_size_bytes = + le32_to_cpu(rlc_hdr->reg_list_size_bytes); + adev->gfx.rlc.register_list_format = + kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + + adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); + if (!adev->gfx.rlc.register_list_format) { + err = -ENOMEM; + goto out; + } + + tmp = (unsigned int *)((uintptr_t)rlc_hdr + + le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); + for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) + adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); + + adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; + + tmp = (unsigned int *)((uintptr_t)rlc_hdr + + le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); + for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) + adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); @@ -447,6 +564,261 @@ out: return err; } +static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) +{ + u32 count = 0; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + /* begin clear state */ + count += 2; + /* context control state */ + count += 3; + + for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) + count += 2 + ext->reg_count; + else + return 0; + } + } + + /* end clear state */ + count += 2; + /* clear state */ + count += 2; + + return count; +} + +static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, + volatile u32 *buffer) +{ + u32 count = 0, i; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + if (adev->gfx.rlc.cs_data == NULL) + return; + if (buffer == NULL) + return; + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + buffer[count++] = cpu_to_le32(0x80000000); + buffer[count++] = cpu_to_le32(0x80000000); + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + buffer[count++] = + cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); + buffer[count++] = cpu_to_le32(ext->reg_index - + PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + buffer[count++] = cpu_to_le32(ext->extent[i]); + } else { + return; + } + } + } + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); + buffer[count++] = cpu_to_le32(0); +} + +static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) +{ + uint32_t data; + + /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ + WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); + WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); + WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); + WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); + + /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ + WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); + + /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ + WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); + + mutex_lock(&adev->grbm_idx_mutex); + /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); + + /* set mmRLC_LB_PARAMS = 0x003F_1006 */ + data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); + data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); + data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); + WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); + + /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ + data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); + data &= 0x0000FFFF; + data |= 0x00C00000; + WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); + + /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */ + WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF); + + /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, + * but used for RLC_LB_CNTL configuration */ + data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; + data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); + data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); + WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); + mutex_unlock(&adev->grbm_idx_mutex); +} + +static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) +{ + WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); +} + +static void rv_init_cp_jump_table(struct amdgpu_device *adev) +{ + const __le32 *fw_data; + volatile u32 *dst_ptr; + int me, i, max_me = 5; + u32 bo_offset = 0; + u32 table_offset, table_size; + + /* write the cp table buffer */ + dst_ptr = adev->gfx.rlc.cp_table_ptr; + for (me = 0; me < max_me; me++) { + if (me == 0) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; + fw_data = (const __le32 *) + (adev->gfx.ce_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 1) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; + fw_data = (const __le32 *) + (adev->gfx.pfp_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 2) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; + fw_data = (const __le32 *) + (adev->gfx.me_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 3) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 4) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; + fw_data = (const __le32 *) + (adev->gfx.mec2_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } + + for (i = 0; i < table_size; i ++) { + dst_ptr[bo_offset + i] = + cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); + } + + bo_offset += table_size; + } +} + +static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) +{ + /* clear state block */ + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + + /* jump table block */ + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); +} + +static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) +{ + volatile u32 *dst_ptr; + u32 dws; + const struct cs_section_def *cs_data; + int r; + + adev->gfx.rlc.cs_data = gfx9_cs_data; + + cs_data = adev->gfx.rlc.cs_data; + + if (cs_data) { + /* clear state block */ + adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); + if (adev->gfx.rlc.clear_state_obj == NULL) { + r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_err(adev->dev, + "(%d) failed to create rlc csb bo\n", r); + gfx_v9_0_rlc_fini(adev); + return r; + } + } + /* set up the cs buffer */ + dst_ptr = adev->gfx.rlc.cs_ptr; + gfx_v9_0_get_csb_buffer(adev, dst_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + if (adev->asic_type == CHIP_RAVEN) { + /* TODO: double check the cp_table_size for RV */ + adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ + if (adev->gfx.rlc.cp_table_obj == NULL) { + r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); + if (r) { + dev_err(adev->dev, + "(%d) failed to create cp table bo\n", r); + gfx_v9_0_rlc_fini(adev); + return r; + } + } + + rv_init_cp_jump_table(adev); + amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + + gfx_v9_0_init_lbpw(adev); + } + + return 0; +} + static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) { int r; @@ -473,8 +845,6 @@ static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) } } -#define MEC_HPD_SIZE 2048 - static int gfx_v9_0_mec_init(struct amdgpu_device *adev) { int r; @@ -482,20 +852,19 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) const __le32 *fw_data; unsigned fw_size; u32 *fw; + size_t mec_hpd_size; const struct gfx_firmware_header_v1_0 *mec_hdr; - /* - * we assign only 1 pipe because all other pipes will - * be handled by KFD - */ - adev->gfx.mec.num_mec = 1; - adev->gfx.mec.num_pipe = 1; - adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + + /* take ownership of the relevant compute queues */ + amdgpu_gfx_compute_queue_acquire(adev); + mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; if (adev->gfx.mec.hpd_eop_obj == NULL) { r = amdgpu_bo_create(adev, - adev->gfx.mec.num_queue * MEC_HPD_SIZE, + mec_hpd_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, &adev->gfx.mec.hpd_eop_obj); @@ -575,131 +944,6 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) return 0; } -static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev) -{ - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - - amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); -} - -static int gfx_v9_0_kiq_init(struct amdgpu_device *adev) -{ - int r; - u32 *hpd; - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - - r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, - &kiq->eop_gpu_addr, (void **)&hpd); - if (r) { - dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); - return r; - } - - memset(hpd, 0, MEC_HPD_SIZE); - - r = amdgpu_bo_reserve(kiq->eop_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); - amdgpu_bo_kunmap(kiq->eop_obj); - amdgpu_bo_unreserve(kiq->eop_obj); - - return 0; -} - -static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, - struct amdgpu_ring *ring, - struct amdgpu_irq_src *irq) -{ - struct amdgpu_kiq *kiq = &adev->gfx.kiq; - int r = 0; - - r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); - if (r) - return r; - - ring->adev = NULL; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_KIQ; - if (adev->gfx.mec2_fw) { - ring->me = 2; - ring->pipe = 0; - } else { - ring->me = 1; - ring->pipe = 1; - } - - ring->queue = 0; - ring->eop_gpu_addr = kiq->eop_gpu_addr; - sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); - r = amdgpu_ring_init(adev, ring, 1024, - irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); - if (r) - dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); - - return r; -} -static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, - struct amdgpu_irq_src *irq) -{ - amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); - amdgpu_ring_fini(ring); -} - -/* create MQD for each compute queue */ -static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) -{ - struct amdgpu_ring *ring = NULL; - int r, i; - - /* create MQD for KIQ */ - ring = &adev->gfx.kiq.ring; - if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, - &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); - if (r) { - dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); - return r; - } - - /*TODO: prepare MQD backup */ - } - - /* create MQD for each KCQ */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, - &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); - if (r) { - dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); - return r; - } - - /* TODO: prepare MQD backup */ - } - } - - return 0; -} - -static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev) -{ - struct amdgpu_ring *ring = NULL; - int i; - - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); - } - - ring = &adev->gfx.kiq.ring; - amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); -} - static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, @@ -770,23 +1014,21 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: - adev->gfx.config.max_shader_engines = 4; - adev->gfx.config.max_cu_per_sh = 16; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 4; - adev->gfx.config.max_texture_channel_caches = 16; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; adev->gfx.config.max_hw_contexts = 8; - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; - adev->gfx.config.gs_vgt_table_depth = 32; - adev->gfx.config.gs_prim_buffer_depth = 1792; gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; break; + case CHIP_RAVEN: + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; + break; default: BUG(); break; @@ -1023,13 +1265,61 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) return 0; } +static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, + int mec, int pipe, int queue) +{ + int r; + unsigned irq_type; + struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; + + ring = &adev->gfx.compute_ring[ring_id]; + + /* mec0 is me1 */ + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + + (ring_id * GFX9_MEC_HPD_SIZE); + sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); + + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + + ring->pipe; + + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024, + &adev->gfx.eop_irq, irq_type); + if (r) + return r; + + + return 0; +} + static int gfx_v9_0_sw_init(void *handle) { - int i, r; + int i, j, k, r, ring_id; struct amdgpu_ring *ring; struct amdgpu_kiq *kiq; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_RAVEN: + adev->gfx.mec.num_mec = 2; + break; + default: + adev->gfx.mec.num_mec = 1; + break; + } + + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 8; + /* KIQ event */ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); if (r) @@ -1062,6 +1352,12 @@ static int gfx_v9_0_sw_init(void *handle) return r; } + r = gfx_v9_0_rlc_init(adev); + if (r) { + DRM_ERROR("Failed to init rlc BOs!\n"); + return r; + } + r = gfx_v9_0_mec_init(adev); if (r) { DRM_ERROR("Failed to init MEC BOs!\n"); @@ -1081,49 +1377,40 @@ static int gfx_v9_0_sw_init(void *handle) return r; } - /* set up the compute queues */ - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - unsigned irq_type; - - /* max 32 queues per MEC */ - if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { - DRM_ERROR("Too many (%d) compute rings!\n", i); - break; + /* set up the compute queues - allocate horizontally across pipes */ + ring_id = 0; + for (i = 0; i < adev->gfx.mec.num_mec; ++i) { + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { + if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) + continue; + + r = gfx_v9_0_compute_ring_init(adev, + ring_id, + i, k, j); + if (r) + return r; + + ring_id++; + } } - ring = &adev->gfx.compute_ring[i]; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1; - ring->me = 1; /* first MEC */ - ring->pipe = i / 8; - ring->queue = i % 8; - ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); - sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); - irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; - /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024, - &adev->gfx.eop_irq, irq_type); - if (r) - return r; } - if (amdgpu_sriov_vf(adev)) { - r = gfx_v9_0_kiq_init(adev); - if (r) { - DRM_ERROR("Failed to init KIQ BOs!\n"); - return r; - } + r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); + if (r) { + DRM_ERROR("Failed to init KIQ BOs!\n"); + return r; + } - kiq = &adev->gfx.kiq; - r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); - if (r) - return r; + kiq = &adev->gfx.kiq; + r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); + if (r) + return r; - /* create MQD for all compute queues as wel as KIQ for SRIOV case */ - r = gfx_v9_0_compute_mqd_sw_init(adev); - if (r) - return r; - } + /* create MQD for all compute queues as wel as KIQ for SRIOV case */ + r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd)); + if (r) + return r; /* reserve GDS, GWS and OA resource for gfx */ r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, @@ -1170,11 +1457,9 @@ static int gfx_v9_0_sw_fini(void *handle) for (i = 0; i < adev->gfx.num_compute_rings; i++) amdgpu_ring_fini(&adev->gfx.compute_ring[i]); - if (amdgpu_sriov_vf(adev)) { - gfx_v9_0_compute_mqd_sw_fini(adev); - gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); - gfx_v9_0_kiq_fini(adev); - } + amdgpu_gfx_compute_mqd_sw_fini(adev); + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); + amdgpu_gfx_kiq_fini(adev); gfx_v9_0_mec_fini(adev); gfx_v9_0_ngg_fini(adev); @@ -1208,11 +1493,6 @@ static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); } -static u32 gfx_v9_0_create_bitmask(u32 bit_width) -{ - return (u32)((1ULL << bit_width) - 1); -} - static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) { u32 data, mask; @@ -1223,8 +1503,8 @@ static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; - mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se / - adev->gfx.config.max_sh_per_se); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se); return (~data) & mask; } @@ -1272,7 +1552,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) sh_mem_config = SH_MEM_ADDRESS_MODE_64 | SH_MEM_ALIGNMENT_MODE_UNALIGNED << - SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; mutex_lock(&adev->srbm_mutex); for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { @@ -1370,9 +1650,6 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, { u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); - if (enable) - return; - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); @@ -1381,6 +1658,373 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); } +static void gfx_v9_0_init_csb(struct amdgpu_device *adev) +{ + /* csib */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), + adev->gfx.rlc.clear_state_gpu_addr >> 32); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), + adev->gfx.rlc.clear_state_size); +} + +static void gfx_v9_0_parse_ind_reg_list(int *register_list_format, + int indirect_offset, + int list_size, + int *unique_indirect_regs, + int *unique_indirect_reg_count, + int max_indirect_reg_count, + int *indirect_start_offsets, + int *indirect_start_offsets_count, + int max_indirect_start_offsets_count) +{ + int idx; + bool new_entry = true; + + for (; indirect_offset < list_size; indirect_offset++) { + + if (new_entry) { + new_entry = false; + indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; + *indirect_start_offsets_count = *indirect_start_offsets_count + 1; + BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count); + } + + if (register_list_format[indirect_offset] == 0xFFFFFFFF) { + new_entry = true; + continue; + } + + indirect_offset += 2; + + /* look for the matching indice */ + for (idx = 0; idx < *unique_indirect_reg_count; idx++) { + if (unique_indirect_regs[idx] == + register_list_format[indirect_offset]) + break; + } + + if (idx >= *unique_indirect_reg_count) { + unique_indirect_regs[*unique_indirect_reg_count] = + register_list_format[indirect_offset]; + idx = *unique_indirect_reg_count; + *unique_indirect_reg_count = *unique_indirect_reg_count + 1; + BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count); + } + + register_list_format[indirect_offset] = idx; + } +} + +static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) +{ + int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + int unique_indirect_reg_count = 0; + + int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + int indirect_start_offsets_count = 0; + + int list_size = 0; + int i = 0; + u32 tmp = 0; + + u32 *register_list_format = + kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); + if (!register_list_format) + return -ENOMEM; + memcpy(register_list_format, adev->gfx.rlc.register_list_format, + adev->gfx.rlc.reg_list_format_size_bytes); + + /* setup unique_indirect_regs array and indirect_start_offsets array */ + gfx_v9_0_parse_ind_reg_list(register_list_format, + GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, + adev->gfx.rlc.reg_list_format_size_bytes >> 2, + unique_indirect_regs, + &unique_indirect_reg_count, + sizeof(unique_indirect_regs)/sizeof(int), + indirect_start_offsets, + &indirect_start_offsets_count, + sizeof(indirect_start_offsets)/sizeof(int)); + + /* enable auto inc in case it is disabled */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); + tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); + + /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), + RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); + for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), + adev->gfx.rlc.register_restore[i]); + + /* load direct register */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0); + for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), + adev->gfx.rlc.register_restore[i]); + + /* load indirect register */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), + adev->gfx.rlc.reg_list_format_start); + for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), + register_list_format[i]); + + /* set save/restore list size */ + list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; + list_size = list_size >> 1; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), + adev->gfx.rlc.reg_restore_list_size); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); + + /* write the starting offsets to RLC scratch ram */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), + adev->gfx.rlc.starting_offsets_start); + for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), + indirect_start_offsets[i]); + + /* load unique indirect regs*/ + for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i, + unique_indirect_regs[i] & 0x3FFFF); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i, + unique_indirect_regs[i] >> 20); + } + + kfree(register_list_format); + return 0; +} + +static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) +{ + u32 tmp = 0; + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); + tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); +} + +static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data = 0; + uint32_t default_data = 0; + + default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); + if (enable == true) { + /* enable GFXIP control over CGPG */ + data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); + + /* update status */ + data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; + data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); + if(default_data != data) + WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); + } else { + /* restore GFXIP control over GCPG */ + data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); + } +} + +static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG)) { + /* init IDLE_POLL_COUNT = 60 */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); + data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; + data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); + + /* init RLC PG Delay */ + data = 0; + data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); + data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); + data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); + data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); + + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); + data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; + data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); + + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); + data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; + data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); + + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); + data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; + + /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ + data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); + + pwr_10_0_gfxip_control_over_cgpg(adev, true); + } +} + +static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data = 0; + uint32_t default_data = 0; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + + if (enable == true) { + data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; + if (default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } else { + data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } +} + +static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data = 0; + uint32_t default_data = 0; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + + if (enable == true) { + data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } else { + data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } +} + +static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data = 0; + uint32_t default_data = 0; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + + if (enable == true) { + data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } else { + data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + } +} + +static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, default_data; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + if (enable == true) + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); +} + +static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, default_data; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + if (enable == true) + data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); + + if (!enable) + /* read any GFX register to wake up GFX */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); +} + +static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, default_data; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + if (enable == true) + data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); +} + +static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, default_data; + + default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); + if (enable == true) + data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); +} + +static void gfx_v9_0_init_pg(struct amdgpu_device *adev) +{ + if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_GFX_SMG | + AMD_PG_SUPPORT_GFX_DMG | + AMD_PG_SUPPORT_CP | + AMD_PG_SUPPORT_GDS | + AMD_PG_SUPPORT_RLC_SMU_HS)) { + gfx_v9_0_init_csb(adev); + gfx_v9_0_init_rlc_save_restore_list(adev); + gfx_v9_0_enable_save_restore_machine(adev); + + if (adev->asic_type == CHIP_RAVEN) { + WREG32(mmRLC_JUMP_TABLE_RESTORE, + adev->gfx.rlc.cp_table_gpu_addr >> 8); + gfx_v9_0_init_gfx_power_gating(adev); + + if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { + gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); + gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); + } else { + gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); + gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); + } + + if (adev->pg_flags & AMD_PG_SUPPORT_CP) + gfx_v9_0_enable_cp_power_gating(adev, true); + else + gfx_v9_0_enable_cp_power_gating(adev, false); + } + } +} + void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) { u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); @@ -1425,7 +2069,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) * default is 0x9C4 to create a 100us interval */ WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr - * to disable the page fault retry interrupts, default is + * to disable the page fault retry interrupts, default is * 0x100 (256) */ WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); } @@ -1474,6 +2118,8 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) gfx_v9_0_rlc_reset(adev); + gfx_v9_0_init_pg(adev); + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { /* legacy rlc firmware loading */ r = gfx_v9_0_rlc_load_microcode(adev); @@ -1481,6 +2127,13 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) return r; } + if (adev->asic_type == CHIP_RAVEN) { + if (amdgpu_lbpw != 0) + gfx_v9_0_enable_lbpw(adev, true); + else + gfx_v9_0_enable_lbpw(adev, false); + } + gfx_v9_0_rlc_start(adev); return 0; @@ -1559,35 +2212,6 @@ static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) return 0; } -static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) -{ - u32 count = 0; - const struct cs_section_def *sect = NULL; - const struct cs_extent_def *ext = NULL; - - /* begin clear state */ - count += 2; - /* context control state */ - count += 3; - - for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { - for (ext = sect->section; ext->extent != NULL; ++ext) { - if (sect->id == SECT_CONTEXT) - count += 2 + ext->reg_count; - else - return 0; - } - } - /* pa_sc_raster_config/pa_sc_raster_config1 */ - count += 4; - /* end clear state */ - count += 2; - /* clear state */ - count += 2; - - return count; -} - static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) { struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; @@ -1730,13 +2354,6 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) udelay(50); } -static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev) -{ - gfx_v9_0_cp_compute_enable(adev, true); - - return 0; -} - static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) { const struct gfx_firmware_header_v1_0 *mec_hdr; @@ -1764,7 +2381,7 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); - + /* MEC1 */ WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, mec_hdr->jt_offset); @@ -1779,45 +2396,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) return 0; } -static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev) -{ - int i, r; - - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - - if (ring->mqd_obj) { - r = amdgpu_bo_reserve(ring->mqd_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); - - amdgpu_bo_unpin(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); - - amdgpu_bo_unref(&ring->mqd_obj); - ring->mqd_obj = NULL; - } - } -} - -static int gfx_v9_0_init_queue(struct amdgpu_ring *ring); - -static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev) -{ - int i, r; - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - if (gfx_v9_0_init_queue(ring)) - dev_warn(adev->dev, "compute queue %d init failed!\n", i); - } - - r = gfx_v9_0_cp_compute_start(adev); - if (r) - return r; - - return 0; -} - /* KIQ functions */ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) { @@ -1833,51 +2411,95 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); } -static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) +static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) { - amdgpu_ring_alloc(ring, 8); - /* set resources */ - amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); - amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ - amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ - amdgpu_ring_write(ring, 0); /* queue mask hi */ - amdgpu_ring_write(ring, 0); /* gws mask lo */ - amdgpu_ring_write(ring, 0); /* gws mask hi */ - amdgpu_ring_write(ring, 0); /* oac mask */ - amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ - amdgpu_ring_commit(ring); - udelay(50); -} + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t scratch, tmp = 0; + uint64_t queue_mask = 0; + int r, i; + + for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { + if (!test_bit(i, adev->gfx.mec.queue_bitmap)) + continue; + + /* This situation may be hit in the future if a new HW + * generation exposes more than 64 queues. If so, the + * definition of queue_mask needs updating */ + if (WARN_ON(i > (sizeof(queue_mask)*8))) { + DRM_ERROR("Invalid KCQ enabled: %d\n", i); + break; + } -static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, - struct amdgpu_ring *ring) -{ - struct amdgpu_device *adev = kiq_ring->adev; - uint64_t mqd_addr, wptr_addr; - - mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); - wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - amdgpu_ring_alloc(kiq_ring, 8); - - amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); - /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ - amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ - (0 << 4) | /* Queue_Sel */ - (0 << 8) | /* VMID */ - (ring->queue << 13 ) | - (ring->pipe << 16) | - ((ring->me == 1 ? 0 : 1) << 18) | - (0 << 21) | /*queue_type: normal compute queue */ - (1 << 24) | /* alloc format: all_on_one_pipe */ - (0 << 26) | /* engine_sel: compute */ - (1 << 29)); /* num_queues: must be 1 */ - amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2)); - amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); - amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); - amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); - amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); + queue_mask |= (1ull << i); + } + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("Failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + + r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); + if (r) { + DRM_ERROR("Failed to lock KIQ (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + + /* set resources */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); + amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | + PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ + amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ + amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* oac mask */ + amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); + uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); + /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ + PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ + PACKET3_MAP_QUEUES_QUEUE(ring->queue) | + PACKET3_MAP_QUEUES_PIPE(ring->pipe) | + PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | + PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ + PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */ + PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ + PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ + amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); + amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); + } + /* write to scratch for completion */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(kiq_ring, 0xDEADBEEF); amdgpu_ring_commit(kiq_ring); - udelay(50); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i >= adev->usec_timeout) { + DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + + return r; } static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) @@ -1902,7 +2524,7 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, - (order_base_2(MEC_HPD_SIZE / 4) - 1)); + (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); mqd->cp_hqd_eop_control = tmp; @@ -2119,47 +2741,69 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct v9_mqd *mqd = ring->mqd_ptr; - bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; - if (is_kiq) { - gfx_v9_0_kiq_setting(&kiq->ring); + gfx_v9_0_kiq_setting(ring); + + if (adev->gfx.in_reset) { /* for GPU_RESET case */ + /* reset MQD to a clean status */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); + + /* reset ring buffer */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v9_0_kiq_init_register(ring); + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); } else { - mqd_idx = ring - &adev->gfx.compute_ring[0]; + memset((void *)mqd, 0, sizeof(*mqd)); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v9_0_mqd_init(ring); + gfx_v9_0_kiq_init_register(ring); + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); } - if (!adev->gfx.in_reset) { + return 0; +} + +static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct v9_mqd *mqd = ring->mqd_ptr; + int mqd_idx = ring - &adev->gfx.compute_ring[0]; + + if (!adev->gfx.in_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v9_0_mqd_init(ring); - if (is_kiq) - gfx_v9_0_kiq_init_register(ring); soc15_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - } else { /* for GPU_RESET case */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); + } else if (adev->gfx.in_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset ring buffer */ ring->wptr = 0; - - if (is_kiq) { - mutex_lock(&adev->srbm_mutex); - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v9_0_kiq_init_register(ring); - soc15_grbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - } + amdgpu_ring_clear_ring(ring); + } else { + amdgpu_ring_clear_ring(ring); } - if (is_kiq) - gfx_v9_0_kiq_enable(ring); - else - gfx_v9_0_map_queue_enable(&kiq->ring, ring); - return 0; } @@ -2194,7 +2838,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v9_0_kiq_init_queue(ring); + r = gfx_v9_0_kcq_init_queue(ring); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -2203,13 +2847,14 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) goto done; } + r = gfx_v9_0_kiq_kcq_enable(adev); done: return r; } static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) { - int r,i; + int r, i; struct amdgpu_ring *ring; if (!(adev->flags & AMD_IS_APU)) @@ -2230,10 +2875,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) if (r) return r; - if (amdgpu_sriov_vf(adev)) - r = gfx_v9_0_kiq_resume(adev); - else - r = gfx_v9_0_cp_compute_resume(adev); + r = gfx_v9_0_kiq_resume(adev); if (r) return r; @@ -2243,6 +2885,13 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) ring->ready = false; return r; } + + ring = &adev->gfx.kiq.ring; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) + ring->ready = false; + for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; @@ -2252,14 +2901,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) ring->ready = false; } - if (amdgpu_sriov_vf(adev)) { - ring = &adev->gfx.kiq.ring; - ring->ready = true; - r = amdgpu_ring_test_ring(ring); - if (r) - ring->ready = false; - } - gfx_v9_0_enable_gui_idle_interrupt(adev, true); return 0; @@ -2307,7 +2948,6 @@ static int gfx_v9_0_hw_fini(void *handle) } gfx_v9_0_cp_enable(adev, false); gfx_v9_0_rlc_stop(adev); - gfx_v9_0_cp_compute_fini(adev); return 0; } @@ -2316,14 +2956,18 @@ static int gfx_v9_0_suspend(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->gfx.in_suspend = true; return gfx_v9_0_hw_fini(adev); } static int gfx_v9_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; - return gfx_v9_0_hw_init(adev); + r = gfx_v9_0_hw_init(adev); + adev->gfx.in_suspend = false; + return r; } static bool gfx_v9_0_is_idle(void *handle) @@ -2470,7 +3114,7 @@ static int gfx_v9_0_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; - adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS; + adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; gfx_v9_0_set_ring_funcs(adev); gfx_v9_0_set_irq_funcs(adev); gfx_v9_0_set_gds_init(adev); @@ -2549,6 +3193,43 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) } } +static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + /* TODO: double check if we need to perform under safe mdoe */ + /* gfx_v9_0_enter_rlc_safe_mode(adev); */ + + if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { + gfx_v9_0_enable_gfx_cg_power_gating(adev, true); + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) + gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); + } else { + gfx_v9_0_enable_gfx_cg_power_gating(adev, false); + gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); + } + + /* gfx_v9_0_exit_rlc_safe_mode(adev); */ +} + +static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, + bool enable) +{ + /* TODO: double check if we need to perform under safe mode */ + /* gfx_v9_0_enter_rlc_safe_mode(adev); */ + + if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) + gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); + else + gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); + + if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) + gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); + else + gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); + + /* gfx_v9_0_exit_rlc_safe_mode(adev); */ +} + static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { @@ -2739,6 +3420,34 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { static int gfx_v9_0_set_powergating_state(void *handle, enum amd_powergating_state state) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool enable = (state == AMD_PG_STATE_GATE) ? true : false; + + switch (adev->asic_type) { + case CHIP_RAVEN: + if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { + gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); + gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); + } else { + gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); + gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); + } + + if (adev->pg_flags & AMD_PG_SUPPORT_CP) + gfx_v9_0_enable_cp_power_gating(adev, true); + else + gfx_v9_0_enable_cp_power_gating(adev, false); + + /* update gfx cgpg state */ + gfx_v9_0_update_gfx_cg_power_gating(adev, enable); + + /* update mgcg state */ + gfx_v9_0_update_gfx_mg_power_gating(adev, enable); + break; + default: + break; + } + return 0; } @@ -2752,6 +3461,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_RAVEN: gfx_v9_0_update_gfx_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); break; @@ -2879,31 +3589,33 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, struct amdgpu_ib *ib, unsigned vm_id, bool ctx_switch) { - u32 header, control = 0; + u32 header, control = 0; - if (ib->flags & AMDGPU_IB_FLAG_CE) - header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); - else - header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); + if (ib->flags & AMDGPU_IB_FLAG_CE) + header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); + else + header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); - control |= ib->length_dw | (vm_id << 24); + control |= ib->length_dw | (vm_id << 24); - if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) - control |= INDIRECT_BUFFER_PRE_ENB(1); + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { + control |= INDIRECT_BUFFER_PRE_ENB(1); - amdgpu_ring_write(ring, header); - BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ - amdgpu_ring_write(ring, + if (!(ib->flags & AMDGPU_IB_FLAG_CE)) + gfx_v9_0_ring_emit_de_meta(ring); + } + + amdgpu_ring_write(ring, header); +BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ + amdgpu_ring_write(ring, #ifdef __BIG_ENDIAN - (2 << 0) | + (2 << 0) | #endif - lower_32_bits(ib->gpu_addr)); - amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); - amdgpu_ring_write(ring, control); + lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, control); } -#define INDIRECT_BUFFER_VALID (1 << 23) - static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, struct amdgpu_ib *ib, unsigned vm_id, bool ctx_switch) @@ -2971,9 +3683,8 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; - pd_addr = pd_addr | 0x1; /* valid bit */ - /* now only use physical base address of PDE and valid */ - BUG_ON(pd_addr & 0xFFFF00000000003EULL); + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; gfx_v9_0_write_data_to_reg(ring, usepfp, true, hub->ctx0_ptb_addr_lo32 + (2 * vm_id), @@ -3130,9 +3841,6 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); amdgpu_ring_write(ring, dw2); amdgpu_ring_write(ring, 0); - - if (amdgpu_sriov_vf(ring->adev)) - gfx_v9_0_ring_emit_de_meta(ring); } static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) @@ -3160,6 +3868,12 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne ring->ring[offset] = (ring->ring_size>>2) - offset + cur; } +static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); + amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ +} + static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) { struct amdgpu_device *adev = ring->adev; @@ -3208,8 +3922,8 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, u32 mec_int_cntl, mec_int_cntl_reg; /* - * amdgpu controls only pipe 0 of MEC1. That's why this function only - * handles the setting of interrupts for this specific pipe. All other + * amdgpu controls only the first MEC. That's why this function only + * handles the setting of interrupts for this specific MEC. All other * pipes' interrupts are set by amdkfd. */ @@ -3218,6 +3932,15 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, case 0: mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); break; + case 1: + mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); + break; + case 2: + mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); + break; + case 3: + mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); + break; default: DRM_DEBUG("invalid pipe %d\n", pipe); return; @@ -3494,6 +4217,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, + .emit_tmz = gfx_v9_0_ring_emit_tmz, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { @@ -3605,6 +4329,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_RAVEN: adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; break; default: @@ -3640,6 +4365,20 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) } } +static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, + u32 bitmap) +{ + u32 data; + + if (!bitmap) + return; + + data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; + data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; + + WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); +} + static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) { u32 data, mask; @@ -3650,7 +4389,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; - mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh); + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); return (~data) & mask; } @@ -3660,11 +4399,12 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, { int i, j, k, counter, active_cu_number = 0; u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; + unsigned disable_masks[4 * 2]; if (!adev || !cu_info) return -EINVAL; - memset(cu_info, 0, sizeof(*cu_info)); + amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { @@ -3673,19 +4413,24 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, ao_bitmap = 0; counter = 0; gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); + if (i < 4 && j < 2) + gfx_v9_0_set_user_cu_inactive_bitmap( + adev, disable_masks[i * 2 + j]); bitmap = gfx_v9_0_get_cu_active_bitmap(adev); cu_info->bitmap[i][j] = bitmap; - for (k = 0; k < 16; k ++) { + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { if (bitmap & mask) { - if (counter < 2) + if (counter < adev->gfx.config.max_cu_per_sh) ao_bitmap |= mask; counter ++; } mask <<= 1; } active_cu_number += counter; - ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + if (i < 2 && j < 2) + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + cu_info->ao_cu_bitmap[i][j] = ao_bitmap; } } gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -3697,218 +4442,6 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, return 0; } -static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) -{ - int r, j; - u32 tmp; - bool use_doorbell = true; - u64 hqd_gpu_addr; - u64 mqd_gpu_addr; - u64 eop_gpu_addr; - u64 wb_gpu_addr; - u32 *buf; - struct v9_mqd *mqd; - struct amdgpu_device *adev; - - adev = ring->adev; - if (ring->mqd_obj == NULL) { - r = amdgpu_bo_create(adev, - sizeof(struct v9_mqd), - PAGE_SIZE,true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, - NULL, &ring->mqd_obj); - if (r) { - dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(ring->mqd_obj, false); - if (unlikely(r != 0)) { - gfx_v9_0_cp_compute_fini(adev); - return r; - } - - r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, - &mqd_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); - gfx_v9_0_cp_compute_fini(adev); - return r; - } - r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); - if (r) { - dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); - gfx_v9_0_cp_compute_fini(adev); - return r; - } - - /* init the mqd struct */ - memset(buf, 0, sizeof(struct v9_mqd)); - - mqd = (struct v9_mqd *)buf; - mqd->header = 0xC0310800; - mqd->compute_pipelinestat_enable = 0x00000001; - mqd->compute_static_thread_mgmt_se0 = 0xffffffff; - mqd->compute_static_thread_mgmt_se1 = 0xffffffff; - mqd->compute_static_thread_mgmt_se2 = 0xffffffff; - mqd->compute_static_thread_mgmt_se3 = 0xffffffff; - mqd->compute_misc_reserved = 0x00000003; - mutex_lock(&adev->srbm_mutex); - soc15_grbm_select(adev, ring->me, - ring->pipe, - ring->queue, 0); - /* disable wptr polling */ - WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); - - /* write the EOP addr */ - BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */ - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE); - eop_gpu_addr >>= 8; - - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr)); - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); - mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr); - mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr); - - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, - (order_base_2(MEC_HPD_SIZE / 4) - 1)); - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp); - - /* enable doorbell? */ - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); - if (use_doorbell) - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - else - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); - - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); - mqd->cp_hqd_pq_doorbell_control = tmp; - - /* disable the queue if it's active */ - ring->wptr = 0; - mqd->cp_hqd_dequeue_request = 0; - mqd->cp_hqd_pq_rptr = 0; - mqd->cp_hqd_pq_wptr_lo = 0; - mqd->cp_hqd_pq_wptr_hi = 0; - if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { - WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); - for (j = 0; j < adev->usec_timeout; j++) { - if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) - break; - udelay(1); - } - WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi); - } - - /* set the pointer to the MQD */ - mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; - mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); - WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); - WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); - - /* set MQD vmid to 0 */ - tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); - WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp); - mqd->cp_mqd_control = tmp; - - /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ - hqd_gpu_addr = ring->gpu_addr >> 8; - mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; - mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); - - /* set up the HQD, this is similar to CP_RB0_CNTL */ - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, - (order_base_2(ring->ring_size / 4) - 1)); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); -#ifdef __BIG_ENDIAN - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); -#endif - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp); - mqd->cp_hqd_pq_control = tmp; - - /* set the wb address wether it's enabled or not */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; - mqd->cp_hqd_pq_rptr_report_addr_hi = - upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, - mqd->cp_hqd_pq_rptr_report_addr_lo); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, - mqd->cp_hqd_pq_rptr_report_addr_hi); - - /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ - wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; - mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, - mqd->cp_hqd_pq_wptr_poll_addr_lo); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, - mqd->cp_hqd_pq_wptr_poll_addr_hi); - - /* enable the doorbell if requested */ - if (use_doorbell) { - WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, - (AMDGPU_DOORBELL64_KIQ * 2) << 2); - WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, - (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2); - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, - DOORBELL_OFFSET, ring->doorbell_index); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); - mqd->cp_hqd_pq_doorbell_control = tmp; - - } else { - mqd->cp_hqd_pq_doorbell_control = 0; - } - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, - mqd->cp_hqd_pq_doorbell_control); - - /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo); - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi); - - /* set the vmid for the queue */ - mqd->cp_hqd_vmid = 0; - WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); - - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); - tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); - WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp); - mqd->cp_hqd_persistent_state = tmp; - - /* activate the queue */ - mqd->cp_hqd_active = 1; - WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active); - - soc15_grbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - - amdgpu_bo_kunmap(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); - - if (use_doorbell) - WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); - - return 0; -} - const struct amdgpu_ip_block_version gfx_v9_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_GFX, diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 005075ff00f7..a42f483767e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -31,178 +31,161 @@ #include "soc15_common.h" -int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) +u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) { - u32 tmp; - u64 value; - u32 i; + return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; +} - /* Program MC. */ - /* Update configuration */ - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), - adev->mc.vram_start >> 18); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), - adev->mc.vram_end >> 18); +static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) +{ + uint64_t value; - value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); + value = adev->gart.table_addr - adev->mc.vram_start + adev->vm_manager.vram_base_offset; - WREG32(SOC15_REG_OFFSET(GC, 0, - mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB), - (u32)(value >> 12)); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB), - (u32)(value >> 44)); + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /*valid bit*/ - if (amdgpu_sriov_vf(adev)) { - /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so - vbios post doesn't program them, for SRIOV driver need to program them */ - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE), - adev->mc.vram_start >> 24); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP), - adev->mc.vram_end >> 24); - } + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + lower_32_bits(value)); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + upper_32_bits(value)); +} + +static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) +{ + gfxhub_v1_0_init_gart_pt_regs(adev); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->mc.gtt_start >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->mc.gtt_start >> 44)); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->mc.gtt_end >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->mc.gtt_end >> 44)); +} + +static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t value; /* Disable AGP. */ - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); - /* GART Enable. */ + /* Program the system aperture low logical page number. */ + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, + adev->mc.vram_start >> 18); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + adev->mc.vram_end >> 18); + + /* Set default page address. */ + value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page.addr >> 12)); + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page.addr >> 44)); + + WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); +} + +static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; /* Setup TLB control */ - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - SYSTEM_ACCESS_MODE, - 3); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ENABLE_ADVANCED_DRIVER_MODEL, - 1); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - SYSTEM_APERTURE_UNMAPPED_ACCESS, - 0); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ECO_BITS, - 0); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - MTYPE, - MTYPE_UC);/* XXX for emulation. */ - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ATC_EN, - 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); + + WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); +} + +static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; /* Setup L2 cache */ - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - ENABLE_L2_FRAGMENT_PROCESSING, - 0); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - L2_PDE0_CACHE_TAG_GENERATION_MODE, - 0);/* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); + /* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - CONTEXT1_IDENTITY_ACCESS_MODE, - 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - IDENTITY_MODE_FRAGMENT_SIZE, - 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2)); + tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp); + WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); tmp = mmVM_L2_CNTL3_DEFAULT; - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp); + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4)); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL4, - VMC_TAP_PDE_REQUEST_PHYSICAL, - 0); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL4, - VMC_TAP_PTE_REQUEST_PHYSICAL, - 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp); - - /* setup context0 */ - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32), - (u32)(adev->mc.gtt_start >> 12)); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32), - (u32)(adev->mc.gtt_start >> 44)); - - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32), - (u32)(adev->mc.gtt_end >> 12)); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32), - (u32)(adev->mc.gtt_end >> 44)); + tmp = mmVM_L2_CNTL4_DEFAULT; + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); +} - BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); - value = adev->gart.table_addr - adev->mc.vram_start - + adev->vm_manager.vram_base_offset; - value &= 0x0000FFFFFFFFF000ULL; - value |= 0x1; /*valid bit*/ +static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) +{ + uint32_t tmp; - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32), - (u32)value); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32), - (u32)(value >> 32)); - - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), - (u32)(adev->dummy_page.addr >> 12)); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32), - (u32)((u64)adev->dummy_page.addr >> 44)); - - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2)); - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, - 1); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); - - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); +} + +static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) +{ + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0XFFFFFFFF); + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x0000000F); + + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, + 0); + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, + 0); - /* Disable identity aperture.*/ - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); + WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); +} - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); +static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) +{ + int i; + uint32_t tmp; for (i = 0; i <= 14; i++) { - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i); + tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, adev->vm_manager.num_level); @@ -223,15 +206,52 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, adev->vm_manager.block_size - 9); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, lower_32_bits(adev->vm_manager.max_pfn - 1)); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, upper_32_bits(adev->vm_manager.max_pfn - 1)); } +} + +static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0 ; i < 18; ++i) { + WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + 2 * i, 0xffffffff); + WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + 2 * i, 0x1f); + } +} + +int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) +{ + if (amdgpu_sriov_vf(adev)) { + /* + * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are + * VF copy registers so vbios post doesn't program them, for + * SRIOV driver need to program them + */ + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, + adev->mc.vram_start >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, + adev->mc.vram_end >> 24); + } + /* GART Enable. */ + gfxhub_v1_0_init_gart_aperture_regs(adev); + gfxhub_v1_0_init_system_aperture_regs(adev); + gfxhub_v1_0_init_tlb_regs(adev); + gfxhub_v1_0_init_cache_regs(adev); + + gfxhub_v1_0_enable_system_domain(adev); + gfxhub_v1_0_disable_identity_aperture(adev); + gfxhub_v1_0_setup_vmid_config(adev); + gfxhub_v1_0_program_invalidation(adev); return 0; } @@ -243,22 +263,20 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) /* Disable all tables */ for (i = 0; i < 16; i++) - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0); + WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); /* Setup TLB control */ - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); /* Setup L2 cache */ - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0); + WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); } /** @@ -271,7 +289,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { u32 tmp; - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL)); + tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, @@ -296,22 +314,11 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp); -} - -static int gfxhub_v1_0_early_init(void *handle) -{ - return 0; -} - -static int gfxhub_v1_0_late_init(void *handle) -{ - return 0; + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } -static int gfxhub_v1_0_sw_init(void *handle) +void gfxhub_v1_0_init(struct amdgpu_device *adev) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; hub->ctx0_ptb_addr_lo32 = @@ -330,96 +337,4 @@ static int gfxhub_v1_0_sw_init(void *handle) SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); - - return 0; -} - -static int gfxhub_v1_0_sw_fini(void *handle) -{ - return 0; } - -static int gfxhub_v1_0_hw_init(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - unsigned i; - - for (i = 0 ; i < 18; ++i) { - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) + - 2 * i, 0xffffffff); - WREG32(SOC15_REG_OFFSET(GC, 0, - mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) + - 2 * i, 0x1f); - } - - return 0; -} - -static int gfxhub_v1_0_hw_fini(void *handle) -{ - return 0; -} - -static int gfxhub_v1_0_suspend(void *handle) -{ - return 0; -} - -static int gfxhub_v1_0_resume(void *handle) -{ - return 0; -} - -static bool gfxhub_v1_0_is_idle(void *handle) -{ - return true; -} - -static int gfxhub_v1_0_wait_for_idle(void *handle) -{ - return 0; -} - -static int gfxhub_v1_0_soft_reset(void *handle) -{ - return 0; -} - -static int gfxhub_v1_0_set_clockgating_state(void *handle, - enum amd_clockgating_state state) -{ - return 0; -} - -static int gfxhub_v1_0_set_powergating_state(void *handle, - enum amd_powergating_state state) -{ - return 0; -} - -const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = { - .name = "gfxhub_v1_0", - .early_init = gfxhub_v1_0_early_init, - .late_init = gfxhub_v1_0_late_init, - .sw_init = gfxhub_v1_0_sw_init, - .sw_fini = gfxhub_v1_0_sw_fini, - .hw_init = gfxhub_v1_0_hw_init, - .hw_fini = gfxhub_v1_0_hw_fini, - .suspend = gfxhub_v1_0_suspend, - .resume = gfxhub_v1_0_resume, - .is_idle = gfxhub_v1_0_is_idle, - .wait_for_idle = gfxhub_v1_0_wait_for_idle, - .soft_reset = gfxhub_v1_0_soft_reset, - .set_clockgating_state = gfxhub_v1_0_set_clockgating_state, - .set_powergating_state = gfxhub_v1_0_set_powergating_state, -}; - -const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block = -{ - .type = AMD_IP_BLOCK_TYPE_GFXHUB, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &gfxhub_v1_0_ip_funcs, -}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h index 5129a8ff0932..d2dbb085f480 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h @@ -28,7 +28,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev); void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev); void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value); - +void gfxhub_v1_0_init(struct amdgpu_device *adev); +u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev); extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs; extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index d860939152df..d0214d942bfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -21,7 +21,7 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "gmc_v6_0.h" #include "amdgpu_ucode.h" @@ -395,6 +395,12 @@ static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } +static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +{ + BUG_ON(addr & 0xFFFFFF0000000FFFULL); + return addr; +} + static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { @@ -614,33 +620,6 @@ static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_fini(adev); } -static int gmc_v6_0_vm_init(struct amdgpu_device *adev) -{ - /* - * number of VMs - * VMID 0 is reserved for System - * amdgpu graphics/compute will use VMIDs 1-7 - * amdkfd will use VMIDs 8-15 - */ - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; - amdgpu_vm_manager_init(adev); - - /* base offset of vram pages */ - if (adev->flags & AMD_IS_APU) { - u64 tmp = RREG32(mmMC_VM_FB_OFFSET); - tmp <<= 22; - adev->vm_manager.vram_base_offset = tmp; - } else - adev->vm_manager.vram_base_offset = 0; - - return 0; -} - -static void gmc_v6_0_vm_fini(struct amdgpu_device *adev) -{ -} - static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client) { @@ -815,14 +794,6 @@ static int gmc_v6_0_early_init(void *handle) gmc_v6_0_set_gart_funcs(adev); gmc_v6_0_set_irq_funcs(adev); - if (adev->flags & AMD_IS_APU) { - adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - } else { - u32 tmp = RREG32(mmMC_SEQ_MISC0); - tmp &= MC_SEQ_MISC0__MT__MASK; - adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); - } - return 0; } @@ -842,6 +813,14 @@ static int gmc_v6_0_sw_init(void *handle) int dma_bits; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->flags & AMD_IS_APU) { + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + } else { + u32 tmp = RREG32(mmMC_SEQ_MISC0); + tmp &= MC_SEQ_MISC0__MT__MASK; + adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); + } + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); if (r) return r; @@ -855,6 +834,8 @@ static int gmc_v6_0_sw_init(void *handle) adev->mc.mc_mask = 0xffffffffffULL; + adev->mc.stolen_size = 256 * 1024; + adev->need_dma32 = false; dma_bits = adev->need_dma32 ? 32 : 40; r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); @@ -887,26 +868,34 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - if (!adev->vm_manager.enabled) { - r = gmc_v6_0_vm_init(adev); - if (r) { - dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); - return r; - } - adev->vm_manager.enabled = true; + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; + amdgpu_vm_manager_init(adev); + + /* base offset of vram pages */ + if (adev->flags & AMD_IS_APU) { + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); + + tmp <<= 22; + adev->vm_manager.vram_base_offset = tmp; + } else { + adev->vm_manager.vram_base_offset = 0; } - return r; + return 0; } static int gmc_v6_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->vm_manager.enabled) { - gmc_v6_0_vm_fini(adev); - adev->vm_manager.enabled = false; - } + amdgpu_vm_manager_fini(adev); gmc_v6_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); @@ -984,16 +973,10 @@ static bool gmc_v6_0_is_idle(void *handle) static int gmc_v6_0_wait_for_idle(void *handle) { unsigned i; - u32 tmp; struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | - SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | - SRBM_STATUS__MCC_BUSY_MASK | - SRBM_STATUS__MCD_BUSY_MASK | - SRBM_STATUS__VMC_BUSY_MASK); - if (!tmp) + if (gmc_v6_0_is_idle(handle)) return 0; udelay(1); } @@ -1146,6 +1129,7 @@ static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v6_0_gart_set_pte_pde, .set_prt = gmc_v6_0_set_prt, + .get_vm_pde = gmc_v6_0_get_vm_pde, .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 2750e5c23813..7e9ea53edf8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -21,7 +21,7 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "cikd.h" #include "cik.h" @@ -472,6 +472,12 @@ static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } +static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +{ + BUG_ON(addr & 0xFFFFFF0000000FFFULL); + return addr; +} + /** * gmc_v8_0_set_fault_enable_default - update VM fault handling * @@ -724,55 +730,6 @@ static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_fini(adev); } -/* - * vm - * VMID 0 is the physical GPU addresses as used by the kernel. - * VMIDs 1-15 are used for userspace clients and are handled - * by the amdgpu vm/hsa code. - */ -/** - * gmc_v7_0_vm_init - cik vm init callback - * - * @adev: amdgpu_device pointer - * - * Inits cik specific vm parameters (number of VMs, base of vram for - * VMIDs 1-15) (CIK). - * Returns 0 for success. - */ -static int gmc_v7_0_vm_init(struct amdgpu_device *adev) -{ - /* - * number of VMs - * VMID 0 is reserved for System - * amdgpu graphics/compute will use VMIDs 1-7 - * amdkfd will use VMIDs 8-15 - */ - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; - amdgpu_vm_manager_init(adev); - - /* base offset of vram pages */ - if (adev->flags & AMD_IS_APU) { - u64 tmp = RREG32(mmMC_VM_FB_OFFSET); - tmp <<= 22; - adev->vm_manager.vram_base_offset = tmp; - } else - adev->vm_manager.vram_base_offset = 0; - - return 0; -} - -/** - * gmc_v7_0_vm_fini - cik vm fini callback - * - * @adev: amdgpu_device pointer - * - * Tear down any asic specific VM setup (CIK). - */ -static void gmc_v7_0_vm_fini(struct amdgpu_device *adev) -{ -} - /** * gmc_v7_0_vm_decode_fault - print human readable fault info * @@ -1013,6 +970,8 @@ static int gmc_v7_0_sw_init(void *handle) */ adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + adev->mc.stolen_size = 256 * 1024; + /* set DMA mask + need_dma32 flags. * PCIE - can handle 40-bits. * IGP - can handle 40-bits @@ -1051,27 +1010,34 @@ static int gmc_v7_0_sw_init(void *handle) if (r) return r; - if (!adev->vm_manager.enabled) { - r = gmc_v7_0_vm_init(adev); - if (r) { - dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); - return r; - } - adev->vm_manager.enabled = true; + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; + amdgpu_vm_manager_init(adev); + + /* base offset of vram pages */ + if (adev->flags & AMD_IS_APU) { + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); + + tmp <<= 22; + adev->vm_manager.vram_base_offset = tmp; + } else { + adev->vm_manager.vram_base_offset = 0; } - return r; + return 0; } static int gmc_v7_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->vm_manager.enabled) { - amdgpu_vm_manager_fini(adev); - gmc_v7_0_vm_fini(adev); - adev->vm_manager.enabled = false; - } + amdgpu_vm_manager_fini(adev); gmc_v7_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); @@ -1335,7 +1301,8 @@ static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v7_0_gart_set_pte_pde, .set_prt = gmc_v7_0_set_prt, - .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags + .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, + .get_vm_pde = gmc_v7_0_get_vm_pde }; static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f56b4089ee9f..cc9f88057cd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -21,7 +21,7 @@ * */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "gmc_v8_0.h" #include "amdgpu_ucode.h" @@ -656,6 +656,12 @@ static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } +static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) +{ + BUG_ON(addr & 0xFFFFFF0000000FFFULL); + return addr; +} + /** * gmc_v8_0_set_fault_enable_default - update VM fault handling * @@ -927,55 +933,6 @@ static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_fini(adev); } -/* - * vm - * VMID 0 is the physical GPU addresses as used by the kernel. - * VMIDs 1-15 are used for userspace clients and are handled - * by the amdgpu vm/hsa code. - */ -/** - * gmc_v8_0_vm_init - cik vm init callback - * - * @adev: amdgpu_device pointer - * - * Inits cik specific vm parameters (number of VMs, base of vram for - * VMIDs 1-15) (CIK). - * Returns 0 for success. - */ -static int gmc_v8_0_vm_init(struct amdgpu_device *adev) -{ - /* - * number of VMs - * VMID 0 is reserved for System - * amdgpu graphics/compute will use VMIDs 1-7 - * amdkfd will use VMIDs 8-15 - */ - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; - amdgpu_vm_manager_init(adev); - - /* base offset of vram pages */ - if (adev->flags & AMD_IS_APU) { - u64 tmp = RREG32(mmMC_VM_FB_OFFSET); - tmp <<= 22; - adev->vm_manager.vram_base_offset = tmp; - } else - adev->vm_manager.vram_base_offset = 0; - - return 0; -} - -/** - * gmc_v8_0_vm_fini - cik vm fini callback - * - * @adev: amdgpu_device pointer - * - * Tear down any asic specific VM setup (CIK). - */ -static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) -{ -} - /** * gmc_v8_0_vm_decode_fault - print human readable fault info * @@ -1097,6 +1054,8 @@ static int gmc_v8_0_sw_init(void *handle) */ adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + adev->mc.stolen_size = 256 * 1024; + /* set DMA mask + need_dma32 flags. * PCIE - can handle 40-bits. * IGP - can handle 40-bits @@ -1135,27 +1094,34 @@ static int gmc_v8_0_sw_init(void *handle) if (r) return r; - if (!adev->vm_manager.enabled) { - r = gmc_v8_0_vm_init(adev); - if (r) { - dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); - return r; - } - adev->vm_manager.enabled = true; + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; + amdgpu_vm_manager_init(adev); + + /* base offset of vram pages */ + if (adev->flags & AMD_IS_APU) { + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); + + tmp <<= 22; + adev->vm_manager.vram_base_offset = tmp; + } else { + adev->vm_manager.vram_base_offset = 0; } - return r; + return 0; } static int gmc_v8_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->vm_manager.enabled) { - amdgpu_vm_manager_fini(adev); - gmc_v8_0_vm_fini(adev); - adev->vm_manager.enabled = false; - } + amdgpu_vm_manager_fini(adev); gmc_v8_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); @@ -1654,7 +1620,8 @@ static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v8_0_gart_set_pte_pde, .set_prt = gmc_v8_0_set_prt, - .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags + .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, + .get_vm_pde = gmc_v8_0_get_vm_pde }; static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index f936332a069d..175ba5f9691c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -33,6 +33,7 @@ #include "soc15_common.h" #include "nbio_v6_1.h" +#include "nbio_v7_0.h" #include "gfxhub_v1_0.h" #include "mmhub_v1_0.h" @@ -215,7 +216,10 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, unsigned i, j; /* flush hdp cache */ - nbio_v6_1_hdp_flush(adev); + if (adev->flags & AMD_IS_APU) + nbio_v7_0_hdp_flush(adev); + else + nbio_v6_1_hdp_flush(adev); spin_lock(&adev->mc.invalidate_lock); @@ -354,17 +358,19 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, return pte_flag; } -static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) +static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr) { - return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; + addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start; + BUG_ON(addr & 0xFFFF00000000003FULL); + return addr; } static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v9_0_gart_set_pte_pde, - .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, - .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, .get_invalidate_req = gmc_v9_0_get_invalidate_req, + .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, + .get_vm_pde = gmc_v9_0_get_vm_pde }; static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) @@ -415,6 +421,11 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, amdgpu_vram_location(adev, &adev->mc, base); adev->mc.gtt_base_align = 0; amdgpu_gtt_location(adev, mc); + /* base offset of vram pages */ + if (adev->flags & AMD_IS_APU) + adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); + else + adev->vm_manager.vram_base_offset = 0; } /** @@ -434,7 +445,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) /* hbm memory channel size */ chansize = 128; - tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); + tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; switch (tmp) { @@ -474,7 +485,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = - nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL; + ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) : + nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL; adev->mc.real_vram_size = adev->mc.mc_vram_size; adev->mc.visible_vram_size = adev->mc.aper_size; @@ -514,64 +526,15 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) return amdgpu_gart_table_vram_alloc(adev); } -/* - * vm - * VMID 0 is the physical GPU addresses as used by the kernel. - * VMIDs 1-15 are used for userspace clients and are handled - * by the amdgpu vm/hsa code. - */ -/** - * gmc_v9_0_vm_init - vm init callback - * - * @adev: amdgpu_device pointer - * - * Inits vega10 specific vm parameters (number of VMs, base of vram for - * VMIDs 1-15) (vega10). - * Returns 0 for success. - */ -static int gmc_v9_0_vm_init(struct amdgpu_device *adev) -{ - /* - * number of VMs - * VMID 0 is reserved for System - * amdgpu graphics/compute will use VMIDs 1-7 - * amdkfd will use VMIDs 8-15 - */ - adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; - - /* TODO: fix num_level for APU when updating vm size and block size */ - if (adev->flags & AMD_IS_APU) - adev->vm_manager.num_level = 1; - else - adev->vm_manager.num_level = 3; - amdgpu_vm_manager_init(adev); - - /* base offset of vram pages */ - /*XXX This value is not zero for APU*/ - adev->vm_manager.vram_base_offset = 0; - - return 0; -} - -/** - * gmc_v9_0_vm_fini - vm fini callback - * - * @adev: amdgpu_device pointer - * - * Tear down any asic specific VM setup. - */ -static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) -{ - return; -} - static int gmc_v9_0_sw_init(void *handle) { int r; int dma_bits; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gfxhub_v1_0_init(adev); + mmhub_v1_0_init(adev); + spin_lock_init(&adev->mc.invalidate_lock); if (adev->flags & AMD_IS_APU) { @@ -609,6 +572,12 @@ static int gmc_v9_0_sw_init(void *handle) */ adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ + /* + * It needs to reserve 8M stolen memory for vega10 + * TODO: Figure out how to avoid that... + */ + adev->mc.stolen_size = 8 * 1024 * 1024; + /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. * IGP - can handle 44-bits @@ -641,15 +610,23 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - if (!adev->vm_manager.enabled) { - r = gmc_v9_0_vm_init(adev); - if (r) { - dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); - return r; - } - adev->vm_manager.enabled = true; - } - return r; + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; + + /* TODO: fix num_level for APU when updating vm size and block size */ + if (adev->flags & AMD_IS_APU) + adev->vm_manager.num_level = 1; + else + adev->vm_manager.num_level = 3; + amdgpu_vm_manager_init(adev); + + return 0; } /** @@ -669,11 +646,7 @@ static int gmc_v9_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->vm_manager.enabled) { - amdgpu_vm_manager_fini(adev); - gmc_v9_0_vm_fini(adev); - adev->vm_manager.enabled = false; - } + amdgpu_vm_manager_fini(adev); gmc_v9_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); @@ -686,6 +659,8 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: break; + case CHIP_RAVEN: + break; default: break; } @@ -715,7 +690,19 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) return r; /* After HDP is initialized, flush HDP.*/ - nbio_v6_1_hdp_flush(adev); + if (adev->flags & AMD_IS_APU) + nbio_v7_0_hdp_flush(adev); + else + nbio_v6_1_hdp_flush(adev); + + switch (adev->asic_type) { + case CHIP_RAVEN: + mmhub_v1_0_initialize_power_gating(adev); + mmhub_v1_0_update_power_gating(adev, true); + break; + default: + break; + } r = gfxhub_v1_0_gart_enable(adev); if (r) @@ -725,12 +712,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); + tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; - WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); + WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); - tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); - WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); + tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); + WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) @@ -781,6 +768,12 @@ static int gmc_v9_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (amdgpu_sriov_vf(adev)) { + /* full access mode, so don't touch any GMC register */ + DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); + return 0; + } + amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); gmc_v9_0_gart_disable(adev); @@ -831,7 +824,16 @@ static int gmc_v9_0_soft_reset(void *handle) static int gmc_v9_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { - return 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return mmhub_v1_0_set_clockgating(adev, state); +} + +static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + mmhub_v1_0_get_clockgating(adev, flags); } static int gmc_v9_0_set_powergating_state(void *handle, @@ -855,6 +857,7 @@ const struct amd_ip_funcs gmc_v9_0_ip_funcs = { .soft_reset = gmc_v9_0_soft_reset, .set_clockgating_state = gmc_v9_0_set_clockgating_state, .set_powergating_state = gmc_v9_0_set_powergating_state, + .get_clockgating_state = gmc_v9_0_get_clockgating_state, }; const struct amdgpu_ip_block_version gmc_v9_0_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index cb622add99a7..7a0ea27ac429 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "vid.h" diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 79a52ad2c80d..3bbf2ccfca89 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -21,7 +21,7 @@ * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "cikd.h" diff --git a/drivers/gpu/drm/amd/amdgpu/kv_smc.c b/drivers/gpu/drm/amd/amdgpu/kv_smc.c index e6b7b42acfe1..b82e33c01571 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_smc.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_smc.c @@ -22,7 +22,7 @@ * Authors: Alex Deucher */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "cikd.h" #include "kv_dpm.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index dbfe48d1207a..9804318f3488 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -34,9 +34,12 @@ #include "soc15_common.h" +#define mmDAGB0_CNTL_MISC2_RV 0x008f +#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 + u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) { - u64 base = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE)); + u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; base <<= 24; @@ -44,184 +47,160 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) return base; } -int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) +static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) { - u32 tmp; - u64 value; - uint64_t addr; - u32 i; + uint64_t value; - /* Program MC. */ - /* Update configuration */ - DRM_INFO("%s -- in\n", __func__); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), - adev->mc.vram_start >> 18); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), - adev->mc.vram_end >> 18); - value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); + value = adev->gart.table_addr - adev->mc.vram_start + adev->vm_manager.vram_base_offset; - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB), - (u32)(value >> 12)); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB), - (u32)(value >> 44)); + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /* valid bit */ - if (amdgpu_sriov_vf(adev)) { - /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so - vbios post doesn't program them, for SRIOV driver need to program them */ - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE), - adev->mc.vram_start >> 24); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP), - adev->mc.vram_end >> 24); - } + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + lower_32_bits(value)); + + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + upper_32_bits(value)); +} + +static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) +{ + mmhub_v1_0_init_gart_pt_regs(adev); + + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->mc.gtt_start >> 12)); + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->mc.gtt_start >> 44)); + + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->mc.gtt_end >> 12)); + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->mc.gtt_end >> 44)); +} + +static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) +{ + uint64_t value; + uint32_t tmp; /* Disable AGP. */ - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); - /* GART Enable. */ + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, + adev->mc.vram_start >> 18); + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + adev->mc.vram_end >> 18); + + /* Set default page address. */ + value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page.addr >> 12)); + WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page.addr >> 44)); + + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); +} + +static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; /* Setup TLB control */ - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - SYSTEM_ACCESS_MODE, - 3); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ENABLE_ADVANCED_DRIVER_MODEL, - 1); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - SYSTEM_APERTURE_UNMAPPED_ACCESS, - 0); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ECO_BITS, - 0); - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - MTYPE, - MTYPE_UC);/* XXX for emulation. */ - tmp = REG_SET_FIELD(tmp, - MC_VM_MX_L1_TLB_CNTL, - ATC_EN, - 1); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); + + WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); +} + +static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) +{ + uint32_t tmp; /* Setup L2 cache */ - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL)); + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - ENABLE_L2_FRAGMENT_PROCESSING, - 0); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - L2_PDE0_CACHE_TAG_GENERATION_MODE, - 0);/* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); + /* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - CONTEXT1_IDENTITY_ACCESS_MODE, - 1); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL, - IDENTITY_MODE_FRAGMENT_SIZE, - 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2)); + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); tmp = mmVM_L2_CNTL3_DEFAULT; - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp); - - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4)); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL4, - VMC_TAP_PDE_REQUEST_PHYSICAL, - 0); - tmp = REG_SET_FIELD(tmp, - VM_L2_CNTL4, - VMC_TAP_PTE_REQUEST_PHYSICAL, - 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp); - - /* setup context0 */ - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32), - (u32)(adev->mc.gtt_start >> 12)); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32), - (u32)(adev->mc.gtt_start >> 44)); - - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32), - (u32)(adev->mc.gtt_end >> 12)); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32), - (u32)(adev->mc.gtt_end >> 44)); - - BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); - value = adev->gart.table_addr - adev->mc.vram_start + - adev->vm_manager.vram_base_offset; - value &= 0x0000FFFFFFFFF000ULL; - value |= 0x1; /* valid bit */ + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32), - (u32)value); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32), - (u32)(value >> 32)); - - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), - (u32)(adev->dummy_page.addr >> 12)); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32), - (u32)((u64)adev->dummy_page.addr >> 44)); - - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2)); - tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, - 1); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); + tmp = mmVM_L2_CNTL4_DEFAULT; + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); +} - addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); - tmp = RREG32(addr); +static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) +{ + uint32_t tmp; + tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp); - - tmp = RREG32(addr); - - /* Disable identity aperture.*/ - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); +} - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); +static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) +{ + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0XFFFFFFFF); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x0000000F); + + WREG32_SOC15(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); + + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, + 0); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, + 0); +} - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); +static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) +{ + int i; + uint32_t tmp; for (i = 0; i <= 14; i++) { - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) - + i); + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, @@ -243,14 +222,270 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, adev->vm_manager.block_size - 9); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + i, tmp); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, lower_32_bits(adev->vm_manager.max_pfn - 1)); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, upper_32_bits(adev->vm_manager.max_pfn - 1)); } +} + +static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < 18; ++i) { + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + 2 * i, 0xffffffff); + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + 2 * i, 0x1f); + } +} + +struct pctl_data { + uint32_t index; + uint32_t data; +}; + +const struct pctl_data pctl0_data[] = { + {0x0, 0x7a640}, + {0x9, 0x2a64a}, + {0xd, 0x2a680}, + {0x11, 0x6a684}, + {0x19, 0xea68e}, + {0x29, 0xa69e}, + {0x2b, 0x34a6c0}, + {0x61, 0x83a707}, + {0xe6, 0x8a7a4}, + {0xf0, 0x1a7b8}, + {0xf3, 0xfa7cc}, + {0x104, 0x17a7dd}, + {0x11d, 0xa7dc}, + {0x11f, 0x12a7f5}, + {0x133, 0xa808}, + {0x135, 0x12a810}, + {0x149, 0x7a82c} +}; +#define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0])) + +#define PCTL0_RENG_EXEC_END_PTR 0x151 +#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640 +#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833 + +const struct pctl_data pctl1_data[] = { + {0x0, 0x39a000}, + {0x3b, 0x44a040}, + {0x81, 0x2a08d}, + {0x85, 0x6ba094}, + {0xf2, 0x18a100}, + {0x10c, 0x4a132}, + {0x112, 0xca141}, + {0x120, 0x2fa158}, + {0x151, 0x17a1d0}, + {0x16a, 0x1a1e9}, + {0x16d, 0x13a1ec}, + {0x182, 0x7a201}, + {0x18b, 0x3a20a}, + {0x190, 0x7a580}, + {0x199, 0xa590}, + {0x19b, 0x4a594}, + {0x1a1, 0x1a59c}, + {0x1a4, 0x7a82c}, + {0x1ad, 0xfa7cc}, + {0x1be, 0x17a7dd}, + {0x1d7, 0x12a810} +}; +#define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0])) + +#define PCTL1_RENG_EXEC_END_PTR 0x1ea +#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 +#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d +#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580 +#define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d +#define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c +#define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833 + +static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev) +{ + uint32_t tmp = 0; + + /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */ + tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, + STCTRL_REGISTER_SAVE_BASE, + PCTL0_STCTRL_REG_SAVE_RANGE0_BASE); + tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, + STCTRL_REGISTER_SAVE_LIMIT, + PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT); + WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp); + + /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */ + tmp = 0; + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, + STCTRL_REGISTER_SAVE_BASE, + PCTL1_STCTRL_REG_SAVE_RANGE0_BASE); + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, + STCTRL_REGISTER_SAVE_LIMIT, + PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT); + WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp); + + /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */ + tmp = 0; + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, + STCTRL_REGISTER_SAVE_BASE, + PCTL1_STCTRL_REG_SAVE_RANGE1_BASE); + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, + STCTRL_REGISTER_SAVE_LIMIT, + PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT); + WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp); + + /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */ + tmp = 0; + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, + STCTRL_REGISTER_SAVE_BASE, + PCTL1_STCTRL_REG_SAVE_RANGE2_BASE); + tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, + STCTRL_REGISTER_SAVE_LIMIT, + PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT); + WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp); +} + +void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev) +{ + uint32_t pctl0_misc = 0; + uint32_t pctl0_reng_execute = 0; + uint32_t pctl1_misc = 0; + uint32_t pctl1_reng_execute = 0; + int i = 0; + + if (amdgpu_sriov_vf(adev)) + return; + + pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC); + pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); + pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC); + pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); + + /* Light sleep must be disabled before writing to pctl0 registers */ + pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; + WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); + + /* Write data used to access ram of register engine */ + for (i = 0; i < PCTL0_DATA_LEN; i++) { + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX, + pctl0_data[i].index); + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA, + pctl0_data[i].data); + } + + /* Set the reng execute end ptr for pctl0 */ + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, + PCTL0_RENG_EXECUTE, + RENG_EXECUTE_END_PTR, + PCTL0_RENG_EXEC_END_PTR); + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); + + /* Light sleep must be disabled before writing to pctl1 registers */ + pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; + WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); + + /* Write data used to access ram of register engine */ + for (i = 0; i < PCTL1_DATA_LEN; i++) { + WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX, + pctl1_data[i].index); + WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA, + pctl1_data[i].data); + } + + /* Set the reng execute end ptr for pctl1 */ + pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, + PCTL1_RENG_EXECUTE, + RENG_EXECUTE_END_PTR, + PCTL1_RENG_EXEC_END_PTR); + WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); + + mmhub_v1_0_power_gating_write_save_ranges(adev); + + /* Re-enable light sleep */ + pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; + WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); + pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; + WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); +} + +void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t pctl0_reng_execute = 0; + uint32_t pctl1_reng_execute = 0; + + if (amdgpu_sriov_vf(adev)) + return; + + pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); + pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); + + if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, + PCTL0_RENG_EXECUTE, + RENG_EXECUTE_ON_PWR_UP, 1); + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, + PCTL0_RENG_EXECUTE, + RENG_EXECUTE_ON_REG_UPDATE, 1); + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); + + pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, + PCTL1_RENG_EXECUTE, + RENG_EXECUTE_ON_PWR_UP, 1); + pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, + PCTL1_RENG_EXECUTE, + RENG_EXECUTE_ON_REG_UPDATE, 1); + WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); + + } else { + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, + PCTL0_RENG_EXECUTE, + RENG_EXECUTE_ON_PWR_UP, 0); + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, + PCTL0_RENG_EXECUTE, + RENG_EXECUTE_ON_REG_UPDATE, 0); + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); + + pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, + PCTL1_RENG_EXECUTE, + RENG_EXECUTE_ON_PWR_UP, 0); + pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, + PCTL1_RENG_EXECUTE, + RENG_EXECUTE_ON_REG_UPDATE, 0); + WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); + } +} + +int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) +{ + if (amdgpu_sriov_vf(adev)) { + /* + * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are + * VF copy registers so vbios post doesn't program them, for + * SRIOV driver need to program them + */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, + adev->mc.vram_start >> 24); + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, + adev->mc.vram_end >> 24); + } + + /* GART Enable. */ + mmhub_v1_0_init_gart_aperture_regs(adev); + mmhub_v1_0_init_system_aperture_regs(adev); + mmhub_v1_0_init_tlb_regs(adev); + mmhub_v1_0_init_cache_regs(adev); + + mmhub_v1_0_enable_system_domain(adev); + mmhub_v1_0_disable_identity_aperture(adev); + mmhub_v1_0_setup_vmid_config(adev); + mmhub_v1_0_program_invalidation(adev); return 0; } @@ -262,22 +497,22 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) /* Disable all tables */ for (i = 0; i < 16; i++) - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0); + WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); /* Setup TLB control */ - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); /* Setup L2 cache */ - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL)); + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), 0); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); } /** @@ -289,7 +524,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { u32 tmp; - tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL)); + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, @@ -314,22 +549,11 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp); + WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } -static int mmhub_v1_0_early_init(void *handle) +void mmhub_v1_0_init(struct amdgpu_device *adev) { - return 0; -} - -static int mmhub_v1_0_late_init(void *handle) -{ - return 0; -} - -static int mmhub_v1_0_sw_init(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; hub->ctx0_ptb_addr_lo32 = @@ -349,69 +573,20 @@ static int mmhub_v1_0_sw_init(void *handle) hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); - return 0; -} - -static int mmhub_v1_0_sw_fini(void *handle) -{ - return 0; -} - -static int mmhub_v1_0_hw_init(void *handle) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - unsigned i; - - for (i = 0; i < 18; ++i) { - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) + - 2 * i, 0xffffffff); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) + - 2 * i, 0x1f); - } - - return 0; -} - -static int mmhub_v1_0_hw_fini(void *handle) -{ - return 0; -} - -static int mmhub_v1_0_suspend(void *handle) -{ - return 0; -} - -static int mmhub_v1_0_resume(void *handle) -{ - return 0; -} - -static bool mmhub_v1_0_is_idle(void *handle) -{ - return true; -} - -static int mmhub_v1_0_wait_for_idle(void *handle) -{ - return 0; -} - -static int mmhub_v1_0_soft_reset(void *handle) -{ - return 0; } static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { - uint32_t def, data, def1, data1, def2, data2; + uint32_t def, data, def1, data1, def2 = 0, data2 = 0; - def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); - def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2)); - def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2)); + def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); + + if (adev->asic_type != CHIP_RAVEN) { + def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); + def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); + } else + def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { data |= ATC_L2_MISC_CG__ENABLE_MASK; @@ -423,12 +598,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + if (adev->asic_type != CHIP_RAVEN) + data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); } else { data &= ~ATC_L2_MISC_CG__ENABLE_MASK; @@ -439,22 +615,27 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); - data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | - DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + if (adev->asic_type != CHIP_RAVEN) + data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); } if (def != data) - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data); + WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); - if (def1 != data1) - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1); + if (def1 != data1) { + if (adev->asic_type != CHIP_RAVEN) + WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); + else + WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); + } - if (def2 != data2) - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2), data2); + if (adev->asic_type != CHIP_RAVEN && def2 != data2) + WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); } static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, @@ -462,7 +643,7 @@ static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, { uint32_t def, data; - def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; @@ -470,7 +651,7 @@ static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; if (def != data) - WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data); + WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); } static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, @@ -478,7 +659,7 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade { uint32_t def, data; - def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); + def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; @@ -486,7 +667,7 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; if (def != data) - WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data); + WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); } static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, @@ -494,7 +675,7 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, { uint32_t def, data; - def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) @@ -503,19 +684,18 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; if(def != data) - WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data); + WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); } -static int mmhub_v1_0_set_clockgating_state(void *handle, - enum amd_clockgating_state state) +int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, + enum amd_clockgating_state state) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (amdgpu_sriov_vf(adev)) return 0; switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_RAVEN: mmhub_v1_0_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); athub_update_medium_grain_clock_gating(adev, @@ -532,54 +712,20 @@ static int mmhub_v1_0_set_clockgating_state(void *handle, return 0; } -static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags) +void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; int data; if (amdgpu_sriov_vf(adev)) *flags = 0; /* AMD_CG_SUPPORT_MC_MGCG */ - data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) *flags |= AMD_CG_SUPPORT_MC_MGCG; /* AMD_CG_SUPPORT_MC_LS */ - data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); + data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) *flags |= AMD_CG_SUPPORT_MC_LS; } - -static int mmhub_v1_0_set_powergating_state(void *handle, - enum amd_powergating_state state) -{ - return 0; -} - -const struct amd_ip_funcs mmhub_v1_0_ip_funcs = { - .name = "mmhub_v1_0", - .early_init = mmhub_v1_0_early_init, - .late_init = mmhub_v1_0_late_init, - .sw_init = mmhub_v1_0_sw_init, - .sw_fini = mmhub_v1_0_sw_fini, - .hw_init = mmhub_v1_0_hw_init, - .hw_fini = mmhub_v1_0_hw_fini, - .suspend = mmhub_v1_0_suspend, - .resume = mmhub_v1_0_resume, - .is_idle = mmhub_v1_0_is_idle, - .wait_for_idle = mmhub_v1_0_wait_for_idle, - .soft_reset = mmhub_v1_0_soft_reset, - .set_clockgating_state = mmhub_v1_0_set_clockgating_state, - .set_powergating_state = mmhub_v1_0_set_powergating_state, - .get_clockgating_state = mmhub_v1_0_get_clockgating_state, -}; - -const struct amdgpu_ip_block_version mmhub_v1_0_ip_block = -{ - .type = AMD_IP_BLOCK_TYPE_MMHUB, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &mmhub_v1_0_ip_funcs, -}; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h index aadedf99c028..57bb940c0ecd 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h @@ -28,6 +28,13 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev); void mmhub_v1_0_gart_disable(struct amdgpu_device *adev); void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value); +void mmhub_v1_0_init(struct amdgpu_device *adev); +int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, + enum amd_clockgating_state state); +void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags); +void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev); +void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, + bool enable); extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs; extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 1493301b6a94..bde3ca3c21c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -124,8 +124,8 @@ static int xgpu_ai_poll_ack(struct amdgpu_device *adev) r = -ETIME; break; } - msleep(1); - timeout -= 1; + mdelay(5); + timeout -= 5; reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL)); @@ -141,12 +141,12 @@ static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) r = xgpu_ai_mailbox_rcv_msg(adev, event); while (r) { if (timeout <= 0) { - pr_err("Doesn't get ack from pf.\n"); + pr_err("Doesn't get msg:%d from pf.\n", event); r = -ETIME; break; } - msleep(1); - timeout -= 1; + mdelay(5); + timeout -= 5; r = xgpu_ai_mailbox_rcv_msg(adev, event); } @@ -165,7 +165,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, /* start to poll ack */ r = xgpu_ai_poll_ack(adev); if (r) - return r; + pr_err("Doesn't get ack from pf, continue\n"); xgpu_ai_mailbox_set_valid(adev, false); @@ -174,8 +174,10 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, req == IDH_REQ_GPU_FINI_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) { r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); - if (r) + if (r) { + pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n"); return r; + } } return 0; @@ -241,7 +243,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, false); + amdgpu_sriov_gpu_reset(adev, NULL); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -264,12 +266,15 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, { int r; - /* see what event we get */ - r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); + /* trigger gpu-reset by hypervisor only if TDR disbaled */ + if (amdgpu_lockup_timeout == 0) { + /* see what event we get */ + r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); - /* only handle FLR_NOTIFY now */ - if (!r) - schedule_work(&adev->virt.flr_work); + /* only handle FLR_NOTIFY now */ + if (!r) + schedule_work(&adev->virt.flr_work); + } return 0; } @@ -296,11 +301,11 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev) { int r; - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); if (r) return r; - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); if (r) { amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 7bdc51b02326..171a658135b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -398,8 +398,8 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev) r = -ETIME; break; } - msleep(1); - timeout -= 1; + mdelay(5); + timeout -= 5; reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); } @@ -418,8 +418,8 @@ static int xgpu_vi_poll_msg(struct amdgpu_device *adev, enum idh_event event) r = -ETIME; break; } - msleep(1); - timeout -= 1; + mdelay(5); + timeout -= 5; r = xgpu_vi_mailbox_rcv_msg(adev, event); } @@ -447,7 +447,7 @@ static int xgpu_vi_send_access_requests(struct amdgpu_device *adev, request == IDH_REQ_GPU_RESET_ACCESS) { r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); if (r) - return r; + pr_err("Doesn't get ack from pf, continue\n"); } return 0; @@ -514,7 +514,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, false); + amdgpu_sriov_gpu_reset(adev, NULL); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -537,12 +537,15 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev, { int r; - /* see what event we get */ - r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); + /* trigger gpu-reset by hypervisor only if TDR disbaled */ + if (amdgpu_lockup_timeout == 0) { + /* see what event we get */ + r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); - /* only handle FLR_NOTIFY now */ - if (!r) - schedule_work(&adev->virt.flr_work); + /* only handle FLR_NOTIFY now */ + if (!r) + schedule_work(&adev->virt.flr_work); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 97057f4a10de..1e272f785def 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -35,7 +35,7 @@ u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) { - u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0)); + u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; @@ -46,32 +46,33 @@ u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, uint32_t idx) { - return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx); + return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); } void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, uint32_t idx, uint32_t val) { - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val); + WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); } void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) { if (enable) - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), - BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); + WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, + BIF_FB_EN__FB_READ_EN_MASK | + BIF_FB_EN__FB_WRITE_EN_MASK); else - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0); + WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); } void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) { - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); + WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); } u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) { - return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE)); + return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); } static const u32 nbio_sdma_doorbell_range_reg[] = @@ -97,15 +98,7 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { - u32 tmp; - - tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN)); - if (enable) - tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); - else - tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); - - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN), tmp); + WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); } void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, @@ -115,23 +108,23 @@ void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, if (enable) { tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | - REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW), - lower_32_bits(adev->doorbell.base)); - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH), - upper_32_bits(adev->doorbell.base)); + WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, + lower_32_bits(adev->doorbell.base)); + WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, + upper_32_bits(adev->doorbell.base)); } - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL), tmp); + WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); } void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { - u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE)); + u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); if (use_doorbell) { ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); @@ -139,7 +132,7 @@ void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, } else ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range); + WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); } void nbio_v6_1_ih_control(struct amdgpu_device *adev) @@ -147,15 +140,15 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev) u32 interrupt_cntl; /* setup interrupt control */ - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8); - interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL)); + WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN */ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl); + WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, @@ -251,8 +244,7 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) { uint32_t reg; - reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, - mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER)); + reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); if (reg & 1) adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c new file mode 100644 index 000000000000..aa04632523fa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -0,0 +1,212 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "nbio_v7_0.h" + +#include "vega10/soc15ip.h" +#include "raven1/NBIO/nbio_7_0_default.h" +#include "raven1/NBIO/nbio_7_0_offset.h" +#include "raven1/NBIO/nbio_7_0_sh_mask.h" +#include "vega10/vega10_enum.h" + +#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c + +u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); + + tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; + tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; + + return tmp; +} + +u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx) +{ + return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); +} + +void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val) +{ + WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); +} + +void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) +{ + if (enable) + WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, + BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); + else + WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); +} + +void nbio_v7_0_hdp_flush(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); +} + +u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) +{ + return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); +} + +static const u32 nbio_sdma_doorbell_range_reg[] = +{ + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE), + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) +}; + +void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index) +{ + u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]); + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); + } else + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); + + WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range); +} + +void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); +} + +void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) +{ + u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); + + if (use_doorbell) { + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); + } else + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); + + WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); +} + +static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset) +{ + uint32_t data; + + WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); + data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); + + return data; +} + +static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset, + uint32_t data) +{ + WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); + WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); +} + +void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + /* NBIF_MGCG_CTRL_LCLK */ + def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) + data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; + else + data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; + + if (def != data) + WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); + + /* SYSHUB_MGCG_CTRL_SOCCLK */ + def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) + data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; + else + data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; + + if (def != data) + nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data); + + /* SYSHUB_MGCG_CTRL_SHUBCLK */ + def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) + data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; + else + data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; + + if (def != data) + nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data); +} + +void nbio_v7_0_ih_control(struct amdgpu_device *adev) +{ + u32 interrupt_cntl; + + /* setup interrupt control */ + WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); + WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); +} + +struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; +struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; + +int nbio_v7_0_init(struct amdgpu_device *adev) +{ + nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); + nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK; + nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK; + + nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); + nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h new file mode 100644 index 000000000000..054ff49427e6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h @@ -0,0 +1,49 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NBIO_V7_0_H__ +#define __NBIO_V7_0_H__ + +#include "soc15_common.h" + +extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; +extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; +int nbio_v7_0_init(struct amdgpu_device *adev); +u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx); +void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val); +void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable); +void nbio_v7_0_hdp_flush(struct amdgpu_device *adev); +u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev); +void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index); +void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable); +void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index); +void nbio_v7_0_ih_control(struct amdgpu_device *adev); +u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev); +void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c new file mode 100644 index 000000000000..2258323a3c26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -0,0 +1,308 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ + +#include <linux/firmware.h> +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v10_0.h" + +#include "vega10/soc15ip.h" +#include "raven1/MP/mp_10_0_offset.h" +#include "raven1/GC/gc_9_1_offset.h" +#include "raven1/SDMA0/sdma0_4_1_offset.h" + +static int +psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) +{ + switch(ucode->ucode_id) { + case AMDGPU_UCODE_ID_SDMA0: + *type = GFX_FW_TYPE_SDMA0; + break; + case AMDGPU_UCODE_ID_SDMA1: + *type = GFX_FW_TYPE_SDMA1; + break; + case AMDGPU_UCODE_ID_CP_CE: + *type = GFX_FW_TYPE_CP_CE; + break; + case AMDGPU_UCODE_ID_CP_PFP: + *type = GFX_FW_TYPE_CP_PFP; + break; + case AMDGPU_UCODE_ID_CP_ME: + *type = GFX_FW_TYPE_CP_ME; + break; + case AMDGPU_UCODE_ID_CP_MEC1: + *type = GFX_FW_TYPE_CP_MEC; + break; + case AMDGPU_UCODE_ID_CP_MEC1_JT: + *type = GFX_FW_TYPE_CP_MEC_ME1; + break; + case AMDGPU_UCODE_ID_CP_MEC2: + *type = GFX_FW_TYPE_CP_MEC; + break; + case AMDGPU_UCODE_ID_CP_MEC2_JT: + *type = GFX_FW_TYPE_CP_MEC_ME2; + break; + case AMDGPU_UCODE_ID_RLC_G: + *type = GFX_FW_TYPE_RLC_G; + break; + case AMDGPU_UCODE_ID_SMC: + *type = GFX_FW_TYPE_SMU; + break; + case AMDGPU_UCODE_ID_UVD: + *type = GFX_FW_TYPE_UVD; + break; + case AMDGPU_UCODE_ID_VCE: + *type = GFX_FW_TYPE_VCE; + break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + return -EINVAL; + } + + return 0; +} + +int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd) +{ + int ret; + uint64_t fw_mem_mc_addr = ucode->mc_addr; + struct common_firmware_header *header; + + memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); + header = (struct common_firmware_header *)ucode->fw; + + cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); + cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes); + + ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); + if (ret) + DRM_ERROR("Unknown firmware type\n"); + + return ret; +} + +int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) +{ + int ret = 0; + unsigned int psp_ring_reg = 0; + struct psp_ring *ring; + struct amdgpu_device *adev = psp->adev; + + ring = &psp->km_ring; + + ring->ring_type = ring_type; + + /* allocate 4k Page of Local Frame Buffer memory for ring */ + ring->ring_size = 0x1000; + ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + if (ret) { + ring->ring_size = 0; + return ret; + } + + /* Write low address of the ring to C2PMSG_69 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); + /* Write high address of the ring to C2PMSG_70 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); + /* Write size of ring to C2PMSG_71 */ + psp_ring_reg = ring->ring_size; + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); + /* Write the ring initialization command to C2PMSG_64 */ + psp_ring_reg = ring_type; + psp_ring_reg = psp_ring_reg << 16; + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); + /* Wait for response flag (bit 31) in C2PMSG_64 */ + psp_ring_reg = 0; + while ((psp_ring_reg & 0x80000000) == 0) { + psp_ring_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64); + } + + return 0; +} + +int psp_v10_0_cmd_submit(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, + int index) +{ + unsigned int psp_write_ptr_reg = 0; + struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + /* KM (GPCOM) prepare write pointer */ + psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); + + /* Update KM RB frame pointer to new frame */ + if ((psp_write_ptr_reg % ring->ring_size) == 0) + write_frame = ring->ring_mem; + else + write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4)); + + /* Update KM RB frame */ + write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); + write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); + write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); + write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); + write_frame->fence_value = index; + + /* Update the write Pointer in DWORDs */ + psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4; + psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg; + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); + + return 0; +} + +static int +psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, + unsigned int *sram_data_reg_offset, + enum AMDGPU_UCODE_ID ucode_id) +{ + int ret = 0; + + switch(ucode_id) { +/* TODO: needs to confirm */ +#if 0 + case AMDGPU_UCODE_ID_SMC: + *sram_offset = 0; + *sram_addr_reg_offset = 0; + *sram_data_reg_offset = 0; + break; +#endif + + case AMDGPU_UCODE_ID_CP_CE: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_PFP: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_ME: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_MEC1: + *sram_offset = 0x10000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_MEC2: + *sram_offset = 0x10000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_RLC_G: + *sram_offset = 0x2000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_SDMA0: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); + break; + +/* TODO: needs to confirm */ +#if 0 + case AMDGPU_UCODE_ID_SDMA1: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; + + case AMDGPU_UCODE_ID_UVD: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; + + case AMDGPU_UCODE_ID_VCE: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; +#endif + + case AMDGPU_UCODE_ID_MAXIMUM: + default: + ret = -EINVAL; + break; + } + + return ret; +} + +bool psp_v10_0_compare_sram_data(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + enum AMDGPU_UCODE_ID ucode_type) +{ + int err = 0; + unsigned int fw_sram_reg_val = 0; + unsigned int fw_sram_addr_reg_offset = 0; + unsigned int fw_sram_data_reg_offset = 0; + unsigned int ucode_size; + uint32_t *ucode_mem = NULL; + struct amdgpu_device *adev = psp->adev; + + err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, + &fw_sram_data_reg_offset, ucode_type); + if (err) + return false; + + WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); + + ucode_size = ucode->ucode_size; + ucode_mem = (uint32_t *)ucode->kaddr; + while (!ucode_size) { + fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); + + if (*ucode_mem != fw_sram_reg_val) + return false; + + ucode_mem++; + /* 4 bytes */ + ucode_size -= 4; + } + + return true; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h new file mode 100644 index 000000000000..2022b7b7151e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h @@ -0,0 +1,41 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ +#ifndef __PSP_V10_0_H__ +#define __PSP_V10_0_H__ + +#include "amdgpu_psp.h" + +extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, + struct psp_gfx_cmd_resp *cmd); +extern int psp_v10_0_ring_init(struct psp_context *psp, + enum psp_ring_type ring_type); +extern int psp_v10_0_cmd_submit(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, + int index); +extern bool psp_v10_0_compare_sram_data(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + enum AMDGPU_UCODE_ID ucode_type); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 60a6407ba267..c98d77d0c8f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -24,7 +24,7 @@ */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_psp.h" #include "amdgpu_ucode.h" @@ -172,7 +172,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) /* Check sOS sign of life register to confirm sys driver and sOS * are already been loaded. */ - sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); if (sol_reg) return 0; @@ -188,10 +188,10 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); /* Provide the sys driver to bootrom */ - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 1 << 16; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); /* there might be handshake issue with hardware which needs delay */ @@ -213,7 +213,7 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) /* Check sOS sign of life register to confirm sys driver and sOS * are already been loaded. */ - sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); if (sol_reg) return 0; @@ -229,17 +229,17 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); /* Provide the PSP secure OS to bootrom */ - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (uint32_t)(psp->fw_pri_mc_addr >> 20)); psp_gfxdrv_command_reg = 2 << 16; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); /* there might be handshake issue with hardware which needs delay */ mdelay(20); #if 0 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), - RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)), + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, true); #endif @@ -254,8 +254,8 @@ int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; - cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr; - cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32); + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); @@ -299,17 +299,17 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) /* Write low address of the ring to C2PMSG_69 */ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); /* Write high address of the ring to C2PMSG_70 */ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); /* Write size of ring to C2PMSG_71 */ psp_ring_reg = ring->ring_size; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); /* Write the ring initialization command to C2PMSG_64 */ psp_ring_reg = ring_type; psp_ring_reg = psp_ring_reg << 16; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); /* there might be handshake issue with hardware which needs delay */ mdelay(20); @@ -332,7 +332,7 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) /* Write the ring destroy command to C2PMSG_64 */ psp_ring_reg = 3 << 16; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); /* there might be handshake issue with hardware which needs delay */ mdelay(20); @@ -361,7 +361,7 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; /* KM (GPCOM) prepare write pointer */ - psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67)); + psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); /* Update KM RB frame pointer to new frame */ /* write_frame ptr increments by size of rb_frame in bytes */ @@ -375,15 +375,15 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); /* Update KM RB frame */ - write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32); - write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr); - write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32); - write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr); + write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); + write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); + write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); + write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); write_frame->fence_value = index; /* Update the write Pointer in DWORDs */ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; - WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg); + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); return 0; } @@ -515,7 +515,7 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) uint32_t reg; reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; - WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg); - reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)); + WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); + reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index a69e5d4e1d2a..1d766ae98dc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); @@ -659,9 +660,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); - ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); - doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); if (ring->use_doorbell) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index ecc70a730a54..4a65697ccc94 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -35,6 +35,7 @@ #include "vega10/MMHUB/mmhub_1_0_offset.h" #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" #include "vega10/HDP/hdp_4_0_offset.h" +#include "raven1/SDMA0/sdma0_4_1_default.h" #include "soc15_common.h" #include "soc15.h" @@ -42,6 +43,10 @@ MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); + +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); @@ -82,6 +87,26 @@ static const u32 golden_settings_sdma_vg10[] = { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002 }; +static const u32 golden_settings_sdma_4_1[] = +{ + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0 +}; + +static const u32 golden_settings_sdma_rv1[] = +{ + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002 +}; + static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) { u32 base = 0; @@ -112,25 +137,19 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_sdma_vg10, (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); break; + case CHIP_RAVEN: + amdgpu_program_register_sequence(adev, + golden_settings_sdma_4_1, + (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); + amdgpu_program_register_sequence(adev, + golden_settings_sdma_rv1, + (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); + break; default: break; } } -static void sdma_v4_0_print_ucode_regs(void *handle) -{ - int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - dev_info(adev->dev, "VEGA10 SDMA ucode registers\n"); - for (i = 0; i < adev->sdma.num_instances; i++) { - dev_info(adev->dev, " SDMA%d_UCODE_ADDR=0x%08X\n", - i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR))); - dev_info(adev->dev, " SDMA%d_UCODE_CHECKSUM=0x%08X\n", - i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM))); - } -} - /** * sdma_v4_0_init_microcode - load ucode images from disk * @@ -158,6 +177,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) case CHIP_VEGA10: chip_name = "vega10"; break; + case CHIP_RAVEN: + chip_name = "raven"; + break; default: BUG(); } @@ -350,7 +372,9 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) u32 ref_and_mask = 0; struct nbio_hdp_flush_reg *nbio_hf_reg; - if (ring->adev->asic_type == CHIP_VEGA10) + if (ring->adev->flags & AMD_IS_APU) + nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; + else nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; if (ring == &ring->adev->sdma.instance[0].ring) @@ -581,7 +605,10 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) } WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell); WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); - nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); + if (adev->flags & AMD_IS_APU) + nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); + else + nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); if (amdgpu_sriov_vf(adev)) sdma_v4_0_ring_set_wptr(ring); @@ -633,6 +660,69 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) return 0; } +static void +sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) +{ + uint32_t def, data; + + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { + /* disable idle interrupt */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); + data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; + + if (data != def) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); + } else { + /* disable idle interrupt */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); + data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; + if (data != def) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); + } +} + +static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) +{ + uint32_t def, data; + + /* Enable HW based PG. */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); + data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; + if (data != def) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); + + /* enable interrupt */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); + data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; + if (data != def) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); + + /* Configure hold time to filter in-valid power on/off request. Use default right now */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); + data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; + data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); + /* Configure switch time for hysteresis purpose. Use default right now */ + data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; + data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); + if(data != def) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); +} + +static void sdma_v4_0_init_pg(struct amdgpu_device *adev) +{ + if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) + return; + + switch (adev->asic_type) { + case CHIP_RAVEN: + sdma_v4_1_init_power_gating(adev); + sdma_v4_1_update_power_gating(adev, true); + break; + default: + break; + } +} + /** * sdma_v4_0_rlc_resume - setup and start the async dma engines * @@ -643,7 +733,8 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) */ static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) { - /* XXX todo */ + sdma_v4_0_init_pg(adev); + return 0; } @@ -699,8 +790,6 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); } - sdma_v4_0_print_ucode_regs(adev); - return 0; } @@ -726,7 +815,6 @@ static int sdma_v4_0_start(struct amdgpu_device *adev) } if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { - DRM_INFO("Loading via direct write\n"); r = sdma_v4_0_load_microcode(adev); if (r) return r; @@ -764,8 +852,6 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - DRM_INFO("In Ring test func\n"); - r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); @@ -1038,9 +1124,8 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; - pd_addr = pd_addr | 0x1; /* valid bit */ - /* now only use physical base address of PDE and valid */ - BUG_ON(pd_addr & 0xFFFF00000000003EULL); + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); @@ -1074,7 +1159,10 @@ static int sdma_v4_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - adev->sdma.num_instances = 2; + if (adev->asic_type == CHIP_RAVEN) + adev->sdma.num_instances = 1; + else + adev->sdma.num_instances = 2; sdma_v4_0_set_ring_funcs(adev); sdma_v4_0_set_buffer_funcs(adev); @@ -1406,6 +1494,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_RAVEN: sdma_v4_0_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); sdma_v4_0_update_medium_grain_light_sleep(adev, @@ -1420,6 +1509,17 @@ static int sdma_v4_0_set_clockgating_state(void *handle, static int sdma_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + switch (adev->asic_type) { + case CHIP_RAVEN: + sdma_v4_1_update_power_gating(adev, + state == AMD_PG_STATE_GATE ? true : false); + break; + default: + break; + } + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index c0b1aabf282f..f45fb0f022b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -24,7 +24,7 @@ #include <linux/firmware.h> #include <linux/slab.h> #include <linux/module.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -971,44 +971,44 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) } static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { - {GRBM_STATUS, false}, - {GB_ADDR_CONFIG, false}, - {MC_ARB_RAMCFG, false}, - {GB_TILE_MODE0, false}, - {GB_TILE_MODE1, false}, - {GB_TILE_MODE2, false}, - {GB_TILE_MODE3, false}, - {GB_TILE_MODE4, false}, - {GB_TILE_MODE5, false}, - {GB_TILE_MODE6, false}, - {GB_TILE_MODE7, false}, - {GB_TILE_MODE8, false}, - {GB_TILE_MODE9, false}, - {GB_TILE_MODE10, false}, - {GB_TILE_MODE11, false}, - {GB_TILE_MODE12, false}, - {GB_TILE_MODE13, false}, - {GB_TILE_MODE14, false}, - {GB_TILE_MODE15, false}, - {GB_TILE_MODE16, false}, - {GB_TILE_MODE17, false}, - {GB_TILE_MODE18, false}, - {GB_TILE_MODE19, false}, - {GB_TILE_MODE20, false}, - {GB_TILE_MODE21, false}, - {GB_TILE_MODE22, false}, - {GB_TILE_MODE23, false}, - {GB_TILE_MODE24, false}, - {GB_TILE_MODE25, false}, - {GB_TILE_MODE26, false}, - {GB_TILE_MODE27, false}, - {GB_TILE_MODE28, false}, - {GB_TILE_MODE29, false}, - {GB_TILE_MODE30, false}, - {GB_TILE_MODE31, false}, - {CC_RB_BACKEND_DISABLE, false, true}, - {GC_USER_RB_BACKEND_DISABLE, false, true}, - {PA_SC_RASTER_CONFIG, false, true}, + {GRBM_STATUS}, + {GB_ADDR_CONFIG}, + {MC_ARB_RAMCFG}, + {GB_TILE_MODE0}, + {GB_TILE_MODE1}, + {GB_TILE_MODE2}, + {GB_TILE_MODE3}, + {GB_TILE_MODE4}, + {GB_TILE_MODE5}, + {GB_TILE_MODE6}, + {GB_TILE_MODE7}, + {GB_TILE_MODE8}, + {GB_TILE_MODE9}, + {GB_TILE_MODE10}, + {GB_TILE_MODE11}, + {GB_TILE_MODE12}, + {GB_TILE_MODE13}, + {GB_TILE_MODE14}, + {GB_TILE_MODE15}, + {GB_TILE_MODE16}, + {GB_TILE_MODE17}, + {GB_TILE_MODE18}, + {GB_TILE_MODE19}, + {GB_TILE_MODE20}, + {GB_TILE_MODE21}, + {GB_TILE_MODE22}, + {GB_TILE_MODE23}, + {GB_TILE_MODE24}, + {GB_TILE_MODE25}, + {GB_TILE_MODE26}, + {GB_TILE_MODE27}, + {GB_TILE_MODE28}, + {GB_TILE_MODE29}, + {GB_TILE_MODE30}, + {GB_TILE_MODE31}, + {CC_RB_BACKEND_DISABLE, true}, + {GC_USER_RB_BACKEND_DISABLE, true}, + {PA_SC_RASTER_CONFIG, true}, }; static uint32_t si_get_register_value(struct amdgpu_device *adev, @@ -1093,13 +1093,13 @@ static int si_read_register(struct amdgpu_device *adev, u32 se_num, *value = 0; for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { + bool indexed = si_allowed_read_registers[i].grbm_indexed; + if (reg_offset != si_allowed_read_registers[i].reg_offset) continue; - if (!si_allowed_read_registers[i].untouched) - *value = si_get_register_value(adev, - si_allowed_read_registers[i].grbm_indexed, - se_num, sh_num, reg_offset); + *value = si_get_register_value(adev, indexed, se_num, sh_num, + reg_offset); return 0; } return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index 7c1c5d127281..a7ad8390981c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -21,7 +21,7 @@ * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_dpm.h" diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index e66084211c74..ce25e03a077d 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "sid.h" diff --git a/drivers/gpu/drm/amd/amdgpu/si_smc.c b/drivers/gpu/drm/amd/amdgpu/si_smc.c index 0726bc3b6f90..4a2fd8b61940 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_smc.c +++ b/drivers/gpu/drm/amd/amdgpu/si_smc.c @@ -23,7 +23,7 @@ */ #include <linux/firmware.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "sid.h" #include "ppsmc.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 6b55d451ae7f..a7341d88a320 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -23,7 +23,7 @@ #include <linux/firmware.h> #include <linux/slab.h> #include <linux/module.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_atomfirmware.h" #include "amdgpu_ih.h" @@ -57,6 +57,7 @@ #include "sdma_v4_0.h" #include "uvd_v7_0.h" #include "vce_v4_0.h" +#include "vcn_v1_0.h" #include "amdgpu_powerplay.h" #include "dce_virtual.h" #include "mxgpu_ai.h" @@ -104,10 +105,10 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) u32 r; struct nbio_pcie_index_data *nbio_pcie_id; - if (adev->asic_type == CHIP_VEGA10) - nbio_pcie_id = &nbio_v6_1_pcie_index_data; + if (adev->flags & AMD_IS_APU) + nbio_pcie_id = &nbio_v7_0_pcie_index_data; else - BUG(); + nbio_pcie_id = &nbio_v6_1_pcie_index_data; address = nbio_pcie_id->index_offset; data = nbio_pcie_id->data_offset; @@ -125,10 +126,10 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) unsigned long flags, address, data; struct nbio_pcie_index_data *nbio_pcie_id; - if (adev->asic_type == CHIP_VEGA10) - nbio_pcie_id = &nbio_v6_1_pcie_index_data; + if (adev->flags & AMD_IS_APU) + nbio_pcie_id = &nbio_v7_0_pcie_index_data; else - BUG(); + nbio_pcie_id = &nbio_v6_1_pcie_index_data; address = nbio_pcie_id->index_offset; data = nbio_pcie_id->data_offset; @@ -199,13 +200,20 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) static u32 soc15_get_config_memsize(struct amdgpu_device *adev) { - return nbio_v6_1_get_memsize(adev); + if (adev->flags & AMD_IS_APU) + return nbio_v7_0_get_memsize(adev); + else + return nbio_v6_1_get_memsize(adev); } static const u32 vega10_golden_init[] = { }; +static const u32 raven_golden_init[] = +{ +}; + static void soc15_init_golden_registers(struct amdgpu_device *adev) { /* Some of the registers might be dependent on GRBM_GFX_INDEX */ @@ -217,6 +225,11 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) vega10_golden_init, (const u32)ARRAY_SIZE(vega10_golden_init)); break; + case CHIP_RAVEN: + amdgpu_program_register_sequence(adev, + raven_golden_init, + (const u32)ARRAY_SIZE(raven_golden_init)); + break; default: break; } @@ -280,29 +293,25 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, return true; } -static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = { - /* todo */ -}; - static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false}, - { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false}, - { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false}, - { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false}, - { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false}, - { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)}, + { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)}, + { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)}, + { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)}, }; static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, @@ -341,41 +350,16 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev, static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { - struct amdgpu_allowed_register_entry *asic_register_table = NULL; - struct amdgpu_allowed_register_entry *asic_register_entry; - uint32_t size, i; + uint32_t i; *value = 0; - switch (adev->asic_type) { - case CHIP_VEGA10: - asic_register_table = vega10_allowed_read_registers; - size = ARRAY_SIZE(vega10_allowed_read_registers); - break; - default: - return -EINVAL; - } - - if (asic_register_table) { - for (i = 0; i < size; i++) { - asic_register_entry = asic_register_table + i; - if (reg_offset != asic_register_entry->reg_offset) - continue; - if (!asic_register_entry->untouched) - *value = soc15_get_register_value(adev, - asic_register_entry->grbm_indexed, - se_num, sh_num, reg_offset); - return 0; - } - } - for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { if (reg_offset != soc15_allowed_read_registers[i].reg_offset) continue; - if (!soc15_allowed_read_registers[i].untouched) - *value = soc15_get_register_value(adev, - soc15_allowed_read_registers[i].grbm_indexed, - se_num, sh_num, reg_offset); + *value = soc15_get_register_value(adev, + soc15_allowed_read_registers[i].grbm_indexed, + se_num, sh_num, reg_offset); return 0; } return -EINVAL; @@ -396,7 +380,10 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { - if (nbio_v6_1_get_memsize(adev) != 0xffffffff) + u32 memsize = (adev->flags & AMD_IS_APU) ? + nbio_v7_0_get_memsize(adev) : + nbio_v6_1_get_memsize(adev); + if (memsize != 0xffffffff) break; udelay(1); } @@ -470,8 +457,12 @@ static void soc15_program_aspm(struct amdgpu_device *adev) static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { - nbio_v6_1_enable_doorbell_aperture(adev, enable); - nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); + if (adev->flags & AMD_IS_APU) { + nbio_v7_0_enable_doorbell_aperture(adev, enable); + } else { + nbio_v6_1_enable_doorbell_aperture(adev, enable); + nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); + } } static const struct amdgpu_ip_block_version vega10_common_ip_block = @@ -493,8 +484,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: amdgpu_ip_block_add(adev, &vega10_common_ip_block); - amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block); - amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block); amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); amdgpu_ip_block_add(adev, &vega10_ih_ip_block); if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) @@ -508,6 +497,18 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); break; + case CHIP_RAVEN: + amdgpu_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); + amdgpu_ip_block_add(adev, &vega10_ih_ip_block); + amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); + amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); + break; default: return -EINVAL; } @@ -517,7 +518,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) { - return nbio_v6_1_get_rev_id(adev); + if (adev->flags & AMD_IS_APU) + return nbio_v7_0_get_rev_id(adev); + else + return nbio_v6_1_get_rev_id(adev); } @@ -560,11 +564,6 @@ static int soc15_common_early_init(void *handle) (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) psp_enabled = true; - if (amdgpu_sriov_vf(adev)) { - amdgpu_virt_init_setting(adev); - xgpu_ai_mailbox_set_irq_funcs(adev); - } - /* * nbio need be used for both sdma and gfx9, but only * initializes once @@ -573,6 +572,9 @@ static int soc15_common_early_init(void *handle) case CHIP_VEGA10: nbio_v6_1_init(adev); break; + case CHIP_RAVEN: + nbio_v7_0_init(adev); + break; default: return -EINVAL; } @@ -603,11 +605,40 @@ static int soc15_common_early_init(void *handle) adev->pg_flags = 0; adev->external_rev_id = 0x1; break; + case CHIP_RAVEN: + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_DRM_MGCG | + AMD_CG_SUPPORT_DRM_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS; + adev->pg_flags = AMD_PG_SUPPORT_SDMA | + AMD_PG_SUPPORT_MMHUB; + adev->external_rev_id = 0x1; + break; default: /* FIXME: not supported yet */ return -EINVAL; } + if (amdgpu_sriov_vf(adev)) { + amdgpu_virt_init_setting(adev); + xgpu_ai_mailbox_set_irq_funcs(adev); + } + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); amdgpu_get_pcie_info(adev); @@ -825,6 +856,20 @@ static int soc15_common_set_clockgating_state(void *handle, soc15_update_df_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); break; + case CHIP_RAVEN: + nbio_v7_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + nbio_v6_1_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_hdp_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_drm_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_drm_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_rom_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index 378a46da585a..acb3cdb119f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -25,6 +25,7 @@ #define __SOC15_H__ #include "nbio_v6_1.h" +#include "nbio_v7_0.h" extern const struct amd_ip_funcs soc15_common_ip_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index e8df6d820dbe..e2d330eed952 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -63,6 +63,13 @@ struct nbio_pcie_index_data { (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ (ip##_BASE__INST##inst##_SEG4 + reg)))))) +#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ + RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ + (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ + (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ + (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ + (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset) + #define WREG32_SOC15(ip, inst, reg, value) \ WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ @@ -70,6 +77,13 @@ struct nbio_pcie_index_data { (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ (ip##_BASE__INST##inst##_SEG4 + reg))))), value) +#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ + WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ + (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ + (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ + (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ + (ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value) + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index 75403c7c8c9e..e79befd80eed 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -132,6 +132,7 @@ * 1 - pfp */ #define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_VALID (1 << 23) #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) /* 0 - LRU * 1 - Stream @@ -259,8 +260,97 @@ #define PACKET3_WAIT_ON_CE_COUNTER 0x86 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 #define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_CMD(x) ((x) << 28) + /* + * x=0: tmz_begin + * x=1: tmz_end + */ + #define PACKET3_SET_RESOURCES 0xA0 +/* 1. header + * 2. CONTROL + * 3. QUEUE_MASK_LO [31:0] + * 4. QUEUE_MASK_HI [31:0] + * 5. GWS_MASK_LO [31:0] + * 6. GWS_MASK_HI [31:0] + * 7. OAC_MASK [15:0] + * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] + */ +# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) +# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) +# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) #define PACKET3_MAP_QUEUES 0xA2 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. MQD_ADDR_LO [31:0] + * 5. MQD_ADDR_HI [31:0] + * 6. WPTR_ADDR_LO [31:0] + * 7. WPTR_ADDR_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) +# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) +# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) +# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) +# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) +# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) +# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2 */ +# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) +# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) +#define PACKET3_UNMAP_QUEUES 0xA3 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. CONTROL3 + * 5. CONTROL4 + * 6. CONTROL5 + */ +/* CONTROL */ +# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) + /* 0 - PREEMPT_QUEUES + * 1 - RESET_QUEUES + * 2 - DISABLE_PROCESS_QUEUES + * 3 - PREEMPT_QUEUES_NO_UNMAP + */ +# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2a */ +# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) +/* CONTROL3a */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) +/* CONTROL3b */ +# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) +/* CONTROL4 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) +/* CONTROL5 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) +#define PACKET3_QUERY_STATUS 0xA4 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. ADDR_LO [31:0] + * 5. ADDR_HI [31:0] + * 6. DATA_LO [31:0] + * 7. DATA_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) +# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) +# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) +/* CONTROL2a */ +# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) +# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) + #define VCE_CMD_NO_OP 0x00000000 #define VCE_CMD_END 0x00000001 diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 3a5097ac2bb4..923df2c0e535 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "vid.h" diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index eca8f6e01e97..987b958368ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -58,7 +58,7 @@ static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); + return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); } /** @@ -73,9 +73,9 @@ static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->uvd.ring_enc[0]) - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR)); + return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); else - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2)); + return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); } /** @@ -89,7 +89,7 @@ static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR)); + return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); } /** @@ -107,9 +107,9 @@ static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) return adev->wb.wb[ring->wptr_offs]; if (ring == &adev->uvd.ring_enc[0]) - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR)); + return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); else - return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2)); + return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); } /** @@ -123,7 +123,7 @@ static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } /** @@ -145,10 +145,10 @@ static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) } if (ring == &adev->uvd.ring_enc[0]) - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); else - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); } @@ -562,7 +562,13 @@ static int uvd_v7_0_hw_fini(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; - uvd_v7_0_stop(adev); + if (!amdgpu_sriov_vf(adev)) + uvd_v7_0_stop(adev); + else { + /* full access mode, so don't touch any UVD register */ + DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); + } + ring->ready = false; return 0; @@ -611,46 +617,46 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) uint32_t offset; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); offset = 0; } else { - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, lower_32_bits(adev->uvd.gpu_addr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, upper_32_bits(adev->uvd.gpu_addr)); offset = size; } - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, lower_32_bits(adev->uvd.gpu_addr + offset)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, upper_32_bits(adev->uvd.gpu_addr + offset)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG), + WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG), + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG), + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); + WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); } static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, @@ -664,29 +670,29 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, size = header->header_size + header->vce_table_size + header->uvd_table_size; /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr)); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); /* 2, update vmid of descriptor */ - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID)); + data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); /* 3, notify mmsch about the size of this descriptor */ - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); /* 4, set resp to zero */ - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); + WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); + data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); loop = 1000; while ((data & 0x10000002) != 0x10000002) { udelay(10); - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); + data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); loop--; if (!loop) break; @@ -696,6 +702,7 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); return -EBUSY; } + WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0); return 0; } @@ -928,7 +935,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) mdelay(1); /* put LMI, VCPU, RBC etc... into reset */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | @@ -940,7 +947,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) mdelay(5); /* initialize UVD memory controller */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL), + WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | @@ -953,23 +960,23 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) lmi_swap_cntl = 0xa; mp_swap_cntl = 0; #endif - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), mp_swap_cntl); + WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); /* take all subblocks out of reset, except VCPU */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); mdelay(5); /* enable VCPU clock */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); /* enable UMC */ @@ -977,14 +984,14 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); /* boot up the VCPU */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0); + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); mdelay(10); for (i = 0; i < 10; ++i) { uint32_t status; for (j = 0; j < 100; ++j) { - status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS)); + status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); if (status & 2) break; mdelay(10); @@ -1025,44 +1032,44 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); /* set the write pointer delay */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); /* set the wb address */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR), + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); /* programm the RB_BASE for ring buffer */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); /* Initialize the ring buffer's read and write pointers */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); - ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); ring = &adev->uvd.ring_enc[0]; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); ring = &adev->uvd.ring_enc[1]; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); return 0; } @@ -1077,7 +1084,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) static void uvd_v7_0_stop(struct amdgpu_device *adev) { /* force RBC into idle state */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); /* Stall UMC and register bus before resetting VCPU */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), @@ -1086,12 +1093,12 @@ static void uvd_v7_0_stop(struct amdgpu_device *adev) mdelay(1); /* put VCPU into reset */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); mdelay(5); /* disable VCPU clock */ - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); /* Unstall UMC and register bus */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, @@ -1196,7 +1203,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) unsigned i; int r; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD); + WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD); r = amdgpu_ring_alloc(ring, 3); if (r) { DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", @@ -1208,7 +1215,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0xDEADBEEF); amdgpu_ring_commit(ring); for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID)); + tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID); if (tmp == 0xDEADBEEF) break; DRM_UDELAY(1); @@ -1309,9 +1316,8 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t data0, data1, mask; unsigned eng = ring->vm_inv_eng; - pd_addr = pd_addr | 0x1; /* valid bit */ - /* now only use physical base address of PDE and valid */ - BUG_ON(pd_addr & 0xFFFF00000000003EULL); + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; data1 = upper_32_bits(pd_addr); @@ -1350,9 +1356,8 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; - pd_addr = pd_addr | 0x1; /* valid bit */ - /* now only use physical base address of PDE and valid */ - BUG_ON(pd_addr & 0xFFFF00000000003EULL); + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); @@ -1408,8 +1413,8 @@ static bool uvd_v7_0_check_soft_reset(void *handle) if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || - (RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS) & - AMDGPU_UVD_STATUS_BUSY_MASK))) + (RREG32_SOC15(UVD, 0, mmUVD_STATUS) & + AMDGPU_UVD_STATUS_BUSY_MASK)) srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); @@ -1516,9 +1521,9 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) { uint32_t data, data1, data2, suvd_flags; - data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL)); - data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE)); - data2 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL)); + data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL); + data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE); + data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL); data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); @@ -1562,18 +1567,18 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); data1 |= suvd_flags; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), data); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), 0); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL), data2); + WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data); + WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0); + WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1); + WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2); } static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) { uint32_t data, data1, cgc_flags, suvd_flags; - data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE)); - data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE)); + data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE); + data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE); cgc_flags = UVD_CGC_GATE__SYS_MASK | UVD_CGC_GATE__UDEC_MASK | @@ -1605,8 +1610,8 @@ static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) data |= cgc_flags; data1 |= suvd_flags; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), data); - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1); + WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data); + WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1); } static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) @@ -1665,7 +1670,7 @@ static int uvd_v7_0_set_powergating_state(void *handle, if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) return 0; - WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), UVD_POWER_STATUS__UVD_PG_EN_MASK); + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); if (state == AMD_PG_STATE_GATE) { uvd_v7_0_stop(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 139f964196b4..1ecd6bb90c1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -190,6 +190,7 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev, dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); return -EBUSY; } + WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); return 0; } @@ -418,15 +419,19 @@ static int vce_v4_0_sw_init(void *handle) if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { const struct common_firmware_header *hdr; + unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); + + adev->vce.saved_bo = kmalloc(size, GFP_KERNEL); + if (!adev->vce.saved_bo) + return -ENOMEM; + hdr = (const struct common_firmware_header *)adev->vce.fw->data; adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].ucode_id = AMDGPU_UCODE_ID_VCE; adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw; adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); DRM_INFO("PSP loading VCE firmware\n"); - } - - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + } else { r = amdgpu_vce_resume(adev); if (r) return r; @@ -465,6 +470,11 @@ static int vce_v4_0_sw_fini(void *handle) /* free MM table */ amdgpu_virt_free_mm_table(adev); + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + kfree(adev->vce.saved_bo); + adev->vce.saved_bo = NULL; + } + r = amdgpu_vce_suspend(adev); if (r) return r; @@ -505,8 +515,14 @@ static int vce_v4_0_hw_fini(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i; - /* vce_v4_0_wait_for_idle(handle); */ - vce_v4_0_stop(adev); + if (!amdgpu_sriov_vf(adev)) { + /* vce_v4_0_wait_for_idle(handle); */ + vce_v4_0_stop(adev); + } else { + /* full access mode, so don't touch any VCE register */ + DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); + } + for (i = 0; i < adev->vce.num_rings; i++) adev->vce.ring[i].ready = false; @@ -515,8 +531,18 @@ static int vce_v4_0_hw_fini(void *handle) static int vce_v4_0_suspend(void *handle) { - int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + + if (adev->vce.vcpu_bo == NULL) + return 0; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); + void *ptr = adev->vce.cpu_addr; + + memcpy_fromio(adev->vce.saved_bo, ptr, size); + } r = vce_v4_0_hw_fini(adev); if (r) @@ -527,12 +553,22 @@ static int vce_v4_0_suspend(void *handle) static int vce_v4_0_resume(void *handle) { - int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; - r = amdgpu_vce_resume(adev); - if (r) - return r; + if (adev->vce.vcpu_bo == NULL) + return -EINVAL; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); + void *ptr = adev->vce.cpu_addr; + + memcpy_toio(ptr, adev->vce.saved_bo, size); + } else { + r = amdgpu_vce_resume(adev); + if (r) + return r; + } return vce_v4_0_hw_init(adev); } @@ -919,9 +955,8 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; - pd_addr = pd_addr | 0x1; /* valid bit */ - /* now only use physical base address of PDE and valid */ - BUG_ON(pd_addr & 0xFFFF00000000003EULL); + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c new file mode 100644 index 000000000000..21e7b88401e1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -0,0 +1,1189 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/firmware.h> +#include <drm/drmP.h> +#include "amdgpu.h" +#include "amdgpu_vcn.h" +#include "soc15d.h" +#include "soc15_common.h" + +#include "vega10/soc15ip.h" +#include "raven1/VCN/vcn_1_0_offset.h" +#include "raven1/VCN/vcn_1_0_sh_mask.h" +#include "vega10/HDP/hdp_4_0_offset.h" +#include "raven1/MMHUB/mmhub_9_1_offset.h" +#include "raven1/MMHUB/mmhub_9_1_sh_mask.h" + +static int vcn_v1_0_start(struct amdgpu_device *adev); +static int vcn_v1_0_stop(struct amdgpu_device *adev); +static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); +static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); +static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); + +/** + * vcn_v1_0_early_init - set function pointers + * + * @handle: amdgpu_device pointer + * + * Set ring and irq function pointers + */ +static int vcn_v1_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->vcn.num_enc_rings = 2; + + vcn_v1_0_set_dec_ring_funcs(adev); + vcn_v1_0_set_enc_ring_funcs(adev); + vcn_v1_0_set_irq_funcs(adev); + + return 0; +} + +/** + * vcn_v1_0_sw_init - sw init for VCN block + * + * @handle: amdgpu_device pointer + * + * Load firmware and sw initialization + */ +static int vcn_v1_0_sw_init(void *handle) +{ + struct amdgpu_ring *ring; + int i, r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* VCN DEC TRAP */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq); + if (r) + return r; + + /* VCN ENC TRAP */ + for (i = 0; i < adev->vcn.num_enc_rings; ++i) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, i + 119, + &adev->vcn.irq); + if (r) + return r; + } + + r = amdgpu_vcn_sw_init(adev); + if (r) + return r; + + r = amdgpu_vcn_resume(adev); + if (r) + return r; + + ring = &adev->vcn.ring_dec; + sprintf(ring->name, "vcn_dec"); + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); + if (r) + return r; + + for (i = 0; i < adev->vcn.num_enc_rings; ++i) { + ring = &adev->vcn.ring_enc[i]; + sprintf(ring->name, "vcn_enc%d", i); + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); + if (r) + return r; + } + + return r; +} + +/** + * vcn_v1_0_sw_fini - sw fini for VCN block + * + * @handle: amdgpu_device pointer + * + * VCN suspend and free up sw allocation + */ +static int vcn_v1_0_sw_fini(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = amdgpu_vcn_suspend(adev); + if (r) + return r; + + r = amdgpu_vcn_sw_fini(adev); + + return r; +} + +/** + * vcn_v1_0_hw_init - start and test VCN block + * + * @handle: amdgpu_device pointer + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int vcn_v1_0_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ring *ring = &adev->vcn.ring_dec; + int i, r; + + r = vcn_v1_0_start(adev); + if (r) + goto done; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + + for (i = 0; i < adev->vcn.num_enc_rings; ++i) { + ring = &adev->vcn.ring_enc[i]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + } + +done: + if (!r) + DRM_INFO("VCN decode and encode initialized successfully.\n"); + + return r; +} + +/** + * vcn_v1_0_hw_fini - stop the hardware block + * + * @handle: amdgpu_device pointer + * + * Stop the VCN block, mark ring as not ready any more + */ +static int vcn_v1_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ring *ring = &adev->vcn.ring_dec; + int r; + + r = vcn_v1_0_stop(adev); + if (r) + return r; + + ring->ready = false; + + return 0; +} + +/** + * vcn_v1_0_suspend - suspend VCN block + * + * @handle: amdgpu_device pointer + * + * HW fini and suspend VCN block + */ +static int vcn_v1_0_suspend(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = vcn_v1_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_vcn_suspend(adev); + + return r; +} + +/** + * vcn_v1_0_resume - resume VCN block + * + * @handle: amdgpu_device pointer + * + * Resume firmware and hw init VCN block + */ +static int vcn_v1_0_resume(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = amdgpu_vcn_resume(adev); + if (r) + return r; + + r = vcn_v1_0_hw_init(adev); + + return r; +} + +/** + * vcn_v1_0_mc_resume - memory controller programming + * + * @adev: amdgpu_device pointer + * + * Let the VCN memory controller know it's offsets + */ +static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) +{ + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr + size)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr + size)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, + AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); + + WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); +} + +/** + * vcn_v1_0_disable_clock_gating - disable VCN clock gating + * + * @adev: amdgpu_device pointer + * @sw: enable SW clock gating + * + * Disable clock gating for VCN block + */ +static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) +{ + uint32_t data; + + /* JPEG disable CGC */ + data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); + + if (sw) + data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; + + data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); + + data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); + data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); + WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); + + /* UVD disable CGC */ + data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); + if (sw) + data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + + data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); + + data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); + data &= ~(UVD_CGC_GATE__SYS_MASK + | UVD_CGC_GATE__UDEC_MASK + | UVD_CGC_GATE__MPEG2_MASK + | UVD_CGC_GATE__REGS_MASK + | UVD_CGC_GATE__RBC_MASK + | UVD_CGC_GATE__LMI_MC_MASK + | UVD_CGC_GATE__LMI_UMC_MASK + | UVD_CGC_GATE__IDCT_MASK + | UVD_CGC_GATE__MPRD_MASK + | UVD_CGC_GATE__MPC_MASK + | UVD_CGC_GATE__LBSI_MASK + | UVD_CGC_GATE__LRBBM_MASK + | UVD_CGC_GATE__UDEC_RE_MASK + | UVD_CGC_GATE__UDEC_CM_MASK + | UVD_CGC_GATE__UDEC_IT_MASK + | UVD_CGC_GATE__UDEC_DB_MASK + | UVD_CGC_GATE__UDEC_MP_MASK + | UVD_CGC_GATE__WCB_MASK + | UVD_CGC_GATE__VCPU_MASK + | UVD_CGC_GATE__SCPU_MASK); + WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); + + data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); + data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK + | UVD_CGC_CTRL__UDEC_CM_MODE_MASK + | UVD_CGC_CTRL__UDEC_IT_MODE_MASK + | UVD_CGC_CTRL__UDEC_DB_MODE_MASK + | UVD_CGC_CTRL__UDEC_MP_MODE_MASK + | UVD_CGC_CTRL__SYS_MODE_MASK + | UVD_CGC_CTRL__UDEC_MODE_MASK + | UVD_CGC_CTRL__MPEG2_MODE_MASK + | UVD_CGC_CTRL__REGS_MODE_MASK + | UVD_CGC_CTRL__RBC_MODE_MASK + | UVD_CGC_CTRL__LMI_MC_MODE_MASK + | UVD_CGC_CTRL__LMI_UMC_MODE_MASK + | UVD_CGC_CTRL__IDCT_MODE_MASK + | UVD_CGC_CTRL__MPRD_MODE_MASK + | UVD_CGC_CTRL__MPC_MODE_MASK + | UVD_CGC_CTRL__LBSI_MODE_MASK + | UVD_CGC_CTRL__LRBBM_MODE_MASK + | UVD_CGC_CTRL__WCB_MODE_MASK + | UVD_CGC_CTRL__VCPU_MODE_MASK + | UVD_CGC_CTRL__SCPU_MODE_MASK); + WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); + + /* turn on */ + data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); + data |= (UVD_SUVD_CGC_GATE__SRE_MASK + | UVD_SUVD_CGC_GATE__SIT_MASK + | UVD_SUVD_CGC_GATE__SMP_MASK + | UVD_SUVD_CGC_GATE__SCM_MASK + | UVD_SUVD_CGC_GATE__SDB_MASK + | UVD_SUVD_CGC_GATE__SRE_H264_MASK + | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK + | UVD_SUVD_CGC_GATE__SIT_H264_MASK + | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK + | UVD_SUVD_CGC_GATE__SCM_H264_MASK + | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK + | UVD_SUVD_CGC_GATE__SDB_H264_MASK + | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK + | UVD_SUVD_CGC_GATE__SCLR_MASK + | UVD_SUVD_CGC_GATE__UVD_SC_MASK + | UVD_SUVD_CGC_GATE__ENT_MASK + | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK + | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK + | UVD_SUVD_CGC_GATE__SITE_MASK + | UVD_SUVD_CGC_GATE__SRE_VP9_MASK + | UVD_SUVD_CGC_GATE__SCM_VP9_MASK + | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK + | UVD_SUVD_CGC_GATE__SDB_VP9_MASK + | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); + WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); + + data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); + data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK + | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK + | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK + | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK + | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK + | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK + | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK + | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK + | UVD_SUVD_CGC_CTRL__IME_MODE_MASK + | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); + WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); +} + +/** + * vcn_v1_0_enable_clock_gating - enable VCN clock gating + * + * @adev: amdgpu_device pointer + * @sw: enable SW clock gating + * + * Enable clock gating for VCN block + */ +static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) +{ + uint32_t data = 0; + + /* enable JPEG CGC */ + data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); + if (sw) + data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); + + data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); + data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); + WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); + + /* enable UVD CGC */ + data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); + if (sw) + data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); + + data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); + data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK + | UVD_CGC_CTRL__UDEC_CM_MODE_MASK + | UVD_CGC_CTRL__UDEC_IT_MODE_MASK + | UVD_CGC_CTRL__UDEC_DB_MODE_MASK + | UVD_CGC_CTRL__UDEC_MP_MODE_MASK + | UVD_CGC_CTRL__SYS_MODE_MASK + | UVD_CGC_CTRL__UDEC_MODE_MASK + | UVD_CGC_CTRL__MPEG2_MODE_MASK + | UVD_CGC_CTRL__REGS_MODE_MASK + | UVD_CGC_CTRL__RBC_MODE_MASK + | UVD_CGC_CTRL__LMI_MC_MODE_MASK + | UVD_CGC_CTRL__LMI_UMC_MODE_MASK + | UVD_CGC_CTRL__IDCT_MODE_MASK + | UVD_CGC_CTRL__MPRD_MODE_MASK + | UVD_CGC_CTRL__MPC_MODE_MASK + | UVD_CGC_CTRL__LBSI_MODE_MASK + | UVD_CGC_CTRL__LRBBM_MODE_MASK + | UVD_CGC_CTRL__WCB_MODE_MASK + | UVD_CGC_CTRL__VCPU_MODE_MASK + | UVD_CGC_CTRL__SCPU_MODE_MASK); + WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); + + data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); + data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK + | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK + | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK + | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK + | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK + | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK + | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK + | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK + | UVD_SUVD_CGC_CTRL__IME_MODE_MASK + | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); + WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); +} + +/** + * vcn_v1_0_start - start VCN block + * + * @adev: amdgpu_device pointer + * + * Setup and start the VCN block + */ +static int vcn_v1_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->vcn.ring_dec; + uint32_t rb_bufsz, tmp; + uint32_t lmi_swap_cntl; + int i, j, r; + + /* disable byte swapping */ + lmi_swap_cntl = 0; + + vcn_v1_0_mc_resume(adev); + + /* disable clock gating */ + vcn_v1_0_disable_clock_gating(adev, true); + + /* disable interupt */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* stall UMC and register bus before resetting VCPU */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + mdelay(1); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, + UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | + UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | + UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | + UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); + mdelay(5); + + /* initialize VCN memory controller */ + WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, + (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + 0x00100000L); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; +#endif + WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); + + /* take all subblocks out of reset, except VCPU */ + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* enable VCPU clock */ + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, + UVD_VCPU_CNTL__CLK_EN_MASK); + + /* enable UMC */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + + /* boot up the VCPU */ + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); + mdelay(10); + + for (i = 0; i < 10; ++i) { + uint32_t status; + + for (j = 0; j < 100; ++j) { + status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + if (r) { + DRM_ERROR("VCN decode not responding, giving up!!!\n"); + return r; + } + /* enable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), + ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); + + /* clear the bit 4 of VCN_STATUS */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); + + /* force RBC into idle state */ + rb_bufsz = order_base_2(ring->ring_size); + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); + + /* set the write pointer delay */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); + + /* set the wb address */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, + (upper_32_bits(ring->gpu_addr) >> 2)); + + /* programm the RB_BASE for ring buffer */ + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); + + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + lower_32_bits(ring->wptr)); + + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, + ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); + + ring = &adev->vcn.ring_enc[0]; + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); + + ring = &adev->vcn.ring_enc[1]; + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); + + return 0; +} + +/** + * vcn_v1_0_stop - stop VCN block + * + * @adev: amdgpu_device pointer + * + * stop the VCN block + */ +static int vcn_v1_0_stop(struct amdgpu_device *adev) +{ + /* force RBC into idle state */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + mdelay(1); + + /* put VCPU into reset */ + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* disable VCPU clock */ + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); + + /* Unstall UMC and register bus */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + + /* enable clock gating */ + vcn_v1_0_enable_clock_gating(adev, true); + + return 0; +} + +static int vcn_v1_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + /* needed for driver unload*/ + return 0; +} + +/** + * vcn_v1_0_dec_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); +} + +/** + * vcn_v1_0_dec_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); +} + +/** + * vcn_v1_0_dec_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); +} + +/** + * vcn_v1_0_dec_ring_insert_start - insert a start command + * + * @ring: amdgpu_ring pointer + * + * Write a start command to the ring. + */ +static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); +} + +/** + * vcn_v1_0_dec_ring_insert_end - insert a end command + * + * @ring: amdgpu_ring pointer + * + * Write a end command to the ring. + */ +static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); +} + +/** + * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write a fence and a trap command to the ring. + */ +static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) +{ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); +} + +/** + * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate + * + * @ring: amdgpu_ring pointer + * + * Emits an hdp invalidate. + */ +static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0)); + amdgpu_ring_write(ring, 1); +} + +/** + * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write ring commands to execute the indirect buffer + */ +static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); + amdgpu_ring_write(ring, vm_id); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); + amdgpu_ring_write(ring, ib->length_dw); +} + +static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, data1); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); +} + +static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1, uint32_t mask) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, data1); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); +} + +static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; + uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + uint32_t data0, data1, mask; + unsigned eng = ring->vm_inv_eng; + + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; + + data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; + data1 = upper_32_bits(pd_addr); + vcn_v1_0_dec_vm_reg_write(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; + data1 = lower_32_bits(pd_addr); + vcn_v1_0_dec_vm_reg_write(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; + data1 = lower_32_bits(pd_addr); + mask = 0xffffffff; + vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); + + /* flush TLB */ + data0 = (hub->vm_inv_eng0_req + eng) << 2; + data1 = req; + vcn_v1_0_dec_vm_reg_write(ring, data0, data1); + + /* wait for flush */ + data0 = (hub->vm_inv_eng0_ack + eng) << 2; + data1 = 1 << vm_id; + mask = 1 << vm_id; + vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); +} + +/** + * vcn_v1_0_enc_ring_get_rptr - get enc read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware enc read pointer + */ +static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vcn.ring_enc[0]) + return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); + else + return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); +} + + /** + * vcn_v1_0_enc_ring_get_wptr - get enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware enc write pointer + */ +static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vcn.ring_enc[0]) + return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); + else + return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); +} + + /** + * vcn_v1_0_enc_ring_set_wptr - set enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the enc write pointer to the hardware + */ +static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vcn.ring_enc[0]) + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, + lower_32_bits(ring->wptr)); + else + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, + lower_32_bits(ring->wptr)); +} + +/** + * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write enc a fence and a trap command to the ring. + */ +static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) +{ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); + amdgpu_ring_write(ring, addr); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); +} + +static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, VCN_ENC_CMD_END); +} + +/** + * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write enc ring commands to execute the indirect buffer + */ +static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) +{ + amdgpu_ring_write(ring, VCN_ENC_CMD_IB); + amdgpu_ring_write(ring, vm_id); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); +} + +static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vm_id, uint64_t pd_addr) +{ + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; + uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); + unsigned eng = ring->vm_inv_eng; + + pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); + pd_addr |= AMDGPU_PTE_VALID; + + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, upper_32_bits(pd_addr)); + + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + /* flush TLB */ + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2); + amdgpu_ring_write(ring, req); + + /* wait for flush */ + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); + amdgpu_ring_write(ring, 1 << vm_id); + amdgpu_ring_write(ring, 1 << vm_id); +} + +static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + return 0; +} + +static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: VCN TRAP\n"); + + switch (entry->src_id) { + case 124: + amdgpu_fence_process(&adev->vcn.ring_dec); + break; + case 119: + amdgpu_fence_process(&adev->vcn.ring_enc[0]); + break; + case 120: + amdgpu_fence_process(&adev->vcn.ring_enc[1]); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { + .name = "vcn_v1_0", + .early_init = vcn_v1_0_early_init, + .late_init = NULL, + .sw_init = vcn_v1_0_sw_init, + .sw_fini = vcn_v1_0_sw_fini, + .hw_init = vcn_v1_0_hw_init, + .hw_fini = vcn_v1_0_hw_fini, + .suspend = vcn_v1_0_suspend, + .resume = vcn_v1_0_resume, + .is_idle = NULL /* vcn_v1_0_is_idle */, + .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */, + .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, + .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, + .soft_reset = NULL /* vcn_v1_0_soft_reset */, + .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, + .set_clockgating_state = vcn_v1_0_set_clockgating_state, + .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */, +}; + +static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_DEC, + .align_mask = 0xf, + .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0), + .support_64bit_ptrs = false, + .vmhub = AMDGPU_MMHUB, + .get_rptr = vcn_v1_0_dec_ring_get_rptr, + .get_wptr = vcn_v1_0_dec_ring_get_wptr, + .set_wptr = vcn_v1_0_dec_ring_set_wptr, + .emit_frame_size = + 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ + 34 + /* vcn_v1_0_dec_ring_emit_vm_flush */ + 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ + 6, + .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ + .emit_ib = vcn_v1_0_dec_ring_emit_ib, + .emit_fence = vcn_v1_0_dec_ring_emit_fence, + .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, + .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate, + .test_ring = amdgpu_vcn_dec_ring_test_ring, + .test_ib = amdgpu_vcn_dec_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_start = vcn_v1_0_dec_ring_insert_start, + .insert_end = vcn_v1_0_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, +}; + +static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_ENC, + .align_mask = 0x3f, + .nop = VCN_ENC_CMD_NO_OP, + .support_64bit_ptrs = false, + .vmhub = AMDGPU_MMHUB, + .get_rptr = vcn_v1_0_enc_ring_get_rptr, + .get_wptr = vcn_v1_0_enc_ring_get_wptr, + .set_wptr = vcn_v1_0_enc_ring_set_wptr, + .emit_frame_size = + 17 + /* vcn_v1_0_enc_ring_emit_vm_flush */ + 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ + 1, /* vcn_v1_0_enc_ring_insert_end */ + .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ + .emit_ib = vcn_v1_0_enc_ring_emit_ib, + .emit_fence = vcn_v1_0_enc_ring_emit_fence, + .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, + .test_ring = amdgpu_vcn_enc_ring_test_ring, + .test_ib = amdgpu_vcn_enc_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = vcn_v1_0_enc_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, +}; + +static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) +{ + adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; + DRM_INFO("VCN decode is enabled in VM mode\n"); +} + +static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->vcn.num_enc_rings; ++i) + adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; + + DRM_INFO("VCN encode is enabled in VM mode\n"); +} + +static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { + .set = vcn_v1_0_set_interrupt_state, + .process = vcn_v1_0_process_interrupt, +}; + +static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->uvd.irq.num_types = adev->vcn.num_enc_rings + 1; + adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; +} + +const struct amdgpu_ip_block_version vcn_v1_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCN, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &vcn_v1_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h new file mode 100644 index 000000000000..2a497a7a4840 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCN_V1_0_H__ +#define __VCN_V1_0_H__ + +extern const struct amdgpu_ip_block_version vcn_v1_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 071f56e439bb..56150e8d1ed2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -20,7 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "soc15.h" @@ -97,7 +97,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) /* disable irqs */ vega10_ih_disable_interrupts(adev); - nbio_v6_1_ih_control(adev); + if (adev->flags & AMD_IS_APU) + nbio_v7_0_ih_control(adev); + else + nbio_v6_1_ih_control(adev); ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ @@ -148,7 +151,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ENABLE, 0); } WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr); - nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); + if (adev->flags & AMD_IS_APU) + nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); + else + nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL)); tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b1132f5e84fc..6cac291c96da 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -21,7 +21,7 @@ * */ #include <linux/slab.h> -#include "drmP.h" +#include <drm/drmP.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" @@ -463,89 +463,83 @@ static void vi_detect_hw_virtualization(struct amdgpu_device *adev) } } -static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { -}; - -static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { -}; - static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { - {mmGRBM_STATUS, false}, - {mmGRBM_STATUS2, false}, - {mmGRBM_STATUS_SE0, false}, - {mmGRBM_STATUS_SE1, false}, - {mmGRBM_STATUS_SE2, false}, - {mmGRBM_STATUS_SE3, false}, - {mmSRBM_STATUS, false}, - {mmSRBM_STATUS2, false}, - {mmSRBM_STATUS3, false}, - {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false}, - {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false}, - {mmCP_STAT, false}, - {mmCP_STALLED_STAT1, false}, - {mmCP_STALLED_STAT2, false}, - {mmCP_STALLED_STAT3, false}, - {mmCP_CPF_BUSY_STAT, false}, - {mmCP_CPF_STALLED_STAT1, false}, - {mmCP_CPF_STATUS, false}, - {mmCP_CPC_BUSY_STAT, false}, - {mmCP_CPC_STALLED_STAT1, false}, - {mmCP_CPC_STATUS, false}, - {mmGB_ADDR_CONFIG, false}, - {mmMC_ARB_RAMCFG, false}, - {mmGB_TILE_MODE0, false}, - {mmGB_TILE_MODE1, false}, - {mmGB_TILE_MODE2, false}, - {mmGB_TILE_MODE3, false}, - {mmGB_TILE_MODE4, false}, - {mmGB_TILE_MODE5, false}, - {mmGB_TILE_MODE6, false}, - {mmGB_TILE_MODE7, false}, - {mmGB_TILE_MODE8, false}, - {mmGB_TILE_MODE9, false}, - {mmGB_TILE_MODE10, false}, - {mmGB_TILE_MODE11, false}, - {mmGB_TILE_MODE12, false}, - {mmGB_TILE_MODE13, false}, - {mmGB_TILE_MODE14, false}, - {mmGB_TILE_MODE15, false}, - {mmGB_TILE_MODE16, false}, - {mmGB_TILE_MODE17, false}, - {mmGB_TILE_MODE18, false}, - {mmGB_TILE_MODE19, false}, - {mmGB_TILE_MODE20, false}, - {mmGB_TILE_MODE21, false}, - {mmGB_TILE_MODE22, false}, - {mmGB_TILE_MODE23, false}, - {mmGB_TILE_MODE24, false}, - {mmGB_TILE_MODE25, false}, - {mmGB_TILE_MODE26, false}, - {mmGB_TILE_MODE27, false}, - {mmGB_TILE_MODE28, false}, - {mmGB_TILE_MODE29, false}, - {mmGB_TILE_MODE30, false}, - {mmGB_TILE_MODE31, false}, - {mmGB_MACROTILE_MODE0, false}, - {mmGB_MACROTILE_MODE1, false}, - {mmGB_MACROTILE_MODE2, false}, - {mmGB_MACROTILE_MODE3, false}, - {mmGB_MACROTILE_MODE4, false}, - {mmGB_MACROTILE_MODE5, false}, - {mmGB_MACROTILE_MODE6, false}, - {mmGB_MACROTILE_MODE7, false}, - {mmGB_MACROTILE_MODE8, false}, - {mmGB_MACROTILE_MODE9, false}, - {mmGB_MACROTILE_MODE10, false}, - {mmGB_MACROTILE_MODE11, false}, - {mmGB_MACROTILE_MODE12, false}, - {mmGB_MACROTILE_MODE13, false}, - {mmGB_MACROTILE_MODE14, false}, - {mmGB_MACROTILE_MODE15, false}, - {mmCC_RB_BACKEND_DISABLE, false, true}, - {mmGC_USER_RB_BACKEND_DISABLE, false, true}, - {mmGB_BACKEND_MAP, false, false}, - {mmPA_SC_RASTER_CONFIG, false, true}, - {mmPA_SC_RASTER_CONFIG_1, false, true}, + {mmGRBM_STATUS}, + {mmGRBM_STATUS2}, + {mmGRBM_STATUS_SE0}, + {mmGRBM_STATUS_SE1}, + {mmGRBM_STATUS_SE2}, + {mmGRBM_STATUS_SE3}, + {mmSRBM_STATUS}, + {mmSRBM_STATUS2}, + {mmSRBM_STATUS3}, + {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET}, + {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, + {mmCP_STAT}, + {mmCP_STALLED_STAT1}, + {mmCP_STALLED_STAT2}, + {mmCP_STALLED_STAT3}, + {mmCP_CPF_BUSY_STAT}, + {mmCP_CPF_STALLED_STAT1}, + {mmCP_CPF_STATUS}, + {mmCP_CPC_BUSY_STAT}, + {mmCP_CPC_STALLED_STAT1}, + {mmCP_CPC_STATUS}, + {mmGB_ADDR_CONFIG}, + {mmMC_ARB_RAMCFG}, + {mmGB_TILE_MODE0}, + {mmGB_TILE_MODE1}, + {mmGB_TILE_MODE2}, + {mmGB_TILE_MODE3}, + {mmGB_TILE_MODE4}, + {mmGB_TILE_MODE5}, + {mmGB_TILE_MODE6}, + {mmGB_TILE_MODE7}, + {mmGB_TILE_MODE8}, + {mmGB_TILE_MODE9}, + {mmGB_TILE_MODE10}, + {mmGB_TILE_MODE11}, + {mmGB_TILE_MODE12}, + {mmGB_TILE_MODE13}, + {mmGB_TILE_MODE14}, + {mmGB_TILE_MODE15}, + {mmGB_TILE_MODE16}, + {mmGB_TILE_MODE17}, + {mmGB_TILE_MODE18}, + {mmGB_TILE_MODE19}, + {mmGB_TILE_MODE20}, + {mmGB_TILE_MODE21}, + {mmGB_TILE_MODE22}, + {mmGB_TILE_MODE23}, + {mmGB_TILE_MODE24}, + {mmGB_TILE_MODE25}, + {mmGB_TILE_MODE26}, + {mmGB_TILE_MODE27}, + {mmGB_TILE_MODE28}, + {mmGB_TILE_MODE29}, + {mmGB_TILE_MODE30}, + {mmGB_TILE_MODE31}, + {mmGB_MACROTILE_MODE0}, + {mmGB_MACROTILE_MODE1}, + {mmGB_MACROTILE_MODE2}, + {mmGB_MACROTILE_MODE3}, + {mmGB_MACROTILE_MODE4}, + {mmGB_MACROTILE_MODE5}, + {mmGB_MACROTILE_MODE6}, + {mmGB_MACROTILE_MODE7}, + {mmGB_MACROTILE_MODE8}, + {mmGB_MACROTILE_MODE9}, + {mmGB_MACROTILE_MODE10}, + {mmGB_MACROTILE_MODE11}, + {mmGB_MACROTILE_MODE12}, + {mmGB_MACROTILE_MODE13}, + {mmGB_MACROTILE_MODE14}, + {mmGB_MACROTILE_MODE15}, + {mmCC_RB_BACKEND_DISABLE, true}, + {mmGC_USER_RB_BACKEND_DISABLE, true}, + {mmGB_BACKEND_MAP, false}, + {mmPA_SC_RASTER_CONFIG, true}, + {mmPA_SC_RASTER_CONFIG_1, true}, }; static uint32_t vi_get_register_value(struct amdgpu_device *adev, @@ -647,51 +641,17 @@ static uint32_t vi_get_register_value(struct amdgpu_device *adev, static int vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { - const struct amdgpu_allowed_register_entry *asic_register_table = NULL; - const struct amdgpu_allowed_register_entry *asic_register_entry; - uint32_t size, i; + uint32_t i; *value = 0; - switch (adev->asic_type) { - case CHIP_TOPAZ: - asic_register_table = tonga_allowed_read_registers; - size = ARRAY_SIZE(tonga_allowed_read_registers); - break; - case CHIP_FIJI: - case CHIP_TONGA: - case CHIP_POLARIS11: - case CHIP_POLARIS10: - case CHIP_POLARIS12: - case CHIP_CARRIZO: - case CHIP_STONEY: - asic_register_table = cz_allowed_read_registers; - size = ARRAY_SIZE(cz_allowed_read_registers); - break; - default: - return -EINVAL; - } - - if (asic_register_table) { - for (i = 0; i < size; i++) { - asic_register_entry = asic_register_table + i; - if (reg_offset != asic_register_entry->reg_offset) - continue; - if (!asic_register_entry->untouched) - *value = vi_get_register_value(adev, - asic_register_entry->grbm_indexed, - se_num, sh_num, reg_offset); - return 0; - } - } - for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { + bool indexed = vi_allowed_read_registers[i].grbm_indexed; + if (reg_offset != vi_allowed_read_registers[i].reg_offset) continue; - if (!vi_allowed_read_registers[i].untouched) - *value = vi_get_register_value(adev, - vi_allowed_read_registers[i].grbm_indexed, - se_num, sh_num, reg_offset); + *value = vi_get_register_value(adev, indexed, se_num, sh_num, + reg_offset); return 0; } return -EINVAL; @@ -934,11 +894,6 @@ static int vi_common_early_init(void *handle) (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) smc_enabled = true; - if (amdgpu_sriov_vf(adev)) { - amdgpu_virt_init_setting(adev); - xgpu_vi_mailbox_set_irq_funcs(adev); - } - adev->rev_id = vi_get_rev_id(adev); adev->external_rev_id = 0xFF; switch (adev->asic_type) { @@ -1073,7 +1028,7 @@ static int vi_common_early_init(void *handle) /* rev0 hardware requires workarounds to support PG */ adev->pg_flags = 0; if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { - adev->pg_flags |= + adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_PIPELINE | AMD_PG_SUPPORT_CP | @@ -1111,6 +1066,11 @@ static int vi_common_early_init(void *handle) return -EINVAL; } + if (amdgpu_sriov_vf(adev)) { + amdgpu_virt_init_setting(adev); + xgpu_vi_mailbox_set_irq_funcs(adev); + } + /* vi use smc load by default */ adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index 5f2ab9c1609a..a6485254a169 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -361,6 +361,12 @@ #define PACKET3_WAIT_ON_CE_COUNTER 0x86 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 #define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_CMD(x) ((x) << 28) + /* + * x=0: tmz_begin + * x=1: tmz_end + */ #define PACKET3_SET_RESOURCES 0xA0 /* 1. header * 2. CONTROL diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 7fc9b0f444cb..b400d5664252 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -2,7 +2,7 @@ # Makefile for Heterogenous System Architecture support for AMD GPU devices # -ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/ \ +ccflags-y := -Idrivers/gpu/drm/amd/include/ \ -Idrivers/gpu/drm/amd/include/asic_reg amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3f95f7cb4019..88187bfc5ea3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -226,6 +226,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->shared_resources = *gpu_resources; + /* We only use the first MEC */ + if (kfd->shared_resources.num_mec > 1) + kfd->shared_resources.num_mec = 1; + /* calculate max size of mqds needed for queues */ size = max_num_of_queues_per_device * kfd->device_info->mqd_size_aligned; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index f49c551195b3..955aa304ff48 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -63,21 +63,44 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) return KFD_MQD_TYPE_CP; } -unsigned int get_first_pipe(struct device_queue_manager *dqm) +static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) +{ + int i; + int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec + + pipe * dqm->dev->shared_resources.num_queue_per_pipe; + + /* queue is available for KFD usage if bit is 1 */ + for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) + if (test_bit(pipe_offset + i, + dqm->dev->shared_resources.queue_bitmap)) + return true; + return false; +} + +unsigned int get_mec_num(struct device_queue_manager *dqm) { BUG_ON(!dqm || !dqm->dev); - return dqm->dev->shared_resources.first_compute_pipe; + + return dqm->dev->shared_resources.num_mec; } -unsigned int get_pipes_num(struct device_queue_manager *dqm) +unsigned int get_queues_num(struct device_queue_manager *dqm) { BUG_ON(!dqm || !dqm->dev); - return dqm->dev->shared_resources.compute_pipe_count; + return bitmap_weight(dqm->dev->shared_resources.queue_bitmap, + KGD_MAX_QUEUES); } -static inline unsigned int get_pipes_num_cpsch(void) +unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) { - return PIPE_PER_ME_CP_SCHEDULING; + BUG_ON(!dqm || !dqm->dev); + return dqm->dev->shared_resources.num_queue_per_pipe; +} + +unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) +{ + BUG_ON(!dqm || !dqm->dev); + return dqm->dev->shared_resources.num_pipe_per_mec; } void program_sh_mem_settings(struct device_queue_manager *dqm, @@ -200,12 +223,16 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) set = false; - for (pipe = dqm->next_pipe_to_allocate, i = 0; i < get_pipes_num(dqm); - pipe = ((pipe + 1) % get_pipes_num(dqm)), ++i) { + for (pipe = dqm->next_pipe_to_allocate, i = 0; i < get_pipes_per_mec(dqm); + pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { + + if (!is_pipe_enabled(dqm, 0, pipe)) + continue; + if (dqm->allocated_queues[pipe] != 0) { bit = find_first_bit( (unsigned long *)&dqm->allocated_queues[pipe], - QUEUES_PER_PIPE); + get_queues_per_pipe(dqm)); clear_bit(bit, (unsigned long *)&dqm->allocated_queues[pipe]); @@ -222,7 +249,7 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) pr_debug("kfd: DQM %s hqd slot - pipe (%d) queue(%d)\n", __func__, q->pipe, q->queue); /* horizontal hqd allocation */ - dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_num(dqm); + dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); return 0; } @@ -469,81 +496,25 @@ set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid, vmid); } -int init_pipelines(struct device_queue_manager *dqm, - unsigned int pipes_num, unsigned int first_pipe) -{ - void *hpdptr; - struct mqd_manager *mqd; - unsigned int i, err, inx; - uint64_t pipe_hpd_addr; - - BUG_ON(!dqm || !dqm->dev); - - pr_debug("kfd: In func %s\n", __func__); - - /* - * Allocate memory for the HPDs. This is hardware-owned per-pipe data. - * The driver never accesses this memory after zeroing it. - * It doesn't even have to be saved/restored on suspend/resume - * because it contains no data when there are no active queues. - */ - - err = kfd_gtt_sa_allocate(dqm->dev, CIK_HPD_EOP_BYTES * pipes_num, - &dqm->pipeline_mem); - - if (err) { - pr_err("kfd: error allocate vidmem num pipes: %d\n", - pipes_num); - return -ENOMEM; - } - - hpdptr = dqm->pipeline_mem->cpu_ptr; - dqm->pipelines_addr = dqm->pipeline_mem->gpu_addr; - - memset(hpdptr, 0, CIK_HPD_EOP_BYTES * pipes_num); - - mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); - if (mqd == NULL) { - kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem); - return -ENOMEM; - } - - for (i = 0; i < pipes_num; i++) { - inx = i + first_pipe; - /* - * HPD buffer on GTT is allocated by amdkfd, no need to waste - * space in GTT for pipelines we don't initialize - */ - pipe_hpd_addr = dqm->pipelines_addr + i * CIK_HPD_EOP_BYTES; - pr_debug("kfd: pipeline address %llX\n", pipe_hpd_addr); - /* = log2(bytes/4)-1 */ - dqm->dev->kfd2kgd->init_pipeline(dqm->dev->kgd, inx, - CIK_HPD_EOP_BYTES_LOG2 - 3, pipe_hpd_addr); - } - - return 0; -} - static void init_interrupts(struct device_queue_manager *dqm) { unsigned int i; BUG_ON(dqm == NULL); - for (i = 0 ; i < get_pipes_num(dqm) ; i++) - dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, - i + get_first_pipe(dqm)); + for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) + if (is_pipe_enabled(dqm, 0, i)) + dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); } static int init_scheduler(struct device_queue_manager *dqm) { - int retval; + int retval = 0; BUG_ON(!dqm); pr_debug("kfd: In %s\n", __func__); - retval = init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm)); return retval; } @@ -554,21 +525,21 @@ static int initialize_nocpsch(struct device_queue_manager *dqm) BUG_ON(!dqm); pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_num(dqm)); + __func__, get_pipes_per_mec(dqm)); mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); dqm->queue_count = dqm->next_pipe_to_allocate = 0; dqm->sdma_queue_count = 0; - dqm->allocated_queues = kcalloc(get_pipes_num(dqm), + dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), sizeof(unsigned int), GFP_KERNEL); if (!dqm->allocated_queues) { mutex_destroy(&dqm->lock); return -ENOMEM; } - for (i = 0; i < get_pipes_num(dqm); i++) - dqm->allocated_queues[i] = (1 << QUEUES_PER_PIPE) - 1; + for (i = 0; i < get_pipes_per_mec(dqm); i++) + dqm->allocated_queues[i] = (1 << get_queues_per_pipe(dqm)) - 1; dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1; dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1; @@ -675,18 +646,38 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, static int set_sched_resources(struct device_queue_manager *dqm) { + int i, mec; struct scheduling_resources res; - unsigned int queue_num, queue_mask; BUG_ON(!dqm); pr_debug("kfd: In func %s\n", __func__); - queue_num = get_pipes_num_cpsch() * QUEUES_PER_PIPE; - queue_mask = (1 << queue_num) - 1; res.vmid_mask = (1 << VMID_PER_DEVICE) - 1; res.vmid_mask <<= KFD_VMID_START_OFFSET; - res.queue_mask = queue_mask << (get_first_pipe(dqm) * QUEUES_PER_PIPE); + + res.queue_mask = 0; + for (i = 0; i < KGD_MAX_QUEUES; ++i) { + mec = (i / dqm->dev->shared_resources.num_queue_per_pipe) + / dqm->dev->shared_resources.num_pipe_per_mec; + + if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap)) + continue; + + /* only acquire queues from the first MEC */ + if (mec > 0) + continue; + + /* This situation may be hit in the future if a new HW + * generation exposes more than 64 queues. If so, the + * definition of res.queue_mask needs updating */ + if (WARN_ON(i > (sizeof(res.queue_mask)*8))) { + pr_err("Invalid queue enabled by amdgpu: %d\n", i); + break; + } + + res.queue_mask |= (1ull << i); + } res.gws_mask = res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; @@ -705,7 +696,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm) BUG_ON(!dqm); pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_num_cpsch()); + __func__, get_pipes_per_mec(dqm)); mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index a625b9137da2..66b9615bc3c1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -30,8 +30,6 @@ #include "kfd_mqd_manager.h" #define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (500) -#define QUEUES_PER_PIPE (8) -#define PIPE_PER_ME_CP_SCHEDULING (3) #define CIK_VMID_NUM (8) #define KFD_VMID_START_OFFSET (8) #define VMID_PER_DEVICE CIK_VMID_NUM @@ -182,10 +180,10 @@ void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops); void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); -int init_pipelines(struct device_queue_manager *dqm, - unsigned int pipes_num, unsigned int first_pipe); -unsigned int get_first_pipe(struct device_queue_manager *dqm); -unsigned int get_pipes_num(struct device_queue_manager *dqm); +unsigned int get_mec_num(struct device_queue_manager *dqm); +unsigned int get_queues_num(struct device_queue_manager *dqm); +unsigned int get_queues_per_pipe(struct device_queue_manager *dqm); +unsigned int get_pipes_per_mec(struct device_queue_manager *dqm); static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c index c6f435aa803f..48dc0561b402 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -151,5 +151,5 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, static int initialize_cpsch_cik(struct device_queue_manager *dqm) { - return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm)); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index ca8c09326b31..7131998848d7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -65,8 +65,7 @@ static void pm_calc_rlib_size(struct packet_manager *pm, /* check if there is over subscription*/ *over_subscription = false; - if ((process_count > 1) || - queue_count > PIPE_PER_ME_CP_SCHEDULING * QUEUES_PER_PIPE) { + if ((process_count > 1) || queue_count > get_queues_num(pm->dqm)) { *over_subscription = true; pr_debug("kfd: over subscribed runlist\n"); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 84d1ffd1eef9..035bbc98a63d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -318,12 +318,13 @@ static struct kfd_process *create_process(const struct task_struct *thread) /* init process apertures*/ process->is_32bit_user_mode = in_compat_syscall(); - if (kfd_init_apertures(process) != 0) - goto err_init_apretures; + err = kfd_init_apertures(process); + if (err != 0) + goto err_init_apertures; return process; -err_init_apretures: +err_init_apertures: pqm_uninit(&process->pqm); err_process_pqm_init: hash_del_rcu(&process->kfd_processes); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index e1fb40b84c72..32cdf2b483db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -209,7 +209,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, /* check if there is over subscription */ if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && ((dev->dqm->processes_count >= VMID_PER_DEVICE) || - (dev->dqm->queue_count >= PIPE_PER_ME_CP_SCHEDULING * QUEUES_PER_PIPE))) { + (dev->dqm->queue_count >= get_queues_num(dev->dqm)))) { pr_err("kfd: over-subscription is not allowed in radeon_kfd.sched_policy == 1\n"); retval = -EPERM; goto err_create_queue; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 1d1ac1ef94f7..70e8c20acb2f 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -48,6 +48,7 @@ enum amd_asic_type { CHIP_POLARIS11, CHIP_POLARIS12, CHIP_VEGA10, + CHIP_RAVEN, CHIP_LAST, }; @@ -75,8 +76,7 @@ enum amd_ip_block_type { AMD_IP_BLOCK_TYPE_UVD, AMD_IP_BLOCK_TYPE_VCE, AMD_IP_BLOCK_TYPE_ACP, - AMD_IP_BLOCK_TYPE_GFXHUB, - AMD_IP_BLOCK_TYPE_MMHUB + AMD_IP_BLOCK_TYPE_VCN }; enum amd_clockgating_state { @@ -184,6 +184,7 @@ enum amd_fan_ctrl_mode { #define AMD_PG_SUPPORT_SAMU (1 << 10) #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) +#define AMD_PG_SUPPORT_MMHUB (1 << 13) enum amd_pm_state_type { /* not used for dpm */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h index 9a4d4c299d5b..abe05bc80752 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -906,6 +906,8 @@ #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h new file mode 100644 index 000000000000..eac125c9e300 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h @@ -0,0 +1,7988 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_1_0_DEFAULT_HEADER +#define _dcn_1_0_DEFAULT_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +#define smnAZCONTROLLER0_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_MINOR_VERSION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_MAJOR_VERSION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WAKE_ENABLE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_STATE_CHANGE_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_GLOBAL_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_STREAM_SYNCHRONIZATION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_WRITE_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_READ_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_SIZE_DEFAULT 0x00000002 +#define smnAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_WRITE_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_SIZE_DEFAULT 0x00000002 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azroot_azdec +#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream0_azdec +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream1_azdec +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream2_azdec +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream3_azdec +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream4_azdec +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream5_azdec +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream6_azdec +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream7_azdec +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +#define mmCRTC8_IDX_DEFAULT 0x00000000 +#define mmCRTC8_DATA_DEFAULT 0x00000000 +#define mmGENFC_WT_DEFAULT 0x00000000 +#define mmGENS1_DEFAULT 0x00000000 +#define mmATTRDW_DEFAULT 0x00000000 +#define mmATTRX_DEFAULT 0x00000000 +#define mmATTRDR_DEFAULT 0x00000000 +#define mmGENMO_WT_DEFAULT 0x00000000 +#define mmGENS0_DEFAULT 0x00000000 +#define mmGENENB_DEFAULT 0x00000000 +#define mmSEQ8_IDX_DEFAULT 0x00000000 +#define mmSEQ8_DATA_DEFAULT 0x00000000 +#define mmDAC_MASK_DEFAULT 0x00000000 +#define mmDAC_R_INDEX_DEFAULT 0x00000000 +#define mmDAC_W_INDEX_DEFAULT 0x00000000 +#define mmDAC_DATA_DEFAULT 0x00000000 +#define mmGENFC_RD_DEFAULT 0x00000000 +#define mmGENMO_RD_DEFAULT 0x00000000 +#define mmGRPH8_IDX_DEFAULT 0x00000000 +#define mmGRPH8_DATA_DEFAULT 0x00000000 +#define mmCRTC8_IDX_1_DEFAULT 0x00000000 +#define mmCRTC8_DATA_1_DEFAULT 0x00000000 +#define mmGENFC_WT_1_DEFAULT 0x00000000 +#define mmGENS1_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmCORB_READ_POINTER_DEFAULT 0x00000000 +#define mmCORB_CONTROL_DEFAULT 0x00000000 +#define mmCORB_STATUS_DEFAULT 0x00000000 +#define mmCORB_SIZE_DEFAULT 0x00000002 +#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 +#define mmRIRB_CONTROL_DEFAULT 0x00000000 +#define mmRIRB_STATUS_DEFAULT 0x00000000 +#define mmRIRB_SIZE_DEFAULT 0x00000002 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 +#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azroot_azdec +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream0_azdec +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream1_azdec +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream2_azdec +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream3_azdec +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream4_azdec +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream5_azdec +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream6_azdec +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream7_azdec +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f +#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f +#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 +#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 +#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 +#define mmD1VGA_CONTROL_DEFAULT 0x00000000 +#define mmD2VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 +#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 +#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 +#define mmD3VGA_CONTROL_DEFAULT 0x00000000 +#define mmD4VGA_CONTROL_DEFAULT 0x00000000 +#define mmD5VGA_CONTROL_DEFAULT 0x00000000 +#define mmD6VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO_DBUF_EN_DEFAULT 0x00000000 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmREFCLK_CNTL_DEFAULT 0x00000000 +#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 +#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 +#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 +#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 +#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 +#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 +#define mmDCE_VERSION_DEFAULT 0x00000000 +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 +#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 +#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 +#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 +#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 +#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 +#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 +#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 +#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 +#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee02dd +#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmSOCCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 +#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 +#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x007f007f +#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 +#define mmOTG0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmOTG1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmOTG2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 +#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmOTG3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 +#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmOTG4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 +#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmOTG5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 +#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDPPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 +#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 +#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 +#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 +#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 +#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 +#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 +#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 +#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 +#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 +#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 +#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 +#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_CNT_CTRL_DEFAULT 0x00000000 +#define mmDCCG_VSYNC_CNT_INT_CTRL_DEFAULT 0x00000000 +#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dccg_dccg_pll_dispdec +#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 +#define mmRBBMIF_STATUS_DEFAULT 0x00000000 +#define mmRBBMIF_INT_STATUS_DEFAULT 0x80000000 +#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 +#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +#define mmDOMAIN0_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN0_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN1_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN1_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN2_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN2_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN3_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN3_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN4_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN4_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN5_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN5_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN6_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN6_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN7_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN7_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN8_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN8_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN9_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN9_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN10_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN10_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN11_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN11_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN12_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN12_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN13_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN13_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN14_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN14_PG_STATUS_DEFAULT 0x00000000 +#define mmDOMAIN15_PG_CONFIG_DEFAULT 0x00000001 +#define mmDOMAIN15_PG_STATUS_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_CONTROL_1_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_CONTROL_2_DEFAULT 0x00000000 +#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 +#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 +#define mmDMU_CLK_CNTL_DEFAULT 0x00000000 +#define mmDMU_MEM_PWR_CNTL_DEFAULT 0x00000000 +#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +#define mmDMCU_CTRL_DEFAULT 0xffff0101 +#define mmDMCU_STATUS_DEFAULT 0x00000001 +#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 +#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 +#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 +#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 +#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 +#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 +#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 +#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 +#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 +#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 +#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 +#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 +#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 +#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 +#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 +#define mmDMCU_INT_CNT_DEFAULT 0x00000000 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 +#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 +#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 +#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 +#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 +#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 +#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 +#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 +#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_DEFAULT 0x00000000 +#define mmDMCU_INT_CNT_CONTINUE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE16_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE17_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE18_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE19_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE20_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE21_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_VREADY_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec +#define mmCNV0_WB_ENABLE_DEFAULT 0x00000000 +#define mmCNV0_WB_EC_CONFIG_DEFAULT 0x55000000 +#define mmCNV0_CNV_MODE_DEFAULT 0x00000000 +#define mmCNV0_CNV_WINDOW_START_DEFAULT 0x00000000 +#define mmCNV0_CNV_WINDOW_SIZE_DEFAULT 0x00100010 +#define mmCNV0_CNV_UPDATE_DEFAULT 0x00000000 +#define mmCNV0_CNV_SOURCE_SIZE_DEFAULT 0x00100010 +#define mmCNV0_CNV_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C11_C12_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C13_C14_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C21_C22_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C23_C24_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C31_C32_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_C33_C34_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 +#define mmCNV0_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff +#define mmCNV0_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff +#define mmCNV0_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff +#define mmCNV0_CNV_TEST_CNTL_DEFAULT 0x00000000 +#define mmCNV0_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 +#define mmCNV0_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 +#define mmCNV0_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 +#define mmCNV0_CNV_INPUT_SELECT_DEFAULT 0x00000001 +#define mmCNV0_WB_SOFT_RESET_DEFAULT 0x00000000 +#define mmCNV0_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 +#define mmCNV0_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 + + +// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec +#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_MODE_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 +#define mmWBSCL0_WBSCL_DEST_SIZE_DEFAULT 0x00010001 +#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL0_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 +#define mmWBSCL0_WBSCL_CLAMP_DEFAULT 0x01fe01fe +#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 +#define mmWBSCL0_WBSCL_TEST_CNTL_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 +#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff +#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 +#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 +#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 +#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec +#define mmCNV1_WB_ENABLE_DEFAULT 0x00000000 +#define mmCNV1_WB_EC_CONFIG_DEFAULT 0x55000000 +#define mmCNV1_CNV_MODE_DEFAULT 0x00000000 +#define mmCNV1_CNV_WINDOW_START_DEFAULT 0x00000000 +#define mmCNV1_CNV_WINDOW_SIZE_DEFAULT 0x00100010 +#define mmCNV1_CNV_UPDATE_DEFAULT 0x00000000 +#define mmCNV1_CNV_SOURCE_SIZE_DEFAULT 0x00100010 +#define mmCNV1_CNV_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C11_C12_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C13_C14_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C21_C22_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C23_C24_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C31_C32_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_C33_C34_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 +#define mmCNV1_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff +#define mmCNV1_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff +#define mmCNV1_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff +#define mmCNV1_CNV_TEST_CNTL_DEFAULT 0x00000000 +#define mmCNV1_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 +#define mmCNV1_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 +#define mmCNV1_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 +#define mmCNV1_CNV_INPUT_SELECT_DEFAULT 0x00000001 +#define mmCNV1_WB_SOFT_RESET_DEFAULT 0x00000000 +#define mmCNV1_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 +#define mmCNV1_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 + + +// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec +#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_MODE_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 +#define mmWBSCL1_WBSCL_DEST_SIZE_DEFAULT 0x00010001 +#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL1_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 +#define mmWBSCL1_WBSCL_CLAMP_DEFAULT 0x01fe01fe +#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 +#define mmWBSCL1_WBSCL_TEST_CNTL_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 +#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff +#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 +#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 +#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 +#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 +#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff + + +// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 +#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +#define mmWBIF0_MISC_CTRL_DEFAULT 0x00010001 +#define mmWBIF0_SMU_WM_CONTROL_DEFAULT 0x00000000 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmWBIF1_MISC_CTRL_DEFAULT 0x00010001 +#define mmWBIF1_SMU_WM_CONTROL_DEFAULT 0x00000000 +#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmVGA_SRC_SPLIT_CNTL_DEFAULT 0x00000000 +#define mmMMHUBBUB_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmMMHUBBUB_MEM_PWR_CNTL_DEFAULT 0x0000c180 +#define mmMMHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 +#define mmMMHUBBUB_SOFT_RESET_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +#define mmMCIF_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +#define mmAZ_CLOCK_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 +#define mmAZALIA_AUDIO_DTO_DEFAULT 0x00300018 +#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 +#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a +#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a +#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 +#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 +#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 +#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +#define mmDCHUBBUB_SDPIF_CFG0_DEFAULT 0x00cd3001 +#define mmDCHUBBUB_SDPIF_CFG1_DEFAULT 0x0000005c +#define mmDCHUBBUB_FORCE_IO_STATUS_0_DEFAULT 0x00000002 +#define mmDCHUBBUB_FORCE_IO_STATUS_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_FB_BASE_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_FB_TOP_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_FB_OFFSET_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_AGP_BOT_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_AGP_TOP_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_AGP_BASE_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_APER_BASE_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_APER_TOP_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_APER_DEF_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_APER_DEF_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +#define mmDCHUBBUB_RET_PATH_DCC_CFG_DEFAULT 0x00000001 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCHUBBUB_CRC_CTRL_DEFAULT 0x00000000 +#define mmDCHUBBUB_CRC0_VAL_R_G_DEFAULT 0x00000000 +#define mmDCHUBBUB_CRC0_VAL_B_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_CRC1_VAL_R_G_DEFAULT 0x00000000 +#define mmDCHUBBUB_CRC1_VAL_B_A_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_DEFAULT 0x01000100 +#define mmDCHUBBUB_ARB_SAT_LEVEL_DEFAULT 0xffffffff +#define mmDCHUBBUB_ARB_QOS_FORCE_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_DEFAULT 0x00000000 +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_DEFAULT 0x00000010 +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_DEFAULT 0x00000000 +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSURFACE_CHECK0_ADDRESS_LSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK0_ADDRESS_MSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK1_ADDRESS_LSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK1_ADDRESS_MSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK2_ADDRESS_LSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK2_ADDRESS_MSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK3_ADDRESS_LSB_DEFAULT 0x00000000 +#define mmSURFACE_CHECK3_ADDRESS_MSB_DEFAULT 0x00000000 +#define mmVTG0_CONTROL_DEFAULT 0x00000000 +#define mmVTG1_CONTROL_DEFAULT 0x00000000 +#define mmVTG2_CONTROL_DEFAULT 0x00000000 +#define mmVTG3_CONTROL_DEFAULT 0x00000000 +#define mmVTG4_CONTROL_DEFAULT 0x00000000 +#define mmVTG5_CONTROL_DEFAULT 0x00000000 +#define mmDCHUBBUB_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 +#define mmDCFCLK_CNTL_DEFAULT 0x80000200 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_DEFAULT 0x00000000 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_DEFAULT 0x00000000 +#define mmDCHUBBUB_VLINE_SNAPSHOT_DEFAULT 0x00000000 +#define mmDCHUBBUB_SPARE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +#define mmHUBP0_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 +#define mmHUBP0_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 +#define mmHUBP0_DCHUBP_CNTL_DEFAULT 0x00001001 +#define mmHUBP0_HUBP_CLK_CNTL_DEFAULT 0x00000000 +#define mmHUBP0_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 +#define mmHUBP0_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_EXPANSION_MODE_DEFAULT 0x00000055 +#define mmHUBPREQ0_DCN_TTU_QOS_WM_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ0_BLANK_OFFSET_0_DEFAULT 0x00000000 +#define mmHUBPREQ0_BLANK_OFFSET_1_DEFAULT 0x00000000 +#define mmHUBPREQ0_DST_DIMENSIONS_DEFAULT 0x00000000 +#define mmHUBPREQ0_DST_AFTER_SCALER_DEFAULT 0x00000000 +#define mmHUBPREQ0_PREFETCH_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ0_PREFETCH_SETTINS_C_DEFAULT 0x00000000 +#define mmHUBPREQ0_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ0_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ0_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ0_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_5_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_6_DEFAULT 0x00000000 +#define mmHUBPREQ0_NOM_PARAMETERS_7_DEFAULT 0x00000000 +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 +#define mmHUBPREQ0_PER_LINE_DELIVERY_DEFAULT 0x00000000 +#define mmHUBPREQ0_CURSOR_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +#define mmHUBPRET0_HUBPRET_CONTROL_DEFAULT 0x00e40000 +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE0_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE1_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec +#define mmCURSOR0_CURSOR_CONTROL_DEFAULT 0x01000000 +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_SIZE_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_POSITION_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_HOT_SPOT_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_DST_OFFSET_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +#define mmHUBP1_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 +#define mmHUBP1_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 +#define mmHUBP1_DCHUBP_CNTL_DEFAULT 0x00001001 +#define mmHUBP1_HUBP_CLK_CNTL_DEFAULT 0x00000000 +#define mmHUBP1_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 +#define mmHUBP1_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_EXPANSION_MODE_DEFAULT 0x00000055 +#define mmHUBPREQ1_DCN_TTU_QOS_WM_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ1_BLANK_OFFSET_0_DEFAULT 0x00000000 +#define mmHUBPREQ1_BLANK_OFFSET_1_DEFAULT 0x00000000 +#define mmHUBPREQ1_DST_DIMENSIONS_DEFAULT 0x00000000 +#define mmHUBPREQ1_DST_AFTER_SCALER_DEFAULT 0x00000000 +#define mmHUBPREQ1_PREFETCH_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ1_PREFETCH_SETTINS_C_DEFAULT 0x00000000 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ1_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_5_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_6_DEFAULT 0x00000000 +#define mmHUBPREQ1_NOM_PARAMETERS_7_DEFAULT 0x00000000 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 +#define mmHUBPREQ1_PER_LINE_DELIVERY_DEFAULT 0x00000000 +#define mmHUBPREQ1_CURSOR_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +#define mmHUBPRET1_HUBPRET_CONTROL_DEFAULT 0x00e40000 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE0_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE1_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec +#define mmCURSOR1_CURSOR_CONTROL_DEFAULT 0x01000000 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_SIZE_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_POSITION_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_HOT_SPOT_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_DST_OFFSET_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +#define mmHUBP2_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 +#define mmHUBP2_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 +#define mmHUBP2_DCHUBP_CNTL_DEFAULT 0x00001001 +#define mmHUBP2_HUBP_CLK_CNTL_DEFAULT 0x00000000 +#define mmHUBP2_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 +#define mmHUBP2_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_EXPANSION_MODE_DEFAULT 0x00000055 +#define mmHUBPREQ2_DCN_TTU_QOS_WM_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 +#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ2_BLANK_OFFSET_0_DEFAULT 0x00000000 +#define mmHUBPREQ2_BLANK_OFFSET_1_DEFAULT 0x00000000 +#define mmHUBPREQ2_DST_DIMENSIONS_DEFAULT 0x00000000 +#define mmHUBPREQ2_DST_AFTER_SCALER_DEFAULT 0x00000000 +#define mmHUBPREQ2_PREFETCH_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ2_PREFETCH_SETTINS_C_DEFAULT 0x00000000 +#define mmHUBPREQ2_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ2_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ2_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ2_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ2_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_5_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_6_DEFAULT 0x00000000 +#define mmHUBPREQ2_NOM_PARAMETERS_7_DEFAULT 0x00000000 +#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 +#define mmHUBPREQ2_PER_LINE_DELIVERY_DEFAULT 0x00000000 +#define mmHUBPREQ2_CURSOR_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +#define mmHUBPRET2_HUBPRET_CONTROL_DEFAULT 0x00e40000 +#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE0_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE1_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 +#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec +#define mmCURSOR2_CURSOR_CONTROL_DEFAULT 0x01000000 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_SIZE_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_POSITION_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_HOT_SPOT_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_DST_OFFSET_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +#define mmHUBP3_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 +#define mmHUBP3_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 +#define mmHUBP3_DCHUBP_CNTL_DEFAULT 0x00001001 +#define mmHUBP3_HUBP_CLK_CNTL_DEFAULT 0x00000000 +#define mmHUBP3_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 +#define mmHUBP3_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 +#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 +#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_EXPANSION_MODE_DEFAULT 0x00000055 +#define mmHUBPREQ3_DCN_TTU_QOS_WM_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 +#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 +#define mmHUBPREQ3_BLANK_OFFSET_0_DEFAULT 0x00000000 +#define mmHUBPREQ3_BLANK_OFFSET_1_DEFAULT 0x00000000 +#define mmHUBPREQ3_DST_DIMENSIONS_DEFAULT 0x00000000 +#define mmHUBPREQ3_DST_AFTER_SCALER_DEFAULT 0x00000000 +#define mmHUBPREQ3_PREFETCH_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ3_PREFETCH_SETTINS_C_DEFAULT 0x00000000 +#define mmHUBPREQ3_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ3_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ3_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ3_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ3_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_0_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_1_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_2_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_3_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_4_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_5_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_6_DEFAULT 0x00000000 +#define mmHUBPREQ3_NOM_PARAMETERS_7_DEFAULT 0x00000000 +#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 +#define mmHUBPREQ3_PER_LINE_DELIVERY_DEFAULT 0x00000000 +#define mmHUBPREQ3_CURSOR_SETTINS_DEFAULT 0x00000000 +#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +#define mmHUBPRET3_HUBPRET_CONTROL_DEFAULT 0x00e40000 +#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE0_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE1_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_INTERRUPT_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 +#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec +#define mmCURSOR3_CURSOR_CONTROL_DEFAULT 0x01000000 +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_SIZE_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_POSITION_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_HOT_SPOT_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_DST_OFFSET_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +#define mmDPP_TOP0_DPP_CONTROL_DEFAULT 0x70000000 +#define mmDPP_TOP0_DPP_SOFT_RESET_DEFAULT 0x00000000 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 +#define mmDPP_TOP0_DPP_CRC_CTRL_DEFAULT 0x00000000 +#define mmDPP_TOP0_HOST_READ_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 +#define mmCNVC_CFG0_FORMAT_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 +#define mmCNVC_CFG0_DENORM_CONTROL_DEFAULT 0x00002000 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 +#define mmCNVC_CFG0_COLOR_KEYER_RED_DEFAULT 0x00000000 +#define mmCNVC_CFG0_COLOR_KEYER_GREEN_DEFAULT 0x00000000 +#define mmCNVC_CFG0_COLOR_KEYER_BLUE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +#define mmCNVC_CUR0_CURSOR0_CONTROL_DEFAULT 0x0003ff00 +#define mmCNVC_CUR0_CURSOR0_COLOR0_DEFAULT 0x00000000 +#define mmCNVC_CUR0_CURSOR0_COLOR1_DEFAULT 0x00000000 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmDSCL0_SCL_MODE_DEFAULT 0x00000000 +#define mmDSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_CONTROL_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmDSCL0_SCL_BLACK_OFFSET_DEFAULT 0x80000000 +#define mmDSCL0_DSCL_UPDATE_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_AUTOCAL_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmDSCL0_OTG_H_BLANK_DEFAULT 0x00000000 +#define mmDSCL0_OTG_V_BLANK_DEFAULT 0x00000000 +#define mmDSCL0_RECOUT_START_DEFAULT 0x00000000 +#define mmDSCL0_RECOUT_SIZE_DEFAULT 0x00000000 +#define mmDSCL0_MPC_SIZE_DEFAULT 0x00000000 +#define mmDSCL0_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmDSCL0_LB_MEMORY_CTRL_DEFAULT 0x00003f00 +#define mmDSCL0_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDSCL0_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDSCL0_OBUF_CONTROL_DEFAULT 0xe0000000 +#define mmDSCL0_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +#define mmCM0_CM_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_COMA_C11_C12_DEFAULT 0x00002000 +#define mmCM0_CM_COMA_C13_C14_DEFAULT 0x00000000 +#define mmCM0_CM_COMA_C21_C22_DEFAULT 0x20000000 +#define mmCM0_CM_COMA_C23_C24_DEFAULT 0x00000000 +#define mmCM0_CM_COMA_C31_C32_DEFAULT 0x00000000 +#define mmCM0_CM_COMA_C33_C34_DEFAULT 0x00002000 +#define mmCM0_CM_COMB_C11_C12_DEFAULT 0x00002000 +#define mmCM0_CM_COMB_C13_C14_DEFAULT 0x00000000 +#define mmCM0_CM_COMB_C21_C22_DEFAULT 0x20000000 +#define mmCM0_CM_COMB_C23_C24_DEFAULT 0x00000000 +#define mmCM0_CM_COMB_C31_C32_DEFAULT 0x00000000 +#define mmCM0_CM_COMB_C33_C34_DEFAULT 0x00002000 +#define mmCM0_CM_IGAM_CONTROL_DEFAULT 0x08000002 +#define mmCM0_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 +#define mmCM0_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCM0_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCM0_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCM0_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 +#define mmCM0_CM_ICSC_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_ICSC_C11_C12_DEFAULT 0x00002000 +#define mmCM0_CM_ICSC_C13_C14_DEFAULT 0x00000000 +#define mmCM0_CM_ICSC_C21_C22_DEFAULT 0x20000000 +#define mmCM0_CM_ICSC_C23_C24_DEFAULT 0x00000000 +#define mmCM0_CM_ICSC_C31_C32_DEFAULT 0x00000000 +#define mmCM0_CM_ICSC_C33_C34_DEFAULT 0x00002000 +#define mmCM0_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCM0_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCM0_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCM0_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCM0_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCM0_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmCM0_CM_OCSC_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_OCSC_C11_C12_DEFAULT 0x00002000 +#define mmCM0_CM_OCSC_C13_C14_DEFAULT 0x00000000 +#define mmCM0_CM_OCSC_C21_C22_DEFAULT 0x20000000 +#define mmCM0_CM_OCSC_C23_C24_DEFAULT 0x00000000 +#define mmCM0_CM_OCSC_C31_C32_DEFAULT 0x00000000 +#define mmCM0_CM_OCSC_C33_C34_DEFAULT 0x00002000 +#define mmCM0_CM_BNS_VALUES_R_DEFAULT 0x20000000 +#define mmCM0_CM_BNS_VALUES_G_DEFAULT 0x20000000 +#define mmCM0_CM_BNS_VALUES_B_DEFAULT 0x20000000 +#define mmCM0_CM_DGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM0_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 +#define mmCM0_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 +#define mmCM0_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 +#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff +#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff +#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff +#define mmCM0_CM_DENORM_CONTROL_DEFAULT 0x00000000 +#define mmCM0_CM_CMOUT_CONTROL_DEFAULT 0x0000000a +#define mmCM0_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmCM0_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCM0_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +#define mmDPP_TOP1_DPP_CONTROL_DEFAULT 0x70000000 +#define mmDPP_TOP1_DPP_SOFT_RESET_DEFAULT 0x00000000 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 +#define mmDPP_TOP1_DPP_CRC_CTRL_DEFAULT 0x00000000 +#define mmDPP_TOP1_HOST_READ_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 +#define mmCNVC_CFG1_FORMAT_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 +#define mmCNVC_CFG1_DENORM_CONTROL_DEFAULT 0x00002000 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 +#define mmCNVC_CFG1_COLOR_KEYER_RED_DEFAULT 0x00000000 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN_DEFAULT 0x00000000 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +#define mmCNVC_CUR1_CURSOR0_CONTROL_DEFAULT 0x0003ff00 +#define mmCNVC_CUR1_CURSOR0_COLOR0_DEFAULT 0x00000000 +#define mmCNVC_CUR1_CURSOR0_COLOR1_DEFAULT 0x00000000 +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmDSCL1_SCL_MODE_DEFAULT 0x00000000 +#define mmDSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_CONTROL_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmDSCL1_SCL_BLACK_OFFSET_DEFAULT 0x80000000 +#define mmDSCL1_DSCL_UPDATE_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_AUTOCAL_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmDSCL1_OTG_H_BLANK_DEFAULT 0x00000000 +#define mmDSCL1_OTG_V_BLANK_DEFAULT 0x00000000 +#define mmDSCL1_RECOUT_START_DEFAULT 0x00000000 +#define mmDSCL1_RECOUT_SIZE_DEFAULT 0x00000000 +#define mmDSCL1_MPC_SIZE_DEFAULT 0x00000000 +#define mmDSCL1_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmDSCL1_LB_MEMORY_CTRL_DEFAULT 0x00003f00 +#define mmDSCL1_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDSCL1_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDSCL1_OBUF_CONTROL_DEFAULT 0xe0000000 +#define mmDSCL1_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +#define mmCM1_CM_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_COMA_C11_C12_DEFAULT 0x00002000 +#define mmCM1_CM_COMA_C13_C14_DEFAULT 0x00000000 +#define mmCM1_CM_COMA_C21_C22_DEFAULT 0x20000000 +#define mmCM1_CM_COMA_C23_C24_DEFAULT 0x00000000 +#define mmCM1_CM_COMA_C31_C32_DEFAULT 0x00000000 +#define mmCM1_CM_COMA_C33_C34_DEFAULT 0x00002000 +#define mmCM1_CM_COMB_C11_C12_DEFAULT 0x00002000 +#define mmCM1_CM_COMB_C13_C14_DEFAULT 0x00000000 +#define mmCM1_CM_COMB_C21_C22_DEFAULT 0x20000000 +#define mmCM1_CM_COMB_C23_C24_DEFAULT 0x00000000 +#define mmCM1_CM_COMB_C31_C32_DEFAULT 0x00000000 +#define mmCM1_CM_COMB_C33_C34_DEFAULT 0x00002000 +#define mmCM1_CM_IGAM_CONTROL_DEFAULT 0x08000002 +#define mmCM1_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 +#define mmCM1_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCM1_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCM1_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCM1_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 +#define mmCM1_CM_ICSC_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_ICSC_C11_C12_DEFAULT 0x00002000 +#define mmCM1_CM_ICSC_C13_C14_DEFAULT 0x00000000 +#define mmCM1_CM_ICSC_C21_C22_DEFAULT 0x20000000 +#define mmCM1_CM_ICSC_C23_C24_DEFAULT 0x00000000 +#define mmCM1_CM_ICSC_C31_C32_DEFAULT 0x00000000 +#define mmCM1_CM_ICSC_C33_C34_DEFAULT 0x00002000 +#define mmCM1_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCM1_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCM1_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCM1_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCM1_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCM1_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmCM1_CM_OCSC_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_OCSC_C11_C12_DEFAULT 0x00002000 +#define mmCM1_CM_OCSC_C13_C14_DEFAULT 0x00000000 +#define mmCM1_CM_OCSC_C21_C22_DEFAULT 0x20000000 +#define mmCM1_CM_OCSC_C23_C24_DEFAULT 0x00000000 +#define mmCM1_CM_OCSC_C31_C32_DEFAULT 0x00000000 +#define mmCM1_CM_OCSC_C33_C34_DEFAULT 0x00002000 +#define mmCM1_CM_BNS_VALUES_R_DEFAULT 0x20000000 +#define mmCM1_CM_BNS_VALUES_G_DEFAULT 0x20000000 +#define mmCM1_CM_BNS_VALUES_B_DEFAULT 0x20000000 +#define mmCM1_CM_DGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM1_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 +#define mmCM1_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 +#define mmCM1_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff +#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff +#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff +#define mmCM1_CM_DENORM_CONTROL_DEFAULT 0x00000000 +#define mmCM1_CM_CMOUT_CONTROL_DEFAULT 0x0000000a +#define mmCM1_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmCM1_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCM1_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +#define mmDPP_TOP2_DPP_CONTROL_DEFAULT 0x70000000 +#define mmDPP_TOP2_DPP_SOFT_RESET_DEFAULT 0x00000000 +#define mmDPP_TOP2_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 +#define mmDPP_TOP2_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 +#define mmDPP_TOP2_DPP_CRC_CTRL_DEFAULT 0x00000000 +#define mmDPP_TOP2_HOST_READ_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 +#define mmCNVC_CFG2_FORMAT_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 +#define mmCNVC_CFG2_DENORM_CONTROL_DEFAULT 0x00002000 +#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 +#define mmCNVC_CFG2_COLOR_KEYER_RED_DEFAULT 0x00000000 +#define mmCNVC_CFG2_COLOR_KEYER_GREEN_DEFAULT 0x00000000 +#define mmCNVC_CFG2_COLOR_KEYER_BLUE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +#define mmCNVC_CUR2_CURSOR0_CONTROL_DEFAULT 0x0003ff00 +#define mmCNVC_CUR2_CURSOR0_COLOR0_DEFAULT 0x00000000 +#define mmCNVC_CUR2_CURSOR0_COLOR1_DEFAULT 0x00000000 +#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 +#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmDSCL2_SCL_MODE_DEFAULT 0x00000000 +#define mmDSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_CONTROL_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 +#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL2_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmDSCL2_SCL_BLACK_OFFSET_DEFAULT 0x80000000 +#define mmDSCL2_DSCL_UPDATE_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_AUTOCAL_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmDSCL2_OTG_H_BLANK_DEFAULT 0x00000000 +#define mmDSCL2_OTG_V_BLANK_DEFAULT 0x00000000 +#define mmDSCL2_RECOUT_START_DEFAULT 0x00000000 +#define mmDSCL2_RECOUT_SIZE_DEFAULT 0x00000000 +#define mmDSCL2_MPC_SIZE_DEFAULT 0x00000000 +#define mmDSCL2_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmDSCL2_LB_MEMORY_CTRL_DEFAULT 0x00003f00 +#define mmDSCL2_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDSCL2_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDSCL2_OBUF_CONTROL_DEFAULT 0xe0000000 +#define mmDSCL2_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +#define mmCM2_CM_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_COMA_C11_C12_DEFAULT 0x00002000 +#define mmCM2_CM_COMA_C13_C14_DEFAULT 0x00000000 +#define mmCM2_CM_COMA_C21_C22_DEFAULT 0x20000000 +#define mmCM2_CM_COMA_C23_C24_DEFAULT 0x00000000 +#define mmCM2_CM_COMA_C31_C32_DEFAULT 0x00000000 +#define mmCM2_CM_COMA_C33_C34_DEFAULT 0x00002000 +#define mmCM2_CM_COMB_C11_C12_DEFAULT 0x00002000 +#define mmCM2_CM_COMB_C13_C14_DEFAULT 0x00000000 +#define mmCM2_CM_COMB_C21_C22_DEFAULT 0x20000000 +#define mmCM2_CM_COMB_C23_C24_DEFAULT 0x00000000 +#define mmCM2_CM_COMB_C31_C32_DEFAULT 0x00000000 +#define mmCM2_CM_COMB_C33_C34_DEFAULT 0x00002000 +#define mmCM2_CM_IGAM_CONTROL_DEFAULT 0x08000002 +#define mmCM2_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 +#define mmCM2_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCM2_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCM2_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCM2_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 +#define mmCM2_CM_ICSC_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_ICSC_C11_C12_DEFAULT 0x00002000 +#define mmCM2_CM_ICSC_C13_C14_DEFAULT 0x00000000 +#define mmCM2_CM_ICSC_C21_C22_DEFAULT 0x20000000 +#define mmCM2_CM_ICSC_C23_C24_DEFAULT 0x00000000 +#define mmCM2_CM_ICSC_C31_C32_DEFAULT 0x00000000 +#define mmCM2_CM_ICSC_C33_C34_DEFAULT 0x00002000 +#define mmCM2_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCM2_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCM2_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCM2_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCM2_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCM2_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmCM2_CM_OCSC_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_OCSC_C11_C12_DEFAULT 0x00002000 +#define mmCM2_CM_OCSC_C13_C14_DEFAULT 0x00000000 +#define mmCM2_CM_OCSC_C21_C22_DEFAULT 0x20000000 +#define mmCM2_CM_OCSC_C23_C24_DEFAULT 0x00000000 +#define mmCM2_CM_OCSC_C31_C32_DEFAULT 0x00000000 +#define mmCM2_CM_OCSC_C33_C34_DEFAULT 0x00002000 +#define mmCM2_CM_BNS_VALUES_R_DEFAULT 0x20000000 +#define mmCM2_CM_BNS_VALUES_G_DEFAULT 0x20000000 +#define mmCM2_CM_BNS_VALUES_B_DEFAULT 0x20000000 +#define mmCM2_CM_DGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM2_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 +#define mmCM2_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 +#define mmCM2_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff +#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff +#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff +#define mmCM2_CM_DENORM_CONTROL_DEFAULT 0x00000000 +#define mmCM2_CM_CMOUT_CONTROL_DEFAULT 0x0000000a +#define mmCM2_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmCM2_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCM2_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON14_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON14_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON14_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +#define mmDPP_TOP3_DPP_CONTROL_DEFAULT 0x70000000 +#define mmDPP_TOP3_DPP_SOFT_RESET_DEFAULT 0x00000000 +#define mmDPP_TOP3_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 +#define mmDPP_TOP3_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 +#define mmDPP_TOP3_DPP_CRC_CTRL_DEFAULT 0x00000000 +#define mmDPP_TOP3_HOST_READ_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 +#define mmCNVC_CFG3_FORMAT_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 +#define mmCNVC_CFG3_DENORM_CONTROL_DEFAULT 0x00002000 +#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 +#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 +#define mmCNVC_CFG3_COLOR_KEYER_RED_DEFAULT 0x00000000 +#define mmCNVC_CFG3_COLOR_KEYER_GREEN_DEFAULT 0x00000000 +#define mmCNVC_CFG3_COLOR_KEYER_BLUE_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +#define mmCNVC_CUR3_CURSOR0_CONTROL_DEFAULT 0x0003ff00 +#define mmCNVC_CUR3_CURSOR0_COLOR0_DEFAULT 0x00000000 +#define mmCNVC_CUR3_CURSOR0_COLOR1_DEFAULT 0x00000000 +#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 +#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmDSCL3_SCL_MODE_DEFAULT 0x00000000 +#define mmDSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_CONTROL_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 +#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmDSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmDSCL3_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmDSCL3_SCL_BLACK_OFFSET_DEFAULT 0x80000000 +#define mmDSCL3_DSCL_UPDATE_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_AUTOCAL_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmDSCL3_OTG_H_BLANK_DEFAULT 0x00000000 +#define mmDSCL3_OTG_V_BLANK_DEFAULT 0x00000000 +#define mmDSCL3_RECOUT_START_DEFAULT 0x00000000 +#define mmDSCL3_RECOUT_SIZE_DEFAULT 0x00000000 +#define mmDSCL3_MPC_SIZE_DEFAULT 0x00000000 +#define mmDSCL3_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmDSCL3_LB_MEMORY_CTRL_DEFAULT 0x00003f00 +#define mmDSCL3_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDSCL3_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDSCL3_OBUF_CONTROL_DEFAULT 0xe0000000 +#define mmDSCL3_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +#define mmCM3_CM_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_COMA_C11_C12_DEFAULT 0x00002000 +#define mmCM3_CM_COMA_C13_C14_DEFAULT 0x00000000 +#define mmCM3_CM_COMA_C21_C22_DEFAULT 0x20000000 +#define mmCM3_CM_COMA_C23_C24_DEFAULT 0x00000000 +#define mmCM3_CM_COMA_C31_C32_DEFAULT 0x00000000 +#define mmCM3_CM_COMA_C33_C34_DEFAULT 0x00002000 +#define mmCM3_CM_COMB_C11_C12_DEFAULT 0x00002000 +#define mmCM3_CM_COMB_C13_C14_DEFAULT 0x00000000 +#define mmCM3_CM_COMB_C21_C22_DEFAULT 0x20000000 +#define mmCM3_CM_COMB_C23_C24_DEFAULT 0x00000000 +#define mmCM3_CM_COMB_C31_C32_DEFAULT 0x00000000 +#define mmCM3_CM_COMB_C33_C34_DEFAULT 0x00002000 +#define mmCM3_CM_IGAM_CONTROL_DEFAULT 0x08000002 +#define mmCM3_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 +#define mmCM3_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCM3_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCM3_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCM3_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 +#define mmCM3_CM_ICSC_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_ICSC_C11_C12_DEFAULT 0x00002000 +#define mmCM3_CM_ICSC_C13_C14_DEFAULT 0x00000000 +#define mmCM3_CM_ICSC_C21_C22_DEFAULT 0x20000000 +#define mmCM3_CM_ICSC_C23_C24_DEFAULT 0x00000000 +#define mmCM3_CM_ICSC_C31_C32_DEFAULT 0x00000000 +#define mmCM3_CM_ICSC_C33_C34_DEFAULT 0x00002000 +#define mmCM3_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCM3_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCM3_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCM3_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCM3_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCM3_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmCM3_CM_OCSC_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_OCSC_C11_C12_DEFAULT 0x00002000 +#define mmCM3_CM_OCSC_C13_C14_DEFAULT 0x00000000 +#define mmCM3_CM_OCSC_C21_C22_DEFAULT 0x20000000 +#define mmCM3_CM_OCSC_C23_C24_DEFAULT 0x00000000 +#define mmCM3_CM_OCSC_C31_C32_DEFAULT 0x00000000 +#define mmCM3_CM_OCSC_C33_C34_DEFAULT 0x00002000 +#define mmCM3_CM_BNS_VALUES_R_DEFAULT 0x20000000 +#define mmCM3_CM_BNS_VALUES_G_DEFAULT 0x20000000 +#define mmCM3_CM_BNS_VALUES_B_DEFAULT 0x20000000 +#define mmCM3_CM_DGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM3_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 +#define mmCM3_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 +#define mmCM3_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 +#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff +#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff +#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff +#define mmCM3_CM_DENORM_CONTROL_DEFAULT 0x00000000 +#define mmCM3_CM_CMOUT_CONTROL_DEFAULT 0x0000000a +#define mmCM3_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmCM3_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmCM3_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON15_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON15_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON15_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +#define mmMPCC0_MPCC_TOP_SEL_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_BOT_SEL_DEFAULT 0x0000000f +#define mmMPCC0_MPCC_OPP_ID_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_CONTROL_DEFAULT 0xffff0061 +#define mmMPCC0_MPCC_SM_CONTROL_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f +#define mmMPCC0_MPCC_TOP_OFFSET_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_BOT_OFFSET_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_OFFSET_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_BG_R_CR_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_BG_G_Y_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_BG_B_CB_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_STALL_STATUS_DEFAULT 0x00000000 +#define mmMPCC0_MPCC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +#define mmMPCC1_MPCC_TOP_SEL_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_BOT_SEL_DEFAULT 0x0000000f +#define mmMPCC1_MPCC_OPP_ID_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_CONTROL_DEFAULT 0xffff0061 +#define mmMPCC1_MPCC_SM_CONTROL_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f +#define mmMPCC1_MPCC_TOP_OFFSET_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_BOT_OFFSET_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_OFFSET_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_BG_R_CR_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_BG_G_Y_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_BG_B_CB_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_STALL_STATUS_DEFAULT 0x00000000 +#define mmMPCC1_MPCC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +#define mmMPCC2_MPCC_TOP_SEL_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_BOT_SEL_DEFAULT 0x0000000f +#define mmMPCC2_MPCC_OPP_ID_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_CONTROL_DEFAULT 0xffff0061 +#define mmMPCC2_MPCC_SM_CONTROL_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f +#define mmMPCC2_MPCC_TOP_OFFSET_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_BOT_OFFSET_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_OFFSET_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_BG_R_CR_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_BG_G_Y_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_BG_B_CB_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_STALL_STATUS_DEFAULT 0x00000000 +#define mmMPCC2_MPCC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +#define mmMPCC3_MPCC_TOP_SEL_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_BOT_SEL_DEFAULT 0x0000000f +#define mmMPCC3_MPCC_OPP_ID_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_CONTROL_DEFAULT 0xffff0061 +#define mmMPCC3_MPCC_SM_CONTROL_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f +#define mmMPCC3_MPCC_TOP_OFFSET_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_BOT_OFFSET_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_OFFSET_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_BG_R_CR_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_BG_G_Y_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_BG_B_CB_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_STALL_STATUS_DEFAULT 0x00000000 +#define mmMPCC3_MPCC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +#define mmMPC_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmMPC_SOFT_RESET_DEFAULT 0x00000000 +#define mmMPC_CRC_CTRL_DEFAULT 0x00000000 +#define mmMPC_CRC_SEL_CONTROL_DEFAULT 0x00000000 +#define mmMPC_CRC_RESULT_AR_DEFAULT 0x00000000 +#define mmMPC_CRC_RESULT_GB_DEFAULT 0x00000000 +#define mmMPC_CRC_RESULT_C_DEFAULT 0x00000000 +#define mmMPC_PERFMON_EVENT_CTRL_DEFAULT 0x00000000 +#define mmMPC_BYPASS_BG_AR_DEFAULT 0x00000000 +#define mmMPC_BYPASS_BG_GB_DEFAULT 0x00000000 +#define mmMPC_OUT0_MUX_DEFAULT 0x0000000f +#define mmMPC_OUT1_MUX_DEFAULT 0x0000000f +#define mmMPC_OUT2_MUX_DEFAULT 0x0000000f +#define mmMPC_OUT3_MUX_DEFAULT 0x0000000f +#define mmMPC_STALL_GRACE_WINDOW_DEFAULT 0x00000000 +#define mmADR_CFG_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 +#define mmADR_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 +#define mmCUR0_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 +#define mmCUR1_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 +#define mmADR_CFG_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 +#define mmADR_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 +#define mmCUR0_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 +#define mmCUR1_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 +#define mmADR_CFG_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 +#define mmADR_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 +#define mmCUR0_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 +#define mmCUR1_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 +#define mmADR_CFG_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 +#define mmADR_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 +#define mmCUR0_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 +#define mmCUR1_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON16_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON16_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON16_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_abm0_dispdec +#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM0_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_CNTL_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 +#define mmABM0_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 +#define mmABM0_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_abm1_dispdec +#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM1_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_CNTL_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 +#define mmABM1_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 +#define mmABM1_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +#define mmOPPBUF0_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +#define mmOPP_PIPE0_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +#define mmOPPBUF1_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +#define mmOPP_PIPE1_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +#define mmOPPBUF2_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +#define mmOPP_PIPE2_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +#define mmOPPBUF3_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +#define mmOPP_PIPE3_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt4_dispdec +#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf4_dispdec +#define mmOPPBUF4_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe4_dispdec +#define mmOPP_PIPE4_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_fmt5_dispdec +#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_oppbuf5_dispdec +#define mmOPPBUF5_OPPBUF_CONTROL_DEFAULT 0x00000000 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe5_dispdec +#define mmOPP_PIPE5_OPP_PIPE_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +#define mmOPP_TOP_CLK_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON17_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON17_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON17_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm0_dispdec +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM0_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm1_dispdec +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM1_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm2_dispdec +#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM2_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM2_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm3_dispdec +#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM3_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM3_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm4_dispdec +#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM4_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM4_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_odm5_dispdec +#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define mmODM5_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmODM5_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg0_dispdec +#define mmOTG0_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG0_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG0_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG0_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG0_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG0_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG0_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG0_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG0_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG0_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG0_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG0_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG0_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG0_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG0_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG0_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG0_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG0_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG0_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG0_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG0_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG0_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG0_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG0_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG0_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG0_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG0_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG0_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG0_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG0_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG0_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG0_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG0_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg1_dispdec +#define mmOTG1_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG1_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG1_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG1_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG1_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG1_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG1_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG1_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG1_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG1_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG1_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG1_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG1_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG1_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG1_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG1_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG1_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG1_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG1_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG1_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG1_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG1_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG1_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG1_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG1_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG1_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG1_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG1_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG1_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG1_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG1_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG1_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG1_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg2_dispdec +#define mmOTG2_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG2_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG2_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG2_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG2_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG2_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG2_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG2_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG2_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG2_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG2_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG2_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG2_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG2_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG2_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG2_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG2_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG2_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG2_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG2_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG2_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG2_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG2_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG2_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG2_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG2_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG2_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG2_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG2_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG2_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG2_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG2_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG2_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG2_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg3_dispdec +#define mmOTG3_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG3_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG3_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG3_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG3_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG3_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG3_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG3_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG3_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG3_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG3_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG3_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG3_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG3_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG3_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG3_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG3_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG3_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG3_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG3_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG3_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG3_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG3_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG3_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG3_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG3_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG3_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG3_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG3_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG3_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG3_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG3_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG3_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG3_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg4_dispdec +#define mmOTG4_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG4_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG4_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG4_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG4_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG4_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG4_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG4_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG4_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG4_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG4_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG4_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG4_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG4_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG4_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG4_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG4_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG4_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG4_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG4_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG4_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG4_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG4_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG4_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG4_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG4_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG4_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG4_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG4_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG4_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG4_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG4_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG4_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG4_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_otg5_dispdec +#define mmOTG5_OTG_H_TOTAL_DEFAULT 0x00000000 +#define mmOTG5_OTG_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG5_OTG_H_SYNC_A_DEFAULT 0x00000000 +#define mmOTG5_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_MID_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_SYNC_A_DEFAULT 0x00000000 +#define mmOTG5_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG5_OTG_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmOTG5_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmOTG5_OTG_CONTROL_DEFAULT 0x80000110 +#define mmOTG5_OTG_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmOTG5_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmOTG5_OTG_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_STATUS_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmOTG5_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmOTG5_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmOTG5_OTG_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_COUNT_RESET_DEFAULT 0x00000000 +#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_STEREO_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmOTG5_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmOTG5_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmOTG5_OTG_MASTER_EN_DEFAULT 0x00000000 +#define mmOTG5_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG5_OTG_BLACK_COLOR_DEFAULT 0x00000000 +#define mmOTG5_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC_CNTL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC2_DATA_B_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC3_DATA_B_DEFAULT 0x00000000 +#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff +#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmOTG5_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmOTG5_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 +#define mmOTG5_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 +#define mmOTG5_OTG_VREADY_PARAM_DEFAULT 0x00000000 +#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmOTG5_OTG_GSL_CONTROL_DEFAULT 0x00020000 +#define mmOTG5_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 +#define mmOTG5_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 +#define mmOTG5_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 +#define mmOTG5_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 +#define mmOTG5_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 +#define mmOTG5_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 +#define mmOTG5_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 +#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmOTG5_OTG_DRR_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 +#define mmOTG5_OTG_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +#define mmDWB_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmGSL_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmOPTC_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmOPTC_MISC_SPARE_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON18_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON18_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON18_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dac_dispdec +#define mmDAC_ENABLE_DEFAULT 0x00000004 +#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmDAC_CRC_EN_DEFAULT 0x00000000 +#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff +#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f +#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff +#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f +#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 +#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 +#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 +#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b +#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 +#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 +#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 +#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 +#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 +#define mmDAC_POWERDOWN_DEFAULT 0x01010100 +#define mmDAC_CONTROL_DEFAULT 0x00000000 +#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 +#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 +#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 +#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 +#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 +#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 +#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 +#define mmDC_I2C_DATA_DEFAULT 0x00000000 +#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 + + +// addressBlock: dce_dc_dio_generic_i2c_dispdec +#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 +#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 +#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 +#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 +#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 +#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 +#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +#define mmDIO_SCRATCH0_DEFAULT 0x00000000 +#define mmDIO_SCRATCH1_DEFAULT 0x00000000 +#define mmDIO_SCRATCH2_DEFAULT 0x00000000 +#define mmDIO_SCRATCH3_DEFAULT 0x00000000 +#define mmDIO_SCRATCH4_DEFAULT 0x00000000 +#define mmDIO_SCRATCH5_DEFAULT 0x00000000 +#define mmDIO_SCRATCH6_DEFAULT 0x00000000 +#define mmDIO_SCRATCH7_DEFAULT 0x00000000 +#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 +#define mmDIO_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDIO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 +#define mmDIO_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDIO_CLK_CNTL_DEFAULT 0x00000000 +#define mmDIO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define mmDIO_STEREOSYNC_SEL_DEFAULT 0x00000000 +#define mmDIO_SOFT_RESET_DEFAULT 0x00000000 +#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 +#define mmDIO_MEM_PWR_STATUS1_DEFAULT 0x00000000 +#define mmDIO_CLK_CNTL2_DEFAULT 0x00000000 +#define mmDIO_CLK_CNTL3_DEFAULT 0x00000000 +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 +#define mmDIO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 +#define mmDIO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd2_dispdec +#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd3_dispdec +#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd4_dispdec +#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_hpd5_dispdec +#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +#define mmDC_PERFMON19_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON19_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON19_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux5_dispdec +#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp_aux6_dispdec +#define mmDP_AUX6_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX6_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig0_dispdec +#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG0_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp0_dispdec +#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP0_DP_VID_N_DEFAULT 0x00002000 +#define mmDP0_DP_VID_M_DEFAULT 0x00000000 +#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP0_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP0_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP0_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP0_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig1_dispdec +#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG1_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp1_dispdec +#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP1_DP_VID_N_DEFAULT 0x00002000 +#define mmDP1_DP_VID_M_DEFAULT 0x00000000 +#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP1_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP1_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP1_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP1_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig2_dispdec +#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG2_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp2_dispdec +#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP2_DP_VID_N_DEFAULT 0x00002000 +#define mmDP2_DP_VID_M_DEFAULT 0x00000000 +#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP2_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP2_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP2_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP2_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig3_dispdec +#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG3_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp3_dispdec +#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP3_DP_VID_N_DEFAULT 0x00002000 +#define mmDP3_DP_VID_M_DEFAULT 0x00000000 +#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP3_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP3_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP3_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP3_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig4_dispdec +#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG4_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp4_dispdec +#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP4_DP_VID_N_DEFAULT 0x00002000 +#define mmDP4_DP_VID_M_DEFAULT 0x00000000 +#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP4_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP4_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP4_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP4_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig5_dispdec +#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG5_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp5_dispdec +#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP5_DP_VID_N_DEFAULT 0x00002000 +#define mmDP5_DP_VID_M_DEFAULT 0x00000000 +#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP5_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP5_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP5_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP5_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dig6_dispdec +#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 +#define mmDIG6_HDMI_DB_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dio_dp6_dispdec +#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP6_DP_VID_N_DEFAULT 0x00002000 +#define mmDP6_DP_VID_M_DEFAULT 0x00000000 +#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 +#define mmDP6_DP_MSO_CNTL_DEFAULT 0xfffffff0 +#define mmDP6_DP_MSO_CNTL1_DEFAULT 0xffffffff +#define mmDP6_DP_DSC_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL2_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL3_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL4_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL5_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL6_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL7_DEFAULT 0x00000000 +#define mmDP6_DP_DB_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_VBID_MISC_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +#define mmDC_GENERICA_DEFAULT 0x00000000 +#define mmDC_GENERICB_DEFAULT 0x00000000 +#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 +#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 +#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01000100 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 +#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 +#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 +#define mmBL_PWM_CNTL_DEFAULT 0x00000000 +#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 +#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 +#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 +#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 +#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 +#define mmDIO_OTG_EXT_VSYNC_CNTL_DEFAULT 0x00000000 +#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 +#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 +#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 +#define mmAUXN_IMPCAL_DEFAULT 0x04000000 +#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 +#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 +#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 +#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 +#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 +#define mmDCIO_USBC_FLIP_EN_SEL_DEFAULT 0x00543210 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 +#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 +#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 +#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 +#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 +#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 +#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 +#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 +#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47fc470f +#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 +#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 +#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c +#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 +#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 +#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 +#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 +#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 +#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 +#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 +#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f +#define mmDC_GPIO_PULLUPEN_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_dcio_dac_dispdec +#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x1c010000 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_DEFAULT 0x00010520 + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x1c010000 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_DEFAULT 0x00010520 + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x1c010000 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_DEFAULT 0x00010520 + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x1c010000 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_DEFAULT 0x00010520 + + +// addressBlock: dce_dc_dcio_dcio_zcal_dispdec +#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec +#define mmCOMP_EN_CTL_DEFAULT 0x00080000 +#define mmCOMP_EN_DFX_DEFAULT 0x00000000 +#define mmZCAL_FUSES_DEFAULT 0x00000000 + + +// addressBlock: vga_vgaseqind +#define ixSEQ00_DEFAULT 0x00000003 +#define ixSEQ01_DEFAULT 0x00000021 +#define ixSEQ02_DEFAULT 0x00000000 +#define ixSEQ03_DEFAULT 0x00000000 +#define ixSEQ04_DEFAULT 0x00000000 + + +// addressBlock: vga_vgacrtind +#define ixCRT00_DEFAULT 0x00000000 +#define ixCRT01_DEFAULT 0x00000000 +#define ixCRT02_DEFAULT 0x00000000 +#define ixCRT03_DEFAULT 0x00000000 +#define ixCRT04_DEFAULT 0x00000000 +#define ixCRT05_DEFAULT 0x00000000 +#define ixCRT06_DEFAULT 0x00000000 +#define ixCRT07_DEFAULT 0x00000000 +#define ixCRT08_DEFAULT 0x00000000 +#define ixCRT09_DEFAULT 0x00000000 +#define ixCRT0A_DEFAULT 0x00000000 +#define ixCRT0B_DEFAULT 0x00000000 +#define ixCRT0C_DEFAULT 0x00000000 +#define ixCRT0D_DEFAULT 0x00000000 +#define ixCRT0E_DEFAULT 0x00000000 +#define ixCRT0F_DEFAULT 0x00000000 +#define ixCRT10_DEFAULT 0x00000000 +#define ixCRT11_DEFAULT 0x00000000 +#define ixCRT12_DEFAULT 0x00000000 +#define ixCRT13_DEFAULT 0x00000000 +#define ixCRT14_DEFAULT 0x00000000 +#define ixCRT15_DEFAULT 0x00000000 +#define ixCRT16_DEFAULT 0x00000000 +#define ixCRT17_DEFAULT 0x00000000 +#define ixCRT18_DEFAULT 0x00000000 +#define ixCRT1E_DEFAULT 0x00000000 +#define ixCRT1F_DEFAULT 0x00000000 +#define ixCRT22_DEFAULT 0x00000000 + + +// addressBlock: vga_vgagrphind +#define ixGRA00_DEFAULT 0x00000000 +#define ixGRA01_DEFAULT 0x00000000 +#define ixGRA02_DEFAULT 0x00000000 +#define ixGRA03_DEFAULT 0x00000000 +#define ixGRA04_DEFAULT 0x00000000 +#define ixGRA05_DEFAULT 0x00000000 +#define ixGRA06_DEFAULT 0x00000000 +#define ixGRA07_DEFAULT 0x00000000 +#define ixGRA08_DEFAULT 0x00000000 + + +// addressBlock: vga_vgaattrind +#define ixATTR00_DEFAULT 0x00000000 +#define ixATTR01_DEFAULT 0x00000000 +#define ixATTR02_DEFAULT 0x00000000 +#define ixATTR03_DEFAULT 0x00000000 +#define ixATTR04_DEFAULT 0x00000000 +#define ixATTR05_DEFAULT 0x00000000 +#define ixATTR06_DEFAULT 0x00000000 +#define ixATTR07_DEFAULT 0x00000000 +#define ixATTR08_DEFAULT 0x00000000 +#define ixATTR09_DEFAULT 0x00000000 +#define ixATTR0A_DEFAULT 0x00000000 +#define ixATTR0B_DEFAULT 0x00000000 +#define ixATTR0C_DEFAULT 0x00000000 +#define ixATTR0D_DEFAULT 0x00000000 +#define ixATTR0E_DEFAULT 0x00000000 +#define ixATTR0F_DEFAULT 0x00000000 +#define ixATTR10_DEFAULT 0x00000000 +#define ixATTR11_DEFAULT 0x00000000 +#define ixATTR12_DEFAULT 0x00000000 +#define ixATTR13_DEFAULT 0x00000000 +#define ixATTR14_DEFAULT 0x00000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// addressBlock: azendpoint_f2codecind +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 + + +// addressBlock: azendpoint_descriptorind +#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 + + +// addressBlock: azendpoint_sinkinfoind +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 + + +// addressBlock: azf0controller_azinputcrc0resultind +#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azf0controller_azinputcrc1resultind +#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azf0controller_azcrc0resultind +#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azf0controller_azcrc1resultind +#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azinputendpoint_f2codecind +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 + + +// addressBlock: azroot_f2codecind +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 + + +// addressBlock: azf0stream0_streamind +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream1_streamind +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream2_streamind +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream3_streamind +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream4_streamind +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream5_streamind +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream6_streamind +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream7_streamind +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream8_streamind +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream9_streamind +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream10_streamind +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream11_streamind +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream12_streamind +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream13_streamind +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream14_streamind +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream15_streamind +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint0_endpointind +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint1_endpointind +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint2_endpointind +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint3_endpointind +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint4_endpointind +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint5_endpointind +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint6_endpointind +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint7_endpointind +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint0_inputendpointind +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint1_inputendpointind +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint2_inputendpointind +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint3_inputendpointind +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint4_inputendpointind +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint5_inputendpointind +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint6_inputendpointind +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint7_inputendpointind +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h new file mode 100644 index 000000000000..b39fb6821faa --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h @@ -0,0 +1,14087 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_1_0_OFFSET_HEADER +#define _dcn_1_0_OFFSET_HEADER + + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x1300000 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x1300000 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x1300000 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x1300000 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x1300000 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x1300020 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x1300040 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x1300060 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x1300080 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0x13000a0 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0x13000c0 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0x13000e0 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +// base address: 0x48 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 +#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +// base address: 0x3b4 +#define mmCRTC8_IDX 0x002d +#define mmCRTC8_IDX_BASE_IDX 1 +#define mmCRTC8_DATA 0x002d +#define mmCRTC8_DATA_BASE_IDX 1 +#define mmGENFC_WT 0x002e +#define mmGENFC_WT_BASE_IDX 1 +#define mmGENS1 0x002e +#define mmGENS1_BASE_IDX 1 +#define mmATTRDW 0x0030 +#define mmATTRDW_BASE_IDX 1 +#define mmATTRX 0x0030 +#define mmATTRX_BASE_IDX 1 +#define mmATTRDR 0x0030 +#define mmATTRDR_BASE_IDX 1 +#define mmGENMO_WT 0x0030 +#define mmGENMO_WT_BASE_IDX 1 +#define mmGENS0 0x0030 +#define mmGENS0_BASE_IDX 1 +#define mmGENENB 0x0030 +#define mmGENENB_BASE_IDX 1 +#define mmSEQ8_IDX 0x0031 +#define mmSEQ8_IDX_BASE_IDX 1 +#define mmSEQ8_DATA 0x0031 +#define mmSEQ8_DATA_BASE_IDX 1 +#define mmDAC_MASK 0x0031 +#define mmDAC_MASK_BASE_IDX 1 +#define mmDAC_R_INDEX 0x0031 +#define mmDAC_R_INDEX_BASE_IDX 1 +#define mmDAC_W_INDEX 0x0032 +#define mmDAC_W_INDEX_BASE_IDX 1 +#define mmDAC_DATA 0x0032 +#define mmDAC_DATA_BASE_IDX 1 +#define mmGENFC_RD 0x0032 +#define mmGENFC_RD_BASE_IDX 1 +#define mmGENMO_RD 0x0033 +#define mmGENMO_RD_BASE_IDX 1 +#define mmGRPH8_IDX 0x0033 +#define mmGRPH8_IDX_BASE_IDX 1 +#define mmGRPH8_DATA 0x0033 +#define mmGRPH8_DATA_BASE_IDX 1 +#define mmCRTC8_IDX_1 0x0035 +#define mmCRTC8_IDX_1_BASE_IDX 1 +#define mmCRTC8_DATA_1 0x0035 +#define mmCRTC8_DATA_1_BASE_IDX 1 +#define mmGENFC_WT_1 0x0036 +#define mmGENFC_WT_1_BASE_IDX 1 +#define mmGENS1_1 0x0036 +#define mmGENS1_1_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define mmCORB_WRITE_POINTER 0x0000 +#define mmCORB_WRITE_POINTER_BASE_IDX 0 +#define mmCORB_READ_POINTER 0x0000 +#define mmCORB_READ_POINTER_BASE_IDX 0 +#define mmCORB_CONTROL 0x0001 +#define mmCORB_CONTROL_BASE_IDX 0 +#define mmCORB_STATUS 0x0001 +#define mmCORB_STATUS_BASE_IDX 0 +#define mmCORB_SIZE 0x0001 +#define mmCORB_SIZE_BASE_IDX 0 +#define mmRIRB_LOWER_BASE_ADDRESS 0x0002 +#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmRIRB_UPPER_BASE_ADDRESS 0x0003 +#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmRIRB_WRITE_POINTER 0x0004 +#define mmRIRB_WRITE_POINTER_BASE_IDX 0 +#define mmRESPONSE_INTERRUPT_COUNT 0x0004 +#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define mmRIRB_CONTROL 0x0005 +#define mmRIRB_CONTROL_BASE_IDX 0 +#define mmRIRB_STATUS 0x0005 +#define mmRIRB_STATUS_BASE_IDX 0 +#define mmRIRB_SIZE 0x0005 +#define mmRIRB_SIZE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define mmIMMEDIATE_COMMAND_STATUS 0x0008 +#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c +#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x0 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x20 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x40 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x60 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x80 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0xa0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0xc0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0xe0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +// base address: 0x48 +//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 +//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +// base address: 0x0 +//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 +//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 +#define mmVGA_RENDER_CONTROL 0x0000 +#define mmVGA_RENDER_CONTROL_BASE_IDX 1 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define mmVGA_MODE_CONTROL 0x0002 +#define mmVGA_MODE_CONTROL_BASE_IDX 1 +#define mmVGA_SURFACE_PITCH_SELECT 0x0003 +#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 +#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define mmVGA_HDP_CONTROL 0x000a +#define mmVGA_HDP_CONTROL_BASE_IDX 1 +#define mmVGA_CACHE_CONTROL 0x000b +#define mmVGA_CACHE_CONTROL_BASE_IDX 1 +#define mmD1VGA_CONTROL 0x000c +#define mmD1VGA_CONTROL_BASE_IDX 1 +#define mmD2VGA_CONTROL 0x000e +#define mmD2VGA_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS 0x0010 +#define mmVGA_STATUS_BASE_IDX 1 +#define mmVGA_INTERRUPT_CONTROL 0x0011 +#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS_CLEAR 0x0012 +#define mmVGA_STATUS_CLEAR_BASE_IDX 1 +#define mmVGA_INTERRUPT_STATUS 0x0013 +#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define mmVGA_MAIN_CONTROL 0x0014 +#define mmVGA_MAIN_CONTROL_BASE_IDX 1 +#define mmVGA_TEST_CONTROL 0x0015 +#define mmVGA_TEST_CONTROL_BASE_IDX 1 +#define mmVGA_QOS_CTRL 0x0018 +#define mmVGA_QOS_CTRL_BASE_IDX 1 +//#define mmVGA_CRTC8_IDX 0x002d +//#define mmVGA_CRTC8_DATA 0x002d +//#define mmVGA_GENFC_WT 0x002e +//#define mmVGA_GENS1 0x002e +//#define mmVGA_ATTRDW 0x0030 +//#define mmVGA_ATTRX 0x0030 +//#define mmVGA_ATTRDR 0x0030 +//#define mmVGA_GENMO_WT 0x0030 +//#define mmVGA_GENS0 0x0030 +//#define mmVGA_GENENB 0x0030 +//#define mmVGA_SEQ8_IDX 0x0031 +//#define mmVGA_SEQ8_DATA 0x0031 +//#define mmVGA_DAC_MASK 0x0031 +//#define mmVGA_DAC_R_INDEX 0x0031 +//#define mmVGA_DAC_W_INDEX 0x0032 +//#define mmVGA_DAC_DATA 0x0032 +//#define mmVGA_GENFC_RD 0x0032 +//#define mmVGA_GENMO_RD 0x0033 +//#define mmVGA_GRPH8_IDX 0x0033 +//#define mmVGA_GRPH8_DATA 0x0033 +//#define mmVGA_CRTC8_IDX_1 0x0035 +//#define mmVGA_CRTC8_DATA_1 0x0035 +//#define mmVGA_GENFC_WT_1 0x0036 +//#define mmVGA_GENS1_1 0x0036 +#define mmD3VGA_CONTROL 0x0038 +#define mmD3VGA_CONTROL_BASE_IDX 1 +#define mmD4VGA_CONTROL 0x0039 +#define mmD4VGA_CONTROL_BASE_IDX 1 +#define mmD5VGA_CONTROL 0x003a +#define mmD5VGA_CONTROL_BASE_IDX 1 +#define mmD6VGA_CONTROL 0x003b +#define mmD6VGA_CONTROL_BASE_IDX 1 +#define mmVGA_SOURCE_SELECT 0x003c +#define mmVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDP_DTO_DBUF_EN 0x0044 +#define mmDP_DTO_DBUF_EN_BASE_IDX 1 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmREFCLK_CNTL 0x0049 +#define mmREFCLK_CNTL_BASE_IDX 1 +#define mmMIPI_CLK_CNTL 0x004a +#define mmMIPI_CLK_CNTL_BASE_IDX 1 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL2 0x004e +#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f +#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CBUS_WRCMD_DELAY 0x0050 +#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1 +#define mmDCCG_DS_DTO_INCR 0x0053 +#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 +#define mmDCCG_DS_DTO_MODULO 0x0054 +#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_DS_CNTL 0x0055 +#define mmDCCG_DS_CNTL_BASE_IDX 1 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define mmSYMCLKG_CLOCK_ENABLE 0x0057 +#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 +#define mmDPREFCLK_CNTL 0x0058 +#define mmDPREFCLK_CNTL_BASE_IDX 1 +#define mmAOMCLK0_CNTL 0x0059 +#define mmAOMCLK0_CNTL_BASE_IDX 1 +#define mmAOMCLK1_CNTL 0x005a +#define mmAOMCLK1_CNTL_BASE_IDX 1 +#define mmAOMCLK2_CNTL 0x005b +#define mmAOMCLK2_CNTL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO2_PHASE 0x005c +#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO2_MODULO 0x005d +#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 +#define mmDCE_VERSION 0x005e +#define mmDCE_VERSION_BASE_IDX 1 +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_CNTL 0x0060 +#define mmDCCG_GTC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_DTO_INCR 0x0061 +#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define mmDCCG_GTC_DTO_MODULO 0x0062 +#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_GTC_CURRENT 0x0063 +#define mmDCCG_GTC_CURRENT_BASE_IDX 1 +#define mmMIPI_DTO_CNTL 0x0065 +#define mmMIPI_DTO_CNTL_BASE_IDX 1 +#define mmMIPI_DTO_PHASE 0x0066 +#define mmMIPI_DTO_PHASE_BASE_IDX 1 +#define mmMIPI_DTO_MODULO 0x0067 +#define mmMIPI_DTO_MODULO_BASE_IDX 1 +#define mmDAC_CLK_ENABLE 0x0068 +#define mmDAC_CLK_ENABLE_BASE_IDX 1 +#define mmDVO_CLK_ENABLE 0x0069 +#define mmDVO_CLK_ENABLE_BASE_IDX 1 +#define mmAVSYNC_COUNTER_WRITE 0x006a +#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1 +#define mmAVSYNC_COUNTER_CONTROL 0x006b +#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1 +#define mmAVSYNC_COUNTER_READ 0x006f +#define mmAVSYNC_COUNTER_READ_BASE_IDX 1 +#define mmMILLISECOND_TIME_BASE_DIV 0x0070 +#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL 0x0073 +#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL 0x0074 +#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CAC_STATUS 0x0077 +#define mmDCCG_CAC_STATUS_BASE_IDX 1 +#define mmPIXCLK1_RESYNC_CNTL 0x0078 +#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1 +#define mmPIXCLK2_RESYNC_CNTL 0x0079 +#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1 +#define mmPIXCLK0_RESYNC_CNTL 0x007a +#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1 +#define mmMICROSECOND_TIME_BASE_DIV 0x007b +#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL2 0x007c +#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_DISP_CNTL_REG 0x007f +#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define mmOTG0_PIXEL_RATE_CNTL 0x0080 +#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO0_PHASE 0x0081 +#define mmDP_DTO0_PHASE_BASE_IDX 1 +#define mmDP_DTO0_MODULO 0x0082 +#define mmDP_DTO0_MODULO_BASE_IDX 1 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG1_PIXEL_RATE_CNTL 0x0084 +#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO1_PHASE 0x0085 +#define mmDP_DTO1_PHASE_BASE_IDX 1 +#define mmDP_DTO1_MODULO 0x0086 +#define mmDP_DTO1_MODULO_BASE_IDX 1 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG2_PIXEL_RATE_CNTL 0x0088 +#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO2_PHASE 0x0089 +#define mmDP_DTO2_PHASE_BASE_IDX 1 +#define mmDP_DTO2_MODULO 0x008a +#define mmDP_DTO2_MODULO_BASE_IDX 1 +#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG3_PIXEL_RATE_CNTL 0x008c +#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO3_PHASE 0x008d +#define mmDP_DTO3_PHASE_BASE_IDX 1 +#define mmDP_DTO3_MODULO 0x008e +#define mmDP_DTO3_MODULO_BASE_IDX 1 +#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG4_PIXEL_RATE_CNTL 0x0090 +#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO4_PHASE 0x0091 +#define mmDP_DTO4_PHASE_BASE_IDX 1 +#define mmDP_DTO4_MODULO 0x0092 +#define mmDP_DTO4_MODULO_BASE_IDX 1 +#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 +#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG5_PIXEL_RATE_CNTL 0x0094 +#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO5_PHASE 0x0095 +#define mmDP_DTO5_PHASE_BASE_IDX 1 +#define mmDP_DTO5_MODULO 0x0096 +#define mmDP_DTO5_MODULO_BASE_IDX 1 +#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 +#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 +#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 +#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 +#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 +#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 +#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKF_CLOCK_ENABLE 0x00a5 +#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 +#define mmDCCG_SOFT_RESET 0x00a6 +#define mmDCCG_SOFT_RESET_BASE_IDX 1 +#define mmDVOACLKD_CNTL 0x00a8 +#define mmDVOACLKD_CNTL_BASE_IDX 1 +#define mmDVOACLKC_MVP_CNTL 0x00a9 +#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1 +#define mmDVOACLKC_CNTL 0x00aa +#define mmDVOACLKC_CNTL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab +#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac +#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad +#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae +#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_MODULE 0x00af +#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 +#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define mmDCCG_TEST_CLK_SEL 0x00be +#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define mmDENTIST_DISPCLK_CNTL 0x0064 +#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 +#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_HI 0x0007 +#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_LOW 0x0008 +#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +// base address: 0x30 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e +#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL 0x000f +#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 +#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_HI 0x0013 +#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_LOW 0x0014 +#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_pll_dispdec +// base address: 0x0 +#define mmPLL_MACRO_CNTL_RESERVED0 0x0018 +#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED1 0x0019 +#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED2 0x001a +#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED3 0x001b +#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED4 0x001c +#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED5 0x001d +#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED6 0x001e +#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED7 0x001f +#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED8 0x0020 +#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED9 0x0021 +#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED10 0x0022 +#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED11 0x0023 +#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED12 0x0024 +#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED13 0x0025 +#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED14 0x0026 +#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED15 0x0027 +#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED16 0x0028 +#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED17 0x0029 +#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED18 0x002a +#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED19 0x002b +#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED20 0x002c +#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED21 0x002d +#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED22 0x002e +#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED23 0x002f +#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED24 0x0030 +#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED25 0x0031 +#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED26 0x0032 +#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED27 0x0033 +#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED28 0x0034 +#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED29 0x0035 +#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED30 0x0036 +#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED31 0x0037 +#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED32 0x0038 +#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED33 0x0039 +#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED34 0x003a +#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED35 0x003b +#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED36 0x003c +#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED37 0x003d +#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED38 0x003e +#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED39 0x003f +#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED40 0x0040 +#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED41 0x0041 +#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define mmRBBMIF_TIMEOUT 0x0055 +#define mmRBBMIF_TIMEOUT_BASE_IDX 2 +#define mmRBBMIF_STATUS 0x0056 +#define mmRBBMIF_STATUS_BASE_IDX 2 +#define mmRBBMIF_INT_STATUS 0x0057 +#define mmRBBMIF_INT_STATUS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS 0x0058 +#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define mmRBBMIF_STATUS_FLAG 0x0059 +#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define mmDOMAIN0_PG_CONFIG 0x008a +#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN0_PG_STATUS 0x008b +#define mmDOMAIN0_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN1_PG_CONFIG 0x008c +#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN1_PG_STATUS 0x008d +#define mmDOMAIN1_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN2_PG_CONFIG 0x008e +#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN2_PG_STATUS 0x008f +#define mmDOMAIN2_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN3_PG_CONFIG 0x0090 +#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN3_PG_STATUS 0x0091 +#define mmDOMAIN3_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN4_PG_CONFIG 0x0092 +#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN4_PG_STATUS 0x0093 +#define mmDOMAIN4_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN5_PG_CONFIG 0x0094 +#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN5_PG_STATUS 0x0095 +#define mmDOMAIN5_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN6_PG_CONFIG 0x0096 +#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN6_PG_STATUS 0x0097 +#define mmDOMAIN6_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN7_PG_CONFIG 0x0098 +#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN7_PG_STATUS 0x0099 +#define mmDOMAIN7_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN8_PG_CONFIG 0x009a +#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN8_PG_STATUS 0x009b +#define mmDOMAIN8_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN9_PG_CONFIG 0x009c +#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN9_PG_STATUS 0x009d +#define mmDOMAIN9_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN10_PG_CONFIG 0x009e +#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN10_PG_STATUS 0x009f +#define mmDOMAIN10_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN11_PG_CONFIG 0x00a0 +#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN11_PG_STATUS 0x00a1 +#define mmDOMAIN11_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN12_PG_CONFIG 0x00a2 +#define mmDOMAIN12_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN12_PG_STATUS 0x00a3 +#define mmDOMAIN12_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN13_PG_CONFIG 0x00a4 +#define mmDOMAIN13_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN13_PG_STATUS 0x00a5 +#define mmDOMAIN13_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN14_PG_CONFIG 0x00a6 +#define mmDOMAIN14_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN14_PG_STATUS 0x00a7 +#define mmDOMAIN14_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN15_PG_CONFIG 0x00a8 +#define mmDOMAIN15_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN15_PG_STATUS 0x00a9 +#define mmDOMAIN15_PG_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_STATUS 0x00aa +#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL_1 0x00ab +#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL_2 0x00ac +#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 +#define mmDC_IP_REQUEST_CNTL 0x00ad +#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 +#define mmDC_PGCNTL_STATUS_REG 0x00ae +#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 +#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 +#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_HI 0x00c5 +#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_LOW 0x00c6 +#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define mmCC_DC_PIPE_DIS 0x00ca +#define mmCC_DC_PIPE_DIS_BASE_IDX 2 +#define mmDMU_CLK_CNTL 0x00cb +#define mmDMU_CLK_CNTL_BASE_IDX 2 +#define mmDMU_MEM_PWR_CNTL 0x00cc +#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd +#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define mmSMU_INTERRUPT_CONTROL 0x00ce +#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +// base address: 0x0 +#define mmDMCU_CTRL 0x00da +#define mmDMCU_CTRL_BASE_IDX 2 +#define mmDMCU_STATUS 0x00db +#define mmDMCU_STATUS_BASE_IDX 2 +#define mmDMCU_PC_START_ADDR 0x00dc +#define mmDMCU_PC_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_START_ADDR 0x00dd +#define mmDMCU_FW_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_END_ADDR 0x00de +#define mmDMCU_FW_END_ADDR_BASE_IDX 2 +#define mmDMCU_FW_ISR_START_ADDR 0x00df +#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_CS_HI 0x00e0 +#define mmDMCU_FW_CS_HI_BASE_IDX 2 +#define mmDMCU_FW_CS_LO 0x00e1 +#define mmDMCU_FW_CS_LO_BASE_IDX 2 +#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 +#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_CTRL 0x00e3 +#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_DATA 0x00e4 +#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_ERAM_RD_CTRL 0x00e5 +#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_RD_DATA 0x00e6 +#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_WR_CTRL 0x00e7 +#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_WR_DATA 0x00e8 +#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_RD_CTRL 0x00e9 +#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_RD_DATA 0x00ea +#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_EVENT_TRIGGER 0x00eb +#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec +#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS 0x00ee +#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_1 0x00ef +#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 +#define mmDC_DMCU_SCRATCH 0x00f5 +#define mmDC_DMCU_SCRATCH_BASE_IDX 2 +#define mmDMCU_INT_CNT 0x00f6 +#define mmDMCU_INT_CNT_BASE_IDX 2 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 +#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 +#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG1 0x00f9 +#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG2 0x00fa +#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG3 0x00fb +#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 +#define mmMASTER_COMM_CMD_REG 0x00fc +#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 +#define mmMASTER_COMM_CNTL_REG 0x00fd +#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG1 0x00fe +#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG2 0x00ff +#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG3 0x0100 +#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 +#define mmSLAVE_COMM_CMD_REG 0x0101 +#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 +#define mmSLAVE_COMM_CNTL_REG 0x0102 +#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 +#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 +#define mmDMCU_INT_CNT_CONTINUE 0x011c +#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ 0x0128 +#define mmDC_GPU_TIMER_READ_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ_CNTL 0x0129 +#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS 0x012a +#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec +// base address: 0x0 +#define mmCNV0_WB_ENABLE 0x01da +#define mmCNV0_WB_ENABLE_BASE_IDX 2 +#define mmCNV0_WB_EC_CONFIG 0x01db +#define mmCNV0_WB_EC_CONFIG_BASE_IDX 2 +#define mmCNV0_CNV_MODE 0x01dc +#define mmCNV0_CNV_MODE_BASE_IDX 2 +#define mmCNV0_CNV_WINDOW_START 0x01dd +#define mmCNV0_CNV_WINDOW_START_BASE_IDX 2 +#define mmCNV0_CNV_WINDOW_SIZE 0x01de +#define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2 +#define mmCNV0_CNV_UPDATE 0x01df +#define mmCNV0_CNV_UPDATE_BASE_IDX 2 +#define mmCNV0_CNV_SOURCE_SIZE 0x01e0 +#define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2 +#define mmCNV0_CNV_CSC_CONTROL 0x01e1 +#define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C11_C12 0x01e2 +#define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C13_C14 0x01e3 +#define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C21_C22 0x01e4 +#define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C23_C24 0x01e5 +#define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C31_C32 0x01e6 +#define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2 +#define mmCNV0_CNV_CSC_C33_C34 0x01e7 +#define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 +#define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea +#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 +#define mmCNV0_CNV_CSC_CLAMP_R 0x01eb +#define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2 +#define mmCNV0_CNV_CSC_CLAMP_G 0x01ec +#define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2 +#define mmCNV0_CNV_CSC_CLAMP_B 0x01ed +#define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2 +#define mmCNV0_CNV_TEST_CNTL 0x01ee +#define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2 +#define mmCNV0_CNV_TEST_CRC_RED 0x01ef +#define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2 +#define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0 +#define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2 +#define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1 +#define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2 +#define mmCNV0_CNV_INPUT_SELECT 0x01f5 +#define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2 +#define mmCNV0_WB_SOFT_RESET 0x01f8 +#define mmCNV0_WB_SOFT_RESET_BASE_IDX 2 +#define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9 +#define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 +#define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa +#define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec +// base address: 0x0 +#define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a +#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b +#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmWBSCL0_WBSCL_MODE 0x020c +#define mmWBSCL0_WBSCL_MODE_BASE_IDX 2 +#define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d +#define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2 +#define mmWBSCL0_WBSCL_DEST_SIZE 0x020e +#define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2 +#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f +#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211 +#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212 +#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214 +#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215 +#define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2 +#define mmWBSCL0_WBSCL_CLAMP 0x0216 +#define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2 +#define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217 +#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 +#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218 +#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219 +#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 +#define mmWBSCL0_WBSCL_TEST_CNTL 0x021a +#define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2 +#define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b +#define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2 +#define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c +#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 +#define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d +#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 +#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e +#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f +#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 +#define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222 +#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0x8e8 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c +#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL 0x023d +#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e +#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_HI 0x0241 +#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_LOW 0x0242 +#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec +// base address: 0x1b0 +#define mmCNV1_WB_ENABLE 0x0246 +#define mmCNV1_WB_ENABLE_BASE_IDX 2 +#define mmCNV1_WB_EC_CONFIG 0x0247 +#define mmCNV1_WB_EC_CONFIG_BASE_IDX 2 +#define mmCNV1_CNV_MODE 0x0248 +#define mmCNV1_CNV_MODE_BASE_IDX 2 +#define mmCNV1_CNV_WINDOW_START 0x0249 +#define mmCNV1_CNV_WINDOW_START_BASE_IDX 2 +#define mmCNV1_CNV_WINDOW_SIZE 0x024a +#define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2 +#define mmCNV1_CNV_UPDATE 0x024b +#define mmCNV1_CNV_UPDATE_BASE_IDX 2 +#define mmCNV1_CNV_SOURCE_SIZE 0x024c +#define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2 +#define mmCNV1_CNV_CSC_CONTROL 0x024d +#define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C11_C12 0x024e +#define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C13_C14 0x024f +#define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C21_C22 0x0250 +#define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C23_C24 0x0251 +#define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C31_C32 0x0252 +#define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2 +#define mmCNV1_CNV_CSC_C33_C34 0x0253 +#define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256 +#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 +#define mmCNV1_CNV_CSC_CLAMP_R 0x0257 +#define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2 +#define mmCNV1_CNV_CSC_CLAMP_G 0x0258 +#define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2 +#define mmCNV1_CNV_CSC_CLAMP_B 0x0259 +#define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2 +#define mmCNV1_CNV_TEST_CNTL 0x025a +#define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2 +#define mmCNV1_CNV_TEST_CRC_RED 0x025b +#define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2 +#define mmCNV1_CNV_TEST_CRC_GREEN 0x025c +#define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2 +#define mmCNV1_CNV_TEST_CRC_BLUE 0x025d +#define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2 +#define mmCNV1_CNV_INPUT_SELECT 0x0261 +#define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2 +#define mmCNV1_WB_SOFT_RESET 0x0264 +#define mmCNV1_WB_SOFT_RESET_BASE_IDX 2 +#define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265 +#define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 +#define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266 +#define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 + + +// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec +// base address: 0x1b0 +#define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276 +#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277 +#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmWBSCL1_WBSCL_MODE 0x0278 +#define mmWBSCL1_WBSCL_MODE_BASE_IDX 2 +#define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279 +#define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2 +#define mmWBSCL1_WBSCL_DEST_SIZE 0x027a +#define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2 +#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b +#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d +#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e +#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280 +#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281 +#define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2 +#define mmWBSCL1_WBSCL_CLAMP 0x0282 +#define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2 +#define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283 +#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 +#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284 +#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285 +#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 +#define mmWBSCL1_WBSCL_TEST_CNTL 0x0286 +#define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2 +#define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287 +#define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2 +#define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288 +#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 +#define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289 +#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 +#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a +#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b +#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 +#define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e +#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 + + +// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0xa98 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8 +#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL 0x02a9 +#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa +#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_HI 0x02ad +#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_LOW 0x02ae +#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5 +#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec +// base address: 0x100 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315 +#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define mmWBIF0_MISC_CTRL 0x0333 +#define mmWBIF0_MISC_CTRL_BASE_IDX 2 +#define mmWBIF0_SMU_WM_CONTROL 0x0334 +#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmWBIF1_MISC_CTRL 0x0337 +#define mmWBIF1_MISC_CTRL_BASE_IDX 2 +#define mmWBIF1_SMU_WM_CONTROL 0x0338 +#define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2 +#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339 +#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a +#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmVGA_SRC_SPLIT_CNTL 0x033b +#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_STATUS 0x033c +#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_CNTL 0x033d +#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_CLOCK_CNTL 0x033e +#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_SOFT_RESET 0x033f +#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define mmMCIF_CONTROL 0x034a +#define mmMCIF_CONTROL_BASE_IDX 2 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b +#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354 +#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL 0x0355 +#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL2 0x0356 +#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_HI 0x0359 +#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_LOW 0x035a +#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define mmAZ_CLOCK_CNTL 0x0372 +#define mmAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c +#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL 0x037d +#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL2 0x037e +#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_HI 0x0381 +#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_LOW 0x0382 +#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO 0x03c3 +#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define mmAZALIA_SOCCLK_CONTROL 0x03c5 +#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 +#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 +#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define mmAZALIA_CORB_DMA_CONTROL 0x03ca +#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd +#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL0 0x03e3 +#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL1 0x03e4 +#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL2 0x03e5 +#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL3 0x03e6 +#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC0_RESULT 0x03e7 +#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL0 0x03e8 +#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL1 0x03e9 +#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL2 0x03ea +#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL3 0x03eb +#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC1_RESULT 0x03ec +#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_CTRL 0x03ee +#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_STATUS 0x03ef +#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +// base address: 0x0 +#define mmDCHUBBUB_SDPIF_CFG0 0x048f +#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_CFG1 0x0490 +#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 +#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 +#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_FB_BASE 0x0493 +#define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_FB_TOP 0x0494 +#define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495 +#define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496 +#define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497 +#define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498 +#define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_APER_BASE 0x0499 +#define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_APER_TOP 0x049a +#define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b +#define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c +#define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3 +#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5 +#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7 +#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8 +#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9 +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +// base address: 0x0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf +#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_CRC_CTRL 0x04e2 +#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3 +#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4 +#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5 +#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6 +#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +// base address: 0x0 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 +#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 +#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519 +#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 +#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 +#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 +#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 +#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 +#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 +#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 +#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 +#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define mmVTG0_CONTROL 0x0528 +#define mmVTG0_CONTROL_BASE_IDX 2 +#define mmVTG1_CONTROL 0x0529 +#define mmVTG1_CONTROL_BASE_IDX 2 +#define mmVTG2_CONTROL 0x052a +#define mmVTG2_CONTROL_BASE_IDX 2 +#define mmVTG3_CONTROL 0x052b +#define mmVTG3_CONTROL_BASE_IDX 2 +#define mmVTG4_CONTROL 0x052c +#define mmVTG4_CONTROL_BASE_IDX 2 +#define mmVTG5_CONTROL 0x052d +#define mmVTG5_CONTROL_BASE_IDX 2 +#define mmDCHUBBUB_SOFT_RESET 0x052e +#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define mmDCHUBBUB_CLOCK_CNTL 0x052f +#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmDCFCLK_CNTL 0x0530 +#define mmDCFCLK_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 +#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define mmDCHUBBUB_SPARE 0x0534 +#define mmDCHUBBUB_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f +#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL 0x0550 +#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL2 0x0551 +#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_HI 0x0554 +#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_LOW 0x0555 +#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559 +#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a +#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_TILING_CONFIG 0x055b +#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_CNTL 0x0566 +#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP0_HUBP_CLK_CNTL 0x0567 +#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568 +#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569 +#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591 +#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b +#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c +#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4 +#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6 +#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7 +#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ0_DST_DIMENSIONS 0x05b8 +#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9 +#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba +#define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb +#define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc +#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd +#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be +#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf +#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1 +#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2 +#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3 +#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4 +#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5 +#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6 +#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7 +#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8 +#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9 +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca +#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ0_CURSOR_SETTINS 0x05cb +#define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2 +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define mmHUBPRET0_HUBPRET_CONTROL 0x05e0 +#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1 +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5 +#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6 +#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7 +#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec +// base address: 0x0 +#define mmCURSOR0_CURSOR_CONTROL 0x05ec +#define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee +#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_CURSOR_SIZE 0x05ef +#define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_CURSOR_POSITION 0x05f0 +#define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1 +#define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2 +#define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3 +#define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4 +#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5 +#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1844 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613 +#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL 0x0614 +#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL2 0x0615 +#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_HI 0x0618 +#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_LOW 0x0619 +#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x310 +#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d +#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e +#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_TILING_CONFIG 0x061f +#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_CNTL 0x062a +#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP1_HUBP_CLK_CNTL 0x062b +#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c +#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d +#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x310 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655 +#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656 +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f +#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660 +#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678 +#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_0 0x067a +#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_1 0x067b +#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ1_DST_DIMENSIONS 0x067c +#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ1_DST_AFTER_SCALER 0x067d +#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINS 0x067e +#define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f +#define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684 +#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685 +#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686 +#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687 +#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688 +#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689 +#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a +#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b +#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c +#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e +#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ1_CURSOR_SETTINS 0x068f +#define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x310 +#define mmHUBPRET1_HUBPRET_CONTROL 0x06a4 +#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6 +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9 +#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa +#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab +#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec +// base address: 0x310 +#define mmCURSOR1_CURSOR_CONTROL 0x06b0 +#define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2 +#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR1_CURSOR_SIZE 0x06b3 +#define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR1_CURSOR_POSITION 0x06b4 +#define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5 +#define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6 +#define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7 +#define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8 +#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9 +#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1b54 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL 0x06d8 +#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9 +#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_HI 0x06dc +#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_LOW 0x06dd +#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x620 +#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1 +#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2 +#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3 +#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP2_DCHUBP_CNTL 0x06ee +#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP2_HUBP_CLK_CNTL 0x06ef +#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0 +#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1 +#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x620 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715 +#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719 +#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a +#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723 +#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724 +#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725 +#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a +#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b +#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c +#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d +#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ2_BLANK_OFFSET_0 0x073e +#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ2_BLANK_OFFSET_1 0x073f +#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ2_DST_DIMENSIONS 0x0740 +#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ2_DST_AFTER_SCALER 0x0741 +#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ2_PREFETCH_SETTINS 0x0742 +#define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2 +#define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743 +#define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744 +#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745 +#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746 +#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747 +#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748 +#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749 +#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a +#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b +#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c +#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d +#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e +#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f +#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750 +#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751 +#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752 +#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ2_CURSOR_SETTINS 0x0753 +#define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2 +#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754 +#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x620 +#define mmHUBPRET2_HUBPRET_CONTROL 0x0768 +#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769 +#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a +#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d +#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e +#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f +#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770 +#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771 +#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec +// base address: 0x620 +#define mmCURSOR2_CURSOR_CONTROL 0x0774 +#define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776 +#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR2_CURSOR_SIZE 0x0777 +#define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR2_CURSOR_POSITION 0x0778 +#define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR2_CURSOR_HOT_SPOT 0x0779 +#define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a +#define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR2_CURSOR_DST_OFFSET 0x077b +#define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c +#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d +#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1e64 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b +#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL 0x079c +#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL2 0x079d +#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_HI 0x07a0 +#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_LOW 0x07a1 +#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0x930 +#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5 +#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6 +#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7 +#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP3_DCHUBP_CNTL 0x07b2 +#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP3_HUBP_CLK_CNTL 0x07b3 +#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4 +#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5 +#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0x930 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9 +#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc +#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd +#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de +#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7 +#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8 +#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9 +#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe +#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff +#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800 +#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801 +#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ3_BLANK_OFFSET_0 0x0802 +#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ3_BLANK_OFFSET_1 0x0803 +#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ3_DST_DIMENSIONS 0x0804 +#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ3_DST_AFTER_SCALER 0x0805 +#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ3_PREFETCH_SETTINS 0x0806 +#define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2 +#define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807 +#define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808 +#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809 +#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a +#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b +#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c +#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d +#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e +#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f +#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810 +#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811 +#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812 +#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813 +#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814 +#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815 +#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816 +#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ3_CURSOR_SETTINS 0x0817 +#define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2 +#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818 +#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0x930 +#define mmHUBPRET3_HUBPRET_CONTROL 0x082c +#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d +#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e +#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831 +#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832 +#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833 +#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834 +#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835 +#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec +// base address: 0x930 +#define mmCURSOR3_CURSOR_CONTROL 0x0838 +#define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839 +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a +#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR3_CURSOR_SIZE 0x083b +#define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR3_CURSOR_POSITION 0x083c +#define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR3_CURSOR_HOT_SPOT 0x083d +#define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e +#define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR3_CURSOR_DST_OFFSET 0x083f +#define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840 +#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841 +#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x2174 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f +#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL 0x0860 +#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL2 0x0861 +#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_HI 0x0864 +#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_LOW 0x0865 +#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define mmDPP_TOP0_DPP_CONTROL 0x0c3d +#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e +#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f +#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41 +#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42 +#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47 +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48 +#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49 +#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2 +#define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a +#define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e +#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f +#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50 +#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58 +#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59 +#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a +#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62 +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63 +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL0_SCL_MODE 0x0c64 +#define mmDSCL0_SCL_MODE_BASE_IDX 2 +#define mmDSCL0_SCL_TAP_CONTROL 0x0c65 +#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_CONTROL 0x0c66 +#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67 +#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a +#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e +#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL0_SCL_BLACK_OFFSET 0x0c73 +#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL0_DSCL_UPDATE 0x0c74 +#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL0_DSCL_AUTOCAL 0x0c75 +#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76 +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77 +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL0_OTG_H_BLANK 0x0c78 +#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL0_OTG_V_BLANK 0x0c79 +#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL0_RECOUT_START 0x0c7a +#define mmDSCL0_RECOUT_START_BASE_IDX 2 +#define mmDSCL0_RECOUT_SIZE 0x0c7b +#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL0_MPC_SIZE 0x0c7c +#define mmDSCL0_MPC_SIZE_BASE_IDX 2 +#define mmDSCL0_LB_DATA_FORMAT 0x0c7d +#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL0_LB_MEMORY_CTRL 0x0c7e +#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL0_LB_V_COUNTER 0x0c7f +#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80 +#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81 +#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL0_OBUF_CONTROL 0x0c82 +#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83 +#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define mmCM0_CM_CONTROL 0x0c92 +#define mmCM0_CM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_COMA_C11_C12 0x0c93 +#define mmCM0_CM_COMA_C11_C12_BASE_IDX 2 +#define mmCM0_CM_COMA_C13_C14 0x0c94 +#define mmCM0_CM_COMA_C13_C14_BASE_IDX 2 +#define mmCM0_CM_COMA_C21_C22 0x0c95 +#define mmCM0_CM_COMA_C21_C22_BASE_IDX 2 +#define mmCM0_CM_COMA_C23_C24 0x0c96 +#define mmCM0_CM_COMA_C23_C24_BASE_IDX 2 +#define mmCM0_CM_COMA_C31_C32 0x0c97 +#define mmCM0_CM_COMA_C31_C32_BASE_IDX 2 +#define mmCM0_CM_COMA_C33_C34 0x0c98 +#define mmCM0_CM_COMA_C33_C34_BASE_IDX 2 +#define mmCM0_CM_COMB_C11_C12 0x0c99 +#define mmCM0_CM_COMB_C11_C12_BASE_IDX 2 +#define mmCM0_CM_COMB_C13_C14 0x0c9a +#define mmCM0_CM_COMB_C13_C14_BASE_IDX 2 +#define mmCM0_CM_COMB_C21_C22 0x0c9b +#define mmCM0_CM_COMB_C21_C22_BASE_IDX 2 +#define mmCM0_CM_COMB_C23_C24 0x0c9c +#define mmCM0_CM_COMB_C23_C24_BASE_IDX 2 +#define mmCM0_CM_COMB_C31_C32 0x0c9d +#define mmCM0_CM_COMB_C31_C32_BASE_IDX 2 +#define mmCM0_CM_COMB_C33_C34 0x0c9e +#define mmCM0_CM_COMB_C33_C34_BASE_IDX 2 +#define mmCM0_CM_IGAM_CONTROL 0x0c9f +#define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0 +#define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1 +#define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2 +#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3 +#define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4 +#define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5 +#define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8 +#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 +#define mmCM0_CM_ICSC_CONTROL 0x0ca9 +#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM0_CM_ICSC_C11_C12 0x0caa +#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM0_CM_ICSC_C13_C14 0x0cab +#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM0_CM_ICSC_C21_C22 0x0cac +#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM0_CM_ICSC_C23_C24 0x0cad +#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM0_CM_ICSC_C31_C32 0x0cae +#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM0_CM_ICSC_C33_C34 0x0caf +#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0 +#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1 +#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2 +#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3 +#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4 +#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5 +#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6 +#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM0_CM_OCSC_CONTROL 0x0cb7 +#define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2 +#define mmCM0_CM_OCSC_C11_C12 0x0cb8 +#define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2 +#define mmCM0_CM_OCSC_C13_C14 0x0cb9 +#define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2 +#define mmCM0_CM_OCSC_C21_C22 0x0cba +#define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2 +#define mmCM0_CM_OCSC_C23_C24 0x0cbb +#define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2 +#define mmCM0_CM_OCSC_C31_C32 0x0cbc +#define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2 +#define mmCM0_CM_OCSC_C33_C34 0x0cbd +#define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2 +#define mmCM0_CM_BNS_VALUES_R 0x0cbe +#define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2 +#define mmCM0_CM_BNS_VALUES_G 0x0cbf +#define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2 +#define mmCM0_CM_BNS_VALUES_B 0x0cc0 +#define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_CONTROL 0x0cc1 +#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2 +#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_DATA 0x0cc3 +#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4 +#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1 +#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2 +#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3 +#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4 +#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5 +#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6 +#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7 +#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8 +#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda +#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb +#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5 +#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6 +#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7 +#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8 +#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9 +#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea +#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb +#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec +#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_RGAM_CONTROL 0x0ced +#define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_RGAM_LUT_INDEX 0x0cee +#define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_RGAM_LUT_DATA 0x0cef +#define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0 +#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3 +#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6 +#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb +#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc +#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd +#define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe +#define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff +#define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00 +#define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01 +#define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02 +#define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03 +#define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04 +#define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05 +#define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06 +#define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07 +#define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08 +#define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09 +#define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a +#define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b +#define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c +#define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d +#define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e +#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f +#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10 +#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13 +#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18 +#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19 +#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a +#define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b +#define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c +#define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d +#define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e +#define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f +#define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20 +#define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21 +#define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22 +#define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23 +#define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24 +#define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25 +#define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26 +#define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27 +#define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28 +#define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29 +#define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a +#define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_HDR_MULT_COEF 0x0d2b +#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c +#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 +#define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d +#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 +#define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e +#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 +#define mmCM0_CM_DENORM_CONTROL 0x0d2f +#define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_CMOUT_CONTROL 0x0d30 +#define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2 +#define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31 +#define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_CTRL 0x0d32 +#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_STATUS 0x0d33 +#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3530 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e +#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f +#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50 +#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_HI 0x0d53 +#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_LOW 0x0d54 +#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x46c +#define mmDPP_TOP1_DPP_CONTROL 0x0d58 +#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59 +#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a +#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b +#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c +#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d +#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x46c +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62 +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63 +#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64 +#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2 +#define mmCNVC_CFG1_DENORM_CONTROL 0x0d65 +#define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69 +#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a +#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b +#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x46c +#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73 +#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74 +#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75 +#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76 +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x46c +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL1_SCL_MODE 0x0d7f +#define mmDSCL1_SCL_MODE_BASE_IDX 2 +#define mmDSCL1_SCL_TAP_CONTROL 0x0d80 +#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_CONTROL 0x0d81 +#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82 +#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83 +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c +#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e +#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL1_DSCL_UPDATE 0x0d8f +#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL1_DSCL_AUTOCAL 0x0d90 +#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL1_OTG_H_BLANK 0x0d93 +#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL1_OTG_V_BLANK 0x0d94 +#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL1_RECOUT_START 0x0d95 +#define mmDSCL1_RECOUT_START_BASE_IDX 2 +#define mmDSCL1_RECOUT_SIZE 0x0d96 +#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL1_MPC_SIZE 0x0d97 +#define mmDSCL1_MPC_SIZE_BASE_IDX 2 +#define mmDSCL1_LB_DATA_FORMAT 0x0d98 +#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL1_LB_MEMORY_CTRL 0x0d99 +#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL1_LB_V_COUNTER 0x0d9a +#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b +#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c +#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL1_OBUF_CONTROL 0x0d9d +#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e +#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x46c +#define mmCM1_CM_CONTROL 0x0dad +#define mmCM1_CM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_COMA_C11_C12 0x0dae +#define mmCM1_CM_COMA_C11_C12_BASE_IDX 2 +#define mmCM1_CM_COMA_C13_C14 0x0daf +#define mmCM1_CM_COMA_C13_C14_BASE_IDX 2 +#define mmCM1_CM_COMA_C21_C22 0x0db0 +#define mmCM1_CM_COMA_C21_C22_BASE_IDX 2 +#define mmCM1_CM_COMA_C23_C24 0x0db1 +#define mmCM1_CM_COMA_C23_C24_BASE_IDX 2 +#define mmCM1_CM_COMA_C31_C32 0x0db2 +#define mmCM1_CM_COMA_C31_C32_BASE_IDX 2 +#define mmCM1_CM_COMA_C33_C34 0x0db3 +#define mmCM1_CM_COMA_C33_C34_BASE_IDX 2 +#define mmCM1_CM_COMB_C11_C12 0x0db4 +#define mmCM1_CM_COMB_C11_C12_BASE_IDX 2 +#define mmCM1_CM_COMB_C13_C14 0x0db5 +#define mmCM1_CM_COMB_C13_C14_BASE_IDX 2 +#define mmCM1_CM_COMB_C21_C22 0x0db6 +#define mmCM1_CM_COMB_C21_C22_BASE_IDX 2 +#define mmCM1_CM_COMB_C23_C24 0x0db7 +#define mmCM1_CM_COMB_C23_C24_BASE_IDX 2 +#define mmCM1_CM_COMB_C31_C32 0x0db8 +#define mmCM1_CM_COMB_C31_C32_BASE_IDX 2 +#define mmCM1_CM_COMB_C33_C34 0x0db9 +#define mmCM1_CM_COMB_C33_C34_BASE_IDX 2 +#define mmCM1_CM_IGAM_CONTROL 0x0dba +#define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb +#define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc +#define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd +#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe +#define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf +#define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0 +#define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3 +#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 +#define mmCM1_CM_ICSC_CONTROL 0x0dc4 +#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM1_CM_ICSC_C11_C12 0x0dc5 +#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM1_CM_ICSC_C13_C14 0x0dc6 +#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM1_CM_ICSC_C21_C22 0x0dc7 +#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM1_CM_ICSC_C23_C24 0x0dc8 +#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM1_CM_ICSC_C31_C32 0x0dc9 +#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM1_CM_ICSC_C33_C34 0x0dca +#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb +#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc +#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd +#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce +#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf +#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0 +#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1 +#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM1_CM_OCSC_CONTROL 0x0dd2 +#define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2 +#define mmCM1_CM_OCSC_C11_C12 0x0dd3 +#define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2 +#define mmCM1_CM_OCSC_C13_C14 0x0dd4 +#define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2 +#define mmCM1_CM_OCSC_C21_C22 0x0dd5 +#define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2 +#define mmCM1_CM_OCSC_C23_C24 0x0dd6 +#define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2 +#define mmCM1_CM_OCSC_C31_C32 0x0dd7 +#define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2 +#define mmCM1_CM_OCSC_C33_C34 0x0dd8 +#define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2 +#define mmCM1_CM_BNS_VALUES_R 0x0dd9 +#define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2 +#define mmCM1_CM_BNS_VALUES_G 0x0dda +#define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2 +#define mmCM1_CM_BNS_VALUES_B 0x0ddb +#define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_CONTROL 0x0ddc +#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd +#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_DATA 0x0dde +#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf +#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec +#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded +#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee +#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def +#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0 +#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1 +#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2 +#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3 +#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00 +#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01 +#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02 +#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03 +#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04 +#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05 +#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06 +#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07 +#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_RGAM_CONTROL 0x0e08 +#define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_RGAM_LUT_INDEX 0x0e09 +#define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_RGAM_LUT_DATA 0x0e0a +#define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b +#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c +#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d +#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e +#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11 +#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16 +#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17 +#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18 +#define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19 +#define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a +#define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b +#define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c +#define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d +#define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e +#define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f +#define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20 +#define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21 +#define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22 +#define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23 +#define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24 +#define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25 +#define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26 +#define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27 +#define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28 +#define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a +#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b +#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e +#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33 +#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34 +#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35 +#define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36 +#define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37 +#define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38 +#define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39 +#define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a +#define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b +#define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c +#define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d +#define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e +#define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f +#define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40 +#define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41 +#define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42 +#define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43 +#define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44 +#define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45 +#define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_HDR_MULT_COEF 0x0e46 +#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49 +#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 +#define mmCM1_CM_DENORM_CONTROL 0x0e4a +#define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_CMOUT_CONTROL 0x0e4b +#define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2 +#define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c +#define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_CTRL 0x0e4d +#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e +#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x399c +#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69 +#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a +#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b +#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_HI 0x0e6e +#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_LOW 0x0e6f +#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0x8d8 +#define mmDPP_TOP2_DPP_CONTROL 0x0e73 +#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74 +#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75 +#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76 +#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77 +#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78 +#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0x8d8 +#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d +#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e +#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f +#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2 +#define mmCNVC_CFG2_DENORM_CONTROL 0x0e80 +#define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82 +#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83 +#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84 +#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85 +#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86 +#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +// base address: 0x8d8 +#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e +#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f +#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90 +#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91 +#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0x8d8 +#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98 +#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99 +#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL2_SCL_MODE 0x0e9a +#define mmDSCL2_SCL_MODE_BASE_IDX 2 +#define mmDSCL2_SCL_TAP_CONTROL 0x0e9b +#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL2_DSCL_CONTROL 0x0e9c +#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d +#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e +#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7 +#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9 +#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL2_DSCL_UPDATE 0x0eaa +#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL2_DSCL_AUTOCAL 0x0eab +#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac +#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead +#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL2_OTG_H_BLANK 0x0eae +#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL2_OTG_V_BLANK 0x0eaf +#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL2_RECOUT_START 0x0eb0 +#define mmDSCL2_RECOUT_START_BASE_IDX 2 +#define mmDSCL2_RECOUT_SIZE 0x0eb1 +#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL2_MPC_SIZE 0x0eb2 +#define mmDSCL2_MPC_SIZE_BASE_IDX 2 +#define mmDSCL2_LB_DATA_FORMAT 0x0eb3 +#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL2_LB_MEMORY_CTRL 0x0eb4 +#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL2_LB_V_COUNTER 0x0eb5 +#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6 +#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7 +#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL2_OBUF_CONTROL 0x0eb8 +#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9 +#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0x8d8 +#define mmCM2_CM_CONTROL 0x0ec8 +#define mmCM2_CM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_COMA_C11_C12 0x0ec9 +#define mmCM2_CM_COMA_C11_C12_BASE_IDX 2 +#define mmCM2_CM_COMA_C13_C14 0x0eca +#define mmCM2_CM_COMA_C13_C14_BASE_IDX 2 +#define mmCM2_CM_COMA_C21_C22 0x0ecb +#define mmCM2_CM_COMA_C21_C22_BASE_IDX 2 +#define mmCM2_CM_COMA_C23_C24 0x0ecc +#define mmCM2_CM_COMA_C23_C24_BASE_IDX 2 +#define mmCM2_CM_COMA_C31_C32 0x0ecd +#define mmCM2_CM_COMA_C31_C32_BASE_IDX 2 +#define mmCM2_CM_COMA_C33_C34 0x0ece +#define mmCM2_CM_COMA_C33_C34_BASE_IDX 2 +#define mmCM2_CM_COMB_C11_C12 0x0ecf +#define mmCM2_CM_COMB_C11_C12_BASE_IDX 2 +#define mmCM2_CM_COMB_C13_C14 0x0ed0 +#define mmCM2_CM_COMB_C13_C14_BASE_IDX 2 +#define mmCM2_CM_COMB_C21_C22 0x0ed1 +#define mmCM2_CM_COMB_C21_C22_BASE_IDX 2 +#define mmCM2_CM_COMB_C23_C24 0x0ed2 +#define mmCM2_CM_COMB_C23_C24_BASE_IDX 2 +#define mmCM2_CM_COMB_C31_C32 0x0ed3 +#define mmCM2_CM_COMB_C31_C32_BASE_IDX 2 +#define mmCM2_CM_COMB_C33_C34 0x0ed4 +#define mmCM2_CM_COMB_C33_C34_BASE_IDX 2 +#define mmCM2_CM_IGAM_CONTROL 0x0ed5 +#define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6 +#define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7 +#define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8 +#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9 +#define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda +#define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb +#define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede +#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 +#define mmCM2_CM_ICSC_CONTROL 0x0edf +#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM2_CM_ICSC_C11_C12 0x0ee0 +#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM2_CM_ICSC_C13_C14 0x0ee1 +#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM2_CM_ICSC_C21_C22 0x0ee2 +#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM2_CM_ICSC_C23_C24 0x0ee3 +#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM2_CM_ICSC_C31_C32 0x0ee4 +#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM2_CM_ICSC_C33_C34 0x0ee5 +#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6 +#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7 +#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8 +#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9 +#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea +#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb +#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec +#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM2_CM_OCSC_CONTROL 0x0eed +#define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2 +#define mmCM2_CM_OCSC_C11_C12 0x0eee +#define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2 +#define mmCM2_CM_OCSC_C13_C14 0x0eef +#define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2 +#define mmCM2_CM_OCSC_C21_C22 0x0ef0 +#define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2 +#define mmCM2_CM_OCSC_C23_C24 0x0ef1 +#define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2 +#define mmCM2_CM_OCSC_C31_C32 0x0ef2 +#define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2 +#define mmCM2_CM_OCSC_C33_C34 0x0ef3 +#define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2 +#define mmCM2_CM_BNS_VALUES_R 0x0ef4 +#define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2 +#define mmCM2_CM_BNS_VALUES_G 0x0ef5 +#define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2 +#define mmCM2_CM_BNS_VALUES_B 0x0ef6 +#define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_CONTROL 0x0ef7 +#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8 +#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_DATA 0x0ef9 +#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa +#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb +#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc +#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd +#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07 +#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08 +#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09 +#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a +#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b +#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c +#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d +#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e +#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f +#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b +#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c +#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d +#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e +#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f +#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20 +#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21 +#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22 +#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_RGAM_CONTROL 0x0f23 +#define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_RGAM_LUT_INDEX 0x0f24 +#define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_RGAM_LUT_DATA 0x0f25 +#define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2 +#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26 +#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29 +#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c +#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31 +#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32 +#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33 +#define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34 +#define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35 +#define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36 +#define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37 +#define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38 +#define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39 +#define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a +#define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b +#define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c +#define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d +#define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e +#define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f +#define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40 +#define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41 +#define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42 +#define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43 +#define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46 +#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49 +#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e +#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f +#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50 +#define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51 +#define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52 +#define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53 +#define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54 +#define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55 +#define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56 +#define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57 +#define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58 +#define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59 +#define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a +#define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b +#define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c +#define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d +#define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e +#define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f +#define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60 +#define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_HDR_MULT_COEF 0x0f61 +#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64 +#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 +#define mmCM2_CM_DENORM_CONTROL 0x0f65 +#define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_CMOUT_CONTROL 0x0f66 +#define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2 +#define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67 +#define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_CTRL 0x0f68 +#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_STATUS 0x0f69 +#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e08 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84 +#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL 0x0f85 +#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86 +#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87 +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88 +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_HI 0x0f89 +#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_LOW 0x0f8a +#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0xd44 +#define mmDPP_TOP3_DPP_CONTROL 0x0f8e +#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f +#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90 +#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91 +#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92 +#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93 +#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0xd44 +#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98 +#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99 +#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a +#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2 +#define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b +#define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d +#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e +#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f +#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0 +#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1 +#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +// base address: 0xd44 +#define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9 +#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa +#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab +#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac +#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0xd44 +#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3 +#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4 +#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL3_SCL_MODE 0x0fb5 +#define mmDSCL3_SCL_MODE_BASE_IDX 2 +#define mmDSCL3_SCL_TAP_CONTROL 0x0fb6 +#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL3_DSCL_CONTROL 0x0fb7 +#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8 +#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9 +#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb +#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd +#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf +#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4 +#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL3_DSCL_UPDATE 0x0fc5 +#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL3_DSCL_AUTOCAL 0x0fc6 +#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7 +#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8 +#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL3_OTG_H_BLANK 0x0fc9 +#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL3_OTG_V_BLANK 0x0fca +#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL3_RECOUT_START 0x0fcb +#define mmDSCL3_RECOUT_START_BASE_IDX 2 +#define mmDSCL3_RECOUT_SIZE 0x0fcc +#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL3_MPC_SIZE 0x0fcd +#define mmDSCL3_MPC_SIZE_BASE_IDX 2 +#define mmDSCL3_LB_DATA_FORMAT 0x0fce +#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL3_LB_MEMORY_CTRL 0x0fcf +#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL3_LB_V_COUNTER 0x0fd0 +#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1 +#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2 +#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL3_OBUF_CONTROL 0x0fd3 +#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4 +#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0xd44 +#define mmCM3_CM_CONTROL 0x0fe3 +#define mmCM3_CM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_COMA_C11_C12 0x0fe4 +#define mmCM3_CM_COMA_C11_C12_BASE_IDX 2 +#define mmCM3_CM_COMA_C13_C14 0x0fe5 +#define mmCM3_CM_COMA_C13_C14_BASE_IDX 2 +#define mmCM3_CM_COMA_C21_C22 0x0fe6 +#define mmCM3_CM_COMA_C21_C22_BASE_IDX 2 +#define mmCM3_CM_COMA_C23_C24 0x0fe7 +#define mmCM3_CM_COMA_C23_C24_BASE_IDX 2 +#define mmCM3_CM_COMA_C31_C32 0x0fe8 +#define mmCM3_CM_COMA_C31_C32_BASE_IDX 2 +#define mmCM3_CM_COMA_C33_C34 0x0fe9 +#define mmCM3_CM_COMA_C33_C34_BASE_IDX 2 +#define mmCM3_CM_COMB_C11_C12 0x0fea +#define mmCM3_CM_COMB_C11_C12_BASE_IDX 2 +#define mmCM3_CM_COMB_C13_C14 0x0feb +#define mmCM3_CM_COMB_C13_C14_BASE_IDX 2 +#define mmCM3_CM_COMB_C21_C22 0x0fec +#define mmCM3_CM_COMB_C21_C22_BASE_IDX 2 +#define mmCM3_CM_COMB_C23_C24 0x0fed +#define mmCM3_CM_COMB_C23_C24_BASE_IDX 2 +#define mmCM3_CM_COMB_C31_C32 0x0fee +#define mmCM3_CM_COMB_C31_C32_BASE_IDX 2 +#define mmCM3_CM_COMB_C33_C34 0x0fef +#define mmCM3_CM_COMB_C33_C34_BASE_IDX 2 +#define mmCM3_CM_IGAM_CONTROL 0x0ff0 +#define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1 +#define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2 +#define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3 +#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4 +#define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5 +#define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6 +#define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9 +#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 +#define mmCM3_CM_ICSC_CONTROL 0x0ffa +#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM3_CM_ICSC_C11_C12 0x0ffb +#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM3_CM_ICSC_C13_C14 0x0ffc +#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM3_CM_ICSC_C21_C22 0x0ffd +#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM3_CM_ICSC_C23_C24 0x0ffe +#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM3_CM_ICSC_C31_C32 0x0fff +#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM3_CM_ICSC_C33_C34 0x1000 +#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001 +#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002 +#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003 +#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004 +#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005 +#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006 +#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007 +#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM3_CM_OCSC_CONTROL 0x1008 +#define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2 +#define mmCM3_CM_OCSC_C11_C12 0x1009 +#define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2 +#define mmCM3_CM_OCSC_C13_C14 0x100a +#define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2 +#define mmCM3_CM_OCSC_C21_C22 0x100b +#define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2 +#define mmCM3_CM_OCSC_C23_C24 0x100c +#define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2 +#define mmCM3_CM_OCSC_C31_C32 0x100d +#define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2 +#define mmCM3_CM_OCSC_C33_C34 0x100e +#define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2 +#define mmCM3_CM_BNS_VALUES_R 0x100f +#define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2 +#define mmCM3_CM_BNS_VALUES_G 0x1010 +#define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2 +#define mmCM3_CM_BNS_VALUES_B 0x1011 +#define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_CONTROL 0x1012 +#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_INDEX 0x1013 +#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_DATA 0x1014 +#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015 +#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022 +#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023 +#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024 +#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025 +#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026 +#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027 +#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028 +#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029 +#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a +#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b +#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c +#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036 +#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037 +#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038 +#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039 +#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a +#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b +#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c +#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d +#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_RGAM_CONTROL 0x103e +#define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_RGAM_LUT_INDEX 0x103f +#define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_RGAM_LUT_DATA 0x1040 +#define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2 +#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041 +#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044 +#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047 +#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c +#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d +#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e +#define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f +#define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050 +#define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051 +#define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052 +#define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053 +#define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054 +#define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055 +#define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056 +#define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057 +#define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058 +#define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059 +#define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a +#define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b +#define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c +#define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d +#define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e +#define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f +#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061 +#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064 +#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069 +#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a +#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b +#define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c +#define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d +#define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e +#define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f +#define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070 +#define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071 +#define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072 +#define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073 +#define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074 +#define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075 +#define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076 +#define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077 +#define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078 +#define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079 +#define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a +#define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b +#define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_HDR_MULT_COEF 0x107c +#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d +#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 +#define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e +#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 +#define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f +#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 +#define mmCM3_CM_DENORM_CONTROL 0x1080 +#define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_CMOUT_CONTROL 0x1081 +#define mmCM3_CM_CMOUT_CONTROL_BASE_IDX 2 +#define mmCM3_CM_CMOUT_RANDOM_SEEDS 0x1082 +#define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_CTRL 0x1083 +#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_STATUS 0x1084 +#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x4274 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x109d +#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x109e +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x109f +#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CNTL 0x10a0 +#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CNTL2 0x10a1 +#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10a2 +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x10a3 +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_HI 0x10a4 +#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_LOW 0x10a5 +#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define mmMPCC0_MPCC_TOP_SEL 0x1630 +#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_BOT_SEL 0x1631 +#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_OPP_ID 0x1632 +#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC0_MPCC_CONTROL 0x1633 +#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC0_MPCC_SM_CONTROL 0x1634 +#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1635 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_TOP_OFFSET 0x1636 +#define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX 2 +#define mmMPCC0_MPCC_BOT_OFFSET 0x1637 +#define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX 2 +#define mmMPCC0_MPCC_OFFSET 0x1638 +#define mmMPCC0_MPCC_OFFSET_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_R_CR 0x1639 +#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_G_Y 0x163a +#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_B_CB 0x163b +#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC0_MPCC_STALL_STATUS 0x163c +#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC0_MPCC_STATUS 0x163d +#define mmMPCC0_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x6c +#define mmMPCC1_MPCC_TOP_SEL 0x164b +#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_BOT_SEL 0x164c +#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_OPP_ID 0x164d +#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC1_MPCC_CONTROL 0x164e +#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC1_MPCC_SM_CONTROL 0x164f +#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1650 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_TOP_OFFSET 0x1651 +#define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX 2 +#define mmMPCC1_MPCC_BOT_OFFSET 0x1652 +#define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX 2 +#define mmMPCC1_MPCC_OFFSET 0x1653 +#define mmMPCC1_MPCC_OFFSET_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_R_CR 0x1654 +#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_G_Y 0x1655 +#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_B_CB 0x1656 +#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC1_MPCC_STALL_STATUS 0x1657 +#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC1_MPCC_STATUS 0x1658 +#define mmMPCC1_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0xd8 +#define mmMPCC2_MPCC_TOP_SEL 0x1666 +#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_BOT_SEL 0x1667 +#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_OPP_ID 0x1668 +#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC2_MPCC_CONTROL 0x1669 +#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC2_MPCC_SM_CONTROL 0x166a +#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x166b +#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_TOP_OFFSET 0x166c +#define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX 2 +#define mmMPCC2_MPCC_BOT_OFFSET 0x166d +#define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX 2 +#define mmMPCC2_MPCC_OFFSET 0x166e +#define mmMPCC2_MPCC_OFFSET_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_R_CR 0x166f +#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_G_Y 0x1670 +#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_B_CB 0x1671 +#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC2_MPCC_STALL_STATUS 0x1672 +#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC2_MPCC_STATUS 0x1673 +#define mmMPCC2_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0x144 +#define mmMPCC3_MPCC_TOP_SEL 0x1681 +#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_BOT_SEL 0x1682 +#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_OPP_ID 0x1683 +#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC3_MPCC_CONTROL 0x1684 +#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC3_MPCC_SM_CONTROL 0x1685 +#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x1686 +#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_TOP_OFFSET 0x1687 +#define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX 2 +#define mmMPCC3_MPCC_BOT_OFFSET 0x1688 +#define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX 2 +#define mmMPCC3_MPCC_OFFSET 0x1689 +#define mmMPCC3_MPCC_OFFSET_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_R_CR 0x168a +#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_G_Y 0x168b +#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_B_CB 0x168c +#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC3_MPCC_STALL_STATUS 0x168d +#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC3_MPCC_STATUS 0x168e +#define mmMPCC3_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define mmMPC_CLOCK_CONTROL 0x1723 +#define mmMPC_CLOCK_CONTROL_BASE_IDX 2 +#define mmMPC_SOFT_RESET 0x1724 +#define mmMPC_SOFT_RESET_BASE_IDX 2 +#define mmMPC_CRC_CTRL 0x1725 +#define mmMPC_CRC_CTRL_BASE_IDX 2 +#define mmMPC_CRC_SEL_CONTROL 0x1726 +#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2 +#define mmMPC_CRC_RESULT_AR 0x1727 +#define mmMPC_CRC_RESULT_AR_BASE_IDX 2 +#define mmMPC_CRC_RESULT_GB 0x1728 +#define mmMPC_CRC_RESULT_GB_BASE_IDX 2 +#define mmMPC_CRC_RESULT_C 0x1729 +#define mmMPC_CRC_RESULT_C_BASE_IDX 2 +#define mmMPC_PERFMON_EVENT_CTRL 0x172c +#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2 +#define mmMPC_BYPASS_BG_AR 0x172d +#define mmMPC_BYPASS_BG_AR_BASE_IDX 2 +#define mmMPC_BYPASS_BG_GB 0x172e +#define mmMPC_BYPASS_BG_GB_BASE_IDX 2 +#define mmMPC_OUT0_MUX 0x172f +#define mmMPC_OUT0_MUX_BASE_IDX 2 +#define mmMPC_OUT1_MUX 0x1730 +#define mmMPC_OUT1_MUX_BASE_IDX 2 +#define mmMPC_OUT2_MUX 0x1731 +#define mmMPC_OUT2_MUX_BASE_IDX 2 +#define mmMPC_OUT3_MUX 0x1732 +#define mmMPC_OUT3_MUX_BASE_IDX 2 +#define mmMPC_STALL_GRACE_WINDOW 0x1756 +#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET0 0x175b +#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET0 0x175c +#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmCUR0_VUPDATE_LOCK_SET0 0x175d +#define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmCUR1_VUPDATE_LOCK_SET0 0x175e +#define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET1 0x175f +#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET1 0x1760 +#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmCUR0_VUPDATE_LOCK_SET1 0x1761 +#define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmCUR1_VUPDATE_LOCK_SET1 0x1762 +#define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1763 +#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET2 0x1764 +#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmCUR0_VUPDATE_LOCK_SET2 0x1765 +#define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmCUR1_VUPDATE_LOCK_SET2 0x1766 +#define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET3 0x1767 +#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET3 0x1768 +#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmCUR0_VUPDATE_LOCK_SET3 0x1769 +#define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmCUR1_VUPDATE_LOCK_SET3 0x176a +#define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x5e90 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x17a4 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x17a5 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x17a6 +#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CNTL 0x17a7 +#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CNTL2 0x17a8 +#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x17a9 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x17aa +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_HI 0x17ab +#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_LOW 0x17ac +#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0 +#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 +#define mmABM0_BL1_PWM_USER_LEVEL 0x17b1 +#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 2 +#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x17b2 +#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 +#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x17b3 +#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 +#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x17b4 +#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 +#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5 +#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 +#define mmABM0_BL1_PWM_ABM_CNTL 0x17b6 +#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 2 +#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7 +#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 +#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x17b8 +#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 +#define mmABM0_DC_ABM1_CNTL 0x17b9 +#define mmABM0_DC_ABM1_CNTL_BASE_IDX 2 +#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x17ba +#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x17be +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf +#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_THRES_12 0x17c0 +#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_THRES_34 0x17c1 +#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 2 +#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x17c2 +#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 +#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4 +#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x17c5 +#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x17c6 +#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x17c7 +#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8 +#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x17c9 +#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca +#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb +#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc +#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x17cd +#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 +#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x17ce +#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf +#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0 +#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1 +#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2 +#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3 +#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_1 0x17d4 +#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_2 0x17d5 +#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_3 0x17d6 +#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_4 0x17d7 +#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_5 0x17d8 +#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_6 0x17d9 +#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_7 0x17da +#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_8 0x17db +#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_9 0x17dc +#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_10 0x17dd +#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_11 0x17de +#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_12 0x17df +#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_13 0x17e0 +#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_14 0x17e1 +#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_15 0x17e2 +#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_16 0x17e3 +#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_17 0x17e4 +#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_18 0x17e5 +#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_19 0x17e6 +#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_20 0x17e7 +#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_21 0x17e8 +#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_22 0x17e9 +#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_23 0x17ea +#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 2 +#define mmABM0_DC_ABM1_HG_RESULT_24 0x17eb +#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 2 +#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x17ec +#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x118 +#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17f6 +#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 +#define mmABM1_BL1_PWM_USER_LEVEL 0x17f7 +#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 2 +#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x17f8 +#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 +#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x17f9 +#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 +#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x17fa +#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 +#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17fb +#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 +#define mmABM1_BL1_PWM_ABM_CNTL 0x17fc +#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 2 +#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17fd +#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 +#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x17fe +#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 +#define mmABM1_DC_ABM1_CNTL 0x17ff +#define mmABM1_DC_ABM1_CNTL_BASE_IDX 2 +#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x1800 +#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x1801 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x1802 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x1803 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x1804 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x1805 +#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_THRES_12 0x1806 +#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_THRES_34 0x1807 +#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 2 +#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x1808 +#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 +#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x180a +#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x180b +#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x180c +#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x180d +#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x180e +#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x180f +#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1810 +#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1811 +#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1812 +#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x1813 +#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 +#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x1814 +#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1815 +#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1816 +#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1817 +#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1818 +#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x1819 +#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_1 0x181a +#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_2 0x181b +#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_3 0x181c +#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_4 0x181d +#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_5 0x181e +#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_6 0x181f +#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_7 0x1820 +#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_8 0x1821 +#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_9 0x1822 +#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_10 0x1823 +#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_11 0x1824 +#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_12 0x1825 +#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_13 0x1826 +#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_14 0x1827 +#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_15 0x1828 +#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_16 0x1829 +#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_17 0x182a +#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_18 0x182b +#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_19 0x182c +#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_20 0x182d +#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_21 0x182e +#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_22 0x182f +#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_23 0x1830 +#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 2 +#define mmABM1_DC_ABM1_HG_RESULT_24 0x1831 +#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 2 +#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x1832 +#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CONTROL 0x1840 +#define mmFMT0_FMT_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1848 +#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1849 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x184a +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 +#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CONTROL 0x189a +#define mmFMT1_FMT_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_CNTL 0x18a2 +#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a3 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a4 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define mmOPPBUF1_OPPBUF_CONTROL 0x18de +#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_CONTROL 0x18f4 +#define mmFMT2_FMT_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_CNTL 0x18fc +#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fd +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fe +#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define mmOPPBUF2_OPPBUF_CONTROL 0x1938 +#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 +#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_CONTROL 0x194e +#define mmFMT3_FMT_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_CNTL 0x1956 +#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1957 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1958 +#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define mmOPPBUF3_OPPBUF_CONTROL 0x1992 +#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a +#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt4_dispdec +// base address: 0x5a0 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 +#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 +#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 +#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_CONTROL 0x19a8 +#define mmFMT4_FMT_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa +#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab +#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac +#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_CNTL 0x19b0 +#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19b1 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19b2 +#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf4_dispdec +// base address: 0x5a0 +#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec +#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe4_dispdec +// base address: 0x5a0 +#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 +#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec +// base address: 0x5a0 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt5_dispdec +// base address: 0x708 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe +#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff +#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 +#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_CONTROL 0x1a02 +#define mmFMT5_FMT_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 +#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 +#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 +#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_CNTL 0x1a0a +#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a0b +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a0c +#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf5_dispdec +// base address: 0x708 +#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 +#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe5_dispdec +// base address: 0x708 +#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e +#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec +// base address: 0x708 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define mmOPP_TOP_CLK_CONTROL 0x1a5e +#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1abe +#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1abf +#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1ac0 +#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CNTL 0x1ac1 +#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CNTL2 0x1ac2 +#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1ac4 +#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_HI 0x1ac5 +#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_LOW 0x1ac6 +#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acd +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1acf +#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1add +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1adf +#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb +#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aed +#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1aef +#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb +#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1afd +#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1aff +#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm4_dispdec +// base address: 0x100 +#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a +#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b +#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0d +#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b0f +#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm5_dispdec +// base address: 0x140 +#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a +#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b +#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1d +#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b1f +#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define mmOTG0_OTG_H_TOTAL 0x1b2a +#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b +#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A 0x1b2c +#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL 0x1b2f +#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 +#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 +#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A 0x1b37 +#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 +#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b +#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e +#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG0_OTG_AVSYNC_COUNTER 0x1b40 +#define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG0_OTG_CONTROL 0x1b41 +#define mmOTG0_OTG_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 +#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43 +#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_FIELD_INDICATION_CONTROL 0x1b46 +#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG0_OTG_STATUS 0x1b49 +#define mmOTG0_OTG_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_POSITION 0x1b4a +#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f +#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_RESET 0x1b50 +#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_STATUS 0x1b53 +#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 +#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a +#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_TEST_PATTERN_CONTROL 0x1b5c +#define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0x1b5d +#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG0_OTG_TEST_PATTERN_COLOR 0x1b5e +#define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_EN 0x1b5f +#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b61 +#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b62 +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG0_OTG_BLACK_COLOR 0x1b63 +#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b64 +#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b65 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b66 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b67 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b68 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b69 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b6a +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC_CNTL 0x1b6b +#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6c +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6d +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6e +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6f +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_RG 0x1b70 +#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_B 0x1b71 +#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b72 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b73 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b74 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b75 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_RG 0x1b76 +#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_B 0x1b77 +#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_RG 0x1b78 +#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_B 0x1b79 +#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_RG 0x1b7a +#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_B 0x1b7b +#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7c +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7d +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b84 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b85 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b86 +#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b87 +#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG0_OTG_CLOCK_CONTROL 0x1b88 +#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b89 +#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_PARAM 0x1b8a +#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VREADY_PARAM 0x1b8b +#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8c +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8d +#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_GSL_CONTROL 0x1b8e +#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8f +#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b90 +#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b91 +#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b92 +#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b93 +#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b94 +#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b95 +#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b96 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b97 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b98 +#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_DRR_CONTROL 0x1b99 +#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9a +#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SPARE_REGISTER 0x1b9b +#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x200 +#define mmOTG1_OTG_H_TOTAL 0x1baa +#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_H_BLANK_START_END 0x1bab +#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A 0x1bac +#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae +#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL 0x1baf +#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A 0x1bb7 +#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb +#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe +#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG1_OTG_AVSYNC_COUNTER 0x1bc0 +#define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG1_OTG_CONTROL 0x1bc1 +#define mmOTG1_OTG_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 +#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3 +#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_FIELD_INDICATION_CONTROL 0x1bc6 +#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG1_OTG_STATUS 0x1bc9 +#define mmOTG1_OTG_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_POSITION 0x1bca +#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf +#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_RESET 0x1bd0 +#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 +#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_UPDATE_LOCK 0x1bda +#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_TEST_PATTERN_CONTROL 0x1bdc +#define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0x1bdd +#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG1_OTG_TEST_PATTERN_COLOR 0x1bde +#define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_EN 0x1bdf +#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1be1 +#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1be2 +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG1_OTG_BLACK_COLOR 0x1be3 +#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be4 +#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be5 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be6 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be7 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be8 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be9 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bea +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC_CNTL 0x1beb +#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bec +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bed +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bee +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bef +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_RG 0x1bf0 +#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_B 0x1bf1 +#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf2 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf3 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf4 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf5 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf6 +#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_B 0x1bf7 +#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf8 +#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_B 0x1bf9 +#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_RG 0x1bfa +#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_B 0x1bfb +#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfc +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfd +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c04 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c05 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c06 +#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c07 +#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG1_OTG_CLOCK_CONTROL 0x1c08 +#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c09 +#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_PARAM 0x1c0a +#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VREADY_PARAM 0x1c0b +#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0c +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0d +#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_GSL_CONTROL 0x1c0e +#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0f +#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c10 +#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c11 +#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c12 +#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c13 +#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c14 +#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c15 +#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c16 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c17 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c18 +#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_DRR_CONTROL 0x1c19 +#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1a +#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SPARE_REGISTER 0x1c1b +#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x400 +#define mmOTG2_OTG_H_TOTAL 0x1c2a +#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b +#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG2_OTG_H_SYNC_A 0x1c2c +#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d +#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e +#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL 0x1c2f +#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 +#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 +#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MID 0x1c32 +#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 +#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 +#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 +#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_V_BLANK_START_END 0x1c36 +#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG2_OTG_V_SYNC_A 0x1c37 +#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 +#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGA_CNTL 0x1c39 +#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a +#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b +#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c +#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d +#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e +#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f +#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG2_OTG_AVSYNC_COUNTER 0x1c40 +#define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG2_OTG_CONTROL 0x1c41 +#define mmOTG2_OTG_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_CONTROL 0x1c42 +#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43 +#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 +#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 +#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_FIELD_INDICATION_CONTROL 0x1c46 +#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 +#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 +#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG2_OTG_STATUS 0x1c49 +#define mmOTG2_OTG_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_POSITION 0x1c4a +#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b +#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c +#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d +#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e +#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f +#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_COUNT_RESET 0x1c50 +#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 +#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 +#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_STATUS 0x1c53 +#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_CONTROL 0x1c54 +#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 +#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 +#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 +#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 +#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 +#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a +#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b +#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_TEST_PATTERN_CONTROL 0x1c5c +#define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0x1c5d +#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG2_OTG_TEST_PATTERN_COLOR 0x1c5e +#define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_EN 0x1c5f +#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c61 +#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c62 +#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG2_OTG_BLACK_COLOR 0x1c63 +#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c64 +#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c65 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c66 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c67 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c68 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c69 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c6a +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC_CNTL 0x1c6b +#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6c +#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6d +#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6e +#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6f +#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_DATA_RG 0x1c70 +#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_DATA_B 0x1c71 +#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c72 +#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c73 +#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c74 +#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c75 +#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_DATA_RG 0x1c76 +#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_DATA_B 0x1c77 +#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC2_DATA_RG 0x1c78 +#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC2_DATA_B 0x1c79 +#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC3_DATA_RG 0x1c7a +#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC3_DATA_B 0x1c7b +#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7c +#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7d +#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c84 +#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c85 +#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c86 +#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c87 +#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG2_OTG_CLOCK_CONTROL 0x1c88 +#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c89 +#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_VUPDATE_PARAM 0x1c8a +#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_VREADY_PARAM 0x1c8b +#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8c +#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8d +#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG2_OTG_GSL_CONTROL 0x1c8e +#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8f +#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c90 +#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c91 +#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c92 +#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c93 +#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c94 +#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c95 +#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c96 +#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c97 +#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c98 +#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_DRR_CONTROL 0x1c99 +#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9a +#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_SPARE_REGISTER 0x1c9b +#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x600 +#define mmOTG3_OTG_H_TOTAL 0x1caa +#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG3_OTG_H_BLANK_START_END 0x1cab +#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG3_OTG_H_SYNC_A 0x1cac +#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad +#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae +#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL 0x1caf +#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 +#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 +#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 +#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 +#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 +#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 +#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 +#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG3_OTG_V_SYNC_A 0x1cb7 +#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 +#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 +#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba +#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb +#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc +#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd +#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe +#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf +#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG3_OTG_AVSYNC_COUNTER 0x1cc0 +#define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG3_OTG_CONTROL 0x1cc1 +#define mmOTG3_OTG_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 +#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3 +#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 +#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 +#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_FIELD_INDICATION_CONTROL 0x1cc6 +#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 +#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 +#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG3_OTG_STATUS 0x1cc9 +#define mmOTG3_OTG_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_POSITION 0x1cca +#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb +#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc +#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd +#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce +#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf +#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_COUNT_RESET 0x1cd0 +#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 +#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 +#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_STATUS 0x1cd3 +#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 +#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 +#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 +#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 +#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 +#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 +#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_UPDATE_LOCK 0x1cda +#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb +#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_TEST_PATTERN_CONTROL 0x1cdc +#define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0x1cdd +#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG3_OTG_TEST_PATTERN_COLOR 0x1cde +#define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_EN 0x1cdf +#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1ce1 +#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1ce2 +#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG3_OTG_BLACK_COLOR 0x1ce3 +#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce4 +#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce5 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce6 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce7 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce8 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce9 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cea +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC_CNTL 0x1ceb +#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cec +#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ced +#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cee +#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cef +#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_DATA_RG 0x1cf0 +#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_DATA_B 0x1cf1 +#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf2 +#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf3 +#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf4 +#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf5 +#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf6 +#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_DATA_B 0x1cf7 +#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf8 +#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC2_DATA_B 0x1cf9 +#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC3_DATA_RG 0x1cfa +#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC3_DATA_B 0x1cfb +#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfc +#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfd +#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d04 +#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d05 +#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d06 +#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d07 +#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG3_OTG_CLOCK_CONTROL 0x1d08 +#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d09 +#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_VUPDATE_PARAM 0x1d0a +#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_VREADY_PARAM 0x1d0b +#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0c +#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0d +#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG3_OTG_GSL_CONTROL 0x1d0e +#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0f +#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d10 +#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d11 +#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d12 +#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d13 +#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d14 +#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d15 +#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d16 +#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d17 +#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d18 +#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_DRR_CONTROL 0x1d19 +#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1a +#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_SPARE_REGISTER 0x1d1b +#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg4_dispdec +// base address: 0x800 +#define mmOTG4_OTG_H_TOTAL 0x1d2a +#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b +#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG4_OTG_H_SYNC_A 0x1d2c +#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d +#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e +#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL 0x1d2f +#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 +#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 +#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MID 0x1d32 +#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 +#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 +#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 +#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_V_BLANK_START_END 0x1d36 +#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG4_OTG_V_SYNC_A 0x1d37 +#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 +#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGA_CNTL 0x1d39 +#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a +#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b +#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c +#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d +#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e +#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f +#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG4_OTG_AVSYNC_COUNTER 0x1d40 +#define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG4_OTG_CONTROL 0x1d41 +#define mmOTG4_OTG_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_CONTROL 0x1d42 +#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43 +#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 +#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 +#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_FIELD_INDICATION_CONTROL 0x1d46 +#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 +#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 +#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG4_OTG_STATUS 0x1d49 +#define mmOTG4_OTG_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_POSITION 0x1d4a +#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b +#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c +#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d +#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e +#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f +#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_COUNT_RESET 0x1d50 +#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 +#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 +#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_STATUS 0x1d53 +#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_CONTROL 0x1d54 +#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 +#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 +#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 +#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 +#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 +#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a +#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b +#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_TEST_PATTERN_CONTROL 0x1d5c +#define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0x1d5d +#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG4_OTG_TEST_PATTERN_COLOR 0x1d5e +#define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_EN 0x1d5f +#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d61 +#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d62 +#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG4_OTG_BLACK_COLOR 0x1d63 +#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d64 +#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d65 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d66 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d67 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d68 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d69 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d6a +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC_CNTL 0x1d6b +#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6c +#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6d +#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6e +#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6f +#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_DATA_RG 0x1d70 +#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_DATA_B 0x1d71 +#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d72 +#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d73 +#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d74 +#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d75 +#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_DATA_RG 0x1d76 +#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_DATA_B 0x1d77 +#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC2_DATA_RG 0x1d78 +#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC2_DATA_B 0x1d79 +#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC3_DATA_RG 0x1d7a +#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC3_DATA_B 0x1d7b +#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7c +#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7d +#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d84 +#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d85 +#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d86 +#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d87 +#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG4_OTG_CLOCK_CONTROL 0x1d88 +#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d89 +#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_VUPDATE_PARAM 0x1d8a +#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_VREADY_PARAM 0x1d8b +#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8c +#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8d +#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG4_OTG_GSL_CONTROL 0x1d8e +#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8f +#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d90 +#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d91 +#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d92 +#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d93 +#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d94 +#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d95 +#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d96 +#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d97 +#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d98 +#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_DRR_CONTROL 0x1d99 +#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9a +#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_SPARE_REGISTER 0x1d9b +#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg5_dispdec +// base address: 0xa00 +#define mmOTG5_OTG_H_TOTAL 0x1daa +#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG5_OTG_H_BLANK_START_END 0x1dab +#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG5_OTG_H_SYNC_A 0x1dac +#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad +#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae +#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL 0x1daf +#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 +#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 +#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MID 0x1db2 +#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 +#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 +#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 +#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_V_BLANK_START_END 0x1db6 +#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG5_OTG_V_SYNC_A 0x1db7 +#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 +#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGA_CNTL 0x1db9 +#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba +#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb +#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc +#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd +#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe +#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf +#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG5_OTG_AVSYNC_COUNTER 0x1dc0 +#define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX 2 +#define mmOTG5_OTG_CONTROL 0x1dc1 +#define mmOTG5_OTG_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 +#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3 +#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 +#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 +#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_FIELD_INDICATION_CONTROL 0x1dc6 +#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 +#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 +#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG5_OTG_STATUS 0x1dc9 +#define mmOTG5_OTG_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_POSITION 0x1dca +#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb +#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc +#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd +#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce +#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf +#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_COUNT_RESET 0x1dd0 +#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 +#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 +#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_STATUS 0x1dd3 +#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 +#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 +#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 +#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 +#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 +#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 +#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_UPDATE_LOCK 0x1dda +#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb +#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_TEST_PATTERN_CONTROL 0x1ddc +#define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0x1ddd +#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmOTG5_OTG_TEST_PATTERN_COLOR 0x1dde +#define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_EN 0x1ddf +#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1de1 +#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1de2 +#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG5_OTG_BLACK_COLOR 0x1de3 +#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de4 +#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de5 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de6 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de7 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de8 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de9 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1dea +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC_CNTL 0x1deb +#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dec +#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ded +#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dee +#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1def +#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_DATA_RG 0x1df0 +#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_DATA_B 0x1df1 +#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df2 +#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df3 +#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df4 +#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df5 +#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_DATA_RG 0x1df6 +#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_DATA_B 0x1df7 +#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC2_DATA_RG 0x1df8 +#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC2_DATA_B 0x1df9 +#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC3_DATA_RG 0x1dfa +#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC3_DATA_B 0x1dfb +#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfc +#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfd +#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e04 +#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e05 +#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e06 +#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e07 +#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG5_OTG_CLOCK_CONTROL 0x1e08 +#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e09 +#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_VUPDATE_PARAM 0x1e0a +#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_VREADY_PARAM 0x1e0b +#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0c +#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0d +#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG5_OTG_GSL_CONTROL 0x1e0e +#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0f +#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e10 +#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e11 +#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e12 +#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e13 +#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e14 +#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e15 +#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e16 +#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e17 +#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e18 +#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_DRR_CONTROL 0x1e19 +#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1a +#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_SPARE_REGISTER 0x1e1b +#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define mmDWB_SOURCE_SELECT 0x1e2a +#define mmDWB_SOURCE_SELECT_BASE_IDX 2 +#define mmGSL_SOURCE_SELECT 0x1e2b +#define mmGSL_SOURCE_SELECT_BASE_IDX 2 +#define mmOPTC_CLOCK_CONTROL 0x1e2c +#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define mmOPTC_MISC_SPARE_REGISTER 0x1e2d +#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1e6a +#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1e6b +#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1e6c +#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CNTL 0x1e6d +#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CNTL2 0x1e6e +#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1e6f +#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1e70 +#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_HI 0x1e71 +#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_LOW 0x1e72 +#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dac_dispdec +// base address: 0x0 +#define mmDAC_ENABLE 0x1e76 +#define mmDAC_ENABLE_BASE_IDX 2 +#define mmDAC_SOURCE_SELECT 0x1e77 +#define mmDAC_SOURCE_SELECT_BASE_IDX 2 +#define mmDAC_CRC_EN 0x1e78 +#define mmDAC_CRC_EN_BASE_IDX 2 +#define mmDAC_CRC_CONTROL 0x1e79 +#define mmDAC_CRC_CONTROL_BASE_IDX 2 +#define mmDAC_CRC_SIG_RGB_MASK 0x1e7a +#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2 +#define mmDAC_CRC_SIG_CONTROL_MASK 0x1e7b +#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2 +#define mmDAC_CRC_SIG_RGB 0x1e7c +#define mmDAC_CRC_SIG_RGB_BASE_IDX 2 +#define mmDAC_CRC_SIG_CONTROL 0x1e7d +#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2 +#define mmDAC_SYNC_TRISTATE_CONTROL 0x1e7e +#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2 +#define mmDAC_STEREOSYNC_SELECT 0x1e7f +#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL 0x1e80 +#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL2 0x1e81 +#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL3 0x1e82 +#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2 +#define mmDAC_AUTODETECT_STATUS 0x1e83 +#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2 +#define mmDAC_AUTODETECT_INT_CONTROL 0x1e84 +#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2 +#define mmDAC_FORCE_OUTPUT_CNTL 0x1e85 +#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2 +#define mmDAC_FORCE_DATA 0x1e86 +#define mmDAC_FORCE_DATA_BASE_IDX 2 +#define mmDAC_POWERDOWN 0x1e87 +#define mmDAC_POWERDOWN_BASE_IDX 2 +#define mmDAC_CONTROL 0x1e88 +#define mmDAC_CONTROL_BASE_IDX 2 +#define mmDAC_COMPARATOR_ENABLE 0x1e89 +#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2 +#define mmDAC_COMPARATOR_OUTPUT 0x1e8a +#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2 +#define mmDAC_PWR_CNTL 0x1e8b +#define mmDAC_PWR_CNTL_BASE_IDX 2 +#define mmDAC_DFT_CONFIG 0x1e8c +#define mmDAC_DFT_CONFIG_BASE_IDX 2 +#define mmDAC_FIFO_STATUS 0x1e8d +#define mmDAC_FIFO_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define mmDC_I2C_CONTROL 0x1e98 +#define mmDC_I2C_CONTROL_BASE_IDX 2 +#define mmDC_I2C_ARBITRATION 0x1e99 +#define mmDC_I2C_ARBITRATION_BASE_IDX 2 +#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDC_I2C_SW_STATUS 0x1e9b +#define mmDC_I2C_SW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c +#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d +#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e +#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f +#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1 +#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_SPEED 0x1ea2 +#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC1_SETUP 0x1ea3 +#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC2_SPEED 0x1ea4 +#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC2_SETUP 0x1ea5 +#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC3_SPEED 0x1ea6 +#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC3_SETUP 0x1ea7 +#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC4_SPEED 0x1ea8 +#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC4_SETUP 0x1ea9 +#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC5_SPEED 0x1eaa +#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC5_SETUP 0x1eab +#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC6_SPEED 0x1eac +#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC6_SETUP 0x1ead +#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION0 0x1eae +#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION1 0x1eaf +#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION2 0x1eb0 +#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION3 0x1eb1 +#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 +#define mmDC_I2C_DATA 0x1eb2 +#define mmDC_I2C_DATA_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1eb3 +#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_SPEED 0x1eb4 +#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_SETUP 0x1eb5 +#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2 +#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_generic_i2c_dispdec +// base address: 0x0 +#define mmGENERIC_I2C_CONTROL 0x1eb8 +#define mmGENERIC_I2C_CONTROL_BASE_IDX 2 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1eb9 +#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmGENERIC_I2C_STATUS 0x1eba +#define mmGENERIC_I2C_STATUS_BASE_IDX 2 +#define mmGENERIC_I2C_SPEED 0x1ebb +#define mmGENERIC_I2C_SPEED_BASE_IDX 2 +#define mmGENERIC_I2C_SETUP 0x1ebc +#define mmGENERIC_I2C_SETUP_BASE_IDX 2 +#define mmGENERIC_I2C_TRANSACTION 0x1ebd +#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2 +#define mmGENERIC_I2C_DATA 0x1ebe +#define mmGENERIC_I2C_DATA_BASE_IDX 2 +#define mmGENERIC_I2C_PIN_SELECTION 0x1ebf +#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define mmDIO_SCRATCH0 0x1eca +#define mmDIO_SCRATCH0_BASE_IDX 2 +#define mmDIO_SCRATCH1 0x1ecb +#define mmDIO_SCRATCH1_BASE_IDX 2 +#define mmDIO_SCRATCH2 0x1ecc +#define mmDIO_SCRATCH2_BASE_IDX 2 +#define mmDIO_SCRATCH3 0x1ecd +#define mmDIO_SCRATCH3_BASE_IDX 2 +#define mmDIO_SCRATCH4 0x1ece +#define mmDIO_SCRATCH4_BASE_IDX 2 +#define mmDIO_SCRATCH5 0x1ecf +#define mmDIO_SCRATCH5_BASE_IDX 2 +#define mmDIO_SCRATCH6 0x1ed0 +#define mmDIO_SCRATCH6_BASE_IDX 2 +#define mmDIO_SCRATCH7 0x1ed1 +#define mmDIO_SCRATCH7_BASE_IDX 2 +#define mmDCE_VCE_CONTROL 0x1ed2 +#define mmDCE_VCE_CONTROL_BASE_IDX 2 +#define mmDIO_MEM_PWR_STATUS 0x1edd +#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL 0x1ede +#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL2 0x1edf +#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL 0x1ee0 +#define mmDIO_CLK_CNTL_BASE_IDX 2 +#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define mmDIO_STEREOSYNC_SEL 0x1eea +#define mmDIO_STEREOSYNC_SEL_BASE_IDX 2 +#define mmDIO_SOFT_RESET 0x1eed +#define mmDIO_SOFT_RESET_BASE_IDX 2 +#define mmDIG_SOFT_RESET 0x1eee +#define mmDIG_SOFT_RESET_BASE_IDX 2 +#define mmDIO_MEM_PWR_STATUS1 0x1ef0 +#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2 +#define mmDIO_CLK_CNTL2 0x1ef2 +#define mmDIO_CLK_CNTL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL3 0x1ef3 +#define mmDIO_CLK_CNTL3_BASE_IDX 2 +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00 +#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01 +#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 +#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +// base address: 0x0 +#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 +#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_CONTROL 0x1f16 +#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +// base address: 0x20 +#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c +#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_CONTROL 0x1f1e +#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd2_dispdec +// base address: 0x40 +#define mmHPD2_DC_HPD_INT_STATUS 0x1f24 +#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 +#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_CONTROL 0x1f26 +#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd3_dispdec +// base address: 0x60 +#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c +#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d +#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_CONTROL 0x1f2e +#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd4_dispdec +// base address: 0x80 +#define mmHPD4_DC_HPD_INT_STATUS 0x1f34 +#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 +#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_CONTROL 0x1f36 +#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd5_dispdec +// base address: 0xa0 +#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c +#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d +#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD5_DC_HPD_CONTROL 0x1f3e +#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40 +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1f44 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1f45 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1f46 +#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CNTL 0x1f47 +#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CNTL2 0x1f48 +#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1f49 +#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1f4a +#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_HI 0x1f4b +#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_LOW 0x1f4c +#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define mmDP_AUX0_AUX_CONTROL 0x1f50 +#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 +#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 +#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_DATA 0x1f56 +#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_DATA 0x1f57 +#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define mmDP_AUX1_AUX_CONTROL 0x1f6c +#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 +#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 +#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_DATA 0x1f72 +#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_DATA 0x1f73 +#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +// base address: 0xe0 +#define mmDP_AUX2_AUX_CONTROL 0x1f88 +#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 +#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a +#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c +#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d +#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_DATA 0x1f8e +#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_DATA 0x1f8f +#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +// base address: 0x150 +#define mmDP_AUX3_AUX_CONTROL 0x1fa4 +#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 +#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 +#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 +#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 +#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_DATA 0x1faa +#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_DATA 0x1fab +#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +// base address: 0x1c0 +#define mmDP_AUX4_AUX_CONTROL 0x1fc0 +#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 +#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 +#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 +#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 +#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_DATA 0x1fc6 +#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_DATA 0x1fc7 +#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc +#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd +#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux5_dispdec +// base address: 0x230 +#define mmDP_AUX5_AUX_CONTROL 0x1fdc +#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd +#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde +#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0 +#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1 +#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_DATA 0x1fe2 +#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX5_AUX_LS_DATA 0x1fe3 +#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux6_dispdec +// base address: 0x2a0 +#define mmDP_AUX6_AUX_CONTROL 0x1ff8 +#define mmDP_AUX6_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_SW_CONTROL 0x1ff9 +#define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_ARB_CONTROL 0x1ffa +#define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_INTERRUPT_CONTROL 0x1ffb +#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_SW_STATUS 0x1ffc +#define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX6_AUX_LS_STATUS 0x1ffd +#define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX6_AUX_SW_DATA 0x1ffe +#define mmDP_AUX6_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX6_AUX_LS_DATA 0x1fff +#define mmDP_AUX6_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0x2000 +#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_TX_CONTROL 0x2001 +#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0x2002 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0x2003 +#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_TX_STATUS 0x2004 +#define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX6_AUX_DPHY_RX_STATUS 0x2005 +#define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0x2007 +#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0x2008 +#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX6_AUX_GTC_SYNC_STATUS 0x2009 +#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define mmDIG0_DIG_FE_CNTL 0x2068 +#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_DIG_CLOCK_PATTERN 0x206b +#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_TEST_PATTERN 0x206c +#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG0_DIG_FIFO_STATUS 0x206e +#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_CONTROL 0x2071 +#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_STATUS 0x2072 +#define mmDIG0_HDMI_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079 +#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_GC 0x207b +#define mmDIG0_HDMI_GC_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_0 0x207d +#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_1 0x207e +#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_2 0x207f +#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_3 0x2080 +#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_4 0x2081 +#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_0 0x2082 +#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_1 0x2083 +#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_2 0x2084 +#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_3 0x2085 +#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG0_HDMI_DB_CONTROL 0x2088 +#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO0 0x208a +#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO1 0x208b +#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_HDR 0x208c +#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_0 0x208d +#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_1 0x208e +#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_2 0x208f +#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_3 0x2090 +#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_4 0x2091 +#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_5 0x2092 +#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_6 0x2093 +#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_7 0x2094 +#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_0 0x2096 +#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_1 0x2097 +#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_0 0x2098 +#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_1 0x2099 +#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_0 0x209a +#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_1 0x209b +#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_0 0x209c +#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_1 0x209d +#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO0 0x209e +#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO1 0x209f +#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_60958_0 0x20a0 +#define mmDIG0_AFMT_60958_0_BASE_IDX 2 +#define mmDIG0_AFMT_60958_1 0x20a1 +#define mmDIG0_AFMT_60958_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3 +#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4 +#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5 +#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6 +#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG0_AFMT_60958_2 0x20a7 +#define mmDIG0_AFMT_60958_2_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_AFMT_STATUS 0x20a9 +#define mmDIG0_AFMT_STATUS_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab +#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac +#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG0_DIG_BE_CNTL 0x20af +#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_BE_EN_CNTL 0x20b0 +#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CNTL 0x20d3 +#define mmDIG0_TMDS_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4 +#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG0_TMDS_CTL_BITS 0x20da +#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db +#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_VERSION 0x20e0 +#define mmDIG0_DIG_VERSION_BASE_IDX 2 +#define mmDIG0_DIG_LANE_ENABLE 0x20e1 +#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG0_AFMT_CNTL 0x20e6 +#define mmDIG0_AFMT_CNTL_BASE_IDX 2 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define mmDP0_DP_LINK_CNTL 0x2108 +#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP0_DP_PIXEL_FORMAT 0x2109 +#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP0_DP_MSA_COLORIMETRY 0x210a +#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP0_DP_CONFIG 0x210b +#define mmDP0_DP_CONFIG_BASE_IDX 2 +#define mmDP0_DP_VID_STREAM_CNTL 0x210c +#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_STEER_FIFO 0x210d +#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP0_DP_MSA_MISC 0x210e +#define mmDP0_DP_MSA_MISC_BASE_IDX 2 +#define mmDP0_DP_VID_TIMING 0x2110 +#define mmDP0_DP_VID_TIMING_BASE_IDX 2 +#define mmDP0_DP_VID_N 0x2111 +#define mmDP0_DP_VID_N_BASE_IDX 2 +#define mmDP0_DP_VID_M 0x2112 +#define mmDP0_DP_VID_M_BASE_IDX 2 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP0_DP_VID_MSA_VBID 0x2115 +#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CNTL 0x2117 +#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM0 0x2119 +#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM1 0x211a +#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM2 0x211b +#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c +#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d +#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_EN 0x211f +#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 +#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 +#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL 0x212b +#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL1 0x212c +#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING1 0x212d +#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING2 0x212e +#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING3 0x212f +#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING4 0x2130 +#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N 0x2131 +#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M 0x2133 +#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_TIMESTAMP 0x2135 +#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 +#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_CNTL 0x2137 +#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 +#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0 0x213a +#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1 0x213b +#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2 0x213c +#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT_UPDATE 0x213d +#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_LINK_TIMING 0x213e +#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP0_DP_MSE_MISC_CNTL 0x213f +#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 +#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 +#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 +#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c +#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d +#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e +#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f +#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL 0x2150 +#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL1 0x2151 +#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP0_DP_DSC_CNTL 0x2152 +#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL2 0x2153 +#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL3 0x2154 +#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL4 0x2155 +#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL5 0x2156 +#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL6 0x2157 +#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL7 0x2158 +#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP0_DP_DB_CNTL 0x2159 +#define mmDP0_DP_DB_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSA_VBID_MISC 0x215a +#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x400 +#define mmDIG1_DIG_FE_CNTL 0x2168 +#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_DIG_CLOCK_PATTERN 0x216b +#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_TEST_PATTERN 0x216c +#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG1_DIG_FIFO_STATUS 0x216e +#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_CONTROL 0x2171 +#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_STATUS 0x2172 +#define mmDIG1_HDMI_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179 +#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_GC 0x217b +#define mmDIG1_HDMI_GC_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_0 0x217d +#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_1 0x217e +#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_2 0x217f +#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_3 0x2180 +#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_4 0x2181 +#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_0 0x2182 +#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_1 0x2183 +#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_2 0x2184 +#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_3 0x2185 +#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG1_HDMI_DB_CONTROL 0x2188 +#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO0 0x218a +#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO1 0x218b +#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_HDR 0x218c +#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_0 0x218d +#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_1 0x218e +#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_2 0x218f +#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_3 0x2190 +#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_4 0x2191 +#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_5 0x2192 +#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_6 0x2193 +#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_7 0x2194 +#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_0 0x2196 +#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_1 0x2197 +#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_0 0x2198 +#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_1 0x2199 +#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_0 0x219a +#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_1 0x219b +#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_0 0x219c +#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_1 0x219d +#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO0 0x219e +#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO1 0x219f +#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_60958_0 0x21a0 +#define mmDIG1_AFMT_60958_0_BASE_IDX 2 +#define mmDIG1_AFMT_60958_1 0x21a1 +#define mmDIG1_AFMT_60958_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3 +#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4 +#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5 +#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6 +#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG1_AFMT_60958_2 0x21a7 +#define mmDIG1_AFMT_60958_2_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_AFMT_STATUS 0x21a9 +#define mmDIG1_AFMT_STATUS_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab +#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac +#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG1_DIG_BE_CNTL 0x21af +#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_BE_EN_CNTL 0x21b0 +#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CNTL 0x21d3 +#define mmDIG1_TMDS_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4 +#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG1_TMDS_CTL_BITS 0x21da +#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db +#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_VERSION 0x21e0 +#define mmDIG1_DIG_VERSION_BASE_IDX 2 +#define mmDIG1_DIG_LANE_ENABLE 0x21e1 +#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG1_AFMT_CNTL 0x21e6 +#define mmDIG1_AFMT_CNTL_BASE_IDX 2 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x400 +#define mmDP1_DP_LINK_CNTL 0x2208 +#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP1_DP_PIXEL_FORMAT 0x2209 +#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP1_DP_MSA_COLORIMETRY 0x220a +#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP1_DP_CONFIG 0x220b +#define mmDP1_DP_CONFIG_BASE_IDX 2 +#define mmDP1_DP_VID_STREAM_CNTL 0x220c +#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_STEER_FIFO 0x220d +#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP1_DP_MSA_MISC 0x220e +#define mmDP1_DP_MSA_MISC_BASE_IDX 2 +#define mmDP1_DP_VID_TIMING 0x2210 +#define mmDP1_DP_VID_TIMING_BASE_IDX 2 +#define mmDP1_DP_VID_N 0x2211 +#define mmDP1_DP_VID_N_BASE_IDX 2 +#define mmDP1_DP_VID_M 0x2212 +#define mmDP1_DP_VID_M_BASE_IDX 2 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP1_DP_VID_MSA_VBID 0x2215 +#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CNTL 0x2217 +#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM0 0x2219 +#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM1 0x221a +#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM2 0x221b +#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c +#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d +#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_EN 0x221f +#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 +#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 +#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL 0x222b +#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL1 0x222c +#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING1 0x222d +#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING2 0x222e +#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING3 0x222f +#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING4 0x2230 +#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N 0x2231 +#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M 0x2233 +#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_TIMESTAMP 0x2235 +#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 +#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_CNTL 0x2237 +#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 +#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0 0x223a +#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1 0x223b +#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2 0x223c +#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT_UPDATE 0x223d +#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_LINK_TIMING 0x223e +#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP1_DP_MSE_MISC_CNTL 0x223f +#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 +#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 +#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 +#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c +#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d +#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e +#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f +#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL 0x2250 +#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL1 0x2251 +#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP1_DP_DSC_CNTL 0x2252 +#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL2 0x2253 +#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL3 0x2254 +#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL4 0x2255 +#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL5 0x2256 +#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL6 0x2257 +#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL7 0x2258 +#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP1_DP_DB_CNTL 0x2259 +#define mmDP1_DP_DB_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSA_VBID_MISC 0x225a +#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x800 +#define mmDIG2_DIG_FE_CNTL 0x2268 +#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a +#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_DIG_CLOCK_PATTERN 0x226b +#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_TEST_PATTERN 0x226c +#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d +#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG2_DIG_FIFO_STATUS 0x226e +#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_CONTROL 0x2271 +#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_STATUS 0x2272 +#define mmDIG2_HDMI_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279 +#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_GC 0x227b +#define mmDIG2_HDMI_GC_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_0 0x227d +#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_1 0x227e +#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_2 0x227f +#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_3 0x2280 +#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_4 0x2281 +#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_0 0x2282 +#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_1 0x2283 +#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_2 0x2284 +#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_3 0x2285 +#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG2_HDMI_DB_CONTROL 0x2288 +#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO0 0x228a +#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO1 0x228b +#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_HDR 0x228c +#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_0 0x228d +#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_1 0x228e +#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_2 0x228f +#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_3 0x2290 +#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_4 0x2291 +#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_5 0x2292 +#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_6 0x2293 +#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_7 0x2294 +#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_0 0x2296 +#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_1 0x2297 +#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_0 0x2298 +#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_1 0x2299 +#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_0 0x229a +#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_1 0x229b +#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_0 0x229c +#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_1 0x229d +#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO0 0x229e +#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO1 0x229f +#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_60958_0 0x22a0 +#define mmDIG2_AFMT_60958_0_BASE_IDX 2 +#define mmDIG2_AFMT_60958_1 0x22a1 +#define mmDIG2_AFMT_60958_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3 +#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4 +#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5 +#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6 +#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG2_AFMT_60958_2 0x22a7 +#define mmDIG2_AFMT_60958_2_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_AFMT_STATUS 0x22a9 +#define mmDIG2_AFMT_STATUS_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab +#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac +#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG2_DIG_BE_CNTL 0x22af +#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_BE_EN_CNTL 0x22b0 +#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CNTL 0x22d3 +#define mmDIG2_TMDS_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4 +#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG2_TMDS_CTL_BITS 0x22da +#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db +#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_VERSION 0x22e0 +#define mmDIG2_DIG_VERSION_BASE_IDX 2 +#define mmDIG2_DIG_LANE_ENABLE 0x22e1 +#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG2_AFMT_CNTL 0x22e6 +#define mmDIG2_AFMT_CNTL_BASE_IDX 2 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x800 +#define mmDP2_DP_LINK_CNTL 0x2308 +#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP2_DP_PIXEL_FORMAT 0x2309 +#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP2_DP_MSA_COLORIMETRY 0x230a +#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP2_DP_CONFIG 0x230b +#define mmDP2_DP_CONFIG_BASE_IDX 2 +#define mmDP2_DP_VID_STREAM_CNTL 0x230c +#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_STEER_FIFO 0x230d +#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP2_DP_MSA_MISC 0x230e +#define mmDP2_DP_MSA_MISC_BASE_IDX 2 +#define mmDP2_DP_VID_TIMING 0x2310 +#define mmDP2_DP_VID_TIMING_BASE_IDX 2 +#define mmDP2_DP_VID_N 0x2311 +#define mmDP2_DP_VID_N_BASE_IDX 2 +#define mmDP2_DP_VID_M 0x2312 +#define mmDP2_DP_VID_M_BASE_IDX 2 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 +#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 +#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP2_DP_VID_MSA_VBID 0x2315 +#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 +#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CNTL 0x2317 +#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM0 0x2319 +#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM1 0x231a +#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM2 0x231b +#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c +#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d +#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e +#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_EN 0x231f +#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_CNTL 0x2320 +#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_RESULT 0x2321 +#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 +#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 +#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 +#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL 0x232b +#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL1 0x232c +#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING1 0x232d +#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING2 0x232e +#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING3 0x232f +#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING4 0x2330 +#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N 0x2331 +#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 +#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M 0x2333 +#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 +#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_TIMESTAMP 0x2335 +#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP2_DP_SEC_PACKET_CNTL 0x2336 +#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_CNTL 0x2337 +#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_UPDATE 0x2339 +#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0 0x233a +#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1 0x233b +#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2 0x233c +#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT_UPDATE 0x233d +#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_LINK_TIMING 0x233e +#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP2_DP_MSE_MISC_CNTL 0x233f +#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0_STATUS 0x2347 +#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1_STATUS 0x2348 +#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2_STATUS 0x2349 +#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c +#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d +#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e +#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f +#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP2_DP_MSO_CNTL 0x2350 +#define mmDP2_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSO_CNTL1 0x2351 +#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP2_DP_DSC_CNTL 0x2352 +#define mmDP2_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL2 0x2353 +#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL3 0x2354 +#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL4 0x2355 +#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL5 0x2356 +#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL6 0x2357 +#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL7 0x2358 +#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP2_DP_DB_CNTL 0x2359 +#define mmDP2_DP_DB_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSA_VBID_MISC 0x235a +#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xc00 +#define mmDIG3_DIG_FE_CNTL 0x2368 +#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a +#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_DIG_CLOCK_PATTERN 0x236b +#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_TEST_PATTERN 0x236c +#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d +#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG3_DIG_FIFO_STATUS 0x236e +#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_CONTROL 0x2371 +#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_STATUS 0x2372 +#define mmDIG3_HDMI_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379 +#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_GC 0x237b +#define mmDIG3_HDMI_GC_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_0 0x237d +#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_1 0x237e +#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_2 0x237f +#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_3 0x2380 +#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_4 0x2381 +#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_0 0x2382 +#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_1 0x2383 +#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_2 0x2384 +#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_3 0x2385 +#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG3_HDMI_DB_CONTROL 0x2388 +#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO0 0x238a +#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO1 0x238b +#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_HDR 0x238c +#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_0 0x238d +#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_1 0x238e +#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_2 0x238f +#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_3 0x2390 +#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_4 0x2391 +#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_5 0x2392 +#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_6 0x2393 +#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_7 0x2394 +#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_0 0x2396 +#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_1 0x2397 +#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_0 0x2398 +#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_1 0x2399 +#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_0 0x239a +#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_1 0x239b +#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_0 0x239c +#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_1 0x239d +#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO0 0x239e +#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO1 0x239f +#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_60958_0 0x23a0 +#define mmDIG3_AFMT_60958_0_BASE_IDX 2 +#define mmDIG3_AFMT_60958_1 0x23a1 +#define mmDIG3_AFMT_60958_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3 +#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4 +#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5 +#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6 +#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG3_AFMT_60958_2 0x23a7 +#define mmDIG3_AFMT_60958_2_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_AFMT_STATUS 0x23a9 +#define mmDIG3_AFMT_STATUS_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab +#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac +#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG3_DIG_BE_CNTL 0x23af +#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_BE_EN_CNTL 0x23b0 +#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CNTL 0x23d3 +#define mmDIG3_TMDS_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4 +#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG3_TMDS_CTL_BITS 0x23da +#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db +#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_VERSION 0x23e0 +#define mmDIG3_DIG_VERSION_BASE_IDX 2 +#define mmDIG3_DIG_LANE_ENABLE 0x23e1 +#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG3_AFMT_CNTL 0x23e6 +#define mmDIG3_AFMT_CNTL_BASE_IDX 2 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xc00 +#define mmDP3_DP_LINK_CNTL 0x2408 +#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP3_DP_PIXEL_FORMAT 0x2409 +#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP3_DP_MSA_COLORIMETRY 0x240a +#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP3_DP_CONFIG 0x240b +#define mmDP3_DP_CONFIG_BASE_IDX 2 +#define mmDP3_DP_VID_STREAM_CNTL 0x240c +#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_STEER_FIFO 0x240d +#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP3_DP_MSA_MISC 0x240e +#define mmDP3_DP_MSA_MISC_BASE_IDX 2 +#define mmDP3_DP_VID_TIMING 0x2410 +#define mmDP3_DP_VID_TIMING_BASE_IDX 2 +#define mmDP3_DP_VID_N 0x2411 +#define mmDP3_DP_VID_N_BASE_IDX 2 +#define mmDP3_DP_VID_M 0x2412 +#define mmDP3_DP_VID_M_BASE_IDX 2 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 +#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 +#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP3_DP_VID_MSA_VBID 0x2415 +#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 +#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CNTL 0x2417 +#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM0 0x2419 +#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM1 0x241a +#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM2 0x241b +#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c +#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d +#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e +#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_EN 0x241f +#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_CNTL 0x2420 +#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_RESULT 0x2421 +#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 +#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 +#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 +#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL 0x242b +#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL1 0x242c +#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING1 0x242d +#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING2 0x242e +#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING3 0x242f +#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING4 0x2430 +#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N 0x2431 +#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 +#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M 0x2433 +#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 +#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_TIMESTAMP 0x2435 +#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP3_DP_SEC_PACKET_CNTL 0x2436 +#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_CNTL 0x2437 +#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_UPDATE 0x2439 +#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0 0x243a +#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1 0x243b +#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2 0x243c +#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT_UPDATE 0x243d +#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_LINK_TIMING 0x243e +#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP3_DP_MSE_MISC_CNTL 0x243f +#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0_STATUS 0x2447 +#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1_STATUS 0x2448 +#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2_STATUS 0x2449 +#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c +#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d +#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e +#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f +#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP3_DP_MSO_CNTL 0x2450 +#define mmDP3_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSO_CNTL1 0x2451 +#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP3_DP_DSC_CNTL 0x2452 +#define mmDP3_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL2 0x2453 +#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL3 0x2454 +#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL4 0x2455 +#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL5 0x2456 +#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL6 0x2457 +#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL7 0x2458 +#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP3_DP_DB_CNTL 0x2459 +#define mmDP3_DP_DB_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSA_VBID_MISC 0x245a +#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1000 +#define mmDIG4_DIG_FE_CNTL 0x2468 +#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a +#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_DIG_CLOCK_PATTERN 0x246b +#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_TEST_PATTERN 0x246c +#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d +#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG4_DIG_FIFO_STATUS 0x246e +#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_CONTROL 0x2471 +#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_STATUS 0x2472 +#define mmDIG4_HDMI_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479 +#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_GC 0x247b +#define mmDIG4_HDMI_GC_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_0 0x247d +#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_1 0x247e +#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_2 0x247f +#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_3 0x2480 +#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_4 0x2481 +#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_0 0x2482 +#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_1 0x2483 +#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_2 0x2484 +#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_3 0x2485 +#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG4_HDMI_DB_CONTROL 0x2488 +#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO0 0x248a +#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO1 0x248b +#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_HDR 0x248c +#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_0 0x248d +#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_1 0x248e +#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_2 0x248f +#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_3 0x2490 +#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_4 0x2491 +#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_5 0x2492 +#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_6 0x2493 +#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_7 0x2494 +#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_0 0x2496 +#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_1 0x2497 +#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_0 0x2498 +#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_1 0x2499 +#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_0 0x249a +#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_1 0x249b +#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_0 0x249c +#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_1 0x249d +#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO0 0x249e +#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO1 0x249f +#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_60958_0 0x24a0 +#define mmDIG4_AFMT_60958_0_BASE_IDX 2 +#define mmDIG4_AFMT_60958_1 0x24a1 +#define mmDIG4_AFMT_60958_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3 +#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4 +#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5 +#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6 +#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG4_AFMT_60958_2 0x24a7 +#define mmDIG4_AFMT_60958_2_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_AFMT_STATUS 0x24a9 +#define mmDIG4_AFMT_STATUS_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab +#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac +#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG4_DIG_BE_CNTL 0x24af +#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_BE_EN_CNTL 0x24b0 +#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CNTL 0x24d3 +#define mmDIG4_TMDS_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4 +#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG4_TMDS_CTL_BITS 0x24da +#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db +#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_VERSION 0x24e0 +#define mmDIG4_DIG_VERSION_BASE_IDX 2 +#define mmDIG4_DIG_LANE_ENABLE 0x24e1 +#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG4_AFMT_CNTL 0x24e6 +#define mmDIG4_AFMT_CNTL_BASE_IDX 2 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1000 +#define mmDP4_DP_LINK_CNTL 0x2508 +#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP4_DP_PIXEL_FORMAT 0x2509 +#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP4_DP_MSA_COLORIMETRY 0x250a +#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP4_DP_CONFIG 0x250b +#define mmDP4_DP_CONFIG_BASE_IDX 2 +#define mmDP4_DP_VID_STREAM_CNTL 0x250c +#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_STEER_FIFO 0x250d +#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP4_DP_MSA_MISC 0x250e +#define mmDP4_DP_MSA_MISC_BASE_IDX 2 +#define mmDP4_DP_VID_TIMING 0x2510 +#define mmDP4_DP_VID_TIMING_BASE_IDX 2 +#define mmDP4_DP_VID_N 0x2511 +#define mmDP4_DP_VID_N_BASE_IDX 2 +#define mmDP4_DP_VID_M 0x2512 +#define mmDP4_DP_VID_M_BASE_IDX 2 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 +#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 +#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP4_DP_VID_MSA_VBID 0x2515 +#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 +#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CNTL 0x2517 +#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM0 0x2519 +#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM1 0x251a +#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM2 0x251b +#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c +#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d +#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e +#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_EN 0x251f +#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_CNTL 0x2520 +#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_RESULT 0x2521 +#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 +#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 +#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 +#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL 0x252b +#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL1 0x252c +#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING1 0x252d +#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING2 0x252e +#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING3 0x252f +#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING4 0x2530 +#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N 0x2531 +#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 +#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M 0x2533 +#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 +#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_TIMESTAMP 0x2535 +#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP4_DP_SEC_PACKET_CNTL 0x2536 +#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_CNTL 0x2537 +#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_UPDATE 0x2539 +#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0 0x253a +#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1 0x253b +#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2 0x253c +#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT_UPDATE 0x253d +#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_LINK_TIMING 0x253e +#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP4_DP_MSE_MISC_CNTL 0x253f +#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0_STATUS 0x2547 +#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1_STATUS 0x2548 +#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2_STATUS 0x2549 +#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c +#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d +#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e +#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f +#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP4_DP_MSO_CNTL 0x2550 +#define mmDP4_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSO_CNTL1 0x2551 +#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP4_DP_DSC_CNTL 0x2552 +#define mmDP4_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL2 0x2553 +#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL3 0x2554 +#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL4 0x2555 +#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL5 0x2556 +#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL6 0x2557 +#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL7 0x2558 +#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP4_DP_DB_CNTL 0x2559 +#define mmDP4_DP_DB_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSA_VBID_MISC 0x255a +#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig5_dispdec +// base address: 0x1400 +#define mmDIG5_DIG_FE_CNTL 0x2568 +#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a +#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG5_DIG_CLOCK_PATTERN 0x256b +#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG5_DIG_TEST_PATTERN 0x256c +#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d +#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG5_DIG_FIFO_STATUS 0x256e +#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_CONTROL 0x2571 +#define mmDIG5_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_STATUS 0x2572 +#define mmDIG5_HDMI_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574 +#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579 +#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_GC 0x257b +#define mmDIG5_HDMI_GC_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_0 0x257d +#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_1 0x257e +#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_2 0x257f +#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_3 0x2580 +#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_4 0x2581 +#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_0 0x2582 +#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_1 0x2583 +#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_2 0x2584 +#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_3 0x2585 +#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG5_HDMI_DB_CONTROL 0x2588 +#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_MPEG_INFO0 0x258a +#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG5_AFMT_MPEG_INFO1 0x258b +#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_HDR 0x258c +#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_0 0x258d +#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_1 0x258e +#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_2 0x258f +#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_3 0x2590 +#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_4 0x2591 +#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_5 0x2592 +#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_6 0x2593 +#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_7 0x2594 +#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_32_0 0x2596 +#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_32_1 0x2597 +#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_44_0 0x2598 +#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_44_1 0x2599 +#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_48_0 0x259a +#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_48_1 0x259b +#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_STATUS_0 0x259c +#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_STATUS_1 0x259d +#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_INFO0 0x259e +#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_INFO1 0x259f +#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG5_AFMT_60958_0 0x25a0 +#define mmDIG5_AFMT_60958_0_BASE_IDX 2 +#define mmDIG5_AFMT_60958_1 0x25a1 +#define mmDIG5_AFMT_60958_1_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3 +#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4 +#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5 +#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6 +#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG5_AFMT_60958_2 0x25a7 +#define mmDIG5_AFMT_60958_2_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG5_AFMT_STATUS 0x25a9 +#define mmDIG5_AFMT_STATUS_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab +#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac +#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG5_DIG_BE_CNTL 0x25af +#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_BE_EN_CNTL 0x25b0 +#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CNTL 0x25d3 +#define mmDIG5_TMDS_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4 +#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5 +#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG5_TMDS_CTL_BITS 0x25da +#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db +#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_VERSION 0x25e0 +#define mmDIG5_DIG_VERSION_BASE_IDX 2 +#define mmDIG5_DIG_LANE_ENABLE 0x25e1 +#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG5_AFMT_CNTL 0x25e6 +#define mmDIG5_AFMT_CNTL_BASE_IDX 2 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp5_dispdec +// base address: 0x1400 +#define mmDP5_DP_LINK_CNTL 0x2608 +#define mmDP5_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP5_DP_PIXEL_FORMAT 0x2609 +#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP5_DP_MSA_COLORIMETRY 0x260a +#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP5_DP_CONFIG 0x260b +#define mmDP5_DP_CONFIG_BASE_IDX 2 +#define mmDP5_DP_VID_STREAM_CNTL 0x260c +#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP5_DP_STEER_FIFO 0x260d +#define mmDP5_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP5_DP_MSA_MISC 0x260e +#define mmDP5_DP_MSA_MISC_BASE_IDX 2 +#define mmDP5_DP_VID_TIMING 0x2610 +#define mmDP5_DP_VID_TIMING_BASE_IDX 2 +#define mmDP5_DP_VID_N 0x2611 +#define mmDP5_DP_VID_N_BASE_IDX 2 +#define mmDP5_DP_VID_M 0x2612 +#define mmDP5_DP_VID_M_BASE_IDX 2 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613 +#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614 +#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP5_DP_VID_MSA_VBID 0x2615 +#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616 +#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CNTL 0x2617 +#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM0 0x2619 +#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM1 0x261a +#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM2 0x261b +#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c +#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d +#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e +#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_EN 0x261f +#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_CNTL 0x2620 +#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_RESULT 0x2621 +#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622 +#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623 +#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624 +#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL 0x262b +#define mmDP5_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL1 0x262c +#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING1 0x262d +#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING2 0x262e +#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING3 0x262f +#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING4 0x2630 +#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_N 0x2631 +#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632 +#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_M 0x2633 +#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634 +#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP5_DP_SEC_TIMESTAMP 0x2635 +#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP5_DP_SEC_PACKET_CNTL 0x2636 +#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSE_RATE_CNTL 0x2637 +#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSE_RATE_UPDATE 0x2639 +#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT0 0x263a +#define mmDP5_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT1 0x263b +#define mmDP5_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT2 0x263c +#define mmDP5_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT_UPDATE 0x263d +#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP5_DP_MSE_LINK_TIMING 0x263e +#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP5_DP_MSE_MISC_CNTL 0x263f +#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644 +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645 +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT0_STATUS 0x2647 +#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT1_STATUS 0x2648 +#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT2_STATUS 0x2649 +#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c +#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d +#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e +#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f +#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP5_DP_MSO_CNTL 0x2650 +#define mmDP5_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSO_CNTL1 0x2651 +#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP5_DP_DSC_CNTL 0x2652 +#define mmDP5_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL2 0x2653 +#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL3 0x2654 +#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL4 0x2655 +#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL5 0x2656 +#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL6 0x2657 +#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL7 0x2658 +#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP5_DP_DB_CNTL 0x2659 +#define mmDP5_DP_DB_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSA_VBID_MISC 0x265a +#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig6_dispdec +// base address: 0x1800 +#define mmDIG6_DIG_FE_CNTL 0x2668 +#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x2669 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x266a +#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG6_DIG_CLOCK_PATTERN 0x266b +#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG6_DIG_TEST_PATTERN 0x266c +#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x266d +#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG6_DIG_FIFO_STATUS 0x266e +#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_CONTROL 0x2671 +#define mmDIG6_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_STATUS 0x2672 +#define mmDIG6_HDMI_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x2673 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x2674 +#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x2675 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x2676 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x2677 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x2678 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x2679 +#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_GC 0x267b +#define mmDIG6_HDMI_GC_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x267c +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_0 0x267d +#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_1 0x267e +#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_2 0x267f +#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_3 0x2680 +#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_4 0x2681 +#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_0 0x2682 +#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_1 0x2683 +#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_2 0x2684 +#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_3 0x2685 +#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0x2686 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0x2687 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG6_HDMI_DB_CONTROL 0x2688 +#define mmDIG6_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_MPEG_INFO0 0x268a +#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG6_AFMT_MPEG_INFO1 0x268b +#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_HDR 0x268c +#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_0 0x268d +#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_1 0x268e +#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_2 0x268f +#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_3 0x2690 +#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_4 0x2691 +#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_5 0x2692 +#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_6 0x2693 +#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_7 0x2694 +#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x2695 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_32_0 0x2696 +#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_32_1 0x2697 +#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_44_0 0x2698 +#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_44_1 0x2699 +#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_48_0 0x269a +#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_48_1 0x269b +#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_STATUS_0 0x269c +#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_STATUS_1 0x269d +#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_INFO0 0x269e +#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_INFO1 0x269f +#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG6_AFMT_60958_0 0x26a0 +#define mmDIG6_AFMT_60958_0_BASE_IDX 2 +#define mmDIG6_AFMT_60958_1 0x26a1 +#define mmDIG6_AFMT_60958_1_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x26a2 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL0 0x26a3 +#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL1 0x26a4 +#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL2 0x26a5 +#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL3 0x26a6 +#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG6_AFMT_60958_2 0x26a7 +#define mmDIG6_AFMT_60958_2_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x26a8 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG6_AFMT_STATUS 0x26a9 +#define mmDIG6_AFMT_STATUS_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x26aa +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x26ab +#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x26ac +#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x26ad +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG6_DIG_BE_CNTL 0x26af +#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_BE_EN_CNTL 0x26b0 +#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CNTL 0x26d3 +#define mmDIG6_TMDS_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CONTROL_CHAR 0x26d4 +#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x26d5 +#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x26d6 +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x26d7 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x26d8 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG6_TMDS_CTL_BITS 0x26da +#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x26db +#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x26dd +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x26de +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_VERSION 0x26e0 +#define mmDIG6_DIG_VERSION_BASE_IDX 2 +#define mmDIG6_DIG_LANE_ENABLE 0x26e1 +#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG6_AFMT_CNTL 0x26e6 +#define mmDIG6_AFMT_CNTL_BASE_IDX 2 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL1 0x26e7 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp6_dispdec +// base address: 0x1800 +#define mmDP6_DP_LINK_CNTL 0x2708 +#define mmDP6_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP6_DP_PIXEL_FORMAT 0x2709 +#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP6_DP_MSA_COLORIMETRY 0x270a +#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP6_DP_CONFIG 0x270b +#define mmDP6_DP_CONFIG_BASE_IDX 2 +#define mmDP6_DP_VID_STREAM_CNTL 0x270c +#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP6_DP_STEER_FIFO 0x270d +#define mmDP6_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP6_DP_MSA_MISC 0x270e +#define mmDP6_DP_MSA_MISC_BASE_IDX 2 +#define mmDP6_DP_VID_TIMING 0x2710 +#define mmDP6_DP_VID_TIMING_BASE_IDX 2 +#define mmDP6_DP_VID_N 0x2711 +#define mmDP6_DP_VID_N_BASE_IDX 2 +#define mmDP6_DP_VID_M 0x2712 +#define mmDP6_DP_VID_M_BASE_IDX 2 +#define mmDP6_DP_LINK_FRAMING_CNTL 0x2713 +#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP6_DP_HBR2_EYE_PATTERN 0x2714 +#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP6_DP_VID_MSA_VBID 0x2715 +#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x2716 +#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CNTL 0x2717 +#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x2718 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM0 0x2719 +#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM1 0x271a +#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM2 0x271b +#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x271c +#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x271d +#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_SCRAM_CNTL 0x271e +#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_EN 0x271f +#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_CNTL 0x2720 +#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_RESULT 0x2721 +#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x2722 +#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x2723 +#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP6_DP_DPHY_FAST_TRAINING 0x2724 +#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x2725 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL 0x272b +#define mmDP6_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL1 0x272c +#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING1 0x272d +#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING2 0x272e +#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING3 0x272f +#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING4 0x2730 +#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_N 0x2731 +#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_N_READBACK 0x2732 +#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_M 0x2733 +#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_M_READBACK 0x2734 +#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP6_DP_SEC_TIMESTAMP 0x2735 +#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP6_DP_SEC_PACKET_CNTL 0x2736 +#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSE_RATE_CNTL 0x2737 +#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSE_RATE_UPDATE 0x2739 +#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT0 0x273a +#define mmDP6_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT1 0x273b +#define mmDP6_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT2 0x273c +#define mmDP6_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT_UPDATE 0x273d +#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP6_DP_MSE_LINK_TIMING 0x273e +#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP6_DP_MSE_MISC_CNTL 0x273f +#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x2744 +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x2745 +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT0_STATUS 0x2747 +#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT1_STATUS 0x2748 +#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT2_STATUS 0x2749 +#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSA_TIMING_PARAM1 0x274c +#define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP6_DP_MSA_TIMING_PARAM2 0x274d +#define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP6_DP_MSA_TIMING_PARAM3 0x274e +#define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP6_DP_MSA_TIMING_PARAM4 0x274f +#define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP6_DP_MSO_CNTL 0x2750 +#define mmDP6_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSO_CNTL1 0x2751 +#define mmDP6_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP6_DP_DSC_CNTL 0x2752 +#define mmDP6_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL2 0x2753 +#define mmDP6_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL3 0x2754 +#define mmDP6_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL4 0x2755 +#define mmDP6_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL5 0x2756 +#define mmDP6_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL6 0x2757 +#define mmDP6_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL7 0x2758 +#define mmDP6_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP6_DP_DB_CNTL 0x2759 +#define mmDP6_DP_DB_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSA_VBID_MISC 0x275a +#define mmDP6_DP_MSA_VBID_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +// base address: 0x0 +#define mmDC_GENERICA 0x2868 +#define mmDC_GENERICA_BASE_IDX 2 +#define mmDC_GENERICB 0x2869 +#define mmDC_GENERICB_BASE_IDX 2 +#define mmDC_REF_CLK_CNTL 0x286b +#define mmDC_REF_CLK_CNTL_BASE_IDX 2 +#define mmDC_GPIO_DEBUG 0x286c +#define mmDC_GPIO_DEBUG_BASE_IDX 2 +#define mmUNIPHYA_LINK_CNTL 0x286d +#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYB_LINK_CNTL 0x286f +#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYC_LINK_CNTL 0x2871 +#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYD_LINK_CNTL 0x2873 +#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYE_LINK_CNTL 0x2875 +#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYF_LINK_CNTL 0x2877 +#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 +#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYG_LINK_CNTL 0x2879 +#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x287a +#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmDCIO_WRCMD_DELAY 0x287e +#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_DVODATA_CONFIG 0x2882 +#define mmDC_DVODATA_CONFIG_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_CNTL 0x2883 +#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_STATE 0x2884 +#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 +#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY1 0x2886 +#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY2 0x2887 +#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 +#define mmBL_PWM_CNTL 0x2888 +#define mmBL_PWM_CNTL_BASE_IDX 2 +#define mmBL_PWM_CNTL2 0x2889 +#define mmBL_PWM_CNTL2_BASE_IDX 2 +#define mmBL_PWM_PERIOD_CNTL 0x288a +#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define mmBL_PWM_GRP1_REG_LOCK 0x288b +#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_CLOCK_CNTL 0x2895 +#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 +#define mmDIO_OTG_EXT_VSYNC_CNTL 0x2898 +#define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX 2 +#define mmDCIO_SOFT_RESET 0x289e +#define mmDCIO_SOFT_RESET_BASE_IDX 2 +#define mmDCIO_DPHY_SEL 0x289f +#define mmDCIO_DPHY_SEL_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKA 0x28a0 +#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKB 0x28a1 +#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PERIOD 0x28a2 +#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2 +#define mmAUXP_IMPCAL 0x28a3 +#define mmAUXP_IMPCAL_BASE_IDX 2 +#define mmAUXN_IMPCAL 0x28a4 +#define mmAUXN_IMPCAL_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL 0x28a5 +#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_AB 0x28a6 +#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKC 0x28a7 +#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKD 0x28a8 +#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL_CD 0x28a9 +#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_CD 0x28aa +#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKE 0x28ab +#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKF 0x28ac +#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL_EF 0x28ad +#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_EF 0x28ae +#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2 +#define mmDCIO_DPCS_TX_INTERRUPT 0x28b3 +#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2 +#define mmDCIO_DPCS_RX_INTERRUPT 0x28b4 +#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2 +#define mmDCIO_SEMAPHORE0 0x28b5 +#define mmDCIO_SEMAPHORE0_BASE_IDX 2 +#define mmDCIO_SEMAPHORE1 0x28b6 +#define mmDCIO_SEMAPHORE1_BASE_IDX 2 +#define mmDCIO_SEMAPHORE2 0x28b7 +#define mmDCIO_SEMAPHORE2_BASE_IDX 2 +#define mmDCIO_SEMAPHORE3 0x28b8 +#define mmDCIO_SEMAPHORE3_BASE_IDX 2 +#define mmDCIO_SEMAPHORE4 0x28b9 +#define mmDCIO_SEMAPHORE4_BASE_IDX 2 +#define mmDCIO_SEMAPHORE5 0x28ba +#define mmDCIO_SEMAPHORE5_BASE_IDX 2 +#define mmDCIO_SEMAPHORE6 0x28bb +#define mmDCIO_SEMAPHORE6_BASE_IDX 2 +#define mmDCIO_SEMAPHORE7 0x28bc +#define mmDCIO_SEMAPHORE7_BASE_IDX 2 +#define mmDCIO_USBC_FLIP_EN_SEL 0x28bd +#define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x28c8 +#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_A 0x28c9 +#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_EN 0x28ca +#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_Y 0x28cb +#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_MASK 0x28cc +#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_A 0x28cd +#define mmDC_GPIO_DVODATA_A_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_EN 0x28ce +#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_Y 0x28cf +#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC1_MASK 0x28d0 +#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC1_A 0x28d1 +#define mmDC_GPIO_DDC1_A_BASE_IDX 2 +#define mmDC_GPIO_DDC1_EN 0x28d2 +#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC1_Y 0x28d3 +#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC2_MASK 0x28d4 +#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC2_A 0x28d5 +#define mmDC_GPIO_DDC2_A_BASE_IDX 2 +#define mmDC_GPIO_DDC2_EN 0x28d6 +#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC2_Y 0x28d7 +#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC3_MASK 0x28d8 +#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC3_A 0x28d9 +#define mmDC_GPIO_DDC3_A_BASE_IDX 2 +#define mmDC_GPIO_DDC3_EN 0x28da +#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC3_Y 0x28db +#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC4_MASK 0x28dc +#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC4_A 0x28dd +#define mmDC_GPIO_DDC4_A_BASE_IDX 2 +#define mmDC_GPIO_DDC4_EN 0x28de +#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC4_Y 0x28df +#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC5_MASK 0x28e0 +#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC5_A 0x28e1 +#define mmDC_GPIO_DDC5_A_BASE_IDX 2 +#define mmDC_GPIO_DDC5_EN 0x28e2 +#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC5_Y 0x28e3 +#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC6_MASK 0x28e4 +#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC6_A 0x28e5 +#define mmDC_GPIO_DDC6_A_BASE_IDX 2 +#define mmDC_GPIO_DDC6_EN 0x28e6 +#define mmDC_GPIO_DDC6_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC6_Y 0x28e7 +#define mmDC_GPIO_DDC6_Y_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_MASK 0x28e8 +#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_A 0x28e9 +#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_EN 0x28ea +#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_Y 0x28eb +#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_MASK 0x28ec +#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_A 0x28ed +#define mmDC_GPIO_SYNCA_A_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_EN 0x28ee +#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_Y 0x28ef +#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2 +#define mmDC_GPIO_GENLK_MASK 0x28f0 +#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENLK_A 0x28f1 +#define mmDC_GPIO_GENLK_A_BASE_IDX 2 +#define mmDC_GPIO_GENLK_EN 0x28f2 +#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 +#define mmDC_GPIO_GENLK_Y 0x28f3 +#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 +#define mmDC_GPIO_HPD_MASK 0x28f4 +#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 +#define mmDC_GPIO_HPD_A 0x28f5 +#define mmDC_GPIO_HPD_A_BASE_IDX 2 +#define mmDC_GPIO_HPD_EN 0x28f6 +#define mmDC_GPIO_HPD_EN_BASE_IDX 2 +#define mmDC_GPIO_HPD_Y 0x28f7 +#define mmDC_GPIO_HPD_Y_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 +#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_A 0x28f9 +#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_EN 0x28fa +#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_Y 0x28fb +#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc +#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd +#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define mmPHY_AUX_CNTL 0x28ff +#define mmPHY_AUX_CNTL_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_MASK 0x2900 +#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_A 0x2901 +#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_EN 0x2902 +#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_Y 0x2903 +#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x2904 +#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2 +#define mmDVO_STRENGTH_CONTROL 0x2905 +#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2 +#define mmDVO_VREF_CONTROL 0x2906 +#define mmDVO_VREF_CONTROL_BASE_IDX 2 +#define mmDVO_SKEW_ADJUST 0x2907 +#define mmDVO_SKEW_ADJUST_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_MASK 0x2910 +#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_A 0x2911 +#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_EN 0x2912 +#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_Y 0x2913 +#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x2914 +#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2 +#define mmDC_GPIO_TX12_EN 0x2915 +#define mmDC_GPIO_TX12_EN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_0 0x2916 +#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_1 0x2917 +#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_2 0x2918 +#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define mmDC_GPIO_RXEN 0x2919 +#define mmDC_GPIO_RXEN_BASE_IDX 2 +#define mmDC_GPIO_PULLUPEN 0x291a +#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dac_dispdec +// base address: 0x0 +#define mmDAC_MACRO_CNTL_RESERVED0 0x2920 +#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED1 0x2921 +#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED2 0x2922 +#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED3 0x2923 +#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec +// base address: 0x0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2962 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2963 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x2964 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x2965 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x2966 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x2967 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x2968 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x2969 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x296a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x296b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x296c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x296d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x296e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x296f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2970 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2971 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2972 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2973 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x2974 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x2975 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x2976 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x2977 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x2978 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x2979 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x297a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x297b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x297c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x297d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x297e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x297f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2980 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2981 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2982 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2983 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x2984 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x2985 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x2986 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x2987 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x2988 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x2989 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x298a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x298b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x298c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x298d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x298e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x298f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x2990 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x2991 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x2992 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x2993 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x2994 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x2995 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x2996 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x2997 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x2998 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x2999 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x299a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x299b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x299c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x299d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x299e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x299f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x29a0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x29a1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x29a2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x29a3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x29a4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x29a5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x29a6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x29a7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x29a8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x29a9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x29aa +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x29ab +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x29ac +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x29ad +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x29ae +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x29af +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x29b0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x29b1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x29b2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x29b3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x29b4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x29b5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x29b6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x29b7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x29b8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x29b9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x29ba +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x29bb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x29bc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x29bd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x29be +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x29bf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x29c0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x29c1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x29c2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x29c3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x29c4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x29c5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x29c6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x29c7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x2928 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x2929 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x292a +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x292b +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x292c +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x292d +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x292e +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x292f +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2930 +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2931 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2932 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2933 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x2934 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x2935 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x2936 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x2937 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x2948 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x2949 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x294a +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x294b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x294c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x294d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x294e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x294f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2950 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2951 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2952 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2953 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x2954 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x2955 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x2956 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x2957 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x2958 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x2959 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x295a +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x295b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x295c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x295d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x295e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x295f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2960 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2961 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2962 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2963 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x2964 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x2965 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x2966 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x2967 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x2968 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x2969 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x296a +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x296b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x296c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x296d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x296e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x296f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2970 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2971 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2972 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2973 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x2974 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x2975 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x2976 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x2977 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x2978 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x2979 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x297a +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x297b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x297c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x297d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x297e +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x297f +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2980 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2981 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2982 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2983 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x2984 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x2985 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x2986 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x2987 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x2988 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x2989 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x298a +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x298b +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x298c +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x298d +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x298e +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x298f +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x2991 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x2992 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x2993 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x2994 +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x29c6 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x29c7 +#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +// base address: 0x360 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2a3a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2a3b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2a3c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2a3d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2a3e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2a3f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2a40 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2a41 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2a42 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2a43 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x2a44 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x2a45 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x2a46 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x2a47 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x2a48 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x2a49 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2a4a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2a4b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2a4c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2a4d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2a4e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2a4f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2a50 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2a51 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2a52 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2a53 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x2a54 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x2a55 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x2a56 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x2a57 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x2a58 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x2a59 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2a5a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2a5b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2a5c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2a5d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2a5e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2a5f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2a60 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2a61 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2a62 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2a63 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x2a64 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x2a65 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x2a66 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x2a67 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x2a68 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x2a69 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2a6a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2a6b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2a6c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2a6d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2a6e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2a6f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2a70 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2a71 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2a72 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2a73 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x2a74 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x2a75 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x2a76 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x2a77 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x2a78 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x2a79 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2a7a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2a7b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2a7c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2a7d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2a7e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2a7f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2a80 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2a81 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2a82 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2a83 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x2a84 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x2a85 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x2a86 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x2a87 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x2a88 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x2a89 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2a8a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2a8b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2a8c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2a8d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2a8e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2a8f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2a90 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2a91 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2a92 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2a93 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x2a94 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x2a95 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x2a96 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x2a97 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x2a98 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x2a99 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x2a9a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x2a9b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x2a9c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x2a9d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x2a9e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x2a9f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec +// base address: 0x360 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2a00 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2a01 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2a02 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2a03 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x2a04 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x2a05 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x2a06 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x2a07 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x2a08 +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x2a09 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2a0a +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2a0b +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2a0c +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2a0d +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2a0e +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2a0f +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec +// base address: 0x360 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2a20 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2a21 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2a22 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2a23 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x2a24 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x2a25 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x2a26 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x2a27 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x2a28 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x2a29 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2a2a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2a2b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2a2c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2a2d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2a2e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2a2f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2a30 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2a31 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2a32 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2a33 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x2a34 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x2a35 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x2a36 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x2a37 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x2a38 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x2a39 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2a3a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2a3b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2a3c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2a3d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2a3e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2a3f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2a40 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2a41 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2a42 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2a43 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x2a44 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x2a45 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x2a46 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x2a47 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x2a48 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x2a49 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2a4a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2a4b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2a4c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2a4d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2a4e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2a4f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2a50 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2a51 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2a52 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2a53 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x2a54 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x2a55 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x2a56 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x2a57 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x2a58 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x2a59 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2a5a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2a5b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2a5c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2a5d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2a5e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2a5f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec +// base address: 0x360 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2a60 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2a61 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2a62 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2a63 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x2a64 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x2a65 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x2a66 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x2a67 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x2a69 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2a6a +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2a6b +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2a6c +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x2a9e +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x2a9f +#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +// base address: 0x6c0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2b12 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2b13 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x2b14 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x2b15 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x2b16 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x2b17 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x2b18 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x2b19 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2b1a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2b1b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2b1c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2b1d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2b1e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2b1f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2b20 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2b21 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2b22 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2b23 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x2b24 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x2b25 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x2b26 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x2b27 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x2b28 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x2b29 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2b2a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2b2b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2b2c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2b2d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2b2e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2b2f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2b30 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2b31 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2b32 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2b33 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x2b34 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x2b35 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x2b36 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x2b37 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x2b38 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x2b39 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2b3a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2b3b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2b3c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2b3d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2b3e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2b3f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2b40 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2b41 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2b42 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2b43 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x2b44 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x2b45 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x2b46 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x2b47 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x2b48 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x2b49 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2b4a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2b4b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2b4c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2b4d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2b4e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2b4f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2b50 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2b51 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2b52 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2b53 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x2b54 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x2b55 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x2b56 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x2b57 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x2b58 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x2b59 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2b5a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2b5b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2b5c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2b5d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2b5e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2b5f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2b60 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2b61 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2b62 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2b63 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x2b64 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x2b65 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x2b66 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x2b67 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x2b68 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x2b69 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2b6a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2b6b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2b6c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2b6d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2b6e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2b6f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2b70 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2b71 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2b72 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2b73 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x2b74 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x2b75 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x2b76 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x2b77 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec +// base address: 0x6c0 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x2ad8 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x2ad9 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x2ada +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x2adb +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x2adc +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x2add +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x2ade +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x2adf +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x2ae0 +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x2ae1 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x2ae2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x2ae3 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x2ae4 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x2ae5 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x2ae6 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x2ae7 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec +// base address: 0x6c0 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x2af8 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x2af9 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2afa +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x2afb +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x2afc +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x2afd +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x2afe +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x2aff +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x2b00 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x2b01 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x2b02 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x2b03 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x2b04 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x2b05 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x2b06 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x2b07 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x2b08 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x2b09 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2b0a +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2b0b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2b0c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2b0d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2b0e +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2b0f +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2b10 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2b11 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2b12 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2b13 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x2b14 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x2b15 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x2b16 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x2b17 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x2b18 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x2b19 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2b1a +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2b1b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2b1c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2b1d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2b1e +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2b1f +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2b20 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2b21 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2b22 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2b23 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x2b24 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x2b25 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x2b26 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x2b27 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x2b28 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x2b29 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2b2a +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2b2b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2b2c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2b2d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2b2e +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2b2f +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2b30 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2b31 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2b32 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2b33 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x2b34 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x2b35 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x2b36 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x2b37 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec +// base address: 0x6c0 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x2b38 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x2b39 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2b3a +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2b3b +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2b3c +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2b3d +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2b3e +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2b3f +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2b41 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2b42 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2b43 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x2b44 +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x2b76 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x2b77 +#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +// base address: 0xa20 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x2bea +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x2beb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x2bec +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x2bed +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x2bee +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x2bef +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x2bf0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x2bf1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x2bf2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x2bf3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x2bf4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x2bf5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x2bf6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x2bf7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x2bf8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x2bf9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x2bfa +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x2bfb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x2bfc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x2bfd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x2bfe +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x2bff +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x2c00 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x2c01 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x2c02 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x2c03 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x2c04 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x2c05 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x2c06 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x2c07 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x2c08 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x2c09 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x2c0a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x2c0b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x2c0c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x2c0d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x2c0e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x2c0f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x2c10 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x2c11 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x2c12 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x2c13 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x2c14 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x2c15 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x2c16 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x2c17 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x2c18 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x2c19 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2c1a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2c1b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2c1c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2c1d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2c1e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2c1f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2c20 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2c21 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2c22 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2c23 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x2c24 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x2c25 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x2c26 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x2c27 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x2c28 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x2c29 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2c2a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2c2b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2c2c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2c2d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2c2e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2c2f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2c30 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2c31 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2c32 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2c33 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x2c34 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x2c35 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x2c36 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x2c37 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x2c38 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x2c39 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2c3a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2c3b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2c3c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2c3d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2c3e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2c3f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2c40 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2c41 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2c42 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2c43 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x2c44 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x2c45 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x2c46 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x2c47 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x2c48 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x2c49 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2c4a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2c4b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2c4c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2c4d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2c4e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2c4f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec +// base address: 0xa20 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2bb0 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2bb1 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2bb2 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2bb3 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x2bb4 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x2bb5 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x2bb6 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x2bb7 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x2bb8 +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x2bb9 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x2bba +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x2bbb +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x2bbc +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x2bbd +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x2bbe +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x2bbf +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec +// base address: 0xa20 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x2bd0 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x2bd1 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2bd2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x2bd3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x2bd4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x2bd5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x2bd6 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x2bd7 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x2bd8 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x2bd9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x2bda +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x2bdb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x2bdc +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x2bdd +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x2bde +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x2bdf +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x2be0 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x2be1 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2be2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x2be3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x2be4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x2be5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x2be6 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x2be7 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x2be8 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x2be9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x2bea +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x2beb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x2bec +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x2bed +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x2bee +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x2bef +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x2bf0 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x2bf1 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2bf2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x2bf3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x2bf4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x2bf5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x2bf6 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x2bf7 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x2bf8 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x2bf9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x2bfa +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x2bfb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x2bfc +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x2bfd +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x2bfe +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x2bff +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x2c00 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x2c01 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2c02 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x2c03 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x2c04 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x2c05 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x2c06 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x2c07 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x2c08 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x2c09 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x2c0a +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x2c0b +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x2c0c +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x2c0d +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x2c0e +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x2c0f +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec +// base address: 0xa20 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x2c10 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x2c11 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x2c12 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x2c13 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x2c14 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x2c15 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x2c16 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x2c17 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x2c19 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2c1a +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2c1b +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2c1c +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x2c4e +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x2c4f +#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_zcal_dispdec +// base address: 0x0 +#define mmZCAL_MACRO_CNTL_RESERVED0 0x2fe8 +#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED1 0x2fe9 +#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED2 0x2fea +#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED3 0x2feb +#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED4 0x2fec +#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2 + + +// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec +// base address: 0x0 +#define mmCOMP_EN_CTL 0x2fe8 +#define mmCOMP_EN_CTL_BASE_IDX 2 +#define mmCOMP_EN_DFX 0x2fe9 +#define mmCOMP_EN_DFX_BASE_IDX 2 +#define mmZCAL_FUSES 0x2fea +#define mmZCAL_FUSES_BASE_IDX 2 + + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// base address: 0x0 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h new file mode 100644 index 000000000000..1e98ce86ed19 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h @@ -0,0 +1,54316 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_1_0_SH_MASK_HEADER +#define _dcn_1_0_SH_MASK_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//AZCONTROLLER0_GLOBAL_CAPABILITIES +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L +#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L +//AZCONTROLLER0_MINOR_VERSION +#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK 0xFFL +//AZCONTROLLER0_MAJOR_VERSION +#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK 0xFFL +//AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//AZCONTROLLER0_GLOBAL_CONTROL +#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x00000001L +#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x00000002L +#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000100L +//AZCONTROLLER0_WAKE_ENABLE +#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x0001L +//AZCONTROLLER0_STATE_CHANGE_STATUS +#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x0001L +//AZCONTROLLER0_GLOBAL_STATUS +#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK 0x00000002L +//AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFFL +//AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY +#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFFL +//AZCONTROLLER0_INTERRUPT_CONTROL +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x00000002L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x00000004L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x00000020L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x00000040L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x00000080L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x00000100L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x00000200L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x00000400L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x00000800L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x00001000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x00002000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x00004000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x00008000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000L +#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000L +//AZCONTROLLER0_INTERRUPT_STATUS +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x00000001L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x00000002L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x00000004L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x00000008L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x00000010L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x00000020L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x00000040L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x00000080L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x00000100L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x00000200L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x00000400L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x00000800L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x00001000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x00002000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x00004000L +#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x00008000L +#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000L +#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000L +//AZCONTROLLER0_WALL_CLOCK_COUNTER +#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xFFFFFFFFL +//AZCONTROLLER0_STREAM_SYNCHRONIZATION +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x00000001L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x00000002L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x00000004L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x00000008L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x00000010L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x00000020L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x00000040L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x00000080L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x00000100L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x00000200L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x00000400L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x00000800L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x00001000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x00002000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x00004000L +#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x00008000L +//AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_CORB_WRITE_POINTER +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER0_CORB_READ_POINTER +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_CORB_CONTROL +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER0_CORB_STATUS +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER0_CORB_SIZE +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_RIRB_WRITE_POINTER +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER0_RIRB_CONTROL +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER0_RIRB_STATUS +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER0_RIRB_SIZE +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +//CRTC8_IDX +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL +//GENFC_WT +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L +//GENS1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1__NO_DISPLAY_MASK 0x01L +#define GENS1__VGA_VSTATUS_MASK 0x08L +#define GENS1__PIXEL_READ_BACK_MASK 0x30L +//ATTRDW +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDW__ATTR_DATA_MASK 0xFFL +//ATTRX +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRX__ATTR_IDX_MASK 0x1FL +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L +//ATTRDR +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xFFL +//GENMO_WT +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_WT__VGA_RAM_EN_MASK 0x02L +#define GENMO_WT__VGA_CKSEL_MASK 0x0CL +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L +//GENS0 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS0__SENSE_SWITCH_MASK 0x10L +#define GENS0__CRT_INTR_MASK 0x80L +//GENENB +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENENB__BLK_IO_BASE_MASK 0xFFL +//SEQ8_IDX +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x07L +//SEQ8_DATA +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL +//DAC_MASK +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xFFL +//DAC_R_INDEX +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL +//DAC_W_INDEX +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL +//DAC_DATA +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_DATA__DAC_DATA_MASK 0x3FL +//GENFC_RD +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L +//GENMO_RD +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L +#define GENMO_RD__VGA_RAM_EN_MASK 0x02L +#define GENMO_RD__VGA_CKSEL_MASK 0x0CL +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L +//GRPH8_IDX +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL +//GRPH8_DATA +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL +//CRTC8_IDX_1 +#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL +//CRTC8_DATA_1 +#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 +#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL +//GENFC_WT_1 +#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L +//GENS1_1 +#define GENS1_1__NO_DISPLAY__SHIFT 0x0 +#define GENS1_1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 +#define GENS1_1__NO_DISPLAY_MASK 0x01L +#define GENS1_1__VGA_VSTATUS_MASK 0x08L +#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//CORB_WRITE_POINTER +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//CORB_READ_POINTER +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//CORB_CONTROL +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//CORB_STATUS +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//CORB_SIZE +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//RIRB_LOWER_BASE_ADDRESS +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//RIRB_UPPER_BASE_ADDRESS +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//RIRB_WRITE_POINTER +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//RESPONSE_INTERRUPT_COUNT +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//RIRB_CONTROL +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//RIRB_STATUS +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//RIRB_SIZE +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//IMMEDIATE_COMMAND_STATUS +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//DMA_POSITION_LOWER_BASE_ADDRESS +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//DMA_POSITION_UPPER_BASE_ADDRESS +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//WALL_CLOCK_COUNTER_ALIAS +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000FFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//REFCLK_CNTL +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L +//MIPI_CLK_CNTL +#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE__SHIFT 0x0 +#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE__SHIFT 0x1 +#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE__SHIFT 0x2 +#define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE_MASK 0x00000001L +#define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE_MASK 0x00000002L +#define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE_MASK 0x00000004L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +//DSICLK_CGTT_BLK_CTRL_REG +#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT 0x0 +#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CBUS_WRCMD_DELAY +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//SYMCLKG_CLOCK_ENABLE +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x00000700L +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x00000100L +//AOMCLK0_CNTL +#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT 0x0 +#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK 0x00000001L +//AOMCLK1_CNTL +#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT 0x0 +#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK 0x00000001L +//AOMCLK2_CNTL +#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT 0x0 +#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK 0x00000001L +//DCCG_AUDIO_DTO2_PHASE +#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO2_MODULO +#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT 0x0 +#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK 0xFFFFFFFFL +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//PHYPLLG_PIXCLK_RESYNC_CNTL +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//MIPI_DTO_CNTL +#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE__SHIFT 0x0 +#define MIPI_DTO_CNTL__MIPI_DTO_ENABLE_MASK 0x00000001L +//MIPI_DTO_PHASE +#define MIPI_DTO_PHASE__MIPI_DTO_PHASE__SHIFT 0x0 +#define MIPI_DTO_PHASE__MIPI_DTO_PHASE_MASK 0xFFFFFFFFL +//MIPI_DTO_MODULO +#define MIPI_DTO_MODULO__MIPI_DTO_MODULO__SHIFT 0x0 +#define MIPI_DTO_MODULO__MIPI_DTO_MODULO_MASK 0xFFFFFFFFL +//DAC_CLK_ENABLE +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L +//DVO_CLK_ENABLE +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L +//AVSYNC_COUNTER_WRITE +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xFFFFFFFFL +//AVSYNC_COUNTER_CONTROL +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x00000001L +//AVSYNC_COUNTER_READ +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xFFFFFFFFL +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x00800000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//PIXCLK1_RESYNC_CNTL +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L +//PIXCLK2_RESYNC_CNTL +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L +//PIXCLK0_RESYNC_CNTL +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLF_PIXCLK_RESYNC_CNTL +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG4_PIXEL_RATE_CNTL +#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 +#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 +#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL__SHIFT 0x8 +#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL__SHIFT 0x9 +#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L +#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L +#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL_MASK 0x00000100L +#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL_MASK 0x00000200L +#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO4_PHASE +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL +//DP_DTO4_MODULO +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL +//OTG4_PHYPLL_PIXEL_RATE_CNTL +#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG5_PIXEL_RATE_CNTL +#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 +#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 +#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL__SHIFT 0x8 +#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL__SHIFT 0x9 +#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L +#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L +#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL_MASK 0x00000100L +#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL_MASK 0x00000200L +#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR_MASK 0x0000C000L +#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO5_PHASE +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL +//DP_DTO5_MODULO +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL +//OTG5_PHYPLL_PIXEL_RATE_CNTL +#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKF_CLOCK_ENABLE +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DVOACLKD_CNTL +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001F00L +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L +//DVOACLKC_MVP_CNTL +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001F00L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L +//DVOACLKC_CNTL +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001F00L +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_pll_dispdec +//PLL_MACRO_CNTL_RESERVED0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED1 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED2 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED3 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED4 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED5 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED6 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED7 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED8 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED9 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED10 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED11 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED12 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED13 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED14 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED15 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED16 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED17 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED18 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED19 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED20 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED21 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED22 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED23 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED24 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED25 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED26 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED27 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED28 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED29 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED30 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED31 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED32 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED33 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED34 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED35 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED36 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED37 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED38 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED39 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED40 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED41 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x3FFFFFFFL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN4_PG_CONFIG +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT 0x8 +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK 0x00000100L +//DOMAIN4_PG_STATUS +#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN5_PG_CONFIG +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT 0x8 +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK 0x00000100L +//DOMAIN5_PG_STATUS +#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN6_PG_CONFIG +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT 0x8 +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK 0x00000100L +//DOMAIN6_PG_STATUS +#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN7_PG_CONFIG +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT 0x8 +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK 0x00000100L +//DOMAIN7_PG_STATUS +#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN8_PG_CONFIG +#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE__SHIFT 0x8 +#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE_MASK 0x00000100L +//DOMAIN8_PG_STATUS +#define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN9_PG_CONFIG +#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE__SHIFT 0x8 +#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE_MASK 0x00000100L +//DOMAIN9_PG_STATUS +#define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN10_PG_CONFIG +#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE__SHIFT 0x8 +#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE_MASK 0x00000100L +//DOMAIN10_PG_STATUS +#define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN11_PG_CONFIG +#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE__SHIFT 0x8 +#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE_MASK 0x00000100L +//DOMAIN11_PG_STATUS +#define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN12_PG_CONFIG +#define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE__SHIFT 0x8 +#define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE_MASK 0x00000100L +//DOMAIN12_PG_STATUS +#define DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN13_PG_CONFIG +#define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE__SHIFT 0x8 +#define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE_MASK 0x00000100L +//DOMAIN13_PG_STATUS +#define DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN14_PG_CONFIG +#define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE__SHIFT 0x8 +#define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE_MASK 0x00000100L +//DOMAIN14_PG_STATUS +#define DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN15_PG_CONFIG +#define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE__SHIFT 0x8 +#define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE_MASK 0x00000100L +//DOMAIN15_PG_STATUS +#define DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0xa +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x12 +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x14 +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x16 +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x18 +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x19 +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x1a +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x1b +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x1c +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x1d +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x1e +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x1f +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00000400L +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00040000L +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00100000L +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00400000L +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x01000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x02000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x04000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x08000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x10000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x20000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x40000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x80000000L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK 0x00100000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00200000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK 0x01000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x02000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK 0x04000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x08000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK 0x10000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x20000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK 0x40000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x80000000L +//DCPG_INTERRUPT_CONTROL_2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK 0x00100000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00200000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK 0x01000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x02000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK 0x04000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x08000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK 0x10000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x20000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK 0x40000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x80000000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L +//DC_PGCNTL_STATUS_REG + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON2_PERFCOUNTER_CNTL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_CNTL2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_STATE +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON2_PERFMON_CNTL +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON2_PERFMON_CNTL2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON2_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON2_PERFMON_CVALUE_LOW +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON2_PERFMON_HI +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFMON_LOW +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x2 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x3 +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x00000003L +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000004L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000008L +//DMU_MEM_PWR_CNTL +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L +//DMCU_SMU_INTERRUPT_CNTL +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +//DMCU_CTRL +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L +//DMCU_STATUS +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +//DMCU_PC_START_ADDR +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_START_ADDR +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_END_ADDR +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_ISR_START_ADDR +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_CS_HI +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL +//DMCU_FW_CS_LO +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL +//DMCU_RAM_ACCESS_CTRL +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +//DMCU_ERAM_WR_CTRL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_WR_DATA +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL +//DMCU_ERAM_RD_CTRL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_RD_DATA +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL +//DMCU_IRAM_WR_CTRL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL +//DMCU_IRAM_WR_DATA +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL +//DMCU_IRAM_RD_CTRL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL +//DMCU_IRAM_RD_DATA +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL +//DMCU_EVENT_TRIGGER +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +//DMCU_UC_INTERNAL_INT_STATUS +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +//DMCU_SS_INTERRUPT_CNTL_STATUS +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L +//DMCU_INTERRUPT_STATUS +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +//DMCU_INTERRUPT_STATUS_1 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L +//DMCU_INTERRUPT_TO_HOST_EN_MASK +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +//DMCU_INTERRUPT_TO_UC_EN_MASK +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +//DC_DMCU_SCRATCH +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL +//DMCU_INT_CNT +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_FW_CHECKSUM_SMPL_BYTE_POS +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL +//DMCU_UC_CLK_GATING_CNTL +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +//MASTER_COMM_DATA_REG1 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG2 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG3 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CMD_REG +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CNTL_REG +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +//SLAVE_COMM_DATA_REG1 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG2 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG3 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CMD_REG +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CNTL_REG +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_STATUS2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_STATUS4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_STATUS5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +//DMCU_DPRX_INTERRUPT_STATUS1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INTERRUPT_STATUS_CONTINUE +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INT_CNT_CONTINUE +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L + + +// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec +//CNV0_WB_ENABLE +#define CNV0_WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define CNV0_WB_ENABLE__WB_ENABLE_MASK 0x00000001L +//CNV0_WB_EC_CONFIG +#define CNV0_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define CNV0_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define CNV0_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define CNV0_WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 +#define CNV0_WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 +#define CNV0_WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 +#define CNV0_WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11 +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13 +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 +#define CNV0_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18 +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define CNV0_WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV0_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L +#define CNV0_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L +#define CNV0_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L +#define CNV0_WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L +#define CNV0_WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L +#define CNV0_WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L +#define CNV0_WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L +#define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L +#define CNV0_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L +#define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L +#define CNV0_WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L +//CNV0_CNV_MODE +#define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV0_CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV0_CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV0_CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV0_CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV0_CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV0_CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV0_CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV0_CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L +#define CNV0_CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L +#define CNV0_CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L +#define CNV0_CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L +#define CNV0_CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L +#define CNV0_CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L +#define CNV0_CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L +#define CNV0_CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L +#define CNV0_CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L +#define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L +//CNV0_CNV_WINDOW_START +#define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL +#define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L +//CNV0_CNV_WINDOW_SIZE +#define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL +#define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L +//CNV0_CNV_UPDATE +#define CNV0_CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV0_CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV0_CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV0_CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L +#define CNV0_CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L +#define CNV0_CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L +//CNV0_CNV_SOURCE_SIZE +#define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL +#define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L +//CNV0_CNV_CSC_CONTROL +#define CNV0_CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 +#define CNV0_CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L +//CNV0_CNV_CSC_C11_C12 +#define CNV0_CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV0_CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV0_CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L +//CNV0_CNV_CSC_C13_C14 +#define CNV0_CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV0_CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV0_CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L +//CNV0_CNV_CSC_C21_C22 +#define CNV0_CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV0_CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV0_CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L +//CNV0_CNV_CSC_C23_C24 +#define CNV0_CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV0_CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV0_CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L +//CNV0_CNV_CSC_C31_C32 +#define CNV0_CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV0_CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV0_CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L +//CNV0_CNV_CSC_C33_C34 +#define CNV0_CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV0_CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV0_CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL +#define CNV0_CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L +//CNV0_CNV_CSC_ROUND_OFFSET_R +#define CNV0_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV0_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL +//CNV0_CNV_CSC_ROUND_OFFSET_G +#define CNV0_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV0_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL +//CNV0_CNV_CSC_ROUND_OFFSET_B +#define CNV0_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV0_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL +//CNV0_CNV_CSC_CLAMP_R +#define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL +#define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L +//CNV0_CNV_CSC_CLAMP_G +#define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL +#define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L +//CNV0_CNV_CSC_CLAMP_B +#define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL +#define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L +//CNV0_CNV_TEST_CNTL +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L +#define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L +//CNV0_CNV_TEST_CRC_RED +#define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L +#define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//CNV0_CNV_TEST_CRC_GREEN +#define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L +#define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//CNV0_CNV_TEST_CRC_BLUE +#define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L +#define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//CNV0_CNV_INPUT_SELECT +#define CNV0_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV0_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define CNV0_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L +#define CNV0_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL +//CNV0_WB_SOFT_RESET +#define CNV0_WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define CNV0_WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L +//CNV0_WB_WARM_UP_MODE_CTL1 +#define CNV0_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 +#define CNV0_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 +#define CNV0_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f +#define CNV0_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL +#define CNV0_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L +#define CNV0_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L +//CNV0_WB_WARM_UP_MODE_CTL2 +#define CNV0_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 +#define CNV0_WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8 +#define CNV0_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL +#define CNV0_WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L + + +// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec +//WBSCL0_WBSCL_COEF_RAM_SELECT +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L +#define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//WBSCL0_WBSCL_COEF_RAM_TAP_DATA +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//WBSCL0_WBSCL_MODE +#define WBSCL0_WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 +#define WBSCL0_WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L +//WBSCL0_WBSCL_TAP_CONTROL +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L +#define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L +//WBSCL0_WBSCL_DEST_SIZE +#define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 +#define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 +#define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL +#define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L +//WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO +#define WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 +#define WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO +#define WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 +#define WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB +#define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR +#define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL0_WBSCL_ROUND_OFFSET +#define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 +#define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL +#define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L +//WBSCL0_WBSCL_CLAMP +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10 +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18 +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L +#define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L +//WBSCL0_WBSCL_OVERFLOW_STATUS +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L +//WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8 +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18 +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L +#define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L +//WBSCL0_WBSCL_TEST_CNTL +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L +#define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L +//WBSCL0_WBSCL_TEST_CRC_RED +#define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8 +#define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 +#define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L +#define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//WBSCL0_WBSCL_TEST_CRC_GREEN +#define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 +#define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL +#define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//WBSCL0_WBSCL_TEST_CRC_BLUE +#define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8 +#define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L +#define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//WBSCL0_WBSCL_BACKPRESSURE_CNT_EN +#define WBSCL0_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define WBSCL0_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//WBSCL0_WB_MCIF_BACKPRESSURE_CNT +#define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 +#define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 +#define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL +#define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L +//WBSCL0_WBSCL_RAM_SHUTDOWN +#define WBSCL0_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0 +#define WBSCL0_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec +//CNV1_WB_ENABLE +#define CNV1_WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define CNV1_WB_ENABLE__WB_ENABLE_MASK 0x00000001L +//CNV1_WB_EC_CONFIG +#define CNV1_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define CNV1_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define CNV1_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define CNV1_WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 +#define CNV1_WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 +#define CNV1_WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 +#define CNV1_WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11 +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13 +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 +#define CNV1_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18 +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define CNV1_WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV1_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L +#define CNV1_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L +#define CNV1_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L +#define CNV1_WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L +#define CNV1_WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L +#define CNV1_WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L +#define CNV1_WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L +#define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L +#define CNV1_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L +#define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L +#define CNV1_WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L +//CNV1_CNV_MODE +#define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV1_CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV1_CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV1_CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV1_CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV1_CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV1_CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV1_CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV1_CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L +#define CNV1_CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L +#define CNV1_CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L +#define CNV1_CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L +#define CNV1_CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L +#define CNV1_CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L +#define CNV1_CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L +#define CNV1_CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L +#define CNV1_CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L +#define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L +//CNV1_CNV_WINDOW_START +#define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL +#define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L +//CNV1_CNV_WINDOW_SIZE +#define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL +#define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L +//CNV1_CNV_UPDATE +#define CNV1_CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV1_CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV1_CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV1_CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L +#define CNV1_CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L +#define CNV1_CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L +//CNV1_CNV_SOURCE_SIZE +#define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL +#define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L +//CNV1_CNV_CSC_CONTROL +#define CNV1_CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 +#define CNV1_CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L +//CNV1_CNV_CSC_C11_C12 +#define CNV1_CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV1_CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV1_CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L +//CNV1_CNV_CSC_C13_C14 +#define CNV1_CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV1_CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV1_CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L +//CNV1_CNV_CSC_C21_C22 +#define CNV1_CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV1_CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV1_CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L +//CNV1_CNV_CSC_C23_C24 +#define CNV1_CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV1_CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV1_CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L +//CNV1_CNV_CSC_C31_C32 +#define CNV1_CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV1_CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV1_CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L +//CNV1_CNV_CSC_C33_C34 +#define CNV1_CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV1_CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV1_CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL +#define CNV1_CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L +//CNV1_CNV_CSC_ROUND_OFFSET_R +#define CNV1_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV1_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL +//CNV1_CNV_CSC_ROUND_OFFSET_G +#define CNV1_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV1_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL +//CNV1_CNV_CSC_ROUND_OFFSET_B +#define CNV1_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV1_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL +//CNV1_CNV_CSC_CLAMP_R +#define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL +#define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L +//CNV1_CNV_CSC_CLAMP_G +#define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL +#define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L +//CNV1_CNV_CSC_CLAMP_B +#define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL +#define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L +//CNV1_CNV_TEST_CNTL +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L +#define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L +//CNV1_CNV_TEST_CRC_RED +#define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L +#define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//CNV1_CNV_TEST_CRC_GREEN +#define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L +#define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//CNV1_CNV_TEST_CRC_BLUE +#define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L +#define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//CNV1_CNV_INPUT_SELECT +#define CNV1_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV1_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define CNV1_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L +#define CNV1_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL +//CNV1_WB_SOFT_RESET +#define CNV1_WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define CNV1_WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L +//CNV1_WB_WARM_UP_MODE_CTL1 +#define CNV1_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 +#define CNV1_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 +#define CNV1_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f +#define CNV1_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL +#define CNV1_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L +#define CNV1_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L +//CNV1_WB_WARM_UP_MODE_CTL2 +#define CNV1_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 +#define CNV1_WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8 +#define CNV1_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL +#define CNV1_WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L + + +// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec +//WBSCL1_WBSCL_COEF_RAM_SELECT +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L +#define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//WBSCL1_WBSCL_COEF_RAM_TAP_DATA +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//WBSCL1_WBSCL_MODE +#define WBSCL1_WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 +#define WBSCL1_WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L +//WBSCL1_WBSCL_TAP_CONTROL +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L +#define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L +//WBSCL1_WBSCL_DEST_SIZE +#define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 +#define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 +#define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL +#define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L +//WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO +#define WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 +#define WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO +#define WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 +#define WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB +#define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR +#define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL1_WBSCL_ROUND_OFFSET +#define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 +#define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL +#define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L +//WBSCL1_WBSCL_CLAMP +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10 +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18 +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L +#define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L +//WBSCL1_WBSCL_OVERFLOW_STATUS +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L +//WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8 +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18 +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L +#define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L +//WBSCL1_WBSCL_TEST_CNTL +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L +#define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L +//WBSCL1_WBSCL_TEST_CRC_RED +#define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8 +#define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 +#define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L +#define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//WBSCL1_WBSCL_TEST_CRC_GREEN +#define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 +#define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL +#define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//WBSCL1_WBSCL_TEST_CRC_BLUE +#define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8 +#define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L +#define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//WBSCL1_WBSCL_BACKPRESSURE_CNT_EN +#define WBSCL1_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define WBSCL1_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//WBSCL1_WB_MCIF_BACKPRESSURE_CNT +#define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 +#define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 +#define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL +#define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L +//WBSCL1_WBSCL_RAM_SHUTDOWN +#define WBSCL1_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0 +#define WBSCL1_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L + + +// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R +#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL +//MCIF_WB0_MCIF_WB_BUFMGR_STATUS +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB0_MCIF_WB_BUF_PITCH +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB0_MCIF_WB_BUF_1_STATUS +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +//MCIF_WB0_MCIF_WB_BUF_2_STATUS +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +//MCIF_WB0_MCIF_WB_BUF_3_STATUS +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +//MCIF_WB0_MCIF_WB_BUF_4_STATUS +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L +//MCIF_WB0_MCIF_WB_SCLK_CHANGE +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL +//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L +//MCIF_WB0_MCIF_WB_WATERMARK +#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL +//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB0_MCIF_WB_WARM_UP_CNTL +#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L +//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MCIF_WB0_MULTI_LEVEL_QOS_CTRL +#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec +//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R +#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL +//MCIF_WB1_MCIF_WB_BUFMGR_STATUS +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB1_MCIF_WB_BUF_PITCH +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB1_MCIF_WB_BUF_1_STATUS +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +//MCIF_WB1_MCIF_WB_BUF_2_STATUS +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +//MCIF_WB1_MCIF_WB_BUF_3_STATUS +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +//MCIF_WB1_MCIF_WB_BUF_4_STATUS +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L +//MCIF_WB1_MCIF_WB_SCLK_CHANGE +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL +//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L +//MCIF_WB1_MCIF_WB_WATERMARK +#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL +//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB1_MCIF_WB_WARM_UP_CNTL +#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L +//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MCIF_WB1_MULTI_LEVEL_QOS_CTRL +#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +//WBIF0_SMU_WM_CONTROL +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT 0x14 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT 0x16 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK 0x00300000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK 0x00400000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF1_MISC_CTRL +#define WBIF1_MISC_CTRL__MCIFWB1_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF1_MISC_CTRL__MCIF_WB1_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF1_MISC_CTRL__MCIFWB1_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF1_MISC_CTRL__MCIF_WB1_SOCCLK_DS_ENABLE_MASK 0x00010000L +//WBIF1_SMU_WM_CONTROL +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_SEL__SHIFT 0x14 +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_REQ__SHIFT 0x16 +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_SEL_MASK 0x00300000L +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_REQ_MASK 0x00400000L +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF1_PHASE0_OUTSTANDING_COUNTER +#define WBIF1_PHASE0_OUTSTANDING_COUNTER__MCIF_WB1_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF1_PHASE0_OUTSTANDING_COUNTER__MCIF_WB1_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF1_PHASE1_OUTSTANDING_COUNTER +#define WBIF1_PHASE1_OUTSTANDING_COUNTER__MCIF_WB1_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF1_PHASE1_OUTSTANDING_COUNTER__MCIF_WB1_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM1_PWR_STATE__SHIFT 0xa +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0xc +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0xe +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM0_PWR_STATE_MASK 0x00000300L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM1_PWR_STATE_MASK 0x00000C00L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM0_PWR_STATE_MASK 0x00003000L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM1_PWR_STATE_MASK 0x0000C000L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_FORCE__SHIFT 0x9 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_DIS__SHIFT 0xb +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_MODE_SEL__SHIFT 0xc +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_LUMA_MEM_EN_NUM__SHIFT 0xe +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_CHROMA_MEM_EN_NUM__SHIFT 0xf +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_FORCE_MASK 0x00000600L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_DIS_MASK 0x00000800L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_MODE_SEL_MASK 0x00003000L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_LUMA_MEM_EN_NUM_MASK 0x00004000L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_CHROMA_MEM_EN_NUM_MASK 0x00008000L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF1_GATE_DIS__SHIFT 0xb +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF1_GATE_DIS__SHIFT 0xc +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF1_GATE_DIS_MASK 0x00000800L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF1_GATE_DIS_MASK 0x00001000L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__WBIF1_SOFT_RESET__SHIFT 0x3 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__WBIF1_SOFT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR__SHIFT 0x7 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0x9 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x14 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000040L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR_MASK 0x00000080L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00000100L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00000200L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK_MASK 0x000FF000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x03F00000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO__SHIFT 0x4 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC__SHIFT 0x5 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC_MASK 0x0000000EL +#define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO_MASK 0x00000010L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC_MASK 0x000000E0L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCHUBBUB_SDPIF_FB_BASE +#define DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE_MASK 0x00FFFFFFL +//DCHUBBUB_SDPIF_FB_TOP +#define DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP__SHIFT 0x0 +#define DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP_MASK 0x00FFFFFFL +//DCHUBBUB_SDPIF_FB_OFFSET +#define DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET__SHIFT 0x0 +#define DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET_MASK 0x00FFFFFFL +//DCHUBBUB_SDPIF_AGP_BOT +#define DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT_MASK 0x03FFFFFFL +//DCHUBBUB_SDPIF_AGP_TOP +#define DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP__SHIFT 0x0 +#define DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP_MASK 0x03FFFFFFL +//DCHUBBUB_SDPIF_AGP_BASE +#define DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE_MASK 0x03FFFFFFL +//DCHUBBUB_SDPIF_APER_BASE +#define DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS__SHIFT 0x1c +#define DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE_MASK 0x0FFFFFFFL +#define DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS_MASK 0x10000000L +//DCHUBBUB_SDPIF_APER_TOP +#define DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP__SHIFT 0x0 +#define DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP_MASK 0x0FFFFFFFL +//DCHUBBUB_SDPIF_APER_DEF_0 +#define DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0__SHIFT 0x0 +#define DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0_MASK 0xFFFFFFFFL +//DCHUBBUB_SDPIF_APER_DEF_1 +#define DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1__SHIFT 0x0 +#define DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1_MASK 0x0000000FL +//DCHUBBUB_SDPIF_MMIO_CNTRL_0 +#define DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN_MASK 0x00000001L +//DCHUBBUB_SDPIF_MMIO_CNTRL_1 +#define DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN__SHIFT 0x8 +#define DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN_MASK 0x00000100L +//DCHUBBUB_SDPIF_MMIO_CNTRL_W +#define DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS__SHIFT 0xd +#define DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS_MASK 0x00002000L +//DCHUBBUB_SDPIF_MARC_BASE_LO_0 +#define DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_BASE_HI_0 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_RELOC_LO_0 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0_MASK 0x00000001L +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_RELOC_HI_0 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_LENGTH_LO_0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_LENGTH_HI_0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_BASE_LO_1 +#define DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_BASE_HI_1 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_RELOC_LO_1 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1_MASK 0x00000001L +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_RELOC_HI_1 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_LENGTH_LO_1 +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_LENGTH_HI_1 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_BASE_LO_2 +#define DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_BASE_HI_2 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_RELOC_LO_2 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2_MASK 0x00000001L +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_RELOC_HI_2 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_LENGTH_LO_2 +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_LENGTH_HI_2 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_BASE_LO_3 +#define DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_BASE_HI_3 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_RELOC_LO_3 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3_MASK 0x00000001L +#define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_RELOC_HI_3 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_MARC_LENGTH_LO_3 +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3__SHIFT 0xc +#define DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3_MASK 0xFFFFF000L +//DCHUBBUB_SDPIF_MARC_LENGTH_HI_3 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3_MASK 0x0000FFFFL +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_DCC_CFG +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L +//DCHUBBUB_RET_PATH_DCC_CFG0_0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG0_1 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_1 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_1 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_1 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_1 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_1 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_1 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_1 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0xe +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00003000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00004000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0x10 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x01FF0000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE__SHIFT 0x2 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE_MASK 0x00000004L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x001FFFFFL +//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x001FFFFFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x001FFFFFL +//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x001FFFFFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x001FFFFFL +//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x001FFFFFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x001FFFFFL +//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x001FFFFFL +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x001FFFFFL +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK__SHIFT 0x6 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK_MASK 0x00000040L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0xf +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0xf +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0xf +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0xf +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//VTG4_CONTROL +#define VTG4_CONTROL__VTG4_FP2__SHIFT 0x0 +#define VTG4_CONTROL__VTG4_VCOUNT_INIT__SHIFT 0xf +#define VTG4_CONTROL__VTG4_ENABLE__SHIFT 0x1f +#define VTG4_CONTROL__VTG4_FP2_MASK 0x00007FFFL +#define VTG4_CONTROL__VTG4_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG4_CONTROL__VTG4_ENABLE_MASK 0x80000000L +//VTG5_CONTROL +#define VTG5_CONTROL__VTG5_FP2__SHIFT 0x0 +#define VTG5_CONTROL__VTG5_VCOUNT_INIT__SHIFT 0xf +#define VTG5_CONTROL__VTG5_ENABLE__SHIFT 0x1f +#define VTG5_CONTROL__VTG5_FP2_MASK 0x00007FFFL +#define VTG5_CONTROL__VTG5_VCOUNT_INIT_MASK 0x3FFF8000L +#define VTG5_CONTROL__VTG5_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL__SHIFT 0x15 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x001FF800L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_MASK 0x7FE00000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_SPARE +#define DCHUBBUB_SPARE__DCHUBBUB_SPARE__SHIFT 0x0 +#define DCHUBBUB_SPARE__DCHUBBUB_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP0_HUBPREQ_DEBUG_DB +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L +//HUBPREQ0_DCSURF_FRAME_PACING_CONTROL +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L +//HUBPREQ0_DCSURF_FRAME_PACING_TIME +#define HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L +//HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ0_DCN_VM_CONTEXT0_STATUS +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L +#define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L +//HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ0_DCN_VM_CONTEXT0_CNTL +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINS +#define HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL +#define HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINS_C +#define HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINS +#define HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec +//CURSOR0_CURSOR_CONTROL +#define CURSOR0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CURSOR0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_CURSOR_SIZE +#define CURSOR0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_CURSOR_POSITION +#define CURSOR0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_CURSOR_HOT_SPOT +#define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_CURSOR_STEREO_CONTROL +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_CURSOR_DST_OFFSET +#define CURSOR0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP1_HUBPREQ_DEBUG_DB +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L +//HUBPREQ1_DCSURF_FRAME_PACING_CONTROL +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L +//HUBPREQ1_DCSURF_FRAME_PACING_TIME +#define HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L +//HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ1_DCN_VM_CONTEXT0_STATUS +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L +#define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L +//HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ1_DCN_VM_CONTEXT0_CNTL +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINS +#define HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL +#define HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINS_C +#define HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINS +#define HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec +//CURSOR1_CURSOR_CONTROL +#define CURSOR1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CURSOR1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR1_CURSOR_SURFACE_ADDRESS +#define CURSOR1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR1_CURSOR_SIZE +#define CURSOR1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR1_CURSOR_POSITION +#define CURSOR1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR1_CURSOR_HOT_SPOT +#define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR1_CURSOR_STEREO_CONTROL +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR1_CURSOR_DST_OFFSET +#define CURSOR1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR1_CURSOR_MEM_PWR_CTRL +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR1_CURSOR_MEM_PWR_STATUS +#define CURSOR1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP2_HUBPREQ_DEBUG_DB +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L +//HUBPREQ2_DCSURF_FRAME_PACING_CONTROL +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L +//HUBPREQ2_DCSURF_FRAME_PACING_TIME +#define HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L +//HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ2_DCN_VM_CONTEXT0_STATUS +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L +#define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L +//HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ2_DCN_VM_CONTEXT0_CNTL +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINS +#define HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL +#define HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINS_C +#define HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINS +#define HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec +//CURSOR2_CURSOR_CONTROL +#define CURSOR2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CURSOR2_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR2_CURSOR_SURFACE_ADDRESS +#define CURSOR2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR2_CURSOR_SIZE +#define CURSOR2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR2_CURSOR_POSITION +#define CURSOR2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR2_CURSOR_HOT_SPOT +#define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR2_CURSOR_STEREO_CONTROL +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR2_CURSOR_DST_OFFSET +#define CURSOR2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR2_CURSOR_MEM_PWR_CTRL +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR2_CURSOR_MEM_PWR_STATUS +#define CURSOR2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP3_HUBPREQ_DEBUG_DB +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L +//HUBPREQ3_DCSURF_FRAME_PACING_CONTROL +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L +//HUBPREQ3_DCSURF_FRAME_PACING_TIME +#define HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L +//HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL +//HUBPREQ3_DCN_VM_CONTEXT0_STATUS +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L +#define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L +//HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//HUBPREQ3_DCN_VM_CONTEXT0_CNTL +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINS +#define HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL +#define HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINS_C +#define HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINS +#define HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec +//CURSOR3_CURSOR_CONTROL +#define CURSOR3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CURSOR3_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR3_CURSOR_SURFACE_ADDRESS +#define CURSOR3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR3_CURSOR_SIZE +#define CURSOR3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR3_CURSOR_POSITION +#define CURSOR3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR3_CURSOR_HOT_SPOT +#define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR3_CURSOR_STEREO_CONTROL +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR3_CURSOR_DST_OFFSET +#define CURSOR3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR3_CURSOR_MEM_PWR_CTRL +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR3_CURSOR_MEM_PWR_STATUS +#define CURSOR3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG0_FCNV_FP_SCALE_BIAS +#define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 +#define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L +//CNVC_CFG0_DENORM_CONTROL +#define CNVC_CFG0_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 +#define CNVC_CFG0_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf +#define CNVC_CFG0_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 +#define CNVC_CFG0_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f +#define CNVC_CFG0_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL +#define CNVC_CFG0_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L +#define CNVC_CFG0_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L +#define CNVC_CFG0_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_OFFSET +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 +#define DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc +#define DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 +#define DSCL0_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L +#define DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L +#define DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L +#define DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L +#define DSCL0_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L +#define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_COMA_C11_C12 +#define CM0_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 +#define CM0_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 +#define CM0_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL +#define CM0_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L +//CM0_CM_COMA_C13_C14 +#define CM0_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 +#define CM0_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 +#define CM0_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL +#define CM0_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L +//CM0_CM_COMA_C21_C22 +#define CM0_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 +#define CM0_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 +#define CM0_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL +#define CM0_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L +//CM0_CM_COMA_C23_C24 +#define CM0_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 +#define CM0_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 +#define CM0_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL +#define CM0_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L +//CM0_CM_COMA_C31_C32 +#define CM0_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 +#define CM0_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 +#define CM0_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL +#define CM0_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L +//CM0_CM_COMA_C33_C34 +#define CM0_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 +#define CM0_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 +#define CM0_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL +#define CM0_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L +//CM0_CM_COMB_C11_C12 +#define CM0_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 +#define CM0_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 +#define CM0_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL +#define CM0_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L +//CM0_CM_COMB_C13_C14 +#define CM0_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 +#define CM0_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 +#define CM0_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL +#define CM0_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L +//CM0_CM_COMB_C21_C22 +#define CM0_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 +#define CM0_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 +#define CM0_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL +#define CM0_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L +//CM0_CM_COMB_C23_C24 +#define CM0_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 +#define CM0_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 +#define CM0_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL +#define CM0_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L +//CM0_CM_COMB_C31_C32 +#define CM0_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 +#define CM0_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 +#define CM0_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL +#define CM0_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L +//CM0_CM_COMB_C33_C34 +#define CM0_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 +#define CM0_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 +#define CM0_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL +#define CM0_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L +//CM0_CM_IGAM_CONTROL +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 +#define CM0_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L +#define CM0_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L +//CM0_CM_IGAM_LUT_RW_CONTROL +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L +#define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L +//CM0_CM_IGAM_LUT_RW_INDEX +#define CM0_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL +//CM0_CM_IGAM_LUT_SEQ_COLOR +#define CM0_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL +//CM0_CM_IGAM_LUT_30_COLOR +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L +#define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L +//CM0_CM_IGAM_LUT_PWL_DATA +#define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 +#define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL +#define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L +//CM0_CM_IGAM_LUT_AUTOFILL +#define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 +#define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L +#define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L +//CM0_CM_IGAM_LUT_BW_OFFSET_BLUE +#define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 +#define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL +#define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L +//CM0_CM_IGAM_LUT_BW_OFFSET_GREEN +#define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 +#define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL +#define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L +//CM0_CM_IGAM_LUT_BW_OFFSET_RED +#define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 +#define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL +#define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L +//CM0_CM_ICSC_CONTROL +#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM0_CM_ICSC_C11_C12 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM0_CM_ICSC_C13_C14 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM0_CM_ICSC_C21_C22 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM0_CM_ICSC_C23_C24 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM0_CM_ICSC_C31_C32 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM0_CM_ICSC_C33_C34 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_OCSC_CONTROL +#define CM0_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 +#define CM0_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L +//CM0_CM_OCSC_C11_C12 +#define CM0_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 +#define CM0_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 +#define CM0_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L +//CM0_CM_OCSC_C13_C14 +#define CM0_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 +#define CM0_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 +#define CM0_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L +//CM0_CM_OCSC_C21_C22 +#define CM0_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 +#define CM0_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 +#define CM0_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L +//CM0_CM_OCSC_C23_C24 +#define CM0_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 +#define CM0_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 +#define CM0_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L +//CM0_CM_OCSC_C31_C32 +#define CM0_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 +#define CM0_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 +#define CM0_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L +//CM0_CM_OCSC_C33_C34 +#define CM0_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 +#define CM0_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 +#define CM0_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL +#define CM0_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L +//CM0_CM_BNS_VALUES_R +#define CM0_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 +#define CM0_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 +#define CM0_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL +#define CM0_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L +//CM0_CM_BNS_VALUES_G +#define CM0_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 +#define CM0_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 +#define CM0_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL +#define CM0_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L +//CM0_CM_BNS_VALUES_B +#define CM0_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 +#define CM0_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 +#define CM0_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL +#define CM0_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_CONTROL +#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM0_CM_DGAM_LUT_INDEX +#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_DGAM_LUT_DATA +#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM0_CM_DGAM_LUT_WRITE_EN_MASK +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +//CM0_CM_DGAM_RAMA_START_CNTL_B +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_START_CNTL_G +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_START_CNTL_R +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL1_B +#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_B +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_END_CNTL1_G +#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_G +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_END_CNTL1_R +#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_R +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_REGION_0_1 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_2_3 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_4_5 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_6_7 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_8_9 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_10_11 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_12_13 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_14_15 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_START_CNTL_B +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_START_CNTL_G +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_START_CNTL_R +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL1_B +#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_B +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_END_CNTL1_G +#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_G +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_END_CNTL1_R +#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_R +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_REGION_0_1 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_2_3 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_4_5 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_6_7 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_8_9 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_10_11 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_12_13 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_14_15 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_CONTROL +#define CM0_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 +#define CM0_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L +//CM0_CM_RGAM_LUT_INDEX +#define CM0_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_RGAM_LUT_DATA +#define CM0_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL +//CM0_CM_RGAM_LUT_WRITE_EN_MASK +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L +//CM0_CM_RGAM_RAMA_START_CNTL_B +#define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_RGAM_RAMA_START_CNTL_G +#define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_RGAM_RAMA_START_CNTL_R +#define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_RGAM_RAMA_SLOPE_CNTL_B +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMA_SLOPE_CNTL_G +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMA_SLOPE_CNTL_R +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMA_END_CNTL1_B +#define CM0_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMA_END_CNTL2_B +#define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMA_END_CNTL1_G +#define CM0_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMA_END_CNTL2_G +#define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMA_END_CNTL1_R +#define CM0_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMA_END_CNTL2_R +#define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMA_REGION_0_1 +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_2_3 +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_4_5 +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_6_7 +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_8_9 +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_10_11 +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_12_13 +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_14_15 +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_16_17 +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_18_19 +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_20_21 +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_22_23 +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_24_25 +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_26_27 +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_28_29 +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_30_31 +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMA_REGION_32_33 +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_START_CNTL_B +#define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_RGAM_RAMB_START_CNTL_G +#define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_RGAM_RAMB_START_CNTL_R +#define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_RGAM_RAMB_SLOPE_CNTL_B +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMB_SLOPE_CNTL_G +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMB_SLOPE_CNTL_R +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_RGAM_RAMB_END_CNTL1_B +#define CM0_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMB_END_CNTL2_B +#define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMB_END_CNTL1_G +#define CM0_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMB_END_CNTL2_G +#define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMB_END_CNTL1_R +#define CM0_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_RGAM_RAMB_END_CNTL2_R +#define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_RGAM_RAMB_REGION_0_1 +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_2_3 +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_4_5 +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_6_7 +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_8_9 +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_10_11 +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_12_13 +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_14_15 +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_16_17 +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_18_19 +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_20_21 +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_22_23 +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_24_25 +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_26_27 +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_28_29 +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_30_31 +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_RGAM_RAMB_REGION_32_33 +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_RANGE_CLAMP_CONTROL_R +#define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 +#define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 +#define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL +#define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L +//CM0_CM_RANGE_CLAMP_CONTROL_G +#define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 +#define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 +#define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL +#define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L +//CM0_CM_RANGE_CLAMP_CONTROL_B +#define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 +#define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 +#define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL +#define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L +//CM0_CM_DENORM_CONTROL +#define CM0_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 +#define CM0_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 +#define CM0_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L +#define CM0_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L +//CM0_CM_CMOUT_CONTROL +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L +#define CM0_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L +//CM0_CM_CMOUT_RANDOM_SEEDS +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L +#define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG1_FCNV_FP_SCALE_BIAS +#define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 +#define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L +//CNVC_CFG1_DENORM_CONTROL +#define CNVC_CFG1_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 +#define CNVC_CFG1_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf +#define CNVC_CFG1_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 +#define CNVC_CFG1_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f +#define CNVC_CFG1_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL +#define CNVC_CFG1_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L +#define CNVC_CFG1_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L +#define CNVC_CFG1_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_OFFSET +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 +#define DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc +#define DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 +#define DSCL1_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L +#define DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L +#define DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L +#define DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L +#define DSCL1_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L +#define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_COMA_C11_C12 +#define CM1_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 +#define CM1_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 +#define CM1_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL +#define CM1_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L +//CM1_CM_COMA_C13_C14 +#define CM1_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 +#define CM1_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 +#define CM1_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL +#define CM1_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L +//CM1_CM_COMA_C21_C22 +#define CM1_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 +#define CM1_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 +#define CM1_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL +#define CM1_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L +//CM1_CM_COMA_C23_C24 +#define CM1_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 +#define CM1_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 +#define CM1_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL +#define CM1_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L +//CM1_CM_COMA_C31_C32 +#define CM1_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 +#define CM1_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 +#define CM1_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL +#define CM1_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L +//CM1_CM_COMA_C33_C34 +#define CM1_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 +#define CM1_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 +#define CM1_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL +#define CM1_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L +//CM1_CM_COMB_C11_C12 +#define CM1_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 +#define CM1_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 +#define CM1_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL +#define CM1_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L +//CM1_CM_COMB_C13_C14 +#define CM1_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 +#define CM1_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 +#define CM1_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL +#define CM1_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L +//CM1_CM_COMB_C21_C22 +#define CM1_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 +#define CM1_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 +#define CM1_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL +#define CM1_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L +//CM1_CM_COMB_C23_C24 +#define CM1_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 +#define CM1_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 +#define CM1_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL +#define CM1_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L +//CM1_CM_COMB_C31_C32 +#define CM1_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 +#define CM1_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 +#define CM1_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL +#define CM1_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L +//CM1_CM_COMB_C33_C34 +#define CM1_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 +#define CM1_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 +#define CM1_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL +#define CM1_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L +//CM1_CM_IGAM_CONTROL +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 +#define CM1_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L +#define CM1_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L +//CM1_CM_IGAM_LUT_RW_CONTROL +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L +#define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L +//CM1_CM_IGAM_LUT_RW_INDEX +#define CM1_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL +//CM1_CM_IGAM_LUT_SEQ_COLOR +#define CM1_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL +//CM1_CM_IGAM_LUT_30_COLOR +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L +#define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L +//CM1_CM_IGAM_LUT_PWL_DATA +#define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 +#define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL +#define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L +//CM1_CM_IGAM_LUT_AUTOFILL +#define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 +#define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L +#define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L +//CM1_CM_IGAM_LUT_BW_OFFSET_BLUE +#define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 +#define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL +#define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L +//CM1_CM_IGAM_LUT_BW_OFFSET_GREEN +#define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 +#define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL +#define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L +//CM1_CM_IGAM_LUT_BW_OFFSET_RED +#define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 +#define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL +#define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L +//CM1_CM_ICSC_CONTROL +#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM1_CM_ICSC_C11_C12 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM1_CM_ICSC_C13_C14 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM1_CM_ICSC_C21_C22 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM1_CM_ICSC_C23_C24 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM1_CM_ICSC_C31_C32 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM1_CM_ICSC_C33_C34 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_OCSC_CONTROL +#define CM1_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 +#define CM1_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L +//CM1_CM_OCSC_C11_C12 +#define CM1_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 +#define CM1_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 +#define CM1_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L +//CM1_CM_OCSC_C13_C14 +#define CM1_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 +#define CM1_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 +#define CM1_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L +//CM1_CM_OCSC_C21_C22 +#define CM1_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 +#define CM1_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 +#define CM1_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L +//CM1_CM_OCSC_C23_C24 +#define CM1_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 +#define CM1_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 +#define CM1_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L +//CM1_CM_OCSC_C31_C32 +#define CM1_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 +#define CM1_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 +#define CM1_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L +//CM1_CM_OCSC_C33_C34 +#define CM1_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 +#define CM1_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 +#define CM1_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL +#define CM1_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L +//CM1_CM_BNS_VALUES_R +#define CM1_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 +#define CM1_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 +#define CM1_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL +#define CM1_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L +//CM1_CM_BNS_VALUES_G +#define CM1_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 +#define CM1_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 +#define CM1_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL +#define CM1_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L +//CM1_CM_BNS_VALUES_B +#define CM1_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 +#define CM1_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 +#define CM1_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL +#define CM1_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_CONTROL +#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM1_CM_DGAM_LUT_INDEX +#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_DGAM_LUT_DATA +#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM1_CM_DGAM_LUT_WRITE_EN_MASK +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +//CM1_CM_DGAM_RAMA_START_CNTL_B +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_START_CNTL_G +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_START_CNTL_R +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL1_B +#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_B +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_END_CNTL1_G +#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_G +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_END_CNTL1_R +#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_R +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_REGION_0_1 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_2_3 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_4_5 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_6_7 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_8_9 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_10_11 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_12_13 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_14_15 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_START_CNTL_B +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_START_CNTL_G +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_START_CNTL_R +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL1_B +#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_B +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_END_CNTL1_G +#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_G +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_END_CNTL1_R +#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_R +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_REGION_0_1 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_2_3 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_4_5 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_6_7 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_8_9 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_10_11 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_12_13 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_14_15 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_CONTROL +#define CM1_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 +#define CM1_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L +//CM1_CM_RGAM_LUT_INDEX +#define CM1_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_RGAM_LUT_DATA +#define CM1_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL +//CM1_CM_RGAM_LUT_WRITE_EN_MASK +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L +//CM1_CM_RGAM_RAMA_START_CNTL_B +#define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_RGAM_RAMA_START_CNTL_G +#define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_RGAM_RAMA_START_CNTL_R +#define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_RGAM_RAMA_SLOPE_CNTL_B +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMA_SLOPE_CNTL_G +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMA_SLOPE_CNTL_R +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMA_END_CNTL1_B +#define CM1_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMA_END_CNTL2_B +#define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMA_END_CNTL1_G +#define CM1_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMA_END_CNTL2_G +#define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMA_END_CNTL1_R +#define CM1_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMA_END_CNTL2_R +#define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMA_REGION_0_1 +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_2_3 +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_4_5 +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_6_7 +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_8_9 +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_10_11 +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_12_13 +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_14_15 +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_16_17 +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_18_19 +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_20_21 +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_22_23 +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_24_25 +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_26_27 +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_28_29 +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_30_31 +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMA_REGION_32_33 +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_START_CNTL_B +#define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_RGAM_RAMB_START_CNTL_G +#define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_RGAM_RAMB_START_CNTL_R +#define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_RGAM_RAMB_SLOPE_CNTL_B +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMB_SLOPE_CNTL_G +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMB_SLOPE_CNTL_R +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_RGAM_RAMB_END_CNTL1_B +#define CM1_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMB_END_CNTL2_B +#define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMB_END_CNTL1_G +#define CM1_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMB_END_CNTL2_G +#define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMB_END_CNTL1_R +#define CM1_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_RGAM_RAMB_END_CNTL2_R +#define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_RGAM_RAMB_REGION_0_1 +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_2_3 +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_4_5 +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_6_7 +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_8_9 +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_10_11 +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_12_13 +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_14_15 +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_16_17 +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_18_19 +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_20_21 +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_22_23 +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_24_25 +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_26_27 +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_28_29 +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_30_31 +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_RGAM_RAMB_REGION_32_33 +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_RANGE_CLAMP_CONTROL_R +#define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 +#define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 +#define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL +#define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L +//CM1_CM_RANGE_CLAMP_CONTROL_G +#define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 +#define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 +#define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL +#define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L +//CM1_CM_RANGE_CLAMP_CONTROL_B +#define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 +#define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 +#define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL +#define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L +//CM1_CM_DENORM_CONTROL +#define CM1_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 +#define CM1_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 +#define CM1_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L +#define CM1_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L +//CM1_CM_CMOUT_CONTROL +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L +#define CM1_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L +//CM1_CM_CMOUT_RANDOM_SEEDS +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L +#define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP2_DPP_CRC_VAL_R_G +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_VAL_B_A +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG2_FCNV_FP_SCALE_BIAS +#define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 +#define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L +//CNVC_CFG2_DENORM_CONTROL +#define CNVC_CFG2_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 +#define CNVC_CFG2_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf +#define CNVC_CFG2_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 +#define CNVC_CFG2_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f +#define CNVC_CFG2_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL +#define CNVC_CFG2_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L +#define CNVC_CFG2_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L +#define CNVC_CFG2_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +//CNVC_CUR2_CURSOR0_CONTROL +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L +//CNVC_CUR2_CURSOR0_COLOR0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_COLOR1 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_OFFSET +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 +#define DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc +#define DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 +#define DSCL2_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L +#define DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L +#define DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L +#define DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L +#define DSCL2_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L +#define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_COMA_C11_C12 +#define CM2_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 +#define CM2_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 +#define CM2_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL +#define CM2_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L +//CM2_CM_COMA_C13_C14 +#define CM2_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 +#define CM2_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 +#define CM2_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL +#define CM2_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L +//CM2_CM_COMA_C21_C22 +#define CM2_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 +#define CM2_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 +#define CM2_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL +#define CM2_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L +//CM2_CM_COMA_C23_C24 +#define CM2_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 +#define CM2_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 +#define CM2_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL +#define CM2_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L +//CM2_CM_COMA_C31_C32 +#define CM2_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 +#define CM2_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 +#define CM2_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL +#define CM2_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L +//CM2_CM_COMA_C33_C34 +#define CM2_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 +#define CM2_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 +#define CM2_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL +#define CM2_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L +//CM2_CM_COMB_C11_C12 +#define CM2_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 +#define CM2_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 +#define CM2_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL +#define CM2_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L +//CM2_CM_COMB_C13_C14 +#define CM2_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 +#define CM2_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 +#define CM2_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL +#define CM2_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L +//CM2_CM_COMB_C21_C22 +#define CM2_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 +#define CM2_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 +#define CM2_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL +#define CM2_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L +//CM2_CM_COMB_C23_C24 +#define CM2_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 +#define CM2_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 +#define CM2_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL +#define CM2_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L +//CM2_CM_COMB_C31_C32 +#define CM2_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 +#define CM2_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 +#define CM2_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL +#define CM2_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L +//CM2_CM_COMB_C33_C34 +#define CM2_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 +#define CM2_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 +#define CM2_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL +#define CM2_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L +//CM2_CM_IGAM_CONTROL +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 +#define CM2_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L +#define CM2_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L +//CM2_CM_IGAM_LUT_RW_CONTROL +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L +#define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L +//CM2_CM_IGAM_LUT_RW_INDEX +#define CM2_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL +//CM2_CM_IGAM_LUT_SEQ_COLOR +#define CM2_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL +//CM2_CM_IGAM_LUT_30_COLOR +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L +#define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L +//CM2_CM_IGAM_LUT_PWL_DATA +#define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 +#define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL +#define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L +//CM2_CM_IGAM_LUT_AUTOFILL +#define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 +#define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L +#define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L +//CM2_CM_IGAM_LUT_BW_OFFSET_BLUE +#define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 +#define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL +#define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L +//CM2_CM_IGAM_LUT_BW_OFFSET_GREEN +#define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 +#define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL +#define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L +//CM2_CM_IGAM_LUT_BW_OFFSET_RED +#define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 +#define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL +#define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L +//CM2_CM_ICSC_CONTROL +#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM2_CM_ICSC_C11_C12 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM2_CM_ICSC_C13_C14 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM2_CM_ICSC_C21_C22 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM2_CM_ICSC_C23_C24 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM2_CM_ICSC_C31_C32 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM2_CM_ICSC_C33_C34 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_CONTROL +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM2_CM_GAMUT_REMAP_C11_C12 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C13_C14 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C21_C22 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C23_C24 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C31_C32 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C33_C34 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM2_CM_OCSC_CONTROL +#define CM2_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 +#define CM2_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L +//CM2_CM_OCSC_C11_C12 +#define CM2_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 +#define CM2_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 +#define CM2_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L +//CM2_CM_OCSC_C13_C14 +#define CM2_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 +#define CM2_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 +#define CM2_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L +//CM2_CM_OCSC_C21_C22 +#define CM2_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 +#define CM2_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 +#define CM2_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L +//CM2_CM_OCSC_C23_C24 +#define CM2_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 +#define CM2_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 +#define CM2_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L +//CM2_CM_OCSC_C31_C32 +#define CM2_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 +#define CM2_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 +#define CM2_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L +//CM2_CM_OCSC_C33_C34 +#define CM2_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 +#define CM2_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 +#define CM2_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL +#define CM2_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L +//CM2_CM_BNS_VALUES_R +#define CM2_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 +#define CM2_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 +#define CM2_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL +#define CM2_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L +//CM2_CM_BNS_VALUES_G +#define CM2_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 +#define CM2_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 +#define CM2_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL +#define CM2_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L +//CM2_CM_BNS_VALUES_B +#define CM2_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 +#define CM2_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 +#define CM2_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL +#define CM2_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_CONTROL +#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM2_CM_DGAM_LUT_INDEX +#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_DGAM_LUT_DATA +#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM2_CM_DGAM_LUT_WRITE_EN_MASK +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +//CM2_CM_DGAM_RAMA_START_CNTL_B +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_START_CNTL_G +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_START_CNTL_R +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL1_B +#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_B +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_END_CNTL1_G +#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_G +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_END_CNTL1_R +#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_R +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_REGION_0_1 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_2_3 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_4_5 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_6_7 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_8_9 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_10_11 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_12_13 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_14_15 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_START_CNTL_B +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_START_CNTL_G +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_START_CNTL_R +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL1_B +#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_B +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_END_CNTL1_G +#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_G +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_END_CNTL1_R +#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_R +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_REGION_0_1 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_2_3 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_4_5 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_6_7 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_8_9 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_10_11 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_12_13 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_14_15 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_CONTROL +#define CM2_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 +#define CM2_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L +//CM2_CM_RGAM_LUT_INDEX +#define CM2_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_RGAM_LUT_DATA +#define CM2_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 +#define CM2_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL +//CM2_CM_RGAM_LUT_WRITE_EN_MASK +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L +//CM2_CM_RGAM_RAMA_START_CNTL_B +#define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_RGAM_RAMA_START_CNTL_G +#define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_RGAM_RAMA_START_CNTL_R +#define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_RGAM_RAMA_SLOPE_CNTL_B +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMA_SLOPE_CNTL_G +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMA_SLOPE_CNTL_R +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMA_END_CNTL1_B +#define CM2_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMA_END_CNTL2_B +#define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMA_END_CNTL1_G +#define CM2_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMA_END_CNTL2_G +#define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMA_END_CNTL1_R +#define CM2_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMA_END_CNTL2_R +#define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMA_REGION_0_1 +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_2_3 +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_4_5 +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_6_7 +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_8_9 +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_10_11 +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_12_13 +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_14_15 +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_16_17 +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_18_19 +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_20_21 +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_22_23 +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_24_25 +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_26_27 +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_28_29 +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_30_31 +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMA_REGION_32_33 +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_START_CNTL_B +#define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_RGAM_RAMB_START_CNTL_G +#define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_RGAM_RAMB_START_CNTL_R +#define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_RGAM_RAMB_SLOPE_CNTL_B +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMB_SLOPE_CNTL_G +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMB_SLOPE_CNTL_R +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_RGAM_RAMB_END_CNTL1_B +#define CM2_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMB_END_CNTL2_B +#define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMB_END_CNTL1_G +#define CM2_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMB_END_CNTL2_G +#define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMB_END_CNTL1_R +#define CM2_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_RGAM_RAMB_END_CNTL2_R +#define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_RGAM_RAMB_REGION_0_1 +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_2_3 +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_4_5 +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_6_7 +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_8_9 +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_10_11 +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_12_13 +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_14_15 +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_16_17 +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_18_19 +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_20_21 +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_22_23 +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_24_25 +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_26_27 +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_28_29 +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_30_31 +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_RGAM_RAMB_REGION_32_33 +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_RANGE_CLAMP_CONTROL_R +#define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 +#define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 +#define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL +#define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L +//CM2_CM_RANGE_CLAMP_CONTROL_G +#define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 +#define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 +#define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL +#define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L +//CM2_CM_RANGE_CLAMP_CONTROL_B +#define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 +#define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 +#define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL +#define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L +//CM2_CM_DENORM_CONTROL +#define CM2_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 +#define CM2_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 +#define CM2_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L +#define CM2_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L +//CM2_CM_CMOUT_CONTROL +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L +#define CM2_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L +//CM2_CM_CMOUT_RANDOM_SEEDS +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L +#define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP3_DPP_CRC_VAL_R_G +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_VAL_B_A +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG3_FCNV_FP_SCALE_BIAS +#define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 +#define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L +//CNVC_CFG3_DENORM_CONTROL +#define CNVC_CFG3_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 +#define CNVC_CFG3_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf +#define CNVC_CFG3_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 +#define CNVC_CFG3_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f +#define CNVC_CFG3_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL +#define CNVC_CFG3_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L +#define CNVC_CFG3_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L +#define CNVC_CFG3_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +//CNVC_CUR3_CURSOR0_CONTROL +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L +//CNVC_CUR3_CURSOR0_COLOR0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_COLOR1 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_OFFSET +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 +#define DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc +#define DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 +#define DSCL3_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L +#define DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L +#define DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L +#define DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L +#define DSCL3_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L +#define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_COMA_C11_C12 +#define CM3_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 +#define CM3_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 +#define CM3_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL +#define CM3_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L +//CM3_CM_COMA_C13_C14 +#define CM3_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 +#define CM3_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 +#define CM3_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL +#define CM3_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L +//CM3_CM_COMA_C21_C22 +#define CM3_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 +#define CM3_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 +#define CM3_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL +#define CM3_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L +//CM3_CM_COMA_C23_C24 +#define CM3_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 +#define CM3_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 +#define CM3_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL +#define CM3_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L +//CM3_CM_COMA_C31_C32 +#define CM3_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 +#define CM3_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 +#define CM3_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL +#define CM3_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L +//CM3_CM_COMA_C33_C34 +#define CM3_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 +#define CM3_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 +#define CM3_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL +#define CM3_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L +//CM3_CM_COMB_C11_C12 +#define CM3_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 +#define CM3_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 +#define CM3_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL +#define CM3_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L +//CM3_CM_COMB_C13_C14 +#define CM3_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 +#define CM3_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 +#define CM3_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL +#define CM3_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L +//CM3_CM_COMB_C21_C22 +#define CM3_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 +#define CM3_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 +#define CM3_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL +#define CM3_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L +//CM3_CM_COMB_C23_C24 +#define CM3_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 +#define CM3_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 +#define CM3_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL +#define CM3_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L +//CM3_CM_COMB_C31_C32 +#define CM3_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 +#define CM3_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 +#define CM3_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL +#define CM3_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L +//CM3_CM_COMB_C33_C34 +#define CM3_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 +#define CM3_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 +#define CM3_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL +#define CM3_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L +//CM3_CM_IGAM_CONTROL +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 +#define CM3_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L +#define CM3_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L +//CM3_CM_IGAM_LUT_RW_CONTROL +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L +#define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L +//CM3_CM_IGAM_LUT_RW_INDEX +#define CM3_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL +//CM3_CM_IGAM_LUT_SEQ_COLOR +#define CM3_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL +//CM3_CM_IGAM_LUT_30_COLOR +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L +#define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L +//CM3_CM_IGAM_LUT_PWL_DATA +#define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 +#define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL +#define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L +//CM3_CM_IGAM_LUT_AUTOFILL +#define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 +#define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L +#define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L +//CM3_CM_IGAM_LUT_BW_OFFSET_BLUE +#define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 +#define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL +#define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L +//CM3_CM_IGAM_LUT_BW_OFFSET_GREEN +#define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 +#define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL +#define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L +//CM3_CM_IGAM_LUT_BW_OFFSET_RED +#define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 +#define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL +#define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L +//CM3_CM_ICSC_CONTROL +#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM3_CM_ICSC_C11_C12 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM3_CM_ICSC_C13_C14 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM3_CM_ICSC_C21_C22 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM3_CM_ICSC_C23_C24 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM3_CM_ICSC_C31_C32 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM3_CM_ICSC_C33_C34 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_CONTROL +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM3_CM_GAMUT_REMAP_C11_C12 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C13_C14 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C21_C22 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C23_C24 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C31_C32 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C33_C34 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM3_CM_OCSC_CONTROL +#define CM3_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 +#define CM3_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L +//CM3_CM_OCSC_C11_C12 +#define CM3_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 +#define CM3_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 +#define CM3_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L +//CM3_CM_OCSC_C13_C14 +#define CM3_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 +#define CM3_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 +#define CM3_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L +//CM3_CM_OCSC_C21_C22 +#define CM3_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 +#define CM3_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 +#define CM3_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L +//CM3_CM_OCSC_C23_C24 +#define CM3_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 +#define CM3_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 +#define CM3_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L +//CM3_CM_OCSC_C31_C32 +#define CM3_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 +#define CM3_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 +#define CM3_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L +//CM3_CM_OCSC_C33_C34 +#define CM3_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 +#define CM3_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 +#define CM3_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL +#define CM3_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L +//CM3_CM_BNS_VALUES_R +#define CM3_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 +#define CM3_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 +#define CM3_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL +#define CM3_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L +//CM3_CM_BNS_VALUES_G +#define CM3_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 +#define CM3_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 +#define CM3_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL +#define CM3_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L +//CM3_CM_BNS_VALUES_B +#define CM3_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 +#define CM3_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 +#define CM3_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL +#define CM3_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_CONTROL +#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM3_CM_DGAM_LUT_INDEX +#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_DGAM_LUT_DATA +#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM3_CM_DGAM_LUT_WRITE_EN_MASK +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +//CM3_CM_DGAM_RAMA_START_CNTL_B +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_START_CNTL_G +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_START_CNTL_R +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL1_B +#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_B +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_END_CNTL1_G +#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_G +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_END_CNTL1_R +#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_R +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_REGION_0_1 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_2_3 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_4_5 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_6_7 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_8_9 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_10_11 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_12_13 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_14_15 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_START_CNTL_B +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_START_CNTL_G +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_START_CNTL_R +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL1_B +#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_B +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_END_CNTL1_G +#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_G +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_END_CNTL1_R +#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_R +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_REGION_0_1 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_2_3 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_4_5 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_6_7 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_8_9 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_10_11 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_12_13 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_14_15 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_CONTROL +#define CM3_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 +#define CM3_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L +//CM3_CM_RGAM_LUT_INDEX +#define CM3_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_RGAM_LUT_DATA +#define CM3_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 +#define CM3_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL +//CM3_CM_RGAM_LUT_WRITE_EN_MASK +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L +//CM3_CM_RGAM_RAMA_START_CNTL_B +#define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_RGAM_RAMA_START_CNTL_G +#define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_RGAM_RAMA_START_CNTL_R +#define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_RGAM_RAMA_SLOPE_CNTL_B +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMA_SLOPE_CNTL_G +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMA_SLOPE_CNTL_R +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMA_END_CNTL1_B +#define CM3_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMA_END_CNTL2_B +#define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMA_END_CNTL1_G +#define CM3_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMA_END_CNTL2_G +#define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMA_END_CNTL1_R +#define CM3_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMA_END_CNTL2_R +#define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMA_REGION_0_1 +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_2_3 +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_4_5 +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_6_7 +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_8_9 +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_10_11 +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_12_13 +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_14_15 +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_16_17 +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_18_19 +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_20_21 +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_22_23 +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_24_25 +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_26_27 +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_28_29 +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_30_31 +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMA_REGION_32_33 +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_START_CNTL_B +#define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_RGAM_RAMB_START_CNTL_G +#define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_RGAM_RAMB_START_CNTL_R +#define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_RGAM_RAMB_SLOPE_CNTL_B +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMB_SLOPE_CNTL_G +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMB_SLOPE_CNTL_R +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_RGAM_RAMB_END_CNTL1_B +#define CM3_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMB_END_CNTL2_B +#define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMB_END_CNTL1_G +#define CM3_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMB_END_CNTL2_G +#define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMB_END_CNTL1_R +#define CM3_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_RGAM_RAMB_END_CNTL2_R +#define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_RGAM_RAMB_REGION_0_1 +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_2_3 +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_4_5 +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_6_7 +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_8_9 +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_10_11 +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_12_13 +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_14_15 +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_16_17 +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_18_19 +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_20_21 +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_22_23 +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_24_25 +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_26_27 +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_28_29 +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_30_31 +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_RGAM_RAMB_REGION_32_33 +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_RANGE_CLAMP_CONTROL_R +#define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 +#define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 +#define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL +#define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L +//CM3_CM_RANGE_CLAMP_CONTROL_G +#define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 +#define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 +#define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL +#define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L +//CM3_CM_RANGE_CLAMP_CONTROL_B +#define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 +#define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 +#define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL +#define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L +//CM3_CM_DENORM_CONTROL +#define CM3_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 +#define CM3_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 +#define CM3_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L +#define CM3_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L +//CM3_CM_CMOUT_CONTROL +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L +#define CM3_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L +//CM3_CM_CMOUT_RANDOM_SEEDS +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L +#define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L +//MPCC0_MPCC_TOP_OFFSET +#define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 +#define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 +#define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL +#define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L +//MPCC0_MPCC_BOT_OFFSET +#define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 +#define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 +#define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL +#define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L +//MPCC0_MPCC_OFFSET +#define MPCC0_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 +#define MPCC0_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 +#define MPCC0_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL +#define MPCC0_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_STALL_STATUS +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 +#define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 +#define MPCC0_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 +#define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 +#define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 +#define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 +#define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 +#define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 +#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L +//MPCC1_MPCC_TOP_OFFSET +#define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 +#define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 +#define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL +#define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L +//MPCC1_MPCC_BOT_OFFSET +#define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 +#define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 +#define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL +#define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L +//MPCC1_MPCC_OFFSET +#define MPCC1_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 +#define MPCC1_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 +#define MPCC1_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL +#define MPCC1_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_STALL_STATUS +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 +#define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 +#define MPCC1_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 +#define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 +#define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 +#define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 +#define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 +#define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 +#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L +//MPCC2_MPCC_TOP_OFFSET +#define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 +#define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 +#define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL +#define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L +//MPCC2_MPCC_BOT_OFFSET +#define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 +#define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 +#define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL +#define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L +//MPCC2_MPCC_OFFSET +#define MPCC2_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 +#define MPCC2_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 +#define MPCC2_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL +#define MPCC2_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_STALL_STATUS +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 +#define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 +#define MPCC2_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 +#define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 +#define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 +#define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 +#define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 +#define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 +#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L +//MPCC3_MPCC_TOP_OFFSET +#define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 +#define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 +#define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL +#define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L +//MPCC3_MPCC_BOT_OFFSET +#define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 +#define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 +#define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL +#define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L +//MPCC3_MPCC_OFFSET +#define MPCC3_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 +#define MPCC3_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 +#define MPCC3_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL +#define MPCC3_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_STALL_STATUS +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 +#define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 +#define MPCC3_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 +#define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 +#define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 +#define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 +#define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 +#define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 +#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_STALL_GRACE_WINDOW +#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT 0x0 +#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK 0x000000FFL +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +#define ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR0_VUPDATE_LOCK_SET0 +#define CUR0_VUPDATE_LOCK_SET0__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR0_VUPDATE_LOCK_SET0__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR1_VUPDATE_LOCK_SET0 +#define CUR1_VUPDATE_LOCK_SET0__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR1_VUPDATE_LOCK_SET0__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +#define ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR0_VUPDATE_LOCK_SET1 +#define CUR0_VUPDATE_LOCK_SET1__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR0_VUPDATE_LOCK_SET1__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR1_VUPDATE_LOCK_SET1 +#define CUR1_VUPDATE_LOCK_SET1__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR1_VUPDATE_LOCK_SET1__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +#define ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR0_VUPDATE_LOCK_SET2 +#define CUR0_VUPDATE_LOCK_SET2__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR0_VUPDATE_LOCK_SET2__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR1_VUPDATE_LOCK_SET2 +#define CUR1_VUPDATE_LOCK_SET2__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR1_VUPDATE_LOCK_SET2__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +#define ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR0_VUPDATE_LOCK_SET3 +#define CUR0_VUPDATE_LOCK_SET3__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR0_VUPDATE_LOCK_SET3__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR1_VUPDATE_LOCK_SET3 +#define CUR1_VUPDATE_LOCK_SET3__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR1_VUPDATE_LOCK_SET3__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_BL1_PWM_GRP2_REG_LOCK +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_12 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_THRES_34 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_1 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_2 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_3 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_4 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_5 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_6 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_7 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_8 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_9 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_10 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_11 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_12 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_13 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_14 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_15 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_16 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_17 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_18 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_19 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_20 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_21 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_22 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_23 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_24 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_BL1_PWM_GRP2_REG_LOCK +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_12 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_THRES_34 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_1 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_2 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_3 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_4 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_5 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_6 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_7 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_8 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_9 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_10 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_11 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_12 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_13 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_14 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_15 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_16 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_17 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_18 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_19 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_20 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_21 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_22 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_23 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_24 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt4_dispdec +//FMT4_FMT_CLAMP_COMPONENT_R +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_COMPONENT_G +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_COMPONENT_B +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT4_FMT_DYNAMIC_EXP_CNTL +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT4_FMT_CONTROL +#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT4_FMT_BIT_DEPTH_CONTROL +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT4_FMT_DITHER_RAND_R_SEED +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT4_FMT_DITHER_RAND_G_SEED +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT4_FMT_DITHER_RAND_B_SEED +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_CNTL +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT4_FMT_MAP420_MEMORY_CONTROL +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf4_dispdec +//OPPBUF4_OPPBUF_CONTROL +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF4_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF4_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe4_dispdec +//OPP_PIPE4_OPP_PIPE_CONTROL +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec +//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt5_dispdec +//FMT5_FMT_CLAMP_COMPONENT_R +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_COMPONENT_G +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_COMPONENT_B +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT5_FMT_DYNAMIC_EXP_CNTL +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT5_FMT_CONTROL +#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT5_FMT_BIT_DEPTH_CONTROL +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT5_FMT_DITHER_RAND_R_SEED +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT5_FMT_DITHER_RAND_G_SEED +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT5_FMT_DITHER_RAND_B_SEED +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_CNTL +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT5_FMT_MAP420_MEMORY_CONTROL +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_opp_oppbuf5_dispdec +//OPPBUF5_OPPBUF_CONTROL +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF5_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF5_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L + + +// addressBlock: dce_dc_opp_opp_pipe5_dispdec +//OPP_PIPE5_OPP_PIPE_CONTROL +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec +//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON17_PERFCOUNTER_CNTL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_CNTL2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_STATE +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON17_PERFMON_CNTL +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON17_PERFMON_CNTL2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON17_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON17_PERFMON_CVALUE_LOW +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON17_PERFMON_HI +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFMON_LOW +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm4_dispdec +//ODM4_OPTC_INPUT_GLOBAL_CONTROL +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM4_OPTC_DATA_SOURCE_SELECT +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM4_OPTC_INPUT_CLOCK_CONTROL +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM4_OPTC_INPUT_SPARE_REGISTER +#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm5_dispdec +//ODM5_OPTC_INPUT_GLOBAL_CONTROL +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +//ODM5_OPTC_DATA_SOURCE_SELECT +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L +//ODM5_OPTC_INPUT_CLOCK_CONTROL +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM5_OPTC_INPUT_SPARE_REGISTER +#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG0_OTG_AVSYNC_COUNTER +#define OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG0_OTG_BLANK_CONTROL +#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG0_OTG_PIPE_ABORT_CONTROL +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_FIELD_INDICATION_CONTROL +#define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_TEST_PATTERN_CONTROL +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG0_OTG_TEST_PATTERN_PARAMETERS +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG0_OTG_TEST_PATTERN_COLOR +#define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_BLANK_DATA_COLOR +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG0_OTG_BLANK_DATA_COLOR_EXT +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG0_OTG_BLACK_COLOR +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG0_OTG_BLACK_COLOR_EXT +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_RANGE_TIMING_INT_STATUS +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG1_OTG_AVSYNC_COUNTER +#define OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG1_OTG_BLANK_CONTROL +#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG1_OTG_PIPE_ABORT_CONTROL +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_FIELD_INDICATION_CONTROL +#define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_TEST_PATTERN_CONTROL +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG1_OTG_TEST_PATTERN_PARAMETERS +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG1_OTG_TEST_PATTERN_COLOR +#define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_BLANK_DATA_COLOR +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG1_OTG_BLANK_DATA_COLOR_EXT +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG1_OTG_BLACK_COLOR +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG1_OTG_BLACK_COLOR_EXT +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_RANGE_TIMING_INT_STATUS +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_FLOW_CONTROL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG2_OTG_AVSYNC_COUNTER +#define OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG2_OTG_BLANK_CONTROL +#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG2_OTG_PIPE_ABORT_CONTROL +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_FIELD_INDICATION_CONTROL +#define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_TEST_PATTERN_CONTROL +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG2_OTG_TEST_PATTERN_PARAMETERS +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG2_OTG_TEST_PATTERN_COLOR +#define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_BLANK_DATA_COLOR +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG2_OTG_BLANK_DATA_COLOR_EXT +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG2_OTG_BLACK_COLOR +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG2_OTG_BLACK_COLOR_EXT +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_RG +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_RG +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_RG +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_RG +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_MANUAL_FLOW_CONTROL +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG2_OTG_RANGE_TIMING_INT_STATUS +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_FLOW_CONTROL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG3_OTG_AVSYNC_COUNTER +#define OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG3_OTG_BLANK_CONTROL +#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG3_OTG_PIPE_ABORT_CONTROL +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_FIELD_INDICATION_CONTROL +#define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_TEST_PATTERN_CONTROL +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG3_OTG_TEST_PATTERN_PARAMETERS +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG3_OTG_TEST_PATTERN_COLOR +#define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_BLANK_DATA_COLOR +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG3_OTG_BLANK_DATA_COLOR_EXT +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG3_OTG_BLACK_COLOR +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG3_OTG_BLACK_COLOR_EXT +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_RG +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_RG +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_RG +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_RG +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_MANUAL_FLOW_CONTROL +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG3_OTG_RANGE_TIMING_INT_STATUS +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg4_dispdec +//OTG4_OTG_H_TOTAL +#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG4_OTG_H_BLANK_START_END +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG4_OTG_H_SYNC_A +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG4_OTG_H_SYNC_A_CNTL +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG4_OTG_H_TIMING_CNTL +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG4_OTG_V_TOTAL +#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MIN +#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MAX +#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MID +#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_CONTROL +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG4_OTG_V_TOTAL_INT_STATUS +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG4_OTG_VSYNC_NOM_INT_STATUS +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG4_OTG_V_BLANK_START_END +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG4_OTG_V_SYNC_A +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG4_OTG_V_SYNC_A_CNTL +#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG4_OTG_TRIGA_CNTL +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG4_OTG_TRIGA_MANUAL_TRIG +#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG4_OTG_TRIGB_CNTL +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG4_OTG_TRIGB_MANUAL_TRIG +#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG4_OTG_FORCE_COUNT_NOW_CNTL +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG4_OTG_FLOW_CONTROL +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG4_OTG_STEREO_FORCE_NEXT_EYE +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG4_OTG_AVSYNC_COUNTER +#define OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG4_OTG_CONTROL +#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG4_OTG_BLANK_CONTROL +#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG4_OTG_PIPE_ABORT_CONTROL +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG4_OTG_INTERLACE_CONTROL +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG4_OTG_INTERLACE_STATUS +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG4_OTG_FIELD_INDICATION_CONTROL +#define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG4_OTG_PIXEL_DATA_READBACK0 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG4_OTG_PIXEL_DATA_READBACK1 +#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG4_OTG_STATUS +#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG4_OTG_STATUS_POSITION +#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG4_OTG_NOM_VERT_POSITION +#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG4_OTG_STATUS_FRAME_COUNT +#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG4_OTG_STATUS_VF_COUNT +#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG4_OTG_STATUS_HV_COUNT +#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG4_OTG_COUNT_CONTROL +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG4_OTG_COUNT_RESET +#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG4_OTG_VERT_SYNC_CONTROL +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG4_OTG_STEREO_STATUS +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG4_OTG_STEREO_CONTROL +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG4_OTG_SNAPSHOT_STATUS +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG4_OTG_SNAPSHOT_CONTROL +#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG4_OTG_SNAPSHOT_POSITION +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG4_OTG_SNAPSHOT_FRAME +#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG4_OTG_INTERRUPT_CONTROL +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG4_OTG_UPDATE_LOCK +#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG4_OTG_DOUBLE_BUFFER_CONTROL +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG4_OTG_TEST_PATTERN_CONTROL +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG4_OTG_TEST_PATTERN_PARAMETERS +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG4_OTG_TEST_PATTERN_COLOR +#define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG4_OTG_MASTER_EN +#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG4_OTG_BLANK_DATA_COLOR +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG4_OTG_BLANK_DATA_COLOR_EXT +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG4_OTG_BLACK_COLOR +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG4_OTG_BLACK_COLOR_EXT +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_CRC_CNTL +#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG4_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_DATA_RG +#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC0_DATA_B +#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_DATA_RG +#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC1_DATA_B +#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC2_DATA_RG +#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC2_DATA_B +#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC3_DATA_RG +#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC3_DATA_B +#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG4_OTG_STATIC_SCREEN_CONTROL +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG4_OTG_3D_STRUCTURE_CONTROL +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG4_OTG_GSL_VSYNC_GAP +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG4_OTG_MASTER_UPDATE_MODE +#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG4_OTG_CLOCK_CONTROL +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG4_OTG_VSTARTUP_PARAM +#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG4_OTG_VUPDATE_PARAM +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG4_OTG_VREADY_PARAM +#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG4_OTG_GLOBAL_SYNC_STATUS +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG4_OTG_MASTER_UPDATE_LOCK +#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG4_OTG_GSL_CONTROL +#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG4_OTG_GSL_WINDOW_X +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG4_OTG_GSL_WINDOW_Y +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG4_OTG_VUPDATE_KEEPOUT +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL0 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG4_OTG_GLOBAL_CONTROL1 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL2 +#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL3 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG4_OTG_TRIG_MANUAL_CONTROL +#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG4_OTG_MANUAL_FLOW_CONTROL +#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG4_OTG_RANGE_TIMING_INT_STATUS +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG4_OTG_DRR_CONTROL +#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG4_OTG_REQUEST_CONTROL +#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG4_OTG_SPARE_REGISTER +#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg5_dispdec +//OTG5_OTG_H_TOTAL +#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG5_OTG_H_BLANK_START_END +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG5_OTG_H_SYNC_A +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG5_OTG_H_SYNC_A_CNTL +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG5_OTG_H_TIMING_CNTL +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG5_OTG_V_TOTAL +#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MIN +#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MAX +#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MID +#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_CONTROL +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG5_OTG_V_TOTAL_INT_STATUS +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +//OTG5_OTG_VSYNC_NOM_INT_STATUS +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG5_OTG_V_BLANK_START_END +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG5_OTG_V_SYNC_A +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG5_OTG_V_SYNC_A_CNTL +#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG5_OTG_TRIGA_CNTL +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG5_OTG_TRIGA_MANUAL_TRIG +#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG5_OTG_TRIGB_CNTL +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG5_OTG_TRIGB_MANUAL_TRIG +#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG5_OTG_FORCE_COUNT_NOW_CNTL +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG5_OTG_FLOW_CONTROL +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG5_OTG_STEREO_FORCE_NEXT_EYE +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG5_OTG_AVSYNC_COUNTER +#define OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 +#define OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL +//OTG5_OTG_CONTROL +#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +//OTG5_OTG_BLANK_CONTROL +#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG5_OTG_PIPE_ABORT_CONTROL +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG5_OTG_INTERLACE_CONTROL +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG5_OTG_INTERLACE_STATUS +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG5_OTG_FIELD_INDICATION_CONTROL +#define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 +#define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L +#define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L +//OTG5_OTG_PIXEL_DATA_READBACK0 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG5_OTG_PIXEL_DATA_READBACK1 +#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG5_OTG_STATUS +#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG5_OTG_STATUS_POSITION +#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG5_OTG_NOM_VERT_POSITION +#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG5_OTG_STATUS_FRAME_COUNT +#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG5_OTG_STATUS_VF_COUNT +#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG5_OTG_STATUS_HV_COUNT +#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG5_OTG_COUNT_CONTROL +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG5_OTG_COUNT_RESET +#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG5_OTG_VERT_SYNC_CONTROL +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG5_OTG_STEREO_STATUS +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG5_OTG_STEREO_CONTROL +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG5_OTG_SNAPSHOT_STATUS +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG5_OTG_SNAPSHOT_CONTROL +#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG5_OTG_SNAPSHOT_POSITION +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG5_OTG_SNAPSHOT_FRAME +#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG5_OTG_INTERRUPT_CONTROL +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG5_OTG_UPDATE_LOCK +#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG5_OTG_DOUBLE_BUFFER_CONTROL +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG5_OTG_TEST_PATTERN_CONTROL +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L +//OTG5_OTG_TEST_PATTERN_PARAMETERS +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L +#define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L +//OTG5_OTG_TEST_PATTERN_COLOR +#define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 +#define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 +#define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL +#define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L +//OTG5_OTG_MASTER_EN +#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG5_OTG_BLANK_DATA_COLOR +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG5_OTG_BLANK_DATA_COLOR_EXT +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG5_OTG_BLACK_COLOR +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG5_OTG_BLACK_COLOR_EXT +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_CRC_CNTL +#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG5_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_DATA_RG +#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC0_DATA_B +#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_DATA_RG +#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC1_DATA_B +#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC2_DATA_RG +#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC2_DATA_B +#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC3_DATA_RG +#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC3_DATA_B +#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG5_OTG_STATIC_SCREEN_CONTROL +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG5_OTG_3D_STRUCTURE_CONTROL +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG5_OTG_GSL_VSYNC_GAP +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG5_OTG_MASTER_UPDATE_MODE +#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG5_OTG_CLOCK_CONTROL +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG5_OTG_VSTARTUP_PARAM +#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG5_OTG_VUPDATE_PARAM +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG5_OTG_VREADY_PARAM +#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG5_OTG_GLOBAL_SYNC_STATUS +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG5_OTG_MASTER_UPDATE_LOCK +#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG5_OTG_GSL_CONTROL +#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +//OTG5_OTG_GSL_WINDOW_X +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG5_OTG_GSL_WINDOW_Y +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG5_OTG_VUPDATE_KEEPOUT +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL0 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG5_OTG_GLOBAL_CONTROL1 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL2 +#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL3 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG5_OTG_TRIG_MANUAL_CONTROL +#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG5_OTG_MANUAL_FLOW_CONTROL +#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG5_OTG_RANGE_TIMING_INT_STATUS +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG5_OTG_DRR_CONTROL +#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG5_OTG_REQUEST_CONTROL +#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG5_OTG_SPARE_REGISTER +#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//DWB_SOURCE_SELECT +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON18_PERFCOUNTER_CNTL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_CNTL2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_STATE +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON18_PERFMON_CNTL +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON18_PERFMON_CNTL2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON18_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON18_PERFMON_CVALUE_LOW +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON18_PERFMON_HI +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFMON_LOW +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dac_dispdec +//DAC_ENABLE +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000CL +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L +//DAC_SOURCE_SELECT +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L +//DAC_CRC_EN +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L +//DAC_CRC_CONTROL +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x00000100L +//DAC_CRC_SIG_RGB_MASK +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003FFL +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000FFC00L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3FF00000L +//DAC_CRC_SIG_CONTROL_MASK +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003FL +//DAC_CRC_SIG_RGB +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003FFL +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000FFC00L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3FF00000L +//DAC_CRC_SIG_CONTROL +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003FL +//DAC_SYNC_TRISTATE_CONTROL +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L +//DAC_STEREOSYNC_SELECT +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L +//DAC_AUTODETECT_CONTROL +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000FF00L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L +//DAC_AUTODETECT_CONTROL2 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000FFL +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L +//DAC_AUTODETECT_CONTROL3 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000FFL +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000FF00L +//DAC_AUTODETECT_STATUS +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L +//DAC_AUTODETECT_INT_CONTROL +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L +//DAC_FORCE_OUTPUT_CNTL +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x01000000L +//DAC_FORCE_DATA +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003FFL +//DAC_POWERDOWN +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L +//DAC_CONTROL +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L +//DAC_COMPARATOR_ENABLE +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L +//DAC_COMPARATOR_OUTPUT +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L +//DAC_PWR_CNTL +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L +//DAC_DFT_CONFIG +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xFFFFFFFFL +//DAC_FIFO_STATUS +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000F0000L +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC6_HW_STATUS +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC6_SPEED +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC6_SETUP +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_DDCVGA_HW_STATUS +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDCVGA_SPEED +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDCVGA_SETUP +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_generic_i2c_dispdec +//GENERIC_I2C_CONTROL +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L +//GENERIC_I2C_INTERRUPT_CONTROL +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L +//GENERIC_I2C_STATUS +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000FL +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L +//GENERIC_I2C_SPEED +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xFFFF0000L +//GENERIC_I2C_SETUP +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xFF000000L +//GENERIC_I2C_TRANSACTION +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000F0000L +//GENERIC_I2C_DATA +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000FF00L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000F0000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L +//GENERIC_I2C_PIN_SELECTION +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007FL +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007F00L + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DCE_VCE_CONTROL +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa +#define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc +#define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe +#define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 +#define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 +#define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 +#define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +#define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L +#define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L +#define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L +#define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L +#define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L +#define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L +#define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb +#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd +#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe +#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 +#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 +#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 +#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 +#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 +#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 +#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L +#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L +#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L +#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L +#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L +#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L +#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L +#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L +#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L +#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L +#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L +#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE__SHIFT 0xb +#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS__SHIFT 0xc +#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE__SHIFT 0xd +#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS__SHIFT 0xe +#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE__SHIFT 0xf +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L +#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE_MASK 0x00000800L +#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE_MASK 0x00002000L +#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE_MASK 0x00008000L +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIO_STEREOSYNC_SEL +#define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 +#define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 +#define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L +#define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L +//DIO_SOFT_RESET +#define DIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 +#define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 +#define DIO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 +#define DIO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 +#define DIO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc +#define DIO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b +#define DIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L +#define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x00000010L +#define DIO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x00000020L +#define DIO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x00000040L +#define DIO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x00001000L +#define DIO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_MEM_PWR_STATUS1 +#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT 0x2 +#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT 0xa +#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK 0x00000004L +#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK 0x00000400L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_PSP_INTERRUPT_STATUS +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_PSP_INTERRUPT_CLEAR +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L +//DIO_GENERIC_INTERRUPT_MESSAGE +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_GENERIC_INTERRUPT_CLEAR +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd5_dispdec +//HPD5_DC_HPD_INT_STATUS +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD5_DC_HPD_INT_CONTROL +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD5_DC_HPD_CONTROL +#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD5_DC_HPD_FAST_TRAIN_CNTL +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD5_DC_HPD_TOGGLE_FILT_CNTL +#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON19_PERFCOUNTER_CNTL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_CNTL2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_STATE +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON19_PERFMON_CNTL +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON19_PERFMON_CNTL2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON19_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON19_PERFMON_CVALUE_LOW +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON19_PERFMON_HI +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFMON_LOW +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_STATUS +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_STATUS +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_STATUS +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux5_dispdec +//DP_AUX5_AUX_CONTROL +#define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX5_AUX_SW_CONTROL +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX5_AUX_ARB_CONTROL +#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX5_AUX_INTERRUPT_CONTROL +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX5_AUX_SW_STATUS +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX5_AUX_LS_STATUS +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX5_AUX_SW_DATA +#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX5_AUX_LS_DATA +#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX5_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX5_AUX_DPHY_TX_CONTROL +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX5_AUX_DPHY_RX_CONTROL0 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX5_AUX_DPHY_RX_CONTROL1 +#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX5_AUX_DPHY_TX_STATUS +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX5_AUX_DPHY_RX_STATUS +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX5_AUX_GTC_SYNC_STATUS +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dp_aux6_dispdec +//DP_AUX6_AUX_CONTROL +#define DP_AUX6_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX6_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX6_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX6_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX6_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX6_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX6_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX6_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX6_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX6_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX6_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX6_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX6_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX6_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX6_AUX_SW_CONTROL +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX6_AUX_ARB_CONTROL +#define DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX6_AUX_INTERRUPT_CONTROL +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX6_AUX_SW_STATUS +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L +//DP_AUX6_AUX_LS_STATUS +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX6_AUX_SW_DATA +#define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX6_AUX_LS_DATA +#define DP_AUX6_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX6_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX6_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX6_AUX_DPHY_TX_CONTROL +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX6_AUX_DPHY_RX_CONTROL0 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX6_AUX_DPHY_RX_CONTROL1 +#define DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +//DP_AUX6_AUX_DPHY_TX_STATUS +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX6_AUX_DPHY_RX_STATUS +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX6_AUX_GTC_SYNC_STATUS +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_STATUS +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG0_AFMT_INTERRUPT_STATUS +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG0_AFMT_ISRC1_0 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG0_AFMT_ISRC1_1 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_2 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_3 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_4 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_0 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_1 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_2 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_3 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG0_AFMT_MPEG_INFO0 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG0_AFMT_MPEG_INFO1 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG0_AFMT_GENERIC_HDR +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_0 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_1 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_2 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_3 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_4 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_5 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_6 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_7 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_AUDIO_INFO0 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG0_AFMT_AUDIO_INFO1 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG0_AFMT_60958_0 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG0_AFMT_60958_1 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG0_AFMT_AUDIO_CRC_CONTROL +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG0_AFMT_RAMP_CONTROL0 +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG0_AFMT_RAMP_CONTROL1 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG0_AFMT_RAMP_CONTROL2 +#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG0_AFMT_RAMP_CONTROL3 +#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG0_AFMT_60958_2 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG0_AFMT_AUDIO_CRC_RESULT +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG0_AFMT_STATUS +#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG0_AFMT_AUDIO_PACKET_CONTROL +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG0_AFMT_VBI_PACKET_CONTROL +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG0_AFMT_INFOFRAME_CONTROL0 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG0_AFMT_AUDIO_SRC_CONTROL +#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_DIG_LANE_ENABLE +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_AFMT_VBI_PACKET_CONTROL1 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_STATUS +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG1_AFMT_INTERRUPT_STATUS +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG1_AFMT_ISRC1_0 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG1_AFMT_ISRC1_1 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_2 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_3 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_4 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_0 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_1 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_2 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_3 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG1_AFMT_MPEG_INFO0 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG1_AFMT_MPEG_INFO1 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG1_AFMT_GENERIC_HDR +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_0 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_1 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_2 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_3 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_4 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_5 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_6 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_7 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_AUDIO_INFO0 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG1_AFMT_AUDIO_INFO1 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG1_AFMT_60958_0 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG1_AFMT_60958_1 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG1_AFMT_AUDIO_CRC_CONTROL +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG1_AFMT_RAMP_CONTROL0 +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG1_AFMT_RAMP_CONTROL1 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG1_AFMT_RAMP_CONTROL2 +#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG1_AFMT_RAMP_CONTROL3 +#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG1_AFMT_60958_2 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG1_AFMT_AUDIO_CRC_RESULT +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG1_AFMT_STATUS +#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG1_AFMT_AUDIO_PACKET_CONTROL +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG1_AFMT_VBI_PACKET_CONTROL +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG1_AFMT_INFOFRAME_CONTROL0 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG1_AFMT_AUDIO_SRC_CONTROL +#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_DIG_LANE_ENABLE +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_AFMT_VBI_PACKET_CONTROL1 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_STATUS +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG2_HDMI_INFOFRAME_CONTROL1 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG2_AFMT_INTERRUPT_STATUS +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG2_AFMT_ISRC1_0 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG2_AFMT_ISRC1_1 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_2 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_3 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_4 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_0 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_1 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_2 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_3 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG2_AFMT_MPEG_INFO0 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG2_AFMT_MPEG_INFO1 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG2_AFMT_GENERIC_HDR +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_0 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_1 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_2 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_3 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_4 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_5 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_6 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_7 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_AFMT_AUDIO_INFO0 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG2_AFMT_AUDIO_INFO1 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG2_AFMT_60958_0 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG2_AFMT_60958_1 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG2_AFMT_AUDIO_CRC_CONTROL +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG2_AFMT_RAMP_CONTROL0 +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG2_AFMT_RAMP_CONTROL1 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG2_AFMT_RAMP_CONTROL2 +#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG2_AFMT_RAMP_CONTROL3 +#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG2_AFMT_60958_2 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG2_AFMT_AUDIO_CRC_RESULT +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG2_AFMT_STATUS +#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG2_AFMT_AUDIO_PACKET_CONTROL +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG2_AFMT_VBI_PACKET_CONTROL +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG2_AFMT_INFOFRAME_CONTROL0 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG2_AFMT_AUDIO_SRC_CONTROL +#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG2_DIG_LANE_ENABLE +#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG2_AFMT_CNTL +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG2_AFMT_VBI_PACKET_CONTROL1 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_EN +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CNTL +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP2_DP_DPHY_CRC_RESULT +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP2_DP_DPHY_CRC_MST_CNTL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_MST_STATUS +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_DSC_CNTL +#define DP2_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP2_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_STATUS +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG3_HDMI_INFOFRAME_CONTROL1 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG3_AFMT_INTERRUPT_STATUS +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG3_AFMT_ISRC1_0 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG3_AFMT_ISRC1_1 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_2 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_3 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_4 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_0 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_1 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_2 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_3 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG3_AFMT_MPEG_INFO0 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG3_AFMT_MPEG_INFO1 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG3_AFMT_GENERIC_HDR +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_0 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_1 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_2 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_3 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_4 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_5 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_6 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_7 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_AFMT_AUDIO_INFO0 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG3_AFMT_AUDIO_INFO1 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG3_AFMT_60958_0 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG3_AFMT_60958_1 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG3_AFMT_AUDIO_CRC_CONTROL +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG3_AFMT_RAMP_CONTROL0 +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG3_AFMT_RAMP_CONTROL1 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG3_AFMT_RAMP_CONTROL2 +#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG3_AFMT_RAMP_CONTROL3 +#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG3_AFMT_60958_2 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG3_AFMT_AUDIO_CRC_RESULT +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG3_AFMT_STATUS +#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG3_AFMT_AUDIO_PACKET_CONTROL +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG3_AFMT_VBI_PACKET_CONTROL +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG3_AFMT_INFOFRAME_CONTROL0 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG3_AFMT_AUDIO_SRC_CONTROL +#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG3_DIG_LANE_ENABLE +#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG3_AFMT_CNTL +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG3_AFMT_VBI_PACKET_CONTROL1 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_EN +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CNTL +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP3_DP_DPHY_CRC_RESULT +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP3_DP_DPHY_CRC_MST_CNTL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_MST_STATUS +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_DSC_CNTL +#define DP3_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP3_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_STATUS +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG4_HDMI_INFOFRAME_CONTROL1 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG4_AFMT_INTERRUPT_STATUS +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG4_AFMT_ISRC1_0 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG4_AFMT_ISRC1_1 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_2 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_3 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_4 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_0 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_1 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_2 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_3 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG4_AFMT_MPEG_INFO0 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG4_AFMT_MPEG_INFO1 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG4_AFMT_GENERIC_HDR +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_0 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_1 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_2 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_3 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_4 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_5 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_6 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_7 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_AFMT_AUDIO_INFO0 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG4_AFMT_AUDIO_INFO1 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG4_AFMT_60958_0 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG4_AFMT_60958_1 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG4_AFMT_AUDIO_CRC_CONTROL +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG4_AFMT_RAMP_CONTROL0 +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG4_AFMT_RAMP_CONTROL1 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG4_AFMT_RAMP_CONTROL2 +#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG4_AFMT_RAMP_CONTROL3 +#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG4_AFMT_60958_2 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG4_AFMT_AUDIO_CRC_RESULT +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG4_AFMT_STATUS +#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG4_AFMT_AUDIO_PACKET_CONTROL +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG4_AFMT_VBI_PACKET_CONTROL +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG4_AFMT_INFOFRAME_CONTROL0 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG4_AFMT_AUDIO_SRC_CONTROL +#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG4_DIG_LANE_ENABLE +#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG4_AFMT_CNTL +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG4_AFMT_VBI_PACKET_CONTROL1 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_EN +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CNTL +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP4_DP_DPHY_CRC_RESULT +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP4_DP_DPHY_CRC_MST_CNTL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_MST_STATUS +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_DSC_CNTL +#define DP4_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP4_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig5_dispdec +//DIG5_DIG_FE_CNTL +#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG5_DIG_OUTPUT_CRC_CNTL +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG5_DIG_OUTPUT_CRC_RESULT +#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG5_DIG_CLOCK_PATTERN +#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG5_DIG_TEST_PATTERN +#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG5_DIG_RANDOM_PATTERN_SEED +#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG5_DIG_FIFO_STATUS +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG5_HDMI_CONTROL +#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG5_HDMI_STATUS +#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG5_HDMI_AUDIO_PACKET_CONTROL +#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG5_HDMI_ACR_PACKET_CONTROL +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG5_HDMI_VBI_PACKET_CONTROL +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG5_HDMI_INFOFRAME_CONTROL0 +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG5_HDMI_INFOFRAME_CONTROL1 +#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG5_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG5_AFMT_INTERRUPT_STATUS +//DIG5_HDMI_GC +#define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG5_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG5_AFMT_ISRC1_0 +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG5_AFMT_ISRC1_1 +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG5_AFMT_ISRC1_2 +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG5_AFMT_ISRC1_3 +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG5_AFMT_ISRC1_4 +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG5_AFMT_ISRC2_0 +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG5_AFMT_ISRC2_1 +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG5_AFMT_ISRC2_2 +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG5_AFMT_ISRC2_3 +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG5_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG5_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG5_HDMI_DB_CONTROL +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG5_AFMT_MPEG_INFO0 +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG5_AFMT_MPEG_INFO1 +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG5_AFMT_GENERIC_HDR +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_0 +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_1 +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_2 +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_3 +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_4 +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_5 +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_6 +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG5_AFMT_GENERIC_7 +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG5_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG5_HDMI_ACR_32_0 +#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG5_HDMI_ACR_32_1 +#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG5_HDMI_ACR_44_0 +#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG5_HDMI_ACR_44_1 +#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG5_HDMI_ACR_48_0 +#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG5_HDMI_ACR_48_1 +#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG5_HDMI_ACR_STATUS_0 +#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG5_HDMI_ACR_STATUS_1 +#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG5_AFMT_AUDIO_INFO0 +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG5_AFMT_AUDIO_INFO1 +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG5_AFMT_60958_0 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG5_AFMT_60958_1 +#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG5_AFMT_AUDIO_CRC_CONTROL +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG5_AFMT_RAMP_CONTROL0 +#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG5_AFMT_RAMP_CONTROL1 +#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG5_AFMT_RAMP_CONTROL2 +#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG5_AFMT_RAMP_CONTROL3 +#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG5_AFMT_60958_2 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG5_AFMT_AUDIO_CRC_RESULT +#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG5_AFMT_STATUS +#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG5_AFMT_AUDIO_PACKET_CONTROL +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG5_AFMT_VBI_PACKET_CONTROL +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG5_AFMT_INFOFRAME_CONTROL0 +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG5_AFMT_AUDIO_SRC_CONTROL +#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG5_DIG_BE_CNTL +#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG5_DIG_BE_EN_CNTL +#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG5_TMDS_CNTL +#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG5_TMDS_CONTROL_CHAR +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG5_TMDS_CONTROL0_FEEDBACK +#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG5_TMDS_STEREOSYNC_CTL_SEL +#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG5_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG5_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG5_TMDS_CTL_BITS +#define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG5_TMDS_DCBALANCER_CONTROL +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG5_TMDS_CTL0_1_GEN_CNTL +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG5_TMDS_CTL2_3_GEN_CNTL +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG5_DIG_VERSION +#define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG5_DIG_LANE_ENABLE +#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG5_AFMT_CNTL +#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG5_AFMT_VBI_PACKET_CONTROL1 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp5_dispdec +//DP5_DP_LINK_CNTL +#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP5_DP_PIXEL_FORMAT +#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP5_DP_MSA_COLORIMETRY +#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP5_DP_CONFIG +#define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP5_DP_VID_STREAM_CNTL +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP5_DP_STEER_FIFO +#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP5_DP_MSA_MISC +#define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP5_DP_VID_TIMING +#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP5_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP5_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP5_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP5_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP5_DP_VID_N +#define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP5_DP_VID_M +#define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP5_DP_LINK_FRAMING_CNTL +#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP5_DP_HBR2_EYE_PATTERN +#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP5_DP_VID_MSA_VBID +#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP5_DP_VID_INTERRUPT_CNTL +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP5_DP_DPHY_CNTL +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP5_DP_DPHY_TRAINING_PATTERN_SEL +#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP5_DP_DPHY_SYM0 +#define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP5_DP_DPHY_SYM1 +#define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP5_DP_DPHY_SYM2 +#define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP5_DP_DPHY_8B10B_CNTL +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP5_DP_DPHY_PRBS_CNTL +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP5_DP_DPHY_SCRAM_CNTL +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP5_DP_DPHY_CRC_EN +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP5_DP_DPHY_CRC_CNTL +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP5_DP_DPHY_CRC_RESULT +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP5_DP_DPHY_CRC_MST_CNTL +#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP5_DP_DPHY_CRC_MST_STATUS +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP5_DP_DPHY_FAST_TRAINING +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP5_DP_DPHY_FAST_TRAINING_STATUS +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP5_DP_SEC_CNTL +#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP5_DP_SEC_CNTL1 +#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP5_DP_SEC_FRAMING1 +#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP5_DP_SEC_FRAMING2 +#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP5_DP_SEC_FRAMING3 +#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP5_DP_SEC_FRAMING4 +#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP5_DP_SEC_AUD_N +#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP5_DP_SEC_AUD_N_READBACK +#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP5_DP_SEC_AUD_M +#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP5_DP_SEC_AUD_M_READBACK +#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP5_DP_SEC_TIMESTAMP +#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP5_DP_SEC_PACKET_CNTL +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP5_DP_MSE_RATE_CNTL +#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP5_DP_MSE_RATE_UPDATE +#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP5_DP_MSE_SAT0 +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP5_DP_MSE_SAT1 +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP5_DP_MSE_SAT2 +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP5_DP_MSE_SAT_UPDATE +#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP5_DP_MSE_LINK_TIMING +#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP5_DP_MSE_MISC_CNTL +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP5_DP_DPHY_BS_SR_SWAP_CNTL +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP5_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP5_DP_MSE_SAT0_STATUS +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP5_DP_MSE_SAT1_STATUS +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP5_DP_MSE_SAT2_STATUS +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP5_DP_MSA_TIMING_PARAM1 +#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP5_DP_MSA_TIMING_PARAM2 +#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP5_DP_MSA_TIMING_PARAM3 +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP5_DP_MSA_TIMING_PARAM4 +#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP5_DP_MSO_CNTL +#define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP5_DP_MSO_CNTL1 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP5_DP_DSC_CNTL +#define DP5_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP5_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP5_DP_SEC_CNTL2 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP5_DP_SEC_CNTL3 +#define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP5_DP_SEC_CNTL4 +#define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP5_DP_SEC_CNTL5 +#define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP5_DP_SEC_CNTL6 +#define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP5_DP_SEC_CNTL7 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP5_DP_DB_CNTL +#define DP5_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP5_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP5_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP5_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP5_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP5_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP5_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP5_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP5_DP_MSA_VBID_MISC +#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dio_dig6_dispdec +//DIG6_DIG_FE_CNTL +#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG6_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG6_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG6_DIG_OUTPUT_CRC_CNTL +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG6_DIG_OUTPUT_CRC_RESULT +#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG6_DIG_CLOCK_PATTERN +#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG6_DIG_TEST_PATTERN +#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG6_DIG_RANDOM_PATTERN_SEED +#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG6_DIG_FIFO_STATUS +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG6_HDMI_CONTROL +#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG6_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG6_HDMI_STATUS +#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG6_HDMI_AUDIO_PACKET_CONTROL +#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG6_HDMI_ACR_PACKET_CONTROL +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG6_HDMI_VBI_PACKET_CONTROL +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG6_HDMI_INFOFRAME_CONTROL0 +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG6_HDMI_INFOFRAME_CONTROL1 +#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG6_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L +//DIG6_AFMT_INTERRUPT_STATUS +//DIG6_HDMI_GC +#define DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG6_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG6_AFMT_ISRC1_0 +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG6_AFMT_ISRC1_1 +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG6_AFMT_ISRC1_2 +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG6_AFMT_ISRC1_3 +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG6_AFMT_ISRC1_4 +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG6_AFMT_ISRC2_0 +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG6_AFMT_ISRC2_1 +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG6_AFMT_ISRC2_2 +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG6_AFMT_ISRC2_3 +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG6_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L +//DIG6_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L +//DIG6_HDMI_DB_CONTROL +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +//DIG6_AFMT_MPEG_INFO0 +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG6_AFMT_MPEG_INFO1 +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG6_AFMT_GENERIC_HDR +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_0 +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_1 +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_2 +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_3 +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_4 +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_5 +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_6 +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG6_AFMT_GENERIC_7 +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG6_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L +#define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L +//DIG6_HDMI_ACR_32_0 +#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG6_HDMI_ACR_32_1 +#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG6_HDMI_ACR_44_0 +#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG6_HDMI_ACR_44_1 +#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG6_HDMI_ACR_48_0 +#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG6_HDMI_ACR_48_1 +#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG6_HDMI_ACR_STATUS_0 +#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG6_HDMI_ACR_STATUS_1 +#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG6_AFMT_AUDIO_INFO0 +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG6_AFMT_AUDIO_INFO1 +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG6_AFMT_60958_0 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG6_AFMT_60958_1 +#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG6_AFMT_AUDIO_CRC_CONTROL +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG6_AFMT_RAMP_CONTROL0 +#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG6_AFMT_RAMP_CONTROL1 +#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG6_AFMT_RAMP_CONTROL2 +#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG6_AFMT_RAMP_CONTROL3 +#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG6_AFMT_60958_2 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG6_AFMT_AUDIO_CRC_RESULT +#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG6_AFMT_STATUS +#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG6_AFMT_AUDIO_PACKET_CONTROL +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +//DIG6_AFMT_VBI_PACKET_CONTROL +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG6_AFMT_INFOFRAME_CONTROL0 +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG6_AFMT_AUDIO_SRC_CONTROL +#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG6_DIG_BE_CNTL +#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG6_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG6_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG6_DIG_BE_EN_CNTL +#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG6_TMDS_CNTL +#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG6_TMDS_CONTROL_CHAR +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG6_TMDS_CONTROL0_FEEDBACK +#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG6_TMDS_STEREOSYNC_CTL_SEL +#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG6_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG6_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG6_TMDS_CTL_BITS +#define DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG6_TMDS_DCBALANCER_CONTROL +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG6_TMDS_CTL0_1_GEN_CNTL +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG6_TMDS_CTL2_3_GEN_CNTL +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG6_DIG_VERSION +#define DIG6_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG6_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG6_DIG_LANE_ENABLE +#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG6_AFMT_CNTL +#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG6_AFMT_VBI_PACKET_CONTROL1 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dp6_dispdec +//DP6_DP_LINK_CNTL +#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP6_DP_PIXEL_FORMAT +#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP6_DP_MSA_COLORIMETRY +#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP6_DP_CONFIG +#define DP6_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP6_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP6_DP_VID_STREAM_CNTL +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP6_DP_STEER_FIFO +#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP6_DP_MSA_MISC +#define DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP6_DP_VID_TIMING +#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP6_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP6_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP6_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP6_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP6_DP_VID_N +#define DP6_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP6_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP6_DP_VID_M +#define DP6_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP6_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP6_DP_LINK_FRAMING_CNTL +#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP6_DP_HBR2_EYE_PATTERN +#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP6_DP_VID_MSA_VBID +#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP6_DP_VID_INTERRUPT_CNTL +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP6_DP_DPHY_CNTL +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP6_DP_DPHY_TRAINING_PATTERN_SEL +#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP6_DP_DPHY_SYM0 +#define DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP6_DP_DPHY_SYM1 +#define DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP6_DP_DPHY_SYM2 +#define DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP6_DP_DPHY_8B10B_CNTL +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP6_DP_DPHY_PRBS_CNTL +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP6_DP_DPHY_SCRAM_CNTL +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP6_DP_DPHY_CRC_EN +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP6_DP_DPHY_CRC_CNTL +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP6_DP_DPHY_CRC_RESULT +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP6_DP_DPHY_CRC_MST_CNTL +#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP6_DP_DPHY_CRC_MST_STATUS +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP6_DP_DPHY_FAST_TRAINING +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP6_DP_DPHY_FAST_TRAINING_STATUS +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP6_DP_SEC_CNTL +#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP6_DP_SEC_CNTL1 +#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP6_DP_SEC_FRAMING1 +#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP6_DP_SEC_FRAMING2 +#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP6_DP_SEC_FRAMING3 +#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP6_DP_SEC_FRAMING4 +#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP6_DP_SEC_AUD_N +#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP6_DP_SEC_AUD_N_READBACK +#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP6_DP_SEC_AUD_M +#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP6_DP_SEC_AUD_M_READBACK +#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP6_DP_SEC_TIMESTAMP +#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP6_DP_SEC_PACKET_CNTL +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP6_DP_MSE_RATE_CNTL +#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP6_DP_MSE_RATE_UPDATE +#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP6_DP_MSE_SAT0 +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP6_DP_MSE_SAT1 +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP6_DP_MSE_SAT2 +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP6_DP_MSE_SAT_UPDATE +#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP6_DP_MSE_LINK_TIMING +#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP6_DP_MSE_MISC_CNTL +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP6_DP_DPHY_BS_SR_SWAP_CNTL +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP6_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP6_DP_MSE_SAT0_STATUS +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP6_DP_MSE_SAT1_STATUS +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP6_DP_MSE_SAT2_STATUS +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP6_DP_MSA_TIMING_PARAM1 +#define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP6_DP_MSA_TIMING_PARAM2 +#define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP6_DP_MSA_TIMING_PARAM3 +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP6_DP_MSA_TIMING_PARAM4 +#define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP6_DP_MSO_CNTL +#define DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP6_DP_MSO_CNTL1 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP6_DP_DSC_CNTL +#define DP6_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 +#define DP6_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L +//DP6_DP_SEC_CNTL2 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP6_DP_SEC_CNTL3 +#define DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP6_DP_SEC_CNTL4 +#define DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP6_DP_SEC_CNTL5 +#define DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP6_DP_SEC_CNTL6 +#define DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP6_DP_SEC_CNTL7 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +//DP6_DP_DB_CNTL +#define DP6_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP6_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP6_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP6_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP6_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP6_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP6_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP6_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +//DP6_DP_MSA_VBID_MISC +#define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L + + +// addressBlock: dce_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//DC_GPIO_DEBUG +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x00020000L +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYF_LINK_CNTL +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYF_CHANNEL_XBAR_CNTL +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYG_LINK_CNTL +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYG_CHANNEL_XBAR_CNTL +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 +#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 +#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0x0000000FL +#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L +#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L +#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L +//DC_DVODATA_CONFIG +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L +//LVTMA_PWRSEQ_CNTL +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +//LVTMA_PWRSEQ_STATE +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L +//LVTMA_PWRSEQ_REF_DIV +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//LVTMA_PWRSEQ_DELAY1 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L +//LVTMA_PWRSEQ_DELAY2 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//BL_PWM_CNTL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//BL_PWM_CNTL2 +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +//BL_PWM_PERIOD_CNTL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//BL_PWM_GRP1_REG_LOCK +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DIO_OTG_EXT_VSYNC_CNTL +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX__SHIFT 0x0 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX__SHIFT 0x4 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX__SHIFT 0x8 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX__SHIFT 0xc +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX__SHIFT 0x10 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX__SHIFT 0x14 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX_MASK 0x00000007L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX_MASK 0x00000070L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX_MASK 0x00000700L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX_MASK 0x00007000L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX_MASK 0x00070000L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX_MASK 0x00700000L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x07000000L +#define DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L +//DCIO_DPHY_SEL +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x00000003L +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0x0000000CL +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x00000030L +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0x000000C0L +//UNIPHY_IMPCAL_LINKA +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L +//UNIPHY_IMPCAL_LINKB +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L +//UNIPHY_IMPCAL_PERIOD +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xFFFFFFFFL +//AUXP_IMPCAL +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000F0000L +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00F00000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0F000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +//AUXN_IMPCAL +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000F0000L +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00F00000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0F000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +//DCIO_IMPCAL_CNTL +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0x0000000FL +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x00078000L +//UNIPHY_IMPCAL_PSW_AB +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007FFFL +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7FFF0000L +//UNIPHY_IMPCAL_LINKC +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L +//UNIPHY_IMPCAL_LINKD +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L +//DCIO_IMPCAL_CNTL_CD +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000FL +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L +//UNIPHY_IMPCAL_PSW_CD +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007FFFL +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7FFF0000L +//UNIPHY_IMPCAL_LINKE +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L +//UNIPHY_IMPCAL_LINKF +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000F0000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00F00000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0F000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L +//DCIO_IMPCAL_CNTL_EF +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000FL +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L +//UNIPHY_IMPCAL_PSW_EF +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007FFFL +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7FFF0000L +//DCIO_DPCS_TX_INTERRUPT +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14 +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x00000001L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x00000002L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x00000004L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x00000008L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x00000010L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x00000020L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x00000040L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x00000080L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x00000100L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x00000200L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x00000400L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x00000800L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x00001000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x00002000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x00004000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x00008000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x00010000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x00020000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x00040000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x00080000L +#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x00100000L +//DCIO_DPCS_RX_INTERRUPT +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2 +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x00000001L +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x00000002L +#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x00000004L +//DCIO_SEMAPHORE0 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE1 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE2 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE3 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE4 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE5 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE6 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xFFFF0000L +//DCIO_SEMAPHORE7 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10 +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0x0000FFFFL +#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xFFFF0000L +//DCIO_USBC_FLIP_EN_SEL +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL__SHIFT 0x0 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL__SHIFT 0x4 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL__SHIFT 0x8 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL__SHIFT 0xc +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL__SHIFT 0x10 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL__SHIFT 0x14 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN__SHIFT 0x18 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN__SHIFT 0x19 +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN__SHIFT 0x1a +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN__SHIFT 0x1b +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN__SHIFT 0x1c +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN__SHIFT 0x1d +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL_MASK 0x00000007L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL_MASK 0x00000070L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL_MASK 0x00000700L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL_MASK 0x00007000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL_MASK 0x00070000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL_MASK 0x00700000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN_MASK 0x01000000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN_MASK 0x02000000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN_MASK 0x04000000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN_MASK 0x08000000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN_MASK 0x10000000L +#define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN_MASK 0x20000000L + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DVODATA_MASK +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00FFFFFFL +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1F000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000L +//DC_GPIO_DVODATA_A +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00FFFFFFL +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1F000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000L +//DC_GPIO_DVODATA_EN +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00FFFFFFL +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1F000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000L +//DC_GPIO_DVODATA_Y +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00FFFFFFL +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1F000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC6_MASK +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC6_A +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L +//DC_GPIO_DDC6_EN +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC6_Y +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_SYNCA_MASK +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK__SHIFT 0x18 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK__SHIFT 0x1c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x000000C0L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x0000C000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK_MASK 0x07000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK_MASK 0x70000000L +//DC_GPIO_SYNCA_A +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L +//DC_GPIO_SYNCA_EN +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L +//DC_GPIO_SYNCA_Y +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_PWRSEQ_MASK +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L +//DC_GPIO_PWRSEQ_A +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L +//DC_GPIO_PWRSEQ_EN +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L +//DC_GPIO_PWRSEQ_Y +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17 +#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00002000L +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x00700000L +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L +#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L +//DC_GPIO_I2CPAD_MASK +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L +//DC_GPIO_I2CPAD_A +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L +//DC_GPIO_I2CPAD_EN +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L +//DC_GPIO_I2CPAD_Y +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L +//DC_GPIO_I2CPAD_STRENGTH +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000F0L +//DVO_STRENGTH_CONTROL +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000FL +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000F0L +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000F00L +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000F000L +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x00070000L +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x00700000L +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x07000000L +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L +//DVO_VREF_CONTROL +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000F0L +//DVO_SKEW_ADJUST +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xFFFFFFFFL +//DC_GPIO_I2S_SPDIF_MASK +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0x0000000FL +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x00000010L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x00000020L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x00000040L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x00000080L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x00000100L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x00000200L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x00000400L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x00000800L +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x00001000L +//DC_GPIO_I2S_SPDIF_A +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0x0000000FL +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x00000010L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x00000020L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x00000040L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x00000080L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x00000100L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x00000200L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x00000400L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x00000800L +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x00001000L +//DC_GPIO_I2S_SPDIF_EN +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11 +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0x0000000FL +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x00000010L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x00000020L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x00000040L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x00000080L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x00000100L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x00000200L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x00000400L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x00000800L +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x00001000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x00002000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x00004000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x00008000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x00010000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x00020000L +#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x00040000L +//DC_GPIO_I2S_SPDIF_Y +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0x0000000FL +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x00000010L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x00000020L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x00000040L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x00000080L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x00000100L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x00000200L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x00000400L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x00000800L +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x00001000L +//DC_GPIO_I2S_SPDIF_STRENGTH +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x00000007L +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x00000700L +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x00003800L +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x00070000L +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x07000000L +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT 0x1f +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK 0x80000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14 +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15 +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L + + +// addressBlock: dce_dc_dcio_dcio_dac_dispdec +//DAC_MACRO_CNTL_RESERVED0 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DAC_MACRO_CNTL_RESERVED1 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DAC_MACRO_CNTL_RESERVED2 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DAC_MACRO_CNTL_RESERVED3 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec +//DC_COMBOPHYCMREGS0_COMMON_FUSE1 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L +//DC_COMBOPHYCMREGS0_COMMON_FUSE2 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT 0xe +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L +//DC_COMBOPHYCMREGS0_COMMON_FUSE3 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L +#define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L +//DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L +#define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L +//DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L +//DC_COMBOPHYCMREGS0_COMMON_TXCNTRL +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L +#define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L +//DC_COMBOPHYCMREGS0_COMMON_TMDP +#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L +#define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L +//DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L +#define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec +//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec +//DC_COMBOPHYPLLREGS0_FREQ_CTRL0 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS0_FREQ_CTRL1 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS0_FREQ_CTRL2 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L +//DC_COMBOPHYPLLREGS0_FREQ_CTRL3 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT 0xc +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L +#define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L +#define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L +//DC_COMBOPHYPLLREGS0_BW_CTRL_FINE +#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL +//DC_COMBOPHYPLLREGS0_CAL_CTRL +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT 0x9 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT 0xb +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT 0xd +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK 0x00000600L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK 0x001FE000L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L +#define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS0_LOOP_CTRL +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK 0x07F00000L +//DC_COMBOPHYPLLREGS0_VREG_CFG +#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT 0xb +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT 0xc +#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT 0xd +#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT 0xf +#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK 0x00000060L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK 0x00020000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L +//DC_COMBOPHYPLLREGS0_OBSERVE0 +#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT 0xa +#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT 0x15 +#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL +#define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK 0x0003FC00L +#define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK 0x00E00000L +//DC_COMBOPHYPLLREGS0_OBSERVE1 +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT 0xa +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT 0xd +#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK 0x0000000FL +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK 0x00000C00L +#define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK 0x3FFF0000L +//DC_COMBOPHYPLLREGS0_DFT_OUT +#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK 0xFFFFFFFFL +//DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L +//DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L + + +// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec +//DC_COMBOPHYCMREGS1_COMMON_FUSE1 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L +//DC_COMBOPHYCMREGS1_COMMON_FUSE2 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT 0xe +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L +//DC_COMBOPHYCMREGS1_COMMON_FUSE3 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L +#define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L +//DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L +#define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L +//DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L +//DC_COMBOPHYCMREGS1_COMMON_TXCNTRL +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L +#define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L +//DC_COMBOPHYCMREGS1_COMMON_TMDP +#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L +#define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L +//DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L +#define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec +//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec +//DC_COMBOPHYPLLREGS1_FREQ_CTRL0 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS1_FREQ_CTRL1 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS1_FREQ_CTRL2 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L +//DC_COMBOPHYPLLREGS1_FREQ_CTRL3 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT 0xc +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L +#define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L +#define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L +//DC_COMBOPHYPLLREGS1_BW_CTRL_FINE +#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL +//DC_COMBOPHYPLLREGS1_CAL_CTRL +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT 0x9 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT 0xb +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT 0xd +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK 0x00000600L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK 0x001FE000L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L +#define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS1_LOOP_CTRL +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK 0x07F00000L +//DC_COMBOPHYPLLREGS1_VREG_CFG +#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT 0xb +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT 0xc +#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT 0xd +#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT 0xf +#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK 0x00000060L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK 0x00020000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L +//DC_COMBOPHYPLLREGS1_OBSERVE0 +#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT 0xa +#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT 0x15 +#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL +#define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK 0x0003FC00L +#define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK 0x00E00000L +//DC_COMBOPHYPLLREGS1_OBSERVE1 +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT 0xa +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT 0xd +#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK 0x0000000FL +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK 0x00000C00L +#define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK 0x3FFF0000L +//DC_COMBOPHYPLLREGS1_DFT_OUT +#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK 0xFFFFFFFFL +//DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L +//DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L + + +// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec +//DC_COMBOPHYCMREGS2_COMMON_FUSE1 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L +//DC_COMBOPHYCMREGS2_COMMON_FUSE2 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT 0xe +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L +//DC_COMBOPHYCMREGS2_COMMON_FUSE3 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L +#define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L +//DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L +#define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L +//DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L +//DC_COMBOPHYCMREGS2_COMMON_TXCNTRL +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L +#define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L +//DC_COMBOPHYCMREGS2_COMMON_TMDP +#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L +#define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L +//DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L +#define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec +//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec +//DC_COMBOPHYPLLREGS2_FREQ_CTRL0 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS2_FREQ_CTRL1 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS2_FREQ_CTRL2 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L +//DC_COMBOPHYPLLREGS2_FREQ_CTRL3 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT 0xc +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L +#define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L +#define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L +//DC_COMBOPHYPLLREGS2_BW_CTRL_FINE +#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL +//DC_COMBOPHYPLLREGS2_CAL_CTRL +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT 0x9 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT 0xb +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT 0xd +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK 0x00000600L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK 0x001FE000L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L +#define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS2_LOOP_CTRL +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK 0x07F00000L +//DC_COMBOPHYPLLREGS2_VREG_CFG +#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT 0xb +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT 0xc +#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT 0xd +#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT 0xf +#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK 0x00000060L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK 0x00020000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L +//DC_COMBOPHYPLLREGS2_OBSERVE0 +#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT 0xa +#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT 0x15 +#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL +#define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK 0x0003FC00L +#define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK 0x00E00000L +//DC_COMBOPHYPLLREGS2_OBSERVE1 +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT 0xa +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT 0xd +#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK 0x0000000FL +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK 0x00000C00L +#define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK 0x3FFF0000L +//DC_COMBOPHYPLLREGS2_DFT_OUT +#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK 0xFFFFFFFFL +//DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L +//DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L + + +// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec +//DC_COMBOPHYCMREGS3_COMMON_FUSE1 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L +//DC_COMBOPHYCMREGS3_COMMON_FUSE2 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT 0xe +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L +//DC_COMBOPHYCMREGS3_COMMON_FUSE3 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L +#define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L +//DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L +#define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L +//DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L +//DC_COMBOPHYCMREGS3_COMMON_TXCNTRL +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L +#define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L +//DC_COMBOPHYCMREGS3_COMMON_TMDP +#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L +#define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L +//DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L +#define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec +//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L +//DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L +//DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L +#define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L +//DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL +//DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 +#define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec +//DC_COMBOPHYPLLREGS3_FREQ_CTRL0 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS3_FREQ_CTRL1 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L +//DC_COMBOPHYPLLREGS3_FREQ_CTRL2 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L +//DC_COMBOPHYPLLREGS3_FREQ_CTRL3 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT 0xc +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L +#define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L +#define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L +//DC_COMBOPHYPLLREGS3_BW_CTRL_FINE +#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL +//DC_COMBOPHYPLLREGS3_CAL_CTRL +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT 0x9 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT 0xb +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT 0xd +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT 0x18 +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK 0x00000600L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK 0x001FE000L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L +#define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK 0xFF000000L +//DC_COMBOPHYPLLREGS3_LOOP_CTRL +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK 0x07F00000L +//DC_COMBOPHYPLLREGS3_VREG_CFG +#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT 0x3 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT 0x7 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT 0xb +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT 0xc +#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT 0xd +#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT 0xf +#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT 0x12 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT 0x14 +#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK 0x00000004L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK 0x00000018L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK 0x00000060L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK 0x00000780L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK 0x00000800L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK 0x00001000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK 0x00020000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK 0x00040000L +#define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L +//DC_COMBOPHYPLLREGS3_OBSERVE0 +#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT 0x6 +#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT 0xa +#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT 0x15 +#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL +#define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK 0x00000040L +#define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK 0x0003FC00L +#define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK 0x00E00000L +//DC_COMBOPHYPLLREGS3_OBSERVE1 +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT 0xa +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT 0xd +#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK 0x0000000FL +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK 0x00000C00L +#define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK 0x00006000L +#define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK 0x3FFF0000L +//DC_COMBOPHYPLLREGS3_DFT_OUT +#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK 0xFFFFFFFFL +//DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L +//DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L +#define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L + + +// addressBlock: dce_dc_dcio_dcio_zcal_dispdec +//ZCAL_MACRO_CNTL_RESERVED0 +#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//ZCAL_MACRO_CNTL_RESERVED1 +#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//ZCAL_MACRO_CNTL_RESERVED2 +#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//ZCAL_MACRO_CNTL_RESERVED3 +#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//ZCAL_MACRO_CNTL_RESERVED4 +#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec +//COMP_EN_CTL +#define COMP_EN_CTL__comp_en__SHIFT 0x0 +#define COMP_EN_CTL__comp_en_override__SHIFT 0x2 +#define COMP_EN_CTL__comp_done__SHIFT 0x4 +#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6 +#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7 +#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8 +#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9 +#define COMP_EN_CTL__zcal_code__SHIFT 0xa +#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10 +#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11 +#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13 +#define COMP_EN_CTL__dsm_sel__SHIFT 0x14 +#define COMP_EN_CTL__comp_en_MASK 0x00000001L +#define COMP_EN_CTL__comp_en_override_MASK 0x00000004L +#define COMP_EN_CTL__comp_done_MASK 0x00000010L +#define COMP_EN_CTL__zcal_code_override_MASK 0x00000040L +#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x00000080L +#define COMP_EN_CTL__zcal_base_en_MASK 0x00000100L +#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x00000200L +#define COMP_EN_CTL__zcal_code_MASK 0x00007C00L +#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x00010000L +#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x00060000L +#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x00080000L +#define COMP_EN_CTL__dsm_sel_MASK 0x00F00000L +//COMP_EN_DFX +#define COMP_EN_DFX__autocal_ron_code__SHIFT 0x0 +#define COMP_EN_DFX__autocal_rtt_code__SHIFT 0x5 +#define COMP_EN_DFX__pre_fused_ron_code__SHIFT 0xb +#define COMP_EN_DFX__pre_fused_rtt_code__SHIFT 0x10 +#define COMP_EN_DFX__broadcast_ron_code__SHIFT 0x16 +#define COMP_EN_DFX__broadcast_rtt_code__SHIFT 0x1b +#define COMP_EN_DFX__autocal_ron_code_MASK 0x0000001FL +#define COMP_EN_DFX__autocal_rtt_code_MASK 0x000003E0L +#define COMP_EN_DFX__pre_fused_ron_code_MASK 0x0000F800L +#define COMP_EN_DFX__pre_fused_rtt_code_MASK 0x001F0000L +#define COMP_EN_DFX__broadcast_ron_code_MASK 0x07C00000L +#define COMP_EN_DFX__broadcast_rtt_code_MASK 0xF8000000L +//ZCAL_FUSES +#define ZCAL_FUSES__fuse_valid__SHIFT 0x0 +#define ZCAL_FUSES__fuse_ron_override_val__SHIFT 0x3 +#define ZCAL_FUSES__fuse_ron_ctl__SHIFT 0xa +#define ZCAL_FUSES__fuse_rtt_override_val__SHIFT 0xd +#define ZCAL_FUSES__fuse_rtt_ctl__SHIFT 0x14 +#define ZCAL_FUSES__fuse_refresh_cal_en__SHIFT 0x16 +#define ZCAL_FUSES__fuse_spare__SHIFT 0x17 +#define ZCAL_FUSES__fuse_valid_MASK 0x00000001L +#define ZCAL_FUSES__fuse_ron_override_val_MASK 0x000001F8L +#define ZCAL_FUSES__fuse_ron_ctl_MASK 0x00000C00L +#define ZCAL_FUSES__fuse_rtt_override_val_MASK 0x0007E000L +#define ZCAL_FUSES__fuse_rtt_ctl_MASK 0x00300000L +#define ZCAL_FUSES__fuse_refresh_cal_en_MASK 0x00400000L +#define ZCAL_FUSES__fuse_spare_MASK 0xFF800000L + + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h new file mode 100644 index 000000000000..582f1a66e354 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h @@ -0,0 +1,4005 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _gc_9_1_DEFAULT_HEADER +#define _gc_9_1_DEFAULT_HEADER + + +// addressBlock: gc_grbmdec +#define mmGRBM_CNTL_DEFAULT 0x00000018 +#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020 +#define mmGRBM_STATUS2_DEFAULT 0x00000000 +#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000 +#define mmGRBM_STATUS_DEFAULT 0x00000000 +#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000 +#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000 +#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000 +#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100 +#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008 +#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030 +#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000 +#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000 +#define mmGRBM_READ_ERROR_DEFAULT 0x00000000 +#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000 +#define mmGRBM_INT_CNTL_DEFAULT 0x00000000 +#define mmGRBM_TRAP_OP_DEFAULT 0x00000000 +#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000 +#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff +#define mmGRBM_TRAP_WD_DEFAULT 0x00000000 +#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff +#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000 +#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000 +#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000 +#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000 +#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000 +#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000 +#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000 +#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000 +#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891 +#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea +#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000 +#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000 +#define mmGRBM_NOWHERE_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000 +#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000 + + +// addressBlock: gc_cpdec +#define mmCP_CPC_STATUS_DEFAULT 0x00000000 +#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000 +#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000 +#define mmCP_CPF_STATUS_DEFAULT 0x00000000 +#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000 +#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000 +#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008 +#define mmCP_MEC_CNTL_DEFAULT 0x50000000 +#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000 +#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000 +#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000 +#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000 +#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004 +#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002 +#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000 +#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000 +#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000 +#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000 +#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000 +#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000 +#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000 +#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000 +#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000 +#define mmCP_STALLED_STAT3_DEFAULT 0x00000000 +#define mmCP_STALLED_STAT1_DEFAULT 0x00000000 +#define mmCP_STALLED_STAT2_DEFAULT 0x00000000 +#define mmCP_BUSY_STAT_DEFAULT 0x00000000 +#define mmCP_STAT_DEFAULT 0x00000000 +#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000 +#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000 +#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808 +#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000 +#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000 +#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000 +#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000 +#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000 +#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000 +#define mmCP_CSF_STAT_DEFAULT 0x00000000 +#define mmCP_ME_CNTL_DEFAULT 0x15000000 +#define mmCP_CNTX_STAT_DEFAULT 0x00000000 +#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000 +#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010 +#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010 +#define mmCP_RB2_RPTR_DEFAULT 0x00000000 +#define mmCP_RB1_RPTR_DEFAULT 0x00000000 +#define mmCP_RB0_RPTR_DEFAULT 0x00000000 +#define mmCP_RB_RPTR_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100 +#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010 +#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030 +#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000 +#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16 +#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040 +#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000 +#define mmCP_STQ_AVAIL_DEFAULT 0x00000000 +#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000 +#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000 +#define mmCP_CMD_INDEX_DEFAULT 0x00000000 +#define mmCP_CMD_DATA_DEFAULT 0x00000000 +#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000 +#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000 +#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000 +#define mmCP_STQ_STAT_DEFAULT 0x00000000 +#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000 +#define mmCP_MEQ_STAT_DEFAULT 0x00000000 +#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000 +#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000 +#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000 +#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000 +#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000 + + +// addressBlock: gc_padec +#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d +#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180 +#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020 +#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020 +#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000 +#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000 +#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092410 +#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040 +#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010 +#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe +#define mmIA_CNTL_STATUS_DEFAULT 0x00000000 +#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000 +#define mmWD_CNTL_STATUS_DEFAULT 0x00000000 +#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x0e020000 +#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000 +#define mmWD_QOS_DEFAULT 0x00000000 +#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011 +#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x0000007f +#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000000ff +#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000 +#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xf8000000 +#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000 +#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000 +#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff +#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000 +#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000 +#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000 +#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000 +#define mmPA_CL_ENHANCE_DEFAULT 0x00000007 +#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000 +#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000018 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 +#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff +#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402 +#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008 +#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8 +#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025 +#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000 +#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000 +#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000 +#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000 +#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600 +#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000 +#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020 +#define mmPA_SC_ENHANCE_DEFAULT 0x00000001 +#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000 +#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000 +#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000 + + +// addressBlock: gc_sqdec +#define mmSQ_CONFIG_DEFAULT 0x01180000 +#define mmSQC_CONFIG_DEFAULT 0x010a2000 +#define mmLDS_CONFIG_DEFAULT 0x00000000 +#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f +#define mmSQ_REG_CREDITS_DEFAULT 0x00000820 +#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01 +#define mmSQ_DSM_CNTL_DEFAULT 0x00000000 +#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000 +#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000 +#define mmSH_MEM_BASES_DEFAULT 0x00000000 +#define mmSH_MEM_CONFIG_DEFAULT 0x00000000 +#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000 +#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000 +#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff +#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000 +#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580 +#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000 +#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000 +#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000 +#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000 +#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTL_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000 +#define mmSQC_EDC_CNT2_DEFAULT 0x00000000 +#define mmSQC_EDC_CNT3_DEFAULT 0x00000000 +#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000 +#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000 +#define mmSQ_IND_INDEX_DEFAULT 0x00000000 +#define mmSQ_IND_DATA_DEFAULT 0x00000000 +#define mmSQ_CMD_DEFAULT 0x00000000 +#define mmSQ_TIME_HI_DEFAULT 0x00000000 +#define mmSQ_TIME_LO_DEFAULT 0x00000000 +#define mmSQ_DS_0_DEFAULT 0x00000000 +#define mmSQ_DS_1_DEFAULT 0x00000000 +#define mmSQ_EXP_0_DEFAULT 0x00000000 +#define mmSQ_EXP_1_DEFAULT 0x00000000 +#define mmSQ_FLAT_0_DEFAULT 0x00000000 +#define mmSQ_FLAT_1_DEFAULT 0x00000000 +#define mmSQ_GLBL_0_DEFAULT 0x00000000 +#define mmSQ_GLBL_1_DEFAULT 0x00000000 +#define mmSQ_INST_DEFAULT 0x00000000 +#define mmSQ_MIMG_0_DEFAULT 0x00000000 +#define mmSQ_MIMG_1_DEFAULT 0x00000000 +#define mmSQ_MTBUF_0_DEFAULT 0x00000000 +#define mmSQ_MTBUF_1_DEFAULT 0x00000000 +#define mmSQ_MUBUF_0_DEFAULT 0x00000000 +#define mmSQ_MUBUF_1_DEFAULT 0x00000000 +#define mmSQ_SCRATCH_0_DEFAULT 0x00000000 +#define mmSQ_SCRATCH_1_DEFAULT 0x00000000 +#define mmSQ_SMEM_0_DEFAULT 0x00000000 +#define mmSQ_SMEM_1_DEFAULT 0x00000000 +#define mmSQ_SOP1_DEFAULT 0x00000000 +#define mmSQ_SOP2_DEFAULT 0x00000000 +#define mmSQ_SOPC_DEFAULT 0x00000000 +#define mmSQ_SOPK_DEFAULT 0x00000000 +#define mmSQ_SOPP_DEFAULT 0x00000000 +#define mmSQ_VINTRP_DEFAULT 0x00000000 +#define mmSQ_VOP1_DEFAULT 0x00000000 +#define mmSQ_VOP2_DEFAULT 0x00000000 +#define mmSQ_VOP3P_0_DEFAULT 0x00000000 +#define mmSQ_VOP3P_1_DEFAULT 0x00000000 +#define mmSQ_VOP3_0_DEFAULT 0x00000000 +#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000 +#define mmSQ_VOP3_1_DEFAULT 0x00000000 +#define mmSQ_VOPC_DEFAULT 0x00000000 +#define mmSQ_VOP_DPP_DEFAULT 0x00000000 +#define mmSQ_VOP_SDWA_DEFAULT 0x00000000 +#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000 +#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000 +#define mmSQ_LB_DATA0_DEFAULT 0x00000000 +#define mmSQ_LB_DATA1_DEFAULT 0x00000000 +#define mmSQ_LB_DATA2_DEFAULT 0x00000000 +#define mmSQ_LB_DATA3_DEFAULT 0x00000000 +#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000 +#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff +#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff +#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff +#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff +#define mmSQC_EDC_CNT_DEFAULT 0x00000000 +#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000 +#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000 +#define mmSQ_EDC_INFO_DEFAULT 0x00000000 +#define mmSQ_EDC_CNT_DEFAULT 0x00000000 +#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000 +#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000 +#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000 +#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000 +#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000 +#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000 +#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000 +#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000 +#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000 +#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000 +#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000 +#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000 +#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000 +#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000 +#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000 +#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480 +#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000 +#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500 +#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000 +#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_shsdec +#define mmSX_DEBUG_1_DEFAULT 0x00000020 +#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff +#define mmSPI_START_PHASE_DEFAULT 0x00000000 +#define mmSPI_GFX_CNTL_DEFAULT 0x00000000 +#define mmSPI_DSM_CNTL_DEFAULT 0x00000000 +#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000 +#define mmSPI_EDC_CNT_DEFAULT 0x00000000 +#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100 +#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000 +#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000 +#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000 +#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff +#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff +#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080 +#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000800 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040 +#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000 +#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000 +#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000 +#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000 +#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000 +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 + + +// addressBlock: gc_tpdec +#define mmTD_CNTL_DEFAULT 0x00000000 +#define mmTD_STATUS_DEFAULT 0x00000000 +#define mmTD_DSM_CNTL_DEFAULT 0x00000000 +#define mmTD_DSM_CNTL2_DEFAULT 0x00000000 +#define mmTD_SCRATCH_DEFAULT 0x00000000 +#define mmTA_CNTL_DEFAULT 0x8004d850 +#define mmTA_CNTL_AUX_DEFAULT 0x00000000 +#define mmTA_RESERVED_010C_DEFAULT 0x00000000 +#define mmTA_GRAD_ADJ_DEFAULT 0x40000040 +#define mmTA_STATUS_DEFAULT 0x00000000 +#define mmTA_SCRATCH_DEFAULT 0x00000000 + + +// addressBlock: gc_gdsdec +#define mmGDS_CONFIG_DEFAULT 0x00000000 +#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000 +#define mmGDS_ENHANCE2_DEFAULT 0x00000000 +#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000 +#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000 +#define mmGDS_EDC_CNT_DEFAULT 0x00000000 +#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000 +#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000 +#define mmGDS_DSM_CNTL_DEFAULT 0x00000000 +#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000 +#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000 +#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000 +#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000 + + +// addressBlock: gc_rbdec +#define mmDB_DEBUG_DEFAULT 0x00000000 +#define mmDB_DEBUG2_DEFAULT 0x00000000 +#define mmDB_DEBUG3_DEFAULT 0x00000000 +#define mmDB_DEBUG4_DEFAULT 0x00000000 +#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000 +#define mmDB_WATERMARKS_DEFAULT 0x01020204 +#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000 +#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000 +#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000 +#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000 +#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000 +#define mmDB_RING_CONTROL_DEFAULT 0x00000001 +#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404 +#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07 +#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00 +#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064 +#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8 +#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8 +#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240 +#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff +#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000 +#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000 +#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000 +#define mmGB_ADDR_CONFIG_DEFAULT 0x26010011 +#define mmGB_BACKEND_MAP_DEFAULT 0x33221100 +#define mmGB_GPU_ID_DEFAULT 0x00000000 +#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210 +#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x26010011 +#define mmGB_TILE_MODE0_DEFAULT 0x00000000 +#define mmGB_TILE_MODE1_DEFAULT 0x00000000 +#define mmGB_TILE_MODE2_DEFAULT 0x00000000 +#define mmGB_TILE_MODE3_DEFAULT 0x00000000 +#define mmGB_TILE_MODE4_DEFAULT 0x00000000 +#define mmGB_TILE_MODE5_DEFAULT 0x00000000 +#define mmGB_TILE_MODE6_DEFAULT 0x00000000 +#define mmGB_TILE_MODE7_DEFAULT 0x00000000 +#define mmGB_TILE_MODE8_DEFAULT 0x00000000 +#define mmGB_TILE_MODE9_DEFAULT 0x00000000 +#define mmGB_TILE_MODE10_DEFAULT 0x00000000 +#define mmGB_TILE_MODE11_DEFAULT 0x00000000 +#define mmGB_TILE_MODE12_DEFAULT 0x00000000 +#define mmGB_TILE_MODE13_DEFAULT 0x00000000 +#define mmGB_TILE_MODE14_DEFAULT 0x00000000 +#define mmGB_TILE_MODE15_DEFAULT 0x00000000 +#define mmGB_TILE_MODE16_DEFAULT 0x00000000 +#define mmGB_TILE_MODE17_DEFAULT 0x00000000 +#define mmGB_TILE_MODE18_DEFAULT 0x00000000 +#define mmGB_TILE_MODE19_DEFAULT 0x00000000 +#define mmGB_TILE_MODE20_DEFAULT 0x00000000 +#define mmGB_TILE_MODE21_DEFAULT 0x00000000 +#define mmGB_TILE_MODE22_DEFAULT 0x00000000 +#define mmGB_TILE_MODE23_DEFAULT 0x00000000 +#define mmGB_TILE_MODE24_DEFAULT 0x00000000 +#define mmGB_TILE_MODE25_DEFAULT 0x00000000 +#define mmGB_TILE_MODE26_DEFAULT 0x00000000 +#define mmGB_TILE_MODE27_DEFAULT 0x00000000 +#define mmGB_TILE_MODE28_DEFAULT 0x00000000 +#define mmGB_TILE_MODE29_DEFAULT 0x00000000 +#define mmGB_TILE_MODE30_DEFAULT 0x00000000 +#define mmGB_TILE_MODE31_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000 +#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000 +#define mmCB_HW_CONTROL_DEFAULT 0x00014107 +#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000 +#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000 +#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000 +#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000 +#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000 +#define mmCB_DCC_CONFIG_DEFAULT 0x04000000 +#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000 +#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000 + + +// addressBlock: gc_ea_gceadec2 +#define mmGCEA_EDC_CNT_DEFAULT 0x00000000 +#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmGCEA_TCC_XBR_CREDITS_DEFAULT 0x637f637f +#define mmGCEA_TCC_XBR_MAXBURST_DEFAULT 0x00003333 +#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000 +#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa +#define mmGCEA_ERR_STATUS_DEFAULT 0x00000000 +#define mmGCEA_MISC2_DEFAULT 0x00000000 +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000 +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000 +#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000 +#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000 + + +// addressBlock: gc_rmi_rmidec +#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000 +#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03 +#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000 +#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000 +#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000 +#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000 +#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000 +#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00 +#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0 +#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564 +#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200 +#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000 +#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000 +#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000 +#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e +#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e +#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00 +#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000 +#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000 +#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000 +#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800 +#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff +#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822 +#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmRMI_SPARE_DEFAULT 0x00000001 +#define mmRMI_SPARE_1_DEFAULT 0x00000000 +#define mmRMI_SPARE_2_DEFAULT 0x00000000 + + +// addressBlock: gc_dbgu_gfx_dbgudec +#define mmport_a_addr_DEFAULT 0x00000000 +#define mmport_a_data_lo_DEFAULT 0x00000000 +#define mmport_a_data_hi_DEFAULT 0x00000000 +#define mmport_b_addr_DEFAULT 0x00000000 +#define mmport_b_data_lo_DEFAULT 0x00000000 +#define mmport_b_data_hi_DEFAULT 0x00000000 +#define mmport_c_addr_DEFAULT 0x00000000 +#define mmport_c_data_lo_DEFAULT 0x00000000 +#define mmport_c_data_hi_DEFAULT 0x00000000 +#define mmport_d_addr_DEFAULT 0x00000000 +#define mmport_d_data_lo_DEFAULT 0x00000000 +#define mmport_d_data_hi_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl2_atcl2dec +#define mmATC_L2_CNTL_DEFAULT 0x000001c9 +#define mmATC_L2_CNTL2_DEFAULT 0x00000100 +#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 +#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 +#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 +#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 +#define mmATC_L2_STATUS_DEFAULT 0x00000000 +#define mmATC_L2_STATUS2_DEFAULT 0x00000000 +#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 +#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: gc_utcl2_vml2pfdec +#define mmVM_L2_CNTL_DEFAULT 0x00080602 +#define mmVM_L2_CNTL2_DEFAULT 0x00000000 +#define mmVM_L2_CNTL3_DEFAULT 0x80100007 +#define mmVM_L2_STATUS_DEFAULT 0x00000000 +#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc +#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff +#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 +#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 +#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 +#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 +#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 +#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: gc_utcl2_vml2vcdec +#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl2_vmsharedpfdec +#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 +#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 +#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 +#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmMC_VM_STEERING_DEFAULT 0x00000001 +#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 +#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl2_vmsharedvcdec +#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 +#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 +#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 +#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 +#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 + + +// addressBlock: gc_ea_gceadec +#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 +#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 +#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924 +#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324 +#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x00000924 +#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x00000924 +#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 +#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 +#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008 +#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmGCEA_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef +#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 +#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 +#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 +#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 +#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmGCEA_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmGCEA_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00102040 +#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmGCEA_SDP_CREDITS_DEFAULT 0x000100bf +#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000000f +#define mmGCEA_MISC_DEFAULT 0x0de03ff0 +#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: gc_tcdec +#define mmTCP_INVALIDATE_DEFAULT 0x00000000 +#define mmTCP_STATUS_DEFAULT 0x00000000 +#define mmTCP_CNTL_DEFAULT 0x2f9c0000 +#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210 +#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98 +#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000f3 +#define mmTCP_CREDIT_DEFAULT 0x804001c0 +#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000 +#define mmTCP_EDC_CNT_DEFAULT 0x00000000 +#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000 +#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000 +#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000 +#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000 +#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000 +#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000 +#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000 +#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000 +#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000 +#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000 +#define mmTCI_STATUS_DEFAULT 0x00000000 +#define mmTCI_CNTL_1_DEFAULT 0x40080022 +#define mmTCI_CNTL_2_DEFAULT 0x00000041 +#define mmTCC_CTRL_DEFAULT 0xf30fff7f +#define mmTCC_CTRL2_DEFAULT 0x0000000f +#define mmTCC_EDC_CNT_DEFAULT 0x00000000 +#define mmTCC_EDC_CNT2_DEFAULT 0x00000000 +#define mmTCC_REDUNDANCY_DEFAULT 0x00000000 +#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000 +#define mmTCC_DSM_CNTL_DEFAULT 0x00000000 +#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000 +#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000 +#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmTCC_WBINVL2_DEFAULT 0x00000010 +#define mmTCC_SOFT_RESET_DEFAULT 0x00000000 +#define mmTCA_CTRL_DEFAULT 0x00000088 +#define mmTCA_BURST_MASK_DEFAULT 0xffffffff +#define mmTCA_BURST_CTRL_DEFAULT 0x00000007 +#define mmTCA_DSM_CNTL_DEFAULT 0x00000000 +#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000 +#define mmTCA_EDC_CNT_DEFAULT 0x00000000 + + +// addressBlock: gc_shdec +#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff +#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff +#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe +#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000 +#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000 +#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000 +#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000 +#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000 +#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000 +#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000 +#define mmCOMPUTE_START_X_DEFAULT 0x00000000 +#define mmCOMPUTE_START_Y_DEFAULT 0x00000000 +#define mmCOMPUTE_START_Z_DEFAULT 0x00000000 +#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000 +#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000 +#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000 +#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001 +#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000 +#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000 +#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000 +#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000 +#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000 +#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000 +#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000 +#define mmCOMPUTE_VMID_DEFAULT 0x00000000 +#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff +#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff +#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000 +#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000 +#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000 +#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000 +#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002 +#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000 +#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000 +#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000 +#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000 +#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000 + + +// addressBlock: gc_cppdec +#define mmCP_DFY_CNTL_DEFAULT 0x00000000 +#define mmCP_DFY_STAT_DEFAULT 0x00000000 +#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_0_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_1_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_2_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_3_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_4_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_5_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_6_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_7_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_8_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_9_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_10_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_11_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_12_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_13_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_14_DEFAULT 0x00000000 +#define mmCP_DFY_DATA_15_DEFAULT 0x00000000 +#define mmCP_DFY_CMD_DEFAULT 0x00000000 +#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c +#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020 +#define mmCPC_INT_INFO_DEFAULT 0x00000000 +#define mmCP_VIRT_STATUS_DEFAULT 0x00000000 +#define mmCPC_INT_ADDR_DEFAULT 0x00000000 +#define mmCPC_INT_PASID_DEFAULT 0x00000000 +#define mmCP_GFX_ERROR_DEFAULT 0x00000000 +#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000 +#define mmCP_RB0_BASE_DEFAULT 0x00000000 +#define mmCP_RB_BASE_DEFAULT 0x00000000 +#define mmCP_RB0_CNTL_DEFAULT 0x00400000 +#define mmCP_RB_CNTL_DEFAULT 0x00400000 +#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000 +#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000 +#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000 +#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000 +#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmGC_PRIV_MODE_DEFAULT 0x00000000 +#define mmCP_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_DEVICE_ID_DEFAULT 0x00000000 +#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020 +#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002 +#define mmCP_FATAL_ERROR_DEFAULT 0x00000000 +#define mmCP_RB_VMID_DEFAULT 0x00000000 +#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000 +#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000 +#define mmCP_RB0_WPTR_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_DEFAULT 0x00000000 +#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000 +#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmCP_RB1_WPTR_DEFAULT 0x00000000 +#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000 +#define mmCP_RB2_WPTR_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044 +#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048 +#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc +#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000 +#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000 +#define mmCP_RB1_BASE_DEFAULT 0x00000000 +#define mmCP_RB1_CNTL_DEFAULT 0x00400000 +#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000 +#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_RB2_BASE_DEFAULT 0x00000000 +#define mmCP_RB2_CNTL_DEFAULT 0x00400000 +#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000 +#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001 +#define mmCP_RB_ACTIVE_DEFAULT 0x00000001 +#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000 +#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000 +#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000 +#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000 +#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000 +#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000 +#define mmCP_PWR_CNTL_DEFAULT 0x00000000 +#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200 +#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000 +#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000 +#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000 +#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000 +#define mmGB_EDC_MODE_DEFAULT 0x00000000 +#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001 +#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000 +#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000 +#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 +#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002 +#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002 +#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000 +#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002 +#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075 +#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007 +#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040 +#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040 +#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000 +#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000 +#define mmCP_VMID_RESET_DEFAULT 0x00000000 +#define mmCPC_INT_CNTL_DEFAULT 0x00000000 +#define mmCPC_INT_STATUS_DEFAULT 0x00000000 +#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000 +#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000 +#define mmCP_PQ_STATUS_DEFAULT 0x00000000 +#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000 +#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000 +#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000 +#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000 +#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000 +#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000 +#define mmCP_VMID_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gc_cppdec2 +#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000 +#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000 +#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 +#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_RB_STATUS_DEFAULT 0x00000000 +#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmCP_SD_CNTL_DEFAULT 0x0000001f +#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000 +#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000 + + +// addressBlock: gc_spipdec +#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000 +#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000 +#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000 +#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff +#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f +#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f +#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000 +#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000 +#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000 +#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000 + + +// addressBlock: gc_cpphqddec +#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000 +#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000 +#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604 +#define mmCP_HPD_STATUS0_DEFAULT 0x01000000 +#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000 +#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000 +#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000 +#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000 +#define mmCP_HQD_VMID_DEFAULT 0x00000000 +#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301 +#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000 +#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 +#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 +#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000 +#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000 +#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000 +#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000 +#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000 +#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000 +#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000 +#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000 +#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000 +#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000 +#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000 +#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000 +#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000 +#define mmCP_MQD_CONTROL_DEFAULT 0x00000100 +#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000 +#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000 +#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 +#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000 +#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000 +#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000 +#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000 +#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000 +#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000 +#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000 +#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000 +#define mmCP_HQD_ERROR_DEFAULT 0x00000000 +#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000 +#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000 +#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_didtdec +#define mmDIDT_IND_INDEX_DEFAULT 0x00000000 +#define mmDIDT_IND_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_gccacdec +#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000 +#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000 +#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000 +#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000 +#define mmGC_CAC_PG_AGGR_LOWER_DEFAULT 0x00000000 +#define mmGC_CAC_PG_AGGR_UPPER_DEFAULT 0x00000000 +#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000 +#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000 +#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000 +#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f +#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000 +#define mmGC_EDC_CTRL_DEFAULT 0x00000000 +#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000 +#define mmGC_EDC_STATUS_DEFAULT 0x00000000 +#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000 +#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000 +#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000 +#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000 +#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000 +#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000 +#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000 + + +// addressBlock: gc_tcpdec +#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000 +#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000 +#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000 +#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000 +#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000 +#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000 +#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000 +#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000 +#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000 +#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000 +#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000 +#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000 +#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000 +#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000 +#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000 +#define mmTCP_CNTL2_DEFAULT 0x0000000a +#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400 +#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000 +#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000 + + +// addressBlock: gc_gdspdec +#define mmGDS_VMID0_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID1_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID2_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID3_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID4_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID5_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID6_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID7_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID8_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID9_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID10_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID11_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID12_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID13_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID14_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000 +#define mmGDS_VMID15_BASE_DEFAULT 0x00000000 +#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000 +#define mmGDS_GWS_VMID0_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID1_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID2_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID3_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID4_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID5_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID6_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID7_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID8_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID9_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID10_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID11_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID12_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID13_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID14_DEFAULT 0x00400000 +#define mmGDS_GWS_VMID15_DEFAULT 0x00400000 +#define mmGDS_OA_VMID0_DEFAULT 0x00000000 +#define mmGDS_OA_VMID1_DEFAULT 0x00000000 +#define mmGDS_OA_VMID2_DEFAULT 0x00000000 +#define mmGDS_OA_VMID3_DEFAULT 0x00000000 +#define mmGDS_OA_VMID4_DEFAULT 0x00000000 +#define mmGDS_OA_VMID5_DEFAULT 0x00000000 +#define mmGDS_OA_VMID6_DEFAULT 0x00000000 +#define mmGDS_OA_VMID7_DEFAULT 0x00000000 +#define mmGDS_OA_VMID8_DEFAULT 0x00000000 +#define mmGDS_OA_VMID9_DEFAULT 0x00000000 +#define mmGDS_OA_VMID10_DEFAULT 0x00000000 +#define mmGDS_OA_VMID11_DEFAULT 0x00000000 +#define mmGDS_OA_VMID12_DEFAULT 0x00000000 +#define mmGDS_OA_VMID13_DEFAULT 0x00000000 +#define mmGDS_OA_VMID14_DEFAULT 0x00000000 +#define mmGDS_OA_VMID15_DEFAULT 0x00000000 +#define mmGDS_GWS_RESET0_DEFAULT 0x00000000 +#define mmGDS_GWS_RESET1_DEFAULT 0x00000000 +#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000 +#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x0000015f +#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000 +#define mmGDS_OA_RESET_DEFAULT 0x00000000 +#define mmGDS_ENHANCE_DEFAULT 0x00000000 +#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000 +#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000 +#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000 +#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000 +#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000 +#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000 +#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000 +#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000 + + +// addressBlock: gc_rasdec +#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000 +#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000 +#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000 +#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000 +#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000 +#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000 +#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000 +#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000 +#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000 +#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000 +#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000 +#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000 + + +// addressBlock: gc_gfxdec0 +#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000 +#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000 +#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000 +#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000 +#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000 +#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000 +#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000 +#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000 +#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000 +#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000 +#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000 +#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000 +#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000 +#define mmDB_Z_INFO_DEFAULT 0x00000000 +#define mmDB_STENCIL_INFO_DEFAULT 0x00000000 +#define mmDB_Z_READ_BASE_DEFAULT 0x00000000 +#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000 +#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000 +#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000 +#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000 +#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000 +#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 +#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 +#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 +#define mmDB_RENDER_FILTER_DEFAULT 0x00000000 +#define mmDB_Z_INFO2_DEFAULT 0x00000000 +#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 +#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 +#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000 +#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000 +#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000 +#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000 +#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000 +#define mmPA_SC_EDGERULE_DEFAULT 0x00000000 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000 +#define mmCB_TARGET_MASK_DEFAULT 0x00000000 +#define mmCB_SHADER_MASK_DEFAULT 0x00000000 +#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000 +#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000 +#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000 +#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000 +#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000 +#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000 +#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000 +#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000 +#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000 +#define mmCP_PIPEID_DEFAULT 0x00000000 +#define mmCP_RINGID_DEFAULT 0x00000000 +#define mmCP_VMID_DEFAULT 0x00000000 +#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 +#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 +#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 +#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000 +#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 +#define mmCB_BLEND_RED_DEFAULT 0x00000000 +#define mmCB_BLEND_GREEN_DEFAULT 0x00000000 +#define mmCB_BLEND_BLUE_DEFAULT 0x00000000 +#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000 +#define mmCB_DCC_CONTROL_DEFAULT 0x00000000 +#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000 +#define mmDB_STENCILREFMASK_DEFAULT 0x00000000 +#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000 +#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000 +#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000 +#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000 +#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000 +#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000 +#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000 +#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000 +#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000 +#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000 +#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000 +#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000 +#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000 +#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000 +#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000 +#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000 +#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000 +#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000 +#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000 +#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000 +#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000 +#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000 +#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000 +#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000 +#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000 +#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000 +#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000 +#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000 +#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000 +#define mmCS_COPY_STATE_DEFAULT 0x00000000 +#define mmGFX_COPY_STATE_DEFAULT 0x00000000 +#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000 +#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000 +#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000 +#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000 +#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000 +#define mmVGT_DMA_BASE_DEFAULT 0x00000000 +#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000 +#define mmVGT_IMMED_DATA_DEFAULT 0x00000000 +#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000 +#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000 +#define mmDB_EQAA_DEFAULT 0x00000000 +#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000 +#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000 +#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000 +#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000 +#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000 +#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000 +#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000 +#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000 +#define mmVGT_HOS_CNTL_DEFAULT 0x00000000 +#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000 +#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000 +#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000 +#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000 +#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000 +#define mmVGT_GROUP_DECR_DEFAULT 0x00000000 +#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000 +#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000 +#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000 +#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000 +#define mmVGT_GS_MODE_DEFAULT 0x00000000 +#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000 +#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000 +#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000 +#define mmVGT_ENHANCE_DEFAULT 0x00000000 +#define mmVGT_GS_PER_ES_DEFAULT 0x00000000 +#define mmVGT_ES_PER_GS_DEFAULT 0x00000000 +#define mmVGT_GS_PER_VS_DEFAULT 0x00000000 +#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000 +#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000 +#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000 +#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000 +#define mmIA_ENHANCE_DEFAULT 0x00000000 +#define mmVGT_DMA_SIZE_DEFAULT 0x00000000 +#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000 +#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000 +#define mmWD_ENHANCE_DEFAULT 0x00000000 +#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000 +#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000 +#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000 +#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 +#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 +#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 +#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000 +#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 +#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 +#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 +#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000 +#define mmVGT_REUSE_OFF_DEFAULT 0x00000000 +#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000 +#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000 +#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000 +#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000 +#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000 +#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000 +#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000 +#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000 +#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000 +#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000 +#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000 +#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000 +#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000 +#define mmVGT_TF_PARAM_DEFAULT 0x00000000 +#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000 +#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000 +#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000 +#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000 +#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000 +#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000 +#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000 +#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000 +#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000 +#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000 +#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000 +#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000 +#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000 +#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000 +#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000 +#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000 +#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000 +#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000 +#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000 +#define mmCB_COLOR0_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR0_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR1_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR1_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR2_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR2_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR3_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR3_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR4_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR4_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR5_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR5_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR6_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR6_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR7_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000 +#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000 +#define mmCB_COLOR7_INFO_DEFAULT 0x00000000 +#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000 +#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000 +#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000 +#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000 +#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000 +#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000 +#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000 +#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000 +#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000 + + +// addressBlock: gc_gfxudec +#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000 +#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000 +#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000 +#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000 +#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000 +#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000 +#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000 +#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000 +#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000 +#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000 +#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000 +#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000 +#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000 +#define mmSCRATCH_REG0_DEFAULT 0x00000000 +#define mmSCRATCH_REG1_DEFAULT 0x00000000 +#define mmSCRATCH_REG2_DEFAULT 0x00000000 +#define mmSCRATCH_REG3_DEFAULT 0x00000000 +#define mmSCRATCH_REG4_DEFAULT 0x00000000 +#define mmSCRATCH_REG5_DEFAULT 0x00000000 +#define mmSCRATCH_REG6_DEFAULT 0x00000000 +#define mmSCRATCH_REG7_DEFAULT 0x00000000 +#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000 +#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000 +#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000 +#define mmSCRATCH_UMSK_DEFAULT 0x00000000 +#define mmSCRATCH_ADDR_DEFAULT 0x00000000 +#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000 +#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000 +#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000 +#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 +#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 +#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000 +#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000 +#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000 +#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000 +#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000 +#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000 +#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000 +#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000 +#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000 +#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000 +#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000 +#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000 +#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020 +#define mmCP_COHER_CNTL_DEFAULT 0x00000000 +#define mmCP_COHER_SIZE_DEFAULT 0x00000000 +#define mmCP_COHER_BASE_DEFAULT 0x00000000 +#define mmCP_COHER_STATUS_DEFAULT 0x00000000 +#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000 +#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000 +#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000 +#define mmCP_DMA_CNTL_DEFAULT 0x00080030 +#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000 +#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000 +#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000 +#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000 +#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000 +#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000 +#define mmCP_RB_OFFSET_DEFAULT 0x00000000 +#define mmCP_IB1_OFFSET_DEFAULT 0x00000000 +#define mmCP_IB2_OFFSET_DEFAULT 0x00000000 +#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000 +#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000 +#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000 +#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000 +#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000 +#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000 +#define mmCP_CE_COUNTER_DEFAULT 0x00000000 +#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000 +#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000 +#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000 +#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000 +#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000 +#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000 +#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000 +#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000 +#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000 +#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000 +#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000 +#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000 +#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000 +#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000 +#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000 +#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000 +#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000 +#define mmCP_ST_BASE_LO_DEFAULT 0x00000000 +#define mmCP_ST_BASE_HI_DEFAULT 0x00000000 +#define mmCP_ST_BUFSZ_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000 +#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000 +#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000 +#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000 +#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000 +#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000 +#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000 +#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000 +#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_INDEX_TYPE_DEFAULT 0x00000000 +#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000 +#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000 +#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000 +#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000 +#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000 +#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000 +#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000 +#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000 +#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000 +#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000 +#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000 +#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000 +#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000 +#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000 +#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000 +#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000 +#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000 +#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000 +#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000 +#define mmVGT_NUM_INDICES_DEFAULT 0x00000000 +#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000 +#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000 +#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000 +#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000 +#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000 +#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000 +#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000 +#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000 +#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000 +#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 +#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 +#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff +#define mmVGT_OBJECT_ID_DEFAULT 0x00000000 +#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 +#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 +#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 +#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff +#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000 +#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff +#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 +#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80 +#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff +#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff +#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249 +#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff +#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000 +#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000 +#define mmSQC_CACHES_DEFAULT 0x00000000 +#define mmSQC_WRITEBACK_DEFAULT 0x00000000 +#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 +#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 +#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040 +#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000 +#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000 +#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000 +#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000 +#define mmGDS_RD_ADDR_DEFAULT 0x00000000 +#define mmGDS_RD_DATA_DEFAULT 0x00000000 +#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000 +#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000 +#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000 +#define mmGDS_WR_ADDR_DEFAULT 0x00000000 +#define mmGDS_WR_DATA_DEFAULT 0x00000000 +#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000 +#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000 +#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000 +#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000 +#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001 +#define mmGDS_ATOM_BASE_DEFAULT 0x00000000 +#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000 +#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000 +#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000 +#define mmGDS_ATOM_DST_DEFAULT 0x00000000 +#define mmGDS_ATOM_OP_DEFAULT 0x00000000 +#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000 +#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000 +#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000 +#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000 +#define mmGDS_ATOM_READ0_DEFAULT 0x00000000 +#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000 +#define mmGDS_ATOM_READ1_DEFAULT 0x00000000 +#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000 +#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000 +#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000 +#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000 +#define mmGDS_OA_CNTL_DEFAULT 0x00000000 +#define mmGDS_OA_COUNTER_DEFAULT 0x00000000 +#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000 +#define mmGDS_OA_INCDEC_DEFAULT 0x00000000 +#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000 +#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688 +#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000104 +#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011 + + +// addressBlock: gc_perfddec +#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000 +#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl2_atcl2pfcntrdec +#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_utcl2_vml2prdec +#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: gc_perfsdec +#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 +#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 +#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 +#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 +#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 +#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 +#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 +#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 +#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000 +#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 +#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 +#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 +#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000 +#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000 +#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000 +#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000 +#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000 +#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000 +#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007 +#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 +#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000 +#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000 +#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff +#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff +#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff +#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430 +#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000 +#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000 +#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff +#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff +#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff +#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff +#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff +#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff +#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff +#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000 +#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000 +#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000 +#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000 +#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000 +#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000 +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000 +#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000 +#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000 +#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 +#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001 +#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000 +#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 +#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240 + + +// addressBlock: gc_utcl2_atcl2pfcntldec +#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: gc_utcl2_vml2pldec +#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: gc_rlcpdec +#define mmRLC_CNTL_DEFAULT 0x00000001 +#define mmRLC_STAT_DEFAULT 0x00000000 +#define mmRLC_SAFE_MODE_DEFAULT 0x00000000 +#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200 +#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000 +#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000 +#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000 +#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000 +#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000 +#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000 +#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000 +#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000 +#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000 +#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000 +#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff +#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000 +#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000 +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000 +#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000 +#define mmRLC_INT_STAT_DEFAULT 0x00000000 +#define mmRLC_LB_CNTL_DEFAULT 0x00000010 +#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800 +#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000 +#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000 +#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000 +#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004 +#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000 +#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000 +#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000 +#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f +#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000 +#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000 +#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000 +#define mmRLC_GPM_STAT_DEFAULT 0x00100016 +#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000 +#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000 +#define mmRLC_PG_CNTL_DEFAULT 0x00000000 +#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808 +#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001 +#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff +#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c +#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711 +#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff +#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff +#define mmRLC_PG_DELAY_DEFAULT 0x00101010 +#define mmRLC_CU_STATUS_DEFAULT 0x00000000 +#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001 +#define mmRLC_LB_PARAMS_DEFAULT 0x00601008 +#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401 +#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003 +#define mmRLC_MAX_PG_CU_DEFAULT 0x0000000b +#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000 +#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000 +#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000 +#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000 +#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000 +#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000 +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000 +#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000 +#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000 +#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000 +#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000 +#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000 +#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff +#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000 +#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000 +#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000 +#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000 +#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000 +#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000 +#define mmRLC_GPR_REG1_DEFAULT 0x00000000 +#define mmRLC_GPR_REG2_DEFAULT 0x00000000 +#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000 +#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000 +#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000 +#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000 +#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000 +#define mmRLC_SRM_CNTL_DEFAULT 0x00000002 +#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000 +#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000 +#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000 +#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000 +#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000 +#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000 +#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000 +#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000 +#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000 +#define mmRLC_SRM_STAT_DEFAULT 0x00000000 +#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000 +#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000 +#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000 +#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000 +#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000 +#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840 +#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000 +#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000 +#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080 +#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080 +#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080 +#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000 +#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000 +#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000 +#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000 +#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000 +#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000 +#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000 +#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000 +#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c +#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711 +#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000 +#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000 +#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000 +#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000 +#define mmRLC_SPARE_INT_DEFAULT 0x00000000 +#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080 +#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000 +#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000 +#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000 +#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000 +#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000 +#define mmRLC_DSM_TRIG_DEFAULT 0x00000000 +#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000 +#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000 +#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000 +#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000 +#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000 +#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000 +#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000 +#define mmRLC_DS_CNTL_DEFAULT 0x00030003 +#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000 + + +// addressBlock: gc_pwrdec +#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200 +#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000 +#define mmCGTS_RD_REG_DEFAULT 0x00000000 +#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000 +#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000 +#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007 +#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 +#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007 +#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005 +#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008 +#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001 +#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a +#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100 +#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100 +#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100 +#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100 +#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100 +#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100 +#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000 +#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000 +#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000 +#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff +#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004 +#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100 +#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100 +#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100 +#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100 +#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100 +#define mmTD_CGTT_CTRL_DEFAULT 0x00000100 +#define mmTA_CGTT_CTRL_DEFAULT 0x00000100 +#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100 +#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100 +#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100 +#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100 +#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100 +#define mmRLC_PWR_CTRL_DEFAULT 0x00000000 +#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100 +#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000 +#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100 +#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100 + + +// addressBlock: gc_ea_pwrdec +#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100 + + +// addressBlock: gc_utcl2_vmsharedhvdec +#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 +#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 +#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 +#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: gc_hypdec +#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000 +#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000 +#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000 +#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000 +#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000 +#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000 +#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000 +#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000 +#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000 +#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000 +#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000 +#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000 +#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000 +#define mmGRBM_CAM_DATA_DEFAULT 0x00000000 +#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000 +#define mmRLC_GFX_RM_CNTL_ADJ_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000 +#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000 +#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000 +#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001 +#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000 +#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000 +#define mmRLC_CLK_CNTL_DEFAULT 0x00000003 +#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000 +#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000 + + +// addressBlock: gccacind +#define ixGC_CAC_CNTL_DEFAULT 0x000001fe +#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000 +#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001 +#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_PG_0_DEFAULT 0x00000001 +#define ixGC_CAC_ACC_PG0_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_PG_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001 +#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000 +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001 +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001 +#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000 +#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000 +#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000 + + +// addressBlock: secacind +#define ixSE_CAC_CNTL_DEFAULT 0x000001fe +#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000 +#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000 + + +// addressBlock: sqind +#define ixSQ_WAVE_MODE_DEFAULT 0x00000000 +#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000 +#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000 +#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000 +#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000 +#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000 +#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000 +#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000 +#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000 +#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000 +#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000 +#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000 +#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000 +#define ixSQ_WAVE_M0_DEFAULT 0x00000000 +#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000 +#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000 +#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000 + + + + + + + + +// addressBlock: didtind +#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00 +#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff +#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004 +#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000 +#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004 +#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff +#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000 +#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000 +#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000 +#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00 +#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000 +#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00 +#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff +#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004 +#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000 +#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004 +#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff +#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000 +#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000 +#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000 +#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000 +#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00 +#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000 +#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000 +#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000 +#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000 +#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00 +#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff +#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004 +#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000 +#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004 +#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff +#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000 +#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000 +#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000 +#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00 +#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000 +#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00 +#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff +#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004 +#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000 +#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004 +#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff +#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000 +#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000 +#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000 +#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00 +#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000 +#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00 +#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff +#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004 +#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000 +#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004 +#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff +#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000 +#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000 +#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000 +#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000 +#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00 +#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000 +#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 +#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 +#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 +#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa +#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000 +#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000 +#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000 +#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 +#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000 +#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000 +#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000 +#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000 +#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000 + + + + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h new file mode 100644 index 000000000000..db7ef5ede0e5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h @@ -0,0 +1,7491 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _gc_9_1_OFFSET_HEADER +#define _gc_9_1_OFFSET_HEADER + + + +// addressBlock: gc_grbmdec +// base address: 0x8000 +#define mmGRBM_CNTL 0x0000 +#define mmGRBM_CNTL_BASE_IDX 0 +#define mmGRBM_SKEW_CNTL 0x0001 +#define mmGRBM_SKEW_CNTL_BASE_IDX 0 +#define mmGRBM_STATUS2 0x0002 +#define mmGRBM_STATUS2_BASE_IDX 0 +#define mmGRBM_PWR_CNTL 0x0003 +#define mmGRBM_PWR_CNTL_BASE_IDX 0 +#define mmGRBM_STATUS 0x0004 +#define mmGRBM_STATUS_BASE_IDX 0 +#define mmGRBM_STATUS_SE0 0x0005 +#define mmGRBM_STATUS_SE0_BASE_IDX 0 +#define mmGRBM_STATUS_SE1 0x0006 +#define mmGRBM_STATUS_SE1_BASE_IDX 0 +#define mmGRBM_SOFT_RESET 0x0008 +#define mmGRBM_SOFT_RESET_BASE_IDX 0 +#define mmGRBM_CGTT_CLK_CNTL 0x000b +#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0 +#define mmGRBM_GFX_CLKEN_CNTL 0x000c +#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d +#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define mmGRBM_STATUS_SE2 0x000e +#define mmGRBM_STATUS_SE2_BASE_IDX 0 +#define mmGRBM_STATUS_SE3 0x000f +#define mmGRBM_STATUS_SE3_BASE_IDX 0 +#define mmGRBM_READ_ERROR 0x0016 +#define mmGRBM_READ_ERROR_BASE_IDX 0 +#define mmGRBM_READ_ERROR2 0x0017 +#define mmGRBM_READ_ERROR2_BASE_IDX 0 +#define mmGRBM_INT_CNTL 0x0018 +#define mmGRBM_INT_CNTL_BASE_IDX 0 +#define mmGRBM_TRAP_OP 0x0019 +#define mmGRBM_TRAP_OP_BASE_IDX 0 +#define mmGRBM_TRAP_ADDR 0x001a +#define mmGRBM_TRAP_ADDR_BASE_IDX 0 +#define mmGRBM_TRAP_ADDR_MSK 0x001b +#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define mmGRBM_TRAP_WD 0x001c +#define mmGRBM_TRAP_WD_BASE_IDX 0 +#define mmGRBM_TRAP_WD_MSK 0x001d +#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define mmGRBM_DSM_BYPASS 0x001e +#define mmGRBM_DSM_BYPASS_BASE_IDX 0 +#define mmGRBM_WRITE_ERROR 0x001f +#define mmGRBM_WRITE_ERROR_BASE_IDX 0 +#define mmGRBM_IOV_ERROR 0x0020 +#define mmGRBM_IOV_ERROR_BASE_IDX 0 +#define mmGRBM_CHIP_REVISION 0x0021 +#define mmGRBM_CHIP_REVISION_BASE_IDX 0 +#define mmGRBM_GFX_CNTL 0x0022 +#define mmGRBM_GFX_CNTL_BASE_IDX 0 +#define mmGRBM_RSMU_CFG 0x0023 +#define mmGRBM_RSMU_CFG_BASE_IDX 0 +#define mmGRBM_IH_CREDIT 0x0024 +#define mmGRBM_IH_CREDIT_BASE_IDX 0 +#define mmGRBM_PWR_CNTL2 0x0025 +#define mmGRBM_PWR_CNTL2_BASE_IDX 0 +#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 +#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 +#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define mmGRBM_RSMU_READ_ERROR 0x0028 +#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 +#define mmGRBM_CHICKEN_BITS 0x0029 +#define mmGRBM_CHICKEN_BITS_BASE_IDX 0 +#define mmGRBM_NOWHERE 0x003f +#define mmGRBM_NOWHERE_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG0 0x0040 +#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG1 0x0041 +#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG2 0x0042 +#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG3 0x0043 +#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG4 0x0044 +#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG5 0x0045 +#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG6 0x0046 +#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 +#define mmGRBM_SCRATCH_REG7 0x0047 +#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 + + +// addressBlock: gc_cpdec +// base address: 0x8200 +#define mmCP_CPC_STATUS 0x0084 +#define mmCP_CPC_STATUS_BASE_IDX 0 +#define mmCP_CPC_BUSY_STAT 0x0085 +#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 +#define mmCP_CPC_STALLED_STAT1 0x0086 +#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define mmCP_CPF_STATUS 0x0087 +#define mmCP_CPF_STATUS_BASE_IDX 0 +#define mmCP_CPF_BUSY_STAT 0x0088 +#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 +#define mmCP_CPF_STALLED_STAT1 0x0089 +#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define mmCP_CPC_GRBM_FREE_COUNT 0x008b +#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define mmCP_MEC_CNTL 0x008d +#define mmCP_MEC_CNTL_BASE_IDX 0 +#define mmCP_MEC_ME1_HEADER_DUMP 0x008e +#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define mmCP_MEC_ME2_HEADER_DUMP 0x008f +#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 +#define mmCP_CPC_SCRATCH_INDEX 0x0090 +#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define mmCP_CPC_SCRATCH_DATA 0x0091 +#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define mmCP_CPF_GRBM_FREE_COUNT 0x0092 +#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define mmCP_CPC_HALT_HYST_COUNT 0x00a7 +#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad +#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0 +#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae +#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0 +#define mmCP_PRT_LOD_STATS_CNTL2 0x00af +#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0 +#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0 +#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0 +#define mmCP_CE_COMPARE_COUNT 0x00c0 +#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 +#define mmCP_CE_DE_COUNT 0x00c1 +#define mmCP_CE_DE_COUNT_BASE_IDX 0 +#define mmCP_DE_CE_COUNT 0x00c2 +#define mmCP_DE_CE_COUNT_BASE_IDX 0 +#define mmCP_DE_LAST_INVAL_COUNT 0x00c3 +#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 +#define mmCP_DE_DE_COUNT 0x00c4 +#define mmCP_DE_DE_COUNT_BASE_IDX 0 +#define mmCP_STALLED_STAT3 0x019c +#define mmCP_STALLED_STAT3_BASE_IDX 0 +#define mmCP_STALLED_STAT1 0x019d +#define mmCP_STALLED_STAT1_BASE_IDX 0 +#define mmCP_STALLED_STAT2 0x019e +#define mmCP_STALLED_STAT2_BASE_IDX 0 +#define mmCP_BUSY_STAT 0x019f +#define mmCP_BUSY_STAT_BASE_IDX 0 +#define mmCP_STAT 0x01a0 +#define mmCP_STAT_BASE_IDX 0 +#define mmCP_ME_HEADER_DUMP 0x01a1 +#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 +#define mmCP_PFP_HEADER_DUMP 0x01a2 +#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define mmCP_GRBM_FREE_COUNT 0x01a3 +#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define mmCP_CE_HEADER_DUMP 0x01a4 +#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 +#define mmCP_PFP_INSTR_PNTR 0x01a5 +#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define mmCP_ME_INSTR_PNTR 0x01a6 +#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 +#define mmCP_CE_INSTR_PNTR 0x01a7 +#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 +#define mmCP_MEC1_INSTR_PNTR 0x01a8 +#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 +#define mmCP_MEC2_INSTR_PNTR 0x01a9 +#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 +#define mmCP_CSF_STAT 0x01b4 +#define mmCP_CSF_STAT_BASE_IDX 0 +#define mmCP_ME_CNTL 0x01b6 +#define mmCP_ME_CNTL_BASE_IDX 0 +#define mmCP_CNTX_STAT 0x01b8 +#define mmCP_CNTX_STAT_BASE_IDX 0 +#define mmCP_ME_PREEMPTION 0x01b9 +#define mmCP_ME_PREEMPTION_BASE_IDX 0 +#define mmCP_ROQ_THRESHOLDS 0x01bc +#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 +#define mmCP_MEQ_STQ_THRESHOLD 0x01bd +#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 +#define mmCP_RB2_RPTR 0x01be +#define mmCP_RB2_RPTR_BASE_IDX 0 +#define mmCP_RB1_RPTR 0x01bf +#define mmCP_RB1_RPTR_BASE_IDX 0 +#define mmCP_RB0_RPTR 0x01c0 +#define mmCP_RB0_RPTR_BASE_IDX 0 +#define mmCP_RB_RPTR 0x01c0 +#define mmCP_RB_RPTR_BASE_IDX 0 +#define mmCP_RB_WPTR_DELAY 0x01c1 +#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 +#define mmCP_RB_WPTR_POLL_CNTL 0x01c2 +#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmCP_ROQ1_THRESHOLDS 0x01d5 +#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define mmCP_ROQ2_THRESHOLDS 0x01d6 +#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define mmCP_STQ_THRESHOLDS 0x01d7 +#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 +#define mmCP_QUEUE_THRESHOLDS 0x01d8 +#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 +#define mmCP_MEQ_THRESHOLDS 0x01d9 +#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define mmCP_ROQ_AVAIL 0x01da +#define mmCP_ROQ_AVAIL_BASE_IDX 0 +#define mmCP_STQ_AVAIL 0x01db +#define mmCP_STQ_AVAIL_BASE_IDX 0 +#define mmCP_ROQ2_AVAIL 0x01dc +#define mmCP_ROQ2_AVAIL_BASE_IDX 0 +#define mmCP_MEQ_AVAIL 0x01dd +#define mmCP_MEQ_AVAIL_BASE_IDX 0 +#define mmCP_CMD_INDEX 0x01de +#define mmCP_CMD_INDEX_BASE_IDX 0 +#define mmCP_CMD_DATA 0x01df +#define mmCP_CMD_DATA_BASE_IDX 0 +#define mmCP_ROQ_RB_STAT 0x01e0 +#define mmCP_ROQ_RB_STAT_BASE_IDX 0 +#define mmCP_ROQ_IB1_STAT 0x01e1 +#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 +#define mmCP_ROQ_IB2_STAT 0x01e2 +#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 +#define mmCP_STQ_STAT 0x01e3 +#define mmCP_STQ_STAT_BASE_IDX 0 +#define mmCP_STQ_WR_STAT 0x01e4 +#define mmCP_STQ_WR_STAT_BASE_IDX 0 +#define mmCP_MEQ_STAT 0x01e5 +#define mmCP_MEQ_STAT_BASE_IDX 0 +#define mmCP_CEQ1_AVAIL 0x01e6 +#define mmCP_CEQ1_AVAIL_BASE_IDX 0 +#define mmCP_CEQ2_AVAIL 0x01e7 +#define mmCP_CEQ2_AVAIL_BASE_IDX 0 +#define mmCP_CE_ROQ_RB_STAT 0x01e8 +#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 +#define mmCP_CE_ROQ_IB1_STAT 0x01e9 +#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 +#define mmCP_CE_ROQ_IB2_STAT 0x01ea +#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 + + +// addressBlock: gc_padec +// base address: 0x8800 +#define mmVGT_VTX_VECT_EJECT_REG 0x022c +#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d +#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e +#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f +#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define mmVGT_LAST_COPY_STATE 0x0230 +#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 +#define mmVGT_CACHE_INVALIDATION 0x0231 +#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 +#define mmVGT_STRMOUT_DELAY 0x0233 +#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 +#define mmVGT_FIFO_DEPTHS 0x0234 +#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 +#define mmVGT_GS_VERTEX_REUSE 0x0235 +#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 +#define mmVGT_MC_LAT_CNTL 0x0236 +#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 +#define mmIA_CNTL_STATUS 0x0237 +#define mmIA_CNTL_STATUS_BASE_IDX 0 +#define mmVGT_CNTL_STATUS 0x023c +#define mmVGT_CNTL_STATUS_BASE_IDX 0 +#define mmWD_CNTL_STATUS 0x023f +#define mmWD_CNTL_STATUS_BASE_IDX 0 +#define mmCC_GC_PRIM_CONFIG 0x0240 +#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 +#define mmGC_USER_PRIM_CONFIG 0x0241 +#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 +#define mmWD_QOS 0x0242 +#define mmWD_QOS_BASE_IDX 0 +#define mmWD_UTCL1_CNTL 0x0243 +#define mmWD_UTCL1_CNTL_BASE_IDX 0 +#define mmWD_UTCL1_STATUS 0x0244 +#define mmWD_UTCL1_STATUS_BASE_IDX 0 +#define mmIA_UTCL1_CNTL 0x0246 +#define mmIA_UTCL1_CNTL_BASE_IDX 0 +#define mmIA_UTCL1_STATUS 0x0247 +#define mmIA_UTCL1_STATUS_BASE_IDX 0 +#define mmVGT_SYS_CONFIG 0x0263 +#define mmVGT_SYS_CONFIG_BASE_IDX 0 +#define mmVGT_VS_MAX_WAVE_ID 0x0268 +#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 +#define mmVGT_GS_MAX_WAVE_ID 0x0269 +#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define mmGFX_PIPE_CONTROL 0x026d +#define mmGFX_PIPE_CONTROL_BASE_IDX 0 +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f +#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270 +#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271 +#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 +#define mmVGT_DMA_CONTROL 0x0272 +#define mmVGT_DMA_CONTROL_BASE_IDX 0 +#define mmVGT_DMA_LS_HS_CONFIG 0x0273 +#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 +#define mmWD_BUF_RESOURCE_1 0x0276 +#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 +#define mmWD_BUF_RESOURCE_2 0x0277 +#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 +#define mmPA_CL_CNTL_STATUS 0x0284 +#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 +#define mmPA_CL_ENHANCE 0x0285 +#define mmPA_CL_ENHANCE_BASE_IDX 0 +#define mmPA_SU_CNTL_STATUS 0x0294 +#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 +#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295 +#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 +#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 +#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc +#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 +#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd +#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 +#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce +#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 +#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf +#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 +#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 +#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 +#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1 +#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 +#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2 +#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 +#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3 +#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 +#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4 +#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 +#define mmPA_SC_FIFO_SIZE 0x02f3 +#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 +#define mmPA_SC_IF_FIFO_SIZE 0x02f5 +#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 +#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 +#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 +#define mmPA_UTCL1_CNTL1 0x02f9 +#define mmPA_UTCL1_CNTL1_BASE_IDX 0 +#define mmPA_UTCL1_CNTL2 0x02fa +#define mmPA_UTCL1_CNTL2_BASE_IDX 0 +#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb +#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 +#define mmPA_SC_ENHANCE 0x02fc +#define mmPA_SC_ENHANCE_BASE_IDX 0 +#define mmPA_SC_ENHANCE_1 0x02fd +#define mmPA_SC_ENHANCE_1_BASE_IDX 0 +#define mmPA_SC_DSM_CNTL 0x02fe +#define mmPA_SC_DSM_CNTL_BASE_IDX 0 +#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff +#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 + + +// addressBlock: gc_sqdec +// base address: 0x8c00 +#define mmSQ_CONFIG 0x0300 +#define mmSQ_CONFIG_BASE_IDX 0 +#define mmSQC_CONFIG 0x0301 +#define mmSQC_CONFIG_BASE_IDX 0 +#define mmLDS_CONFIG 0x0302 +#define mmLDS_CONFIG_BASE_IDX 0 +#define mmSQ_RANDOM_WAVE_PRI 0x0303 +#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define mmSQ_REG_CREDITS 0x0304 +#define mmSQ_REG_CREDITS_BASE_IDX 0 +#define mmSQ_FIFO_SIZES 0x0305 +#define mmSQ_FIFO_SIZES_BASE_IDX 0 +#define mmSQ_DSM_CNTL 0x0306 +#define mmSQ_DSM_CNTL_BASE_IDX 0 +#define mmSQ_DSM_CNTL2 0x0307 +#define mmSQ_DSM_CNTL2_BASE_IDX 0 +#define mmSQ_RUNTIME_CONFIG 0x0308 +#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 +#define mmSH_MEM_BASES 0x030a +#define mmSH_MEM_BASES_BASE_IDX 0 +#define mmSH_MEM_CONFIG 0x030d +#define mmSH_MEM_CONFIG_BASE_IDX 0 +#define mmCC_GC_SHADER_RATE_CONFIG 0x0312 +#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 +#define mmGC_USER_SHADER_RATE_CONFIG 0x0313 +#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 +#define mmSQ_INTERRUPT_AUTO_MASK 0x0314 +#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define mmSQ_INTERRUPT_MSG_CTRL 0x0315 +#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define mmSQ_UTCL1_CNTL1 0x0317 +#define mmSQ_UTCL1_CNTL1_BASE_IDX 0 +#define mmSQ_UTCL1_CNTL2 0x0318 +#define mmSQ_UTCL1_CNTL2_BASE_IDX 0 +#define mmSQ_UTCL1_STATUS 0x0319 +#define mmSQ_UTCL1_STATUS_BASE_IDX 0 +#define mmSQ_SHADER_TBA_LO 0x031c +#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 +#define mmSQ_SHADER_TBA_HI 0x031d +#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 +#define mmSQ_SHADER_TMA_LO 0x031e +#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 +#define mmSQ_SHADER_TMA_HI 0x031f +#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 +#define mmSQC_DSM_CNTL 0x0320 +#define mmSQC_DSM_CNTL_BASE_IDX 0 +#define mmSQC_DSM_CNTLA 0x0321 +#define mmSQC_DSM_CNTLA_BASE_IDX 0 +#define mmSQC_DSM_CNTLB 0x0322 +#define mmSQC_DSM_CNTLB_BASE_IDX 0 +#define mmSQC_DSM_CNTL2 0x0325 +#define mmSQC_DSM_CNTL2_BASE_IDX 0 +#define mmSQC_DSM_CNTL2A 0x0326 +#define mmSQC_DSM_CNTL2A_BASE_IDX 0 +#define mmSQC_DSM_CNTL2B 0x0327 +#define mmSQC_DSM_CNTL2B_BASE_IDX 0 +#define mmSQC_EDC_FUE_CNTL 0x032b +#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0 +#define mmSQC_EDC_CNT2 0x032c +#define mmSQC_EDC_CNT2_BASE_IDX 0 +#define mmSQC_EDC_CNT3 0x032d +#define mmSQC_EDC_CNT3_BASE_IDX 0 +#define mmSQ_REG_TIMESTAMP 0x0374 +#define mmSQ_REG_TIMESTAMP_BASE_IDX 0 +#define mmSQ_CMD_TIMESTAMP 0x0375 +#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0 +#define mmSQ_IND_INDEX 0x0378 +#define mmSQ_IND_INDEX_BASE_IDX 0 +#define mmSQ_IND_DATA 0x0379 +#define mmSQ_IND_DATA_BASE_IDX 0 +#define mmSQ_CMD 0x037b +#define mmSQ_CMD_BASE_IDX 0 +#define mmSQ_TIME_HI 0x037c +#define mmSQ_TIME_HI_BASE_IDX 0 +#define mmSQ_TIME_LO 0x037d +#define mmSQ_TIME_LO_BASE_IDX 0 +#define mmSQ_DS_0 0x037f +#define mmSQ_DS_0_BASE_IDX 0 +#define mmSQ_DS_1 0x037f +#define mmSQ_DS_1_BASE_IDX 0 +#define mmSQ_EXP_0 0x037f +#define mmSQ_EXP_0_BASE_IDX 0 +#define mmSQ_EXP_1 0x037f +#define mmSQ_EXP_1_BASE_IDX 0 +#define mmSQ_FLAT_0 0x037f +#define mmSQ_FLAT_0_BASE_IDX 0 +#define mmSQ_FLAT_1 0x037f +#define mmSQ_FLAT_1_BASE_IDX 0 +#define mmSQ_GLBL_0 0x037f +#define mmSQ_GLBL_0_BASE_IDX 0 +#define mmSQ_GLBL_1 0x037f +#define mmSQ_GLBL_1_BASE_IDX 0 +#define mmSQ_INST 0x037f +#define mmSQ_INST_BASE_IDX 0 +#define mmSQ_MIMG_0 0x037f +#define mmSQ_MIMG_0_BASE_IDX 0 +#define mmSQ_MIMG_1 0x037f +#define mmSQ_MIMG_1_BASE_IDX 0 +#define mmSQ_MTBUF_0 0x037f +#define mmSQ_MTBUF_0_BASE_IDX 0 +#define mmSQ_MTBUF_1 0x037f +#define mmSQ_MTBUF_1_BASE_IDX 0 +#define mmSQ_MUBUF_0 0x037f +#define mmSQ_MUBUF_0_BASE_IDX 0 +#define mmSQ_MUBUF_1 0x037f +#define mmSQ_MUBUF_1_BASE_IDX 0 +#define mmSQ_SCRATCH_0 0x037f +#define mmSQ_SCRATCH_0_BASE_IDX 0 +#define mmSQ_SCRATCH_1 0x037f +#define mmSQ_SCRATCH_1_BASE_IDX 0 +#define mmSQ_SMEM_0 0x037f +#define mmSQ_SMEM_0_BASE_IDX 0 +#define mmSQ_SMEM_1 0x037f +#define mmSQ_SMEM_1_BASE_IDX 0 +#define mmSQ_SOP1 0x037f +#define mmSQ_SOP1_BASE_IDX 0 +#define mmSQ_SOP2 0x037f +#define mmSQ_SOP2_BASE_IDX 0 +#define mmSQ_SOPC 0x037f +#define mmSQ_SOPC_BASE_IDX 0 +#define mmSQ_SOPK 0x037f +#define mmSQ_SOPK_BASE_IDX 0 +#define mmSQ_SOPP 0x037f +#define mmSQ_SOPP_BASE_IDX 0 +#define mmSQ_VINTRP 0x037f +#define mmSQ_VINTRP_BASE_IDX 0 +#define mmSQ_VOP1 0x037f +#define mmSQ_VOP1_BASE_IDX 0 +#define mmSQ_VOP2 0x037f +#define mmSQ_VOP2_BASE_IDX 0 +#define mmSQ_VOP3P_0 0x037f +#define mmSQ_VOP3P_0_BASE_IDX 0 +#define mmSQ_VOP3P_1 0x037f +#define mmSQ_VOP3P_1_BASE_IDX 0 +#define mmSQ_VOP3_0 0x037f +#define mmSQ_VOP3_0_BASE_IDX 0 +#define mmSQ_VOP3_0_SDST_ENC 0x037f +#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0 +#define mmSQ_VOP3_1 0x037f +#define mmSQ_VOP3_1_BASE_IDX 0 +#define mmSQ_VOPC 0x037f +#define mmSQ_VOPC_BASE_IDX 0 +#define mmSQ_VOP_DPP 0x037f +#define mmSQ_VOP_DPP_BASE_IDX 0 +#define mmSQ_VOP_SDWA 0x037f +#define mmSQ_VOP_SDWA_BASE_IDX 0 +#define mmSQ_VOP_SDWA_SDST_ENC 0x037f +#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 +#define mmSQ_LB_CTR_CTRL 0x0398 +#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 +#define mmSQ_LB_DATA0 0x0399 +#define mmSQ_LB_DATA0_BASE_IDX 0 +#define mmSQ_LB_DATA1 0x039a +#define mmSQ_LB_DATA1_BASE_IDX 0 +#define mmSQ_LB_DATA2 0x039b +#define mmSQ_LB_DATA2_BASE_IDX 0 +#define mmSQ_LB_DATA3 0x039c +#define mmSQ_LB_DATA3_BASE_IDX 0 +#define mmSQ_LB_CTR_SEL 0x039d +#define mmSQ_LB_CTR_SEL_BASE_IDX 0 +#define mmSQ_LB_CTR0_CU 0x039e +#define mmSQ_LB_CTR0_CU_BASE_IDX 0 +#define mmSQ_LB_CTR1_CU 0x039f +#define mmSQ_LB_CTR1_CU_BASE_IDX 0 +#define mmSQ_LB_CTR2_CU 0x03a0 +#define mmSQ_LB_CTR2_CU_BASE_IDX 0 +#define mmSQ_LB_CTR3_CU 0x03a1 +#define mmSQ_LB_CTR3_CU_BASE_IDX 0 +#define mmSQC_EDC_CNT 0x03a2 +#define mmSQC_EDC_CNT_BASE_IDX 0 +#define mmSQ_EDC_SEC_CNT 0x03a3 +#define mmSQ_EDC_SEC_CNT_BASE_IDX 0 +#define mmSQ_EDC_DED_CNT 0x03a4 +#define mmSQ_EDC_DED_CNT_BASE_IDX 0 +#define mmSQ_EDC_INFO 0x03a5 +#define mmSQ_EDC_INFO_BASE_IDX 0 +#define mmSQ_EDC_CNT 0x03a6 +#define mmSQ_EDC_CNT_BASE_IDX 0 +#define mmSQ_EDC_FUE_CNTL 0x03a7 +#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 +#define mmSQ_WREXEC_EXEC_HI 0x03b1 +#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 +#define mmSQ_WREXEC_EXEC_LO 0x03b1 +#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 +#define mmSQ_BUF_RSRC_WORD0 0x03c0 +#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0 +#define mmSQ_BUF_RSRC_WORD1 0x03c1 +#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0 +#define mmSQ_BUF_RSRC_WORD2 0x03c2 +#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0 +#define mmSQ_BUF_RSRC_WORD3 0x03c3 +#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD0 0x03c4 +#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD1 0x03c5 +#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD2 0x03c6 +#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD3 0x03c7 +#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD4 0x03c8 +#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD5 0x03c9 +#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD6 0x03ca +#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0 +#define mmSQ_IMG_RSRC_WORD7 0x03cb +#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0 +#define mmSQ_IMG_SAMP_WORD0 0x03cc +#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0 +#define mmSQ_IMG_SAMP_WORD1 0x03cd +#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0 +#define mmSQ_IMG_SAMP_WORD2 0x03ce +#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0 +#define mmSQ_IMG_SAMP_WORD3 0x03cf +#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0 +#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0 +#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 +#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1 +#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 +#define mmSQ_M0_GPR_IDX_WORD 0x03d2 +#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0 +#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3 +#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 +#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4 +#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 +#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5 +#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 +#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6 +#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 +#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7 +#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 +#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8 +#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: gc_shsdec +// base address: 0x9000 +#define mmSX_DEBUG_1 0x0419 +#define mmSX_DEBUG_1_BASE_IDX 0 +#define mmSPI_PS_MAX_WAVE_ID 0x043a +#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define mmSPI_START_PHASE 0x043b +#define mmSPI_START_PHASE_BASE_IDX 0 +#define mmSPI_GFX_CNTL 0x043c +#define mmSPI_GFX_CNTL_BASE_IDX 0 +#define mmSPI_DSM_CNTL 0x0443 +#define mmSPI_DSM_CNTL_BASE_IDX 0 +#define mmSPI_DSM_CNTL2 0x0444 +#define mmSPI_DSM_CNTL2_BASE_IDX 0 +#define mmSPI_EDC_CNT 0x0445 +#define mmSPI_EDC_CNT_BASE_IDX 0 +#define mmSPI_CONFIG_PS_CU_EN 0x0452 +#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_CNTL 0x04aa +#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab +#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac +#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad +#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae +#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af +#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0 +#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1 +#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2 +#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3 +#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4 +#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5 +#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6 +#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7 +#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8 +#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9 +#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba +#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb +#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc +#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd +#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_9 0x04be +#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf +#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0 +#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1 +#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2 +#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3 +#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4 +#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5 +#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6 +#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7 +#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8 +#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9 +#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define mmSPI_LB_CTR_CTRL 0x04d4 +#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 +#define mmSPI_LB_CU_MASK 0x04d5 +#define mmSPI_LB_CU_MASK_BASE_IDX 0 +#define mmSPI_LB_DATA_REG 0x04d6 +#define mmSPI_LB_DATA_REG_BASE_IDX 0 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 +#define mmSPI_GDS_CREDITS 0x04d8 +#define mmSPI_GDS_CREDITS_BASE_IDX 0 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 +#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db +#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 +#define mmSPI_LB_DATA_WAVES 0x04e4 +#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 +#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 +#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 +#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 +#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 +#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 +#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 + + +// addressBlock: gc_tpdec +// base address: 0x9400 +#define mmTD_CNTL 0x0525 +#define mmTD_CNTL_BASE_IDX 0 +#define mmTD_STATUS 0x0526 +#define mmTD_STATUS_BASE_IDX 0 +#define mmTD_DSM_CNTL 0x052f +#define mmTD_DSM_CNTL_BASE_IDX 0 +#define mmTD_DSM_CNTL2 0x0530 +#define mmTD_DSM_CNTL2_BASE_IDX 0 +#define mmTD_SCRATCH 0x0533 +#define mmTD_SCRATCH_BASE_IDX 0 +#define mmTA_CNTL 0x0541 +#define mmTA_CNTL_BASE_IDX 0 +#define mmTA_CNTL_AUX 0x0542 +#define mmTA_CNTL_AUX_BASE_IDX 0 +#define mmTA_RESERVED_010C 0x0543 +#define mmTA_RESERVED_010C_BASE_IDX 0 +#define mmTA_GRAD_ADJ 0x0544 +#define mmTA_GRAD_ADJ_BASE_IDX 0 +#define mmTA_STATUS 0x0548 +#define mmTA_STATUS_BASE_IDX 0 +#define mmTA_SCRATCH 0x0564 +#define mmTA_SCRATCH_BASE_IDX 0 + + +// addressBlock: gc_gdsdec +// base address: 0x9700 +#define mmGDS_CONFIG 0x05c0 +#define mmGDS_CONFIG_BASE_IDX 0 +#define mmGDS_CNTL_STATUS 0x05c1 +#define mmGDS_CNTL_STATUS_BASE_IDX 0 +#define mmGDS_ENHANCE2 0x05c2 +#define mmGDS_ENHANCE2_BASE_IDX 0 +#define mmGDS_PROTECTION_FAULT 0x05c3 +#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 +#define mmGDS_VM_PROTECTION_FAULT 0x05c4 +#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 +#define mmGDS_EDC_CNT 0x05c5 +#define mmGDS_EDC_CNT_BASE_IDX 0 +#define mmGDS_EDC_GRBM_CNT 0x05c6 +#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 +#define mmGDS_EDC_OA_DED 0x05c7 +#define mmGDS_EDC_OA_DED_BASE_IDX 0 +#define mmGDS_DSM_CNTL 0x05ca +#define mmGDS_DSM_CNTL_BASE_IDX 0 +#define mmGDS_EDC_OA_PHY_CNT 0x05cb +#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 +#define mmGDS_EDC_OA_PIPE_CNT 0x05cc +#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 +#define mmGDS_DSM_CNTL2 0x05cd +#define mmGDS_DSM_CNTL2_BASE_IDX 0 +#define mmGDS_WD_GDS_CSB 0x05ce +#define mmGDS_WD_GDS_CSB_BASE_IDX 0 + + +// addressBlock: gc_rbdec +// base address: 0x9800 +#define mmDB_DEBUG 0x060c +#define mmDB_DEBUG_BASE_IDX 0 +#define mmDB_DEBUG2 0x060d +#define mmDB_DEBUG2_BASE_IDX 0 +#define mmDB_DEBUG3 0x060e +#define mmDB_DEBUG3_BASE_IDX 0 +#define mmDB_DEBUG4 0x060f +#define mmDB_DEBUG4_BASE_IDX 0 +#define mmDB_CREDIT_LIMIT 0x0614 +#define mmDB_CREDIT_LIMIT_BASE_IDX 0 +#define mmDB_WATERMARKS 0x0615 +#define mmDB_WATERMARKS_BASE_IDX 0 +#define mmDB_SUBTILE_CONTROL 0x0616 +#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 +#define mmDB_FREE_CACHELINES 0x0617 +#define mmDB_FREE_CACHELINES_BASE_IDX 0 +#define mmDB_FIFO_DEPTH1 0x0618 +#define mmDB_FIFO_DEPTH1_BASE_IDX 0 +#define mmDB_FIFO_DEPTH2 0x0619 +#define mmDB_FIFO_DEPTH2_BASE_IDX 0 +#define mmDB_EXCEPTION_CONTROL 0x061a +#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define mmDB_RING_CONTROL 0x061b +#define mmDB_RING_CONTROL_BASE_IDX 0 +#define mmDB_MEM_ARB_WATERMARKS 0x061c +#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define mmDB_RMI_CACHE_POLICY 0x061e +#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0 +#define mmDB_DFSM_CONFIG 0x0630 +#define mmDB_DFSM_CONFIG_BASE_IDX 0 +#define mmDB_DFSM_WATERMARK 0x0631 +#define mmDB_DFSM_WATERMARK_BASE_IDX 0 +#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632 +#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 +#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633 +#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 +#define mmDB_DFSM_WATCHDOG 0x0634 +#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 +#define mmDB_DFSM_FLUSH_ENABLE 0x0635 +#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 +#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636 +#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 +#define mmCC_RB_REDUNDANCY 0x063c +#define mmCC_RB_REDUNDANCY_BASE_IDX 0 +#define mmCC_RB_BACKEND_DISABLE 0x063d +#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define mmGB_ADDR_CONFIG 0x063e +#define mmGB_ADDR_CONFIG_BASE_IDX 0 +#define mmGB_BACKEND_MAP 0x063f +#define mmGB_BACKEND_MAP_BASE_IDX 0 +#define mmGB_GPU_ID 0x0640 +#define mmGB_GPU_ID_BASE_IDX 0 +#define mmCC_RB_DAISY_CHAIN 0x0641 +#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 +#define mmGB_ADDR_CONFIG_READ 0x0642 +#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmGB_TILE_MODE0 0x0644 +#define mmGB_TILE_MODE0_BASE_IDX 0 +#define mmGB_TILE_MODE1 0x0645 +#define mmGB_TILE_MODE1_BASE_IDX 0 +#define mmGB_TILE_MODE2 0x0646 +#define mmGB_TILE_MODE2_BASE_IDX 0 +#define mmGB_TILE_MODE3 0x0647 +#define mmGB_TILE_MODE3_BASE_IDX 0 +#define mmGB_TILE_MODE4 0x0648 +#define mmGB_TILE_MODE4_BASE_IDX 0 +#define mmGB_TILE_MODE5 0x0649 +#define mmGB_TILE_MODE5_BASE_IDX 0 +#define mmGB_TILE_MODE6 0x064a +#define mmGB_TILE_MODE6_BASE_IDX 0 +#define mmGB_TILE_MODE7 0x064b +#define mmGB_TILE_MODE7_BASE_IDX 0 +#define mmGB_TILE_MODE8 0x064c +#define mmGB_TILE_MODE8_BASE_IDX 0 +#define mmGB_TILE_MODE9 0x064d +#define mmGB_TILE_MODE9_BASE_IDX 0 +#define mmGB_TILE_MODE10 0x064e +#define mmGB_TILE_MODE10_BASE_IDX 0 +#define mmGB_TILE_MODE11 0x064f +#define mmGB_TILE_MODE11_BASE_IDX 0 +#define mmGB_TILE_MODE12 0x0650 +#define mmGB_TILE_MODE12_BASE_IDX 0 +#define mmGB_TILE_MODE13 0x0651 +#define mmGB_TILE_MODE13_BASE_IDX 0 +#define mmGB_TILE_MODE14 0x0652 +#define mmGB_TILE_MODE14_BASE_IDX 0 +#define mmGB_TILE_MODE15 0x0653 +#define mmGB_TILE_MODE15_BASE_IDX 0 +#define mmGB_TILE_MODE16 0x0654 +#define mmGB_TILE_MODE16_BASE_IDX 0 +#define mmGB_TILE_MODE17 0x0655 +#define mmGB_TILE_MODE17_BASE_IDX 0 +#define mmGB_TILE_MODE18 0x0656 +#define mmGB_TILE_MODE18_BASE_IDX 0 +#define mmGB_TILE_MODE19 0x0657 +#define mmGB_TILE_MODE19_BASE_IDX 0 +#define mmGB_TILE_MODE20 0x0658 +#define mmGB_TILE_MODE20_BASE_IDX 0 +#define mmGB_TILE_MODE21 0x0659 +#define mmGB_TILE_MODE21_BASE_IDX 0 +#define mmGB_TILE_MODE22 0x065a +#define mmGB_TILE_MODE22_BASE_IDX 0 +#define mmGB_TILE_MODE23 0x065b +#define mmGB_TILE_MODE23_BASE_IDX 0 +#define mmGB_TILE_MODE24 0x065c +#define mmGB_TILE_MODE24_BASE_IDX 0 +#define mmGB_TILE_MODE25 0x065d +#define mmGB_TILE_MODE25_BASE_IDX 0 +#define mmGB_TILE_MODE26 0x065e +#define mmGB_TILE_MODE26_BASE_IDX 0 +#define mmGB_TILE_MODE27 0x065f +#define mmGB_TILE_MODE27_BASE_IDX 0 +#define mmGB_TILE_MODE28 0x0660 +#define mmGB_TILE_MODE28_BASE_IDX 0 +#define mmGB_TILE_MODE29 0x0661 +#define mmGB_TILE_MODE29_BASE_IDX 0 +#define mmGB_TILE_MODE30 0x0662 +#define mmGB_TILE_MODE30_BASE_IDX 0 +#define mmGB_TILE_MODE31 0x0663 +#define mmGB_TILE_MODE31_BASE_IDX 0 +#define mmGB_MACROTILE_MODE0 0x0664 +#define mmGB_MACROTILE_MODE0_BASE_IDX 0 +#define mmGB_MACROTILE_MODE1 0x0665 +#define mmGB_MACROTILE_MODE1_BASE_IDX 0 +#define mmGB_MACROTILE_MODE2 0x0666 +#define mmGB_MACROTILE_MODE2_BASE_IDX 0 +#define mmGB_MACROTILE_MODE3 0x0667 +#define mmGB_MACROTILE_MODE3_BASE_IDX 0 +#define mmGB_MACROTILE_MODE4 0x0668 +#define mmGB_MACROTILE_MODE4_BASE_IDX 0 +#define mmGB_MACROTILE_MODE5 0x0669 +#define mmGB_MACROTILE_MODE5_BASE_IDX 0 +#define mmGB_MACROTILE_MODE6 0x066a +#define mmGB_MACROTILE_MODE6_BASE_IDX 0 +#define mmGB_MACROTILE_MODE7 0x066b +#define mmGB_MACROTILE_MODE7_BASE_IDX 0 +#define mmGB_MACROTILE_MODE8 0x066c +#define mmGB_MACROTILE_MODE8_BASE_IDX 0 +#define mmGB_MACROTILE_MODE9 0x066d +#define mmGB_MACROTILE_MODE9_BASE_IDX 0 +#define mmGB_MACROTILE_MODE10 0x066e +#define mmGB_MACROTILE_MODE10_BASE_IDX 0 +#define mmGB_MACROTILE_MODE11 0x066f +#define mmGB_MACROTILE_MODE11_BASE_IDX 0 +#define mmGB_MACROTILE_MODE12 0x0670 +#define mmGB_MACROTILE_MODE12_BASE_IDX 0 +#define mmGB_MACROTILE_MODE13 0x0671 +#define mmGB_MACROTILE_MODE13_BASE_IDX 0 +#define mmGB_MACROTILE_MODE14 0x0672 +#define mmGB_MACROTILE_MODE14_BASE_IDX 0 +#define mmGB_MACROTILE_MODE15 0x0673 +#define mmGB_MACROTILE_MODE15_BASE_IDX 0 +#define mmCB_HW_CONTROL 0x0680 +#define mmCB_HW_CONTROL_BASE_IDX 0 +#define mmCB_HW_CONTROL_1 0x0681 +#define mmCB_HW_CONTROL_1_BASE_IDX 0 +#define mmCB_HW_CONTROL_2 0x0682 +#define mmCB_HW_CONTROL_2_BASE_IDX 0 +#define mmCB_HW_CONTROL_3 0x0683 +#define mmCB_HW_CONTROL_3_BASE_IDX 0 +#define mmCB_HW_MEM_ARBITER_RD 0x0686 +#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 +#define mmCB_HW_MEM_ARBITER_WR 0x0687 +#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 +#define mmCB_DCC_CONFIG 0x0688 +#define mmCB_DCC_CONFIG_BASE_IDX 0 +#define mmGC_USER_RB_REDUNDANCY 0x06de +#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 +#define mmGC_USER_RB_BACKEND_DISABLE 0x06df +#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 + + +// addressBlock: gc_ea_gceadec2 +// base address: 0x9c00 +#define mmGCEA_EDC_CNT 0x0701 +#define mmGCEA_EDC_CNT_BASE_IDX 0 +#define mmGCEA_EDC_CNT2 0x0702 +#define mmGCEA_EDC_CNT2_BASE_IDX 0 +#define mmGCEA_DSM_CNTL 0x0703 +#define mmGCEA_DSM_CNTL_BASE_IDX 0 +#define mmGCEA_DSM_CNTLA 0x0704 +#define mmGCEA_DSM_CNTLA_BASE_IDX 0 +#define mmGCEA_DSM_CNTLB 0x0705 +#define mmGCEA_DSM_CNTLB_BASE_IDX 0 +#define mmGCEA_DSM_CNTL2 0x0706 +#define mmGCEA_DSM_CNTL2_BASE_IDX 0 +#define mmGCEA_DSM_CNTL2A 0x0707 +#define mmGCEA_DSM_CNTL2A_BASE_IDX 0 +#define mmGCEA_DSM_CNTL2B 0x0708 +#define mmGCEA_DSM_CNTL2B_BASE_IDX 0 +#define mmGCEA_TCC_XBR_CREDITS 0x0709 +#define mmGCEA_TCC_XBR_CREDITS_BASE_IDX 0 +#define mmGCEA_TCC_XBR_MAXBURST 0x070a +#define mmGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 +#define mmGCEA_PROBE_CNTL 0x070b +#define mmGCEA_PROBE_CNTL_BASE_IDX 0 +#define mmGCEA_PROBE_MAP 0x070c +#define mmGCEA_PROBE_MAP_BASE_IDX 0 +#define mmGCEA_ERR_STATUS 0x070d +#define mmGCEA_ERR_STATUS_BASE_IDX 0 +#define mmGCEA_MISC2 0x070e +#define mmGCEA_MISC2_BASE_IDX 0 +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x070f +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0710 +#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x0711 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x0712 +#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 +#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x0713 +#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 +#define mmGCEA_SDP_ENABLE 0x0714 +#define mmGCEA_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: gc_rmi_rmidec +// base address: 0x9e00 +#define mmRMI_GENERAL_CNTL 0x0780 +#define mmRMI_GENERAL_CNTL_BASE_IDX 0 +#define mmRMI_GENERAL_CNTL1 0x0781 +#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 +#define mmRMI_GENERAL_STATUS 0x0782 +#define mmRMI_GENERAL_STATUS_BASE_IDX 0 +#define mmRMI_SUBBLOCK_STATUS0 0x0783 +#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 +#define mmRMI_SUBBLOCK_STATUS1 0x0784 +#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 +#define mmRMI_SUBBLOCK_STATUS2 0x0785 +#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 +#define mmRMI_SUBBLOCK_STATUS3 0x0786 +#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 +#define mmRMI_XBAR_CONFIG 0x0787 +#define mmRMI_XBAR_CONFIG_BASE_IDX 0 +#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788 +#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 +#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789 +#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 +#define mmRMI_DEMUX_CNTL 0x078a +#define mmRMI_DEMUX_CNTL_BASE_IDX 0 +#define mmRMI_UTCL1_CNTL1 0x078b +#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 +#define mmRMI_UTCL1_CNTL2 0x078c +#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 +#define mmRMI_UTC_UNIT_CONFIG 0x078d +#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 +#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e +#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 +#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f +#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 +#define mmRMI_SCOREBOARD_CNTL 0x0790 +#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 +#define mmRMI_SCOREBOARD_STATUS0 0x0791 +#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 +#define mmRMI_SCOREBOARD_STATUS1 0x0792 +#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 +#define mmRMI_SCOREBOARD_STATUS2 0x0793 +#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 +#define mmRMI_XBAR_ARBITER_CONFIG 0x0794 +#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 +#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795 +#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 +#define mmRMI_CLOCK_CNTRL 0x0796 +#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 +#define mmRMI_UTCL1_STATUS 0x0797 +#define mmRMI_UTCL1_STATUS_BASE_IDX 0 +#define mmRMI_SPARE 0x079e +#define mmRMI_SPARE_BASE_IDX 0 +#define mmRMI_SPARE_1 0x079f +#define mmRMI_SPARE_1_BASE_IDX 0 +#define mmRMI_SPARE_2 0x07a0 +#define mmRMI_SPARE_2_BASE_IDX 0 + + +// addressBlock: gc_dbgu_gfx_dbgudec +// base address: 0x9f00 +#define mmport_a_addr 0x07c0 +#define mmport_a_addr_BASE_IDX 0 +#define mmport_a_data_lo 0x07c1 +#define mmport_a_data_lo_BASE_IDX 0 +#define mmport_a_data_hi 0x07c2 +#define mmport_a_data_hi_BASE_IDX 0 +#define mmport_b_addr 0x07c3 +#define mmport_b_addr_BASE_IDX 0 +#define mmport_b_data_lo 0x07c4 +#define mmport_b_data_lo_BASE_IDX 0 +#define mmport_b_data_hi 0x07c5 +#define mmport_b_data_hi_BASE_IDX 0 +#define mmport_c_addr 0x07c6 +#define mmport_c_addr_BASE_IDX 0 +#define mmport_c_data_lo 0x07c7 +#define mmport_c_data_lo_BASE_IDX 0 +#define mmport_c_data_hi 0x07c8 +#define mmport_c_data_hi_BASE_IDX 0 +#define mmport_d_addr 0x07c9 +#define mmport_d_addr_BASE_IDX 0 +#define mmport_d_data_lo 0x07ca +#define mmport_d_data_lo_BASE_IDX 0 +#define mmport_d_data_hi 0x07cb +#define mmport_d_data_hi_BASE_IDX 0 + + +// addressBlock: gc_utcl2_atcl2dec +// base address: 0xa000 +#define mmATC_L2_CNTL 0x0800 +#define mmATC_L2_CNTL_BASE_IDX 0 +#define mmATC_L2_CNTL2 0x0801 +#define mmATC_L2_CNTL2_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA0 0x0804 +#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA1 0x0805 +#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA2 0x0806 +#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 +#define mmATC_L2_CNTL3 0x0807 +#define mmATC_L2_CNTL3_BASE_IDX 0 +#define mmATC_L2_STATUS 0x0808 +#define mmATC_L2_STATUS_BASE_IDX 0 +#define mmATC_L2_STATUS2 0x0809 +#define mmATC_L2_STATUS2_BASE_IDX 0 +#define mmATC_L2_MISC_CG 0x080a +#define mmATC_L2_MISC_CG_BASE_IDX 0 +#define mmATC_L2_MEM_POWER_LS 0x080b +#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define mmATC_L2_CGTT_CLK_CTRL 0x080c +#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vml2pfdec +// base address: 0xa100 +#define mmVM_L2_CNTL 0x0840 +#define mmVM_L2_CNTL_BASE_IDX 0 +#define mmVM_L2_CNTL2 0x0841 +#define mmVM_L2_CNTL2_BASE_IDX 0 +#define mmVM_L2_CNTL3 0x0842 +#define mmVM_L2_CNTL3_BASE_IDX 0 +#define mmVM_L2_STATUS 0x0843 +#define mmVM_L2_STATUS_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844 +#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847 +#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848 +#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b +#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define mmVM_L2_CNTL4 0x0857 +#define mmVM_L2_CNTL4_BASE_IDX 0 +#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858 +#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859 +#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a +#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define mmVM_L2_CACHE_PARITY_CNTL 0x085b +#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define mmVM_L2_CGTT_CLK_CTRL 0x085e +#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vml2vcdec +// base address: 0xa200 +#define mmVM_CONTEXT0_CNTL 0x0880 +#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT1_CNTL 0x0881 +#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT2_CNTL 0x0882 +#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT3_CNTL 0x0883 +#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT4_CNTL 0x0884 +#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT5_CNTL 0x0885 +#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT6_CNTL 0x0886 +#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT7_CNTL 0x0887 +#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT8_CNTL 0x0888 +#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT9_CNTL 0x0889 +#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT10_CNTL 0x088a +#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT11_CNTL 0x088b +#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT12_CNTL 0x088c +#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT13_CNTL 0x088d +#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT14_CNTL 0x088e +#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT15_CNTL 0x088f +#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 +#define mmVM_CONTEXTS_DISABLE 0x0890 +#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_SEM 0x0891 +#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_SEM 0x0892 +#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_SEM 0x0893 +#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_SEM 0x0894 +#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_SEM 0x0895 +#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_SEM 0x0896 +#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_SEM 0x0897 +#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_SEM 0x0898 +#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_SEM 0x0899 +#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_SEM 0x089a +#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_SEM 0x089b +#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_SEM 0x089c +#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_SEM 0x089d +#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_SEM 0x089e +#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_SEM 0x089f +#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_SEM 0x08a0 +#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_SEM 0x08a1 +#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_SEM 0x08a2 +#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_REQ 0x08a3 +#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_REQ 0x08a4 +#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_REQ 0x08a5 +#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_REQ 0x08a6 +#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_REQ 0x08a7 +#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_REQ 0x08a8 +#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_REQ 0x08a9 +#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_REQ 0x08aa +#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_REQ 0x08ab +#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_REQ 0x08ac +#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_REQ 0x08ad +#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_REQ 0x08ae +#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_REQ 0x08af +#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_REQ 0x08b0 +#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_REQ 0x08b1 +#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_REQ 0x08b2 +#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_REQ 0x08b3 +#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_REQ 0x08b4 +#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ACK 0x08b5 +#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ACK 0x08b6 +#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ACK 0x08b7 +#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ACK 0x08b8 +#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ACK 0x08b9 +#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ACK 0x08ba +#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ACK 0x08bb +#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ACK 0x08bc +#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ACK 0x08bd +#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ACK 0x08be +#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ACK 0x08bf +#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ACK 0x08c0 +#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ACK 0x08c1 +#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ACK 0x08c2 +#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ACK 0x08c3 +#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ACK 0x08c4 +#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ACK 0x08c5 +#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ACK 0x08c6 +#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vmsharedpfdec +// base address: 0xa590 +#define mmMC_VM_NB_MMIOBASE 0x0964 +#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 +#define mmMC_VM_NB_MMIOLIMIT 0x0965 +#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 +#define mmMC_VM_NB_PCI_CTRL 0x0966 +#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 +#define mmMC_VM_NB_PCI_ARB 0x0967 +#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 +#define mmMC_VM_FB_OFFSET 0x096b +#define mmMC_VM_FB_OFFSET_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define mmMC_VM_STEERING 0x096e +#define mmMC_VM_STEERING_BASE_IDX 0 +#define mmMC_SHARED_VIRT_RESET_REQ 0x096f +#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define mmMC_MEM_POWER_LS 0x0970 +#define mmMC_MEM_POWER_LS_BASE_IDX 0 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define mmMC_VM_APT_CNTL 0x0973 +#define mmMC_VM_APT_CNTL_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 + + +// addressBlock: gc_utcl2_vmsharedvcdec +// base address: 0xa600 +#define mmMC_VM_FB_LOCATION_BASE 0x0980 +#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define mmMC_VM_FB_LOCATION_TOP 0x0981 +#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define mmMC_VM_AGP_TOP 0x0982 +#define mmMC_VM_AGP_TOP_BASE_IDX 0 +#define mmMC_VM_AGP_BOT 0x0983 +#define mmMC_VM_AGP_BOT_BASE_IDX 0 +#define mmMC_VM_AGP_BASE 0x0984 +#define mmMC_VM_AGP_BASE_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB_CNTL 0x0987 +#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: gc_ea_gceadec +// base address: 0xa800 +#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 +#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 +#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 +#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 +#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 +#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define mmGCEA_DRAM_RD_LAZY 0x0a06 +#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0 +#define mmGCEA_DRAM_WR_LAZY 0x0a07 +#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0 +#define mmGCEA_DRAM_RD_CAM_CNTL 0x0a08 +#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define mmGCEA_DRAM_WR_CAM_CNTL 0x0a09 +#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define mmGCEA_DRAM_PAGE_BURST 0x0a0a +#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_AGE 0x0a0b +#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_AGE 0x0a0c +#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_QUEUING 0x0a0d +#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_QUEUING 0x0a0e +#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_FIXED 0x0a0f +#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_FIXED 0x0a10 +#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_URGENCY 0x0a11 +#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_URGENCY 0x0a12 +#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 +#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 +#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmGCEA_ADDRNORM_BASE_ADDR0 0x0a32 +#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x0a33 +#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define mmGCEA_ADDRNORM_BASE_ADDR1 0x0a34 +#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x0a35 +#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x0a36 +#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define mmGCEA_ADDRNORM_HOLE_CNTL 0x0a41 +#define mmGCEA_ADDRNORM_HOLE_CNTL_BASE_IDX 0 +#define mmGCEA_ADDRDEC_BANK_CFG 0x0a42 +#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define mmGCEA_ADDRDEC_MISC_CFG 0x0a43 +#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x0a44 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x0a45 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x0a46 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x0a47 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x0a48 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x0a49 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x0a4a +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x0a4b +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x0a4c +#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 +#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a4d +#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a58 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a59 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a5a +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a5b +#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a5c +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a5d +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a5e +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a5f +#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a60 +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a61 +#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a62 +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a63 +#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a64 +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a65 +#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a66 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a67 +#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a68 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a69 +#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a6a +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a6b +#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x0a6c +#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x0a6d +#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a6e +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a6f +#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a70 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a71 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a72 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a73 +#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a74 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a75 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a76 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a77 +#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a78 +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a79 +#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a7a +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a7b +#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a7c +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a7d +#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a7e +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a7f +#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a80 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a81 +#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a82 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a83 +#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x0a84 +#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x0a85 +#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a86 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a87 +#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x0ad0 +#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x0ad1 +#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x0ad2 +#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x0ad3 +#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmGCEA_IO_RD_COMBINE_FLUSH 0x0ad4 +#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define mmGCEA_IO_WR_COMBINE_FLUSH 0x0ad5 +#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define mmGCEA_IO_GROUP_BURST 0x0ad6 +#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_AGE 0x0ad7 +#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_AGE 0x0ad8 +#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_QUEUING 0x0ad9 +#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_QUEUING 0x0ada +#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_FIXED 0x0adb +#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_FIXED 0x0adc +#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_URGENCY 0x0add +#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_URGENCY 0x0ade +#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x0adf +#define mmGCEA_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x0ae0 +#define mmGCEA_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae1 +#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae2 +#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae3 +#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae4 +#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x0ae5 +#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x0ae6 +#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmGCEA_SDP_ARB_DRAM 0x0ae7 +#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0 +#define mmGCEA_SDP_ARB_FINAL 0x0ae9 +#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0 +#define mmGCEA_SDP_DRAM_PRIORITY 0x0aea +#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define mmGCEA_SDP_IO_PRIORITY 0x0aec +#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0 +#define mmGCEA_SDP_CREDITS 0x0aed +#define mmGCEA_SDP_CREDITS_BASE_IDX 0 +#define mmGCEA_SDP_TAG_RESERVE0 0x0aee +#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 +#define mmGCEA_SDP_TAG_RESERVE1 0x0aef +#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 +#define mmGCEA_SDP_VCC_RESERVE0 0x0af0 +#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 +#define mmGCEA_SDP_VCC_RESERVE1 0x0af1 +#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 +#define mmGCEA_SDP_VCD_RESERVE0 0x0af2 +#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 +#define mmGCEA_SDP_VCD_RESERVE1 0x0af3 +#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 +#define mmGCEA_SDP_REQ_CNTL 0x0af4 +#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0 +#define mmGCEA_MISC 0x0af5 +#define mmGCEA_MISC_BASE_IDX 0 +#define mmGCEA_LATENCY_SAMPLING 0x0af6 +#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0 +#define mmGCEA_PERFCOUNTER_LO 0x0af7 +#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0 +#define mmGCEA_PERFCOUNTER_HI 0x0af8 +#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0 +#define mmGCEA_PERFCOUNTER0_CFG 0x0af9 +#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmGCEA_PERFCOUNTER1_CFG 0x0afa +#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x0afb +#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: gc_tcdec +// base address: 0xac00 +#define mmTCP_INVALIDATE 0x0b00 +#define mmTCP_INVALIDATE_BASE_IDX 0 +#define mmTCP_STATUS 0x0b01 +#define mmTCP_STATUS_BASE_IDX 0 +#define mmTCP_CNTL 0x0b02 +#define mmTCP_CNTL_BASE_IDX 0 +#define mmTCP_CHAN_STEER_LO 0x0b03 +#define mmTCP_CHAN_STEER_LO_BASE_IDX 0 +#define mmTCP_CHAN_STEER_HI 0x0b04 +#define mmTCP_CHAN_STEER_HI_BASE_IDX 0 +#define mmTCP_ADDR_CONFIG 0x0b05 +#define mmTCP_ADDR_CONFIG_BASE_IDX 0 +#define mmTCP_CREDIT 0x0b06 +#define mmTCP_CREDIT_BASE_IDX 0 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 +#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 +#define mmTCP_EDC_CNT 0x0b17 +#define mmTCP_EDC_CNT_BASE_IDX 0 +#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a +#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 +#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b +#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 +#define mmTC_CFG_L1_STORE_POLICY 0x0b1c +#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0 +#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d +#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 +#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e +#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 +#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f +#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 +#define mmTC_CFG_L2_STORE_POLICY1 0x0b20 +#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 +#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21 +#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 +#define mmTC_CFG_L1_VOLATILE 0x0b22 +#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0 +#define mmTC_CFG_L2_VOLATILE 0x0b23 +#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0 +#define mmTCI_STATUS 0x0b61 +#define mmTCI_STATUS_BASE_IDX 0 +#define mmTCI_CNTL_1 0x0b62 +#define mmTCI_CNTL_1_BASE_IDX 0 +#define mmTCI_CNTL_2 0x0b63 +#define mmTCI_CNTL_2_BASE_IDX 0 +#define mmTCC_CTRL 0x0b80 +#define mmTCC_CTRL_BASE_IDX 0 +#define mmTCC_CTRL2 0x0b81 +#define mmTCC_CTRL2_BASE_IDX 0 +#define mmTCC_EDC_CNT 0x0b82 +#define mmTCC_EDC_CNT_BASE_IDX 0 +#define mmTCC_EDC_CNT2 0x0b83 +#define mmTCC_EDC_CNT2_BASE_IDX 0 +#define mmTCC_REDUNDANCY 0x0b84 +#define mmTCC_REDUNDANCY_BASE_IDX 0 +#define mmTCC_EXE_DISABLE 0x0b85 +#define mmTCC_EXE_DISABLE_BASE_IDX 0 +#define mmTCC_DSM_CNTL 0x0b86 +#define mmTCC_DSM_CNTL_BASE_IDX 0 +#define mmTCC_DSM_CNTLA 0x0b87 +#define mmTCC_DSM_CNTLA_BASE_IDX 0 +#define mmTCC_DSM_CNTL2 0x0b88 +#define mmTCC_DSM_CNTL2_BASE_IDX 0 +#define mmTCC_DSM_CNTL2A 0x0b89 +#define mmTCC_DSM_CNTL2A_BASE_IDX 0 +#define mmTCC_DSM_CNTL2B 0x0b8a +#define mmTCC_DSM_CNTL2B_BASE_IDX 0 +#define mmTCC_WBINVL2 0x0b8b +#define mmTCC_WBINVL2_BASE_IDX 0 +#define mmTCC_SOFT_RESET 0x0b8c +#define mmTCC_SOFT_RESET_BASE_IDX 0 +#define mmTCA_CTRL 0x0bc0 +#define mmTCA_CTRL_BASE_IDX 0 +#define mmTCA_BURST_MASK 0x0bc1 +#define mmTCA_BURST_MASK_BASE_IDX 0 +#define mmTCA_BURST_CTRL 0x0bc2 +#define mmTCA_BURST_CTRL_BASE_IDX 0 +#define mmTCA_DSM_CNTL 0x0bc3 +#define mmTCA_DSM_CNTL_BASE_IDX 0 +#define mmTCA_DSM_CNTL2 0x0bc4 +#define mmTCA_DSM_CNTL2_BASE_IDX 0 +#define mmTCA_EDC_CNT 0x0bc5 +#define mmTCA_EDC_CNT_BASE_IDX 0 + + +// addressBlock: gc_shdec +// base address: 0xb000 +#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07 +#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_PS 0x0c08 +#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_PS 0x0c09 +#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a +#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b +#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c +#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d +#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e +#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f +#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10 +#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11 +#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12 +#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13 +#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14 +#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15 +#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16 +#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17 +#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18 +#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19 +#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a +#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b +#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c +#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d +#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e +#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f +#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20 +#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21 +#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22 +#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23 +#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24 +#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25 +#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26 +#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27 +#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28 +#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29 +#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a +#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b +#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46 +#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 +#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47 +#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_VS 0x0c48 +#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_VS 0x0c49 +#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a +#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b +#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c +#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d +#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e +#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f +#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50 +#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51 +#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52 +#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53 +#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54 +#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55 +#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56 +#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57 +#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58 +#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59 +#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a +#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b +#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c +#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d +#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e +#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f +#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60 +#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61 +#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62 +#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63 +#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64 +#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65 +#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66 +#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67 +#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68 +#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69 +#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a +#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b +#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c +#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81 +#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_ES 0x0c84 +#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_ES 0x0c85 +#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87 +#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_GS 0x0c88 +#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_GS 0x0c89 +#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a +#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b +#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc +#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd +#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce +#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf +#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0 +#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1 +#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2 +#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3 +#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4 +#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5 +#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6 +#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7 +#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8 +#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9 +#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda +#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb +#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc +#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd +#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde +#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf +#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0 +#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1 +#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2 +#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3 +#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4 +#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5 +#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6 +#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7 +#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8 +#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9 +#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea +#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb +#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01 +#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 +#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 +#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_LS 0x0d04 +#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_LS 0x0d05 +#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07 +#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_LO_HS 0x0d08 +#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_HI_HS 0x0d09 +#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a +#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b +#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c +#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d +#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e +#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f +#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10 +#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11 +#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12 +#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13 +#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14 +#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15 +#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16 +#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17 +#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18 +#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19 +#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a +#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b +#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c +#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d +#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e +#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f +#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20 +#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21 +#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22 +#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23 +#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24 +#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25 +#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26 +#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27 +#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28 +#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29 +#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a +#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b +#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c +#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d +#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e +#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f +#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50 +#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51 +#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52 +#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53 +#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54 +#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55 +#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56 +#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57 +#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58 +#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59 +#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a +#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b +#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c +#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d +#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e +#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f +#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60 +#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61 +#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62 +#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63 +#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64 +#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65 +#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66 +#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67 +#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68 +#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69 +#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a +#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 +#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b +#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00 +#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define mmCOMPUTE_DIM_X 0x0e01 +#define mmCOMPUTE_DIM_X_BASE_IDX 0 +#define mmCOMPUTE_DIM_Y 0x0e02 +#define mmCOMPUTE_DIM_Y_BASE_IDX 0 +#define mmCOMPUTE_DIM_Z 0x0e03 +#define mmCOMPUTE_DIM_Z_BASE_IDX 0 +#define mmCOMPUTE_START_X 0x0e04 +#define mmCOMPUTE_START_X_BASE_IDX 0 +#define mmCOMPUTE_START_Y 0x0e05 +#define mmCOMPUTE_START_Y_BASE_IDX 0 +#define mmCOMPUTE_START_Z 0x0e06 +#define mmCOMPUTE_START_Z_BASE_IDX 0 +#define mmCOMPUTE_NUM_THREAD_X 0x0e07 +#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define mmCOMPUTE_NUM_THREAD_Y 0x0e08 +#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define mmCOMPUTE_NUM_THREAD_Z 0x0e09 +#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a +#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b +#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define mmCOMPUTE_PGM_LO 0x0e0c +#define mmCOMPUTE_PGM_LO_BASE_IDX 0 +#define mmCOMPUTE_PGM_HI 0x0e0d +#define mmCOMPUTE_PGM_HI_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e +#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f +#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 +#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define mmCOMPUTE_PGM_RSRC1 0x0e12 +#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define mmCOMPUTE_PGM_RSRC2 0x0e13 +#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define mmCOMPUTE_VMID 0x0e14 +#define mmCOMPUTE_VMID_BASE_IDX 0 +#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15 +#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define mmCOMPUTE_TMPRING_SIZE 0x0e18 +#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define mmCOMPUTE_RESTART_X 0x0e1b +#define mmCOMPUTE_RESTART_X_BASE_IDX 0 +#define mmCOMPUTE_RESTART_Y 0x0e1c +#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 +#define mmCOMPUTE_RESTART_Z 0x0e1d +#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 +#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e +#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define mmCOMPUTE_MISC_RESERVED 0x0e1f +#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define mmCOMPUTE_DISPATCH_ID 0x0e20 +#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define mmCOMPUTE_THREADGROUP_ID 0x0e21 +#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define mmCOMPUTE_RELAUNCH 0x0e22 +#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_0 0x0e40 +#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_1 0x0e41 +#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_2 0x0e42 +#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_3 0x0e43 +#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_4 0x0e44 +#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_5 0x0e45 +#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_6 0x0e46 +#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_7 0x0e47 +#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_8 0x0e48 +#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_9 0x0e49 +#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_10 0x0e4a +#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_11 0x0e4b +#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_12 0x0e4c +#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_13 0x0e4d +#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_14 0x0e4e +#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define mmCOMPUTE_USER_DATA_15 0x0e4f +#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define mmCOMPUTE_NOWHERE 0x0e7f +#define mmCOMPUTE_NOWHERE_BASE_IDX 0 + + +// addressBlock: gc_cppdec +// base address: 0xc080 +#define mmCP_DFY_CNTL 0x1020 +#define mmCP_DFY_CNTL_BASE_IDX 0 +#define mmCP_DFY_STAT 0x1021 +#define mmCP_DFY_STAT_BASE_IDX 0 +#define mmCP_DFY_ADDR_HI 0x1022 +#define mmCP_DFY_ADDR_HI_BASE_IDX 0 +#define mmCP_DFY_ADDR_LO 0x1023 +#define mmCP_DFY_ADDR_LO_BASE_IDX 0 +#define mmCP_DFY_DATA_0 0x1024 +#define mmCP_DFY_DATA_0_BASE_IDX 0 +#define mmCP_DFY_DATA_1 0x1025 +#define mmCP_DFY_DATA_1_BASE_IDX 0 +#define mmCP_DFY_DATA_2 0x1026 +#define mmCP_DFY_DATA_2_BASE_IDX 0 +#define mmCP_DFY_DATA_3 0x1027 +#define mmCP_DFY_DATA_3_BASE_IDX 0 +#define mmCP_DFY_DATA_4 0x1028 +#define mmCP_DFY_DATA_4_BASE_IDX 0 +#define mmCP_DFY_DATA_5 0x1029 +#define mmCP_DFY_DATA_5_BASE_IDX 0 +#define mmCP_DFY_DATA_6 0x102a +#define mmCP_DFY_DATA_6_BASE_IDX 0 +#define mmCP_DFY_DATA_7 0x102b +#define mmCP_DFY_DATA_7_BASE_IDX 0 +#define mmCP_DFY_DATA_8 0x102c +#define mmCP_DFY_DATA_8_BASE_IDX 0 +#define mmCP_DFY_DATA_9 0x102d +#define mmCP_DFY_DATA_9_BASE_IDX 0 +#define mmCP_DFY_DATA_10 0x102e +#define mmCP_DFY_DATA_10_BASE_IDX 0 +#define mmCP_DFY_DATA_11 0x102f +#define mmCP_DFY_DATA_11_BASE_IDX 0 +#define mmCP_DFY_DATA_12 0x1030 +#define mmCP_DFY_DATA_12_BASE_IDX 0 +#define mmCP_DFY_DATA_13 0x1031 +#define mmCP_DFY_DATA_13_BASE_IDX 0 +#define mmCP_DFY_DATA_14 0x1032 +#define mmCP_DFY_DATA_14_BASE_IDX 0 +#define mmCP_DFY_DATA_15 0x1033 +#define mmCP_DFY_DATA_15_BASE_IDX 0 +#define mmCP_DFY_CMD 0x1034 +#define mmCP_DFY_CMD_BASE_IDX 0 +#define mmCP_EOPQ_WAIT_TIME 0x1035 +#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036 +#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define mmCPC_INT_INFO 0x1037 +#define mmCPC_INT_INFO_BASE_IDX 0 +#define mmCP_VIRT_STATUS 0x1038 +#define mmCP_VIRT_STATUS_BASE_IDX 0 +#define mmCPC_INT_ADDR 0x1039 +#define mmCPC_INT_ADDR_BASE_IDX 0 +#define mmCPC_INT_PASID 0x103a +#define mmCPC_INT_PASID_BASE_IDX 0 +#define mmCP_GFX_ERROR 0x103b +#define mmCP_GFX_ERROR_BASE_IDX 0 +#define mmCPG_UTCL1_CNTL 0x103c +#define mmCPG_UTCL1_CNTL_BASE_IDX 0 +#define mmCPC_UTCL1_CNTL 0x103d +#define mmCPC_UTCL1_CNTL_BASE_IDX 0 +#define mmCPF_UTCL1_CNTL 0x103e +#define mmCPF_UTCL1_CNTL_BASE_IDX 0 +#define mmCP_AQL_SMM_STATUS 0x103f +#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 +#define mmCP_RB0_BASE 0x1040 +#define mmCP_RB0_BASE_BASE_IDX 0 +#define mmCP_RB_BASE 0x1040 +#define mmCP_RB_BASE_BASE_IDX 0 +#define mmCP_RB0_CNTL 0x1041 +#define mmCP_RB0_CNTL_BASE_IDX 0 +#define mmCP_RB_CNTL 0x1041 +#define mmCP_RB_CNTL_BASE_IDX 0 +#define mmCP_RB_RPTR_WR 0x1042 +#define mmCP_RB_RPTR_WR_BASE_IDX 0 +#define mmCP_RB0_RPTR_ADDR 0x1043 +#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define mmCP_RB_RPTR_ADDR 0x1043 +#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 +#define mmCP_RB0_RPTR_ADDR_HI 0x1044 +#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define mmCP_RB_RPTR_ADDR_HI 0x1044 +#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmCP_RB0_BUFSZ_MASK 0x1045 +#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define mmCP_RB_BUFSZ_MASK 0x1045 +#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 +#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 +#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmGC_PRIV_MODE 0x1048 +#define mmGC_PRIV_MODE_BASE_IDX 0 +#define mmCP_INT_CNTL 0x1049 +#define mmCP_INT_CNTL_BASE_IDX 0 +#define mmCP_INT_STATUS 0x104a +#define mmCP_INT_STATUS_BASE_IDX 0 +#define mmCP_DEVICE_ID 0x104b +#define mmCP_DEVICE_ID_BASE_IDX 0 +#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c +#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define mmCP_RING_PRIORITY_CNTS 0x104c +#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define mmCP_ME0_PIPE0_PRIORITY 0x104d +#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define mmCP_RING0_PRIORITY 0x104d +#define mmCP_RING0_PRIORITY_BASE_IDX 0 +#define mmCP_ME0_PIPE1_PRIORITY 0x104e +#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 +#define mmCP_RING1_PRIORITY 0x104e +#define mmCP_RING1_PRIORITY_BASE_IDX 0 +#define mmCP_ME0_PIPE2_PRIORITY 0x104f +#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 +#define mmCP_RING2_PRIORITY 0x104f +#define mmCP_RING2_PRIORITY_BASE_IDX 0 +#define mmCP_FATAL_ERROR 0x1050 +#define mmCP_FATAL_ERROR_BASE_IDX 0 +#define mmCP_RB_VMID 0x1051 +#define mmCP_RB_VMID_BASE_IDX 0 +#define mmCP_ME0_PIPE0_VMID 0x1052 +#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define mmCP_ME0_PIPE1_VMID 0x1053 +#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 +#define mmCP_RB0_WPTR 0x1054 +#define mmCP_RB0_WPTR_BASE_IDX 0 +#define mmCP_RB_WPTR 0x1054 +#define mmCP_RB_WPTR_BASE_IDX 0 +#define mmCP_RB0_WPTR_HI 0x1055 +#define mmCP_RB0_WPTR_HI_BASE_IDX 0 +#define mmCP_RB_WPTR_HI 0x1055 +#define mmCP_RB_WPTR_HI_BASE_IDX 0 +#define mmCP_RB1_WPTR 0x1056 +#define mmCP_RB1_WPTR_BASE_IDX 0 +#define mmCP_RB1_WPTR_HI 0x1057 +#define mmCP_RB1_WPTR_HI_BASE_IDX 0 +#define mmCP_RB2_WPTR 0x1058 +#define mmCP_RB2_WPTR_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL 0x1059 +#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a +#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b +#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c +#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d +#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define mmCPG_UTCL1_ERROR 0x105e +#define mmCPG_UTCL1_ERROR_BASE_IDX 0 +#define mmCPC_UTCL1_ERROR 0x105f +#define mmCPC_UTCL1_ERROR_BASE_IDX 0 +#define mmCP_RB1_BASE 0x1060 +#define mmCP_RB1_BASE_BASE_IDX 0 +#define mmCP_RB1_CNTL 0x1061 +#define mmCP_RB1_CNTL_BASE_IDX 0 +#define mmCP_RB1_RPTR_ADDR 0x1062 +#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 +#define mmCP_RB1_RPTR_ADDR_HI 0x1063 +#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 +#define mmCP_RB2_BASE 0x1065 +#define mmCP_RB2_BASE_BASE_IDX 0 +#define mmCP_RB2_CNTL 0x1066 +#define mmCP_RB2_CNTL_BASE_IDX 0 +#define mmCP_RB2_RPTR_ADDR 0x1067 +#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 +#define mmCP_RB2_RPTR_ADDR_HI 0x1068 +#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 +#define mmCP_RB0_ACTIVE 0x1069 +#define mmCP_RB0_ACTIVE_BASE_IDX 0 +#define mmCP_RB_ACTIVE 0x1069 +#define mmCP_RB_ACTIVE_BASE_IDX 0 +#define mmCP_INT_CNTL_RING0 0x106a +#define mmCP_INT_CNTL_RING0_BASE_IDX 0 +#define mmCP_INT_CNTL_RING1 0x106b +#define mmCP_INT_CNTL_RING1_BASE_IDX 0 +#define mmCP_INT_CNTL_RING2 0x106c +#define mmCP_INT_CNTL_RING2_BASE_IDX 0 +#define mmCP_INT_STATUS_RING0 0x106d +#define mmCP_INT_STATUS_RING0_BASE_IDX 0 +#define mmCP_INT_STATUS_RING1 0x106e +#define mmCP_INT_STATUS_RING1_BASE_IDX 0 +#define mmCP_INT_STATUS_RING2 0x106f +#define mmCP_INT_STATUS_RING2_BASE_IDX 0 +#define mmCP_PWR_CNTL 0x1078 +#define mmCP_PWR_CNTL_BASE_IDX 0 +#define mmCP_MEM_SLP_CNTL 0x1079 +#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 +#define mmCP_ECC_FIRSTOCCURRENCE 0x107a +#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b +#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c +#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d +#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 +#define mmGB_EDC_MODE 0x107e +#define mmGB_EDC_MODE_BASE_IDX 0 +#define mmCP_PQ_WPTR_POLL_CNTL 0x1083 +#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084 +#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define mmCP_ME1_PIPE0_INT_CNTL 0x1085 +#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define mmCP_ME1_PIPE1_INT_CNTL 0x1086 +#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define mmCP_ME1_PIPE2_INT_CNTL 0x1087 +#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define mmCP_ME1_PIPE3_INT_CNTL 0x1088 +#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define mmCP_ME2_PIPE0_INT_CNTL 0x1089 +#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 +#define mmCP_ME2_PIPE1_INT_CNTL 0x108a +#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 +#define mmCP_ME2_PIPE2_INT_CNTL 0x108b +#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 +#define mmCP_ME2_PIPE3_INT_CNTL 0x108c +#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 +#define mmCP_ME1_PIPE0_INT_STATUS 0x108d +#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define mmCP_ME1_PIPE1_INT_STATUS 0x108e +#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define mmCP_ME1_PIPE2_INT_STATUS 0x108f +#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define mmCP_ME1_PIPE3_INT_STATUS 0x1090 +#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define mmCP_ME2_PIPE0_INT_STATUS 0x1091 +#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 +#define mmCP_ME2_PIPE1_INT_STATUS 0x1092 +#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 +#define mmCP_ME2_PIPE2_INT_STATUS 0x1093 +#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 +#define mmCP_ME2_PIPE3_INT_STATUS 0x1094 +#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 +#define mmCC_GC_EDC_CONFIG 0x1098 +#define mmCC_GC_EDC_CONFIG_BASE_IDX 0 +#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099 +#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define mmCP_ME1_PIPE0_PRIORITY 0x109a +#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define mmCP_ME1_PIPE1_PRIORITY 0x109b +#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define mmCP_ME1_PIPE2_PRIORITY 0x109c +#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define mmCP_ME1_PIPE3_PRIORITY 0x109d +#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e +#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define mmCP_ME2_PIPE0_PRIORITY 0x109f +#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 +#define mmCP_ME2_PIPE1_PRIORITY 0x10a0 +#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 +#define mmCP_ME2_PIPE2_PRIORITY 0x10a1 +#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 +#define mmCP_ME2_PIPE3_PRIORITY 0x10a2 +#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 +#define mmCP_CE_PRGRM_CNTR_START 0x10a3 +#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 +#define mmCP_PFP_PRGRM_CNTR_START 0x10a4 +#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define mmCP_ME_PRGRM_CNTR_START 0x10a5 +#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6 +#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7 +#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 +#define mmCP_CE_INTR_ROUTINE_START 0x10a8 +#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 +#define mmCP_PFP_INTR_ROUTINE_START 0x10a9 +#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define mmCP_ME_INTR_ROUTINE_START 0x10aa +#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab +#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac +#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 +#define mmCP_CONTEXT_CNTL 0x10ad +#define mmCP_CONTEXT_CNTL_BASE_IDX 0 +#define mmCP_MAX_CONTEXT 0x10ae +#define mmCP_MAX_CONTEXT_BASE_IDX 0 +#define mmCP_IQ_WAIT_TIME1 0x10af +#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define mmCP_IQ_WAIT_TIME2 0x10b0 +#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define mmCP_RB0_BASE_HI 0x10b1 +#define mmCP_RB0_BASE_HI_BASE_IDX 0 +#define mmCP_RB1_BASE_HI 0x10b2 +#define mmCP_RB1_BASE_HI_BASE_IDX 0 +#define mmCP_VMID_RESET 0x10b3 +#define mmCP_VMID_RESET_BASE_IDX 0 +#define mmCPC_INT_CNTL 0x10b4 +#define mmCPC_INT_CNTL_BASE_IDX 0 +#define mmCPC_INT_STATUS 0x10b5 +#define mmCPC_INT_STATUS_BASE_IDX 0 +#define mmCP_VMID_PREEMPT 0x10b6 +#define mmCP_VMID_PREEMPT_BASE_IDX 0 +#define mmCPC_INT_CNTX_ID 0x10b7 +#define mmCPC_INT_CNTX_ID_BASE_IDX 0 +#define mmCP_PQ_STATUS 0x10b8 +#define mmCP_PQ_STATUS_BASE_IDX 0 +#define mmCP_CPC_IC_BASE_LO 0x10b9 +#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0 +#define mmCP_CPC_IC_BASE_HI 0x10ba +#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0 +#define mmCP_CPC_IC_BASE_CNTL 0x10bb +#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0 +#define mmCP_CPC_IC_OP_CNTL 0x10bc +#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0 +#define mmCP_MEC1_F32_INT_DIS 0x10bd +#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 +#define mmCP_MEC2_F32_INT_DIS 0x10be +#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 +#define mmCP_VMID_STATUS 0x10bf +#define mmCP_VMID_STATUS_BASE_IDX 0 + + +// addressBlock: gc_cppdec2 +// base address: 0xc600 +#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 +#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 +#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 +#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 +#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 +#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 +#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 +#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 +#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 +#define mmCP_RB_DOORBELL_CLEAR 0x1188 +#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define mmCP_GFX_MQD_CONTROL 0x11a0 +#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define mmCP_GFX_MQD_BASE_ADDR 0x11a1 +#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2 +#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define mmCP_RB_STATUS 0x11a3 +#define mmCP_RB_STATUS_BASE_IDX 0 +#define mmCPG_UTCL1_STATUS 0x11b4 +#define mmCPG_UTCL1_STATUS_BASE_IDX 0 +#define mmCPC_UTCL1_STATUS 0x11b5 +#define mmCPC_UTCL1_STATUS_BASE_IDX 0 +#define mmCPF_UTCL1_STATUS 0x11b6 +#define mmCPF_UTCL1_STATUS_BASE_IDX 0 +#define mmCP_SD_CNTL 0x11b7 +#define mmCP_SD_CNTL_BASE_IDX 0 +#define mmCP_SOFT_RESET_CNTL 0x11b9 +#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define mmCP_CPC_GFX_CNTL 0x11ba +#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: gc_spipdec +// base address: 0xc700 +#define mmSPI_ARB_PRIORITY 0x11c0 +#define mmSPI_ARB_PRIORITY_BASE_IDX 0 +#define mmSPI_ARB_CYCLES_0 0x11c1 +#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 +#define mmSPI_ARB_CYCLES_1 0x11c2 +#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7 +#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 +#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9 +#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca +#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb +#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc +#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd +#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce +#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf +#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0 +#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define mmSPI_COMPUTE_QUEUE_RESET 0x11db +#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc +#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd +#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de +#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df +#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0 +#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1 +#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2 +#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3 +#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4 +#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5 +#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea +#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb +#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec +#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed +#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee +#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef +#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0 +#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1 +#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 +#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4 +#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5 +#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6 +#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7 +#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa +#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 +#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb +#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 +#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc +#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 +#define mmSPI_ARB_CNTL_0 0x11fd +#define mmSPI_ARB_CNTL_0_BASE_IDX 0 + + +// addressBlock: gc_cpphqddec +// base address: 0xc800 +#define mmCP_HQD_GFX_CONTROL 0x123e +#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define mmCP_HQD_GFX_STATUS 0x123f +#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 +#define mmCP_HPD_ROQ_OFFSETS 0x1240 +#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 +#define mmCP_HPD_STATUS0 0x1241 +#define mmCP_HPD_STATUS0_BASE_IDX 0 +#define mmCP_HPD_UTCL1_CNTL 0x1242 +#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define mmCP_HPD_UTCL1_ERROR 0x1243 +#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244 +#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define mmCP_MQD_BASE_ADDR 0x1245 +#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 +#define mmCP_MQD_BASE_ADDR_HI 0x1246 +#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_ACTIVE 0x1247 +#define mmCP_HQD_ACTIVE_BASE_IDX 0 +#define mmCP_HQD_VMID 0x1248 +#define mmCP_HQD_VMID_BASE_IDX 0 +#define mmCP_HQD_PERSISTENT_STATE 0x1249 +#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define mmCP_HQD_PIPE_PRIORITY 0x124a +#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define mmCP_HQD_QUEUE_PRIORITY 0x124b +#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define mmCP_HQD_QUANTUM 0x124c +#define mmCP_HQD_QUANTUM_BASE_IDX 0 +#define mmCP_HQD_PQ_BASE 0x124d +#define mmCP_HQD_PQ_BASE_BASE_IDX 0 +#define mmCP_HQD_PQ_BASE_HI 0x124e +#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define mmCP_HQD_PQ_RPTR 0x124f +#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 +#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define mmCP_HQD_PQ_CONTROL 0x1256 +#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define mmCP_HQD_IB_BASE_ADDR 0x1257 +#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258 +#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_IB_RPTR 0x1259 +#define mmCP_HQD_IB_RPTR_BASE_IDX 0 +#define mmCP_HQD_IB_CONTROL 0x125a +#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 +#define mmCP_HQD_IQ_TIMER 0x125b +#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 +#define mmCP_HQD_IQ_RPTR 0x125c +#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 +#define mmCP_HQD_DEQUEUE_REQUEST 0x125d +#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define mmCP_HQD_DMA_OFFLOAD 0x125e +#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define mmCP_HQD_OFFLOAD 0x125e +#define mmCP_HQD_OFFLOAD_BASE_IDX 0 +#define mmCP_HQD_SEMA_CMD 0x125f +#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 +#define mmCP_HQD_MSG_TYPE 0x1260 +#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 +#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261 +#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262 +#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263 +#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264 +#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define mmCP_HQD_HQ_SCHEDULER0 0x1265 +#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define mmCP_HQD_HQ_STATUS0 0x1265 +#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define mmCP_HQD_HQ_CONTROL0 0x1266 +#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define mmCP_HQD_HQ_SCHEDULER1 0x1266 +#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define mmCP_MQD_CONTROL 0x1267 +#define mmCP_MQD_CONTROL_BASE_IDX 0 +#define mmCP_HQD_HQ_STATUS1 0x1268 +#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define mmCP_HQD_HQ_CONTROL1 0x1269 +#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define mmCP_HQD_EOP_BASE_ADDR 0x126a +#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b +#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_EOP_CONTROL 0x126c +#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define mmCP_HQD_EOP_RPTR 0x126d +#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 +#define mmCP_HQD_EOP_WPTR 0x126e +#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 +#define mmCP_HQD_EOP_EVENTS 0x126f +#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272 +#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273 +#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define mmCP_HQD_CNTL_STACK_SIZE 0x1274 +#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define mmCP_HQD_WG_STATE_OFFSET 0x1275 +#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define mmCP_HQD_CTX_SAVE_SIZE 0x1276 +#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277 +#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define mmCP_HQD_ERROR 0x1278 +#define mmCP_HQD_ERROR_BASE_IDX 0 +#define mmCP_HQD_EOP_WPTR_MEM 0x1279 +#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define mmCP_HQD_AQL_CONTROL 0x127a +#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define mmCP_HQD_PQ_WPTR_LO 0x127b +#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define mmCP_HQD_PQ_WPTR_HI 0x127c +#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 + + +// addressBlock: gc_didtdec +// base address: 0xca00 +#define mmDIDT_IND_INDEX 0x1280 +#define mmDIDT_IND_INDEX_BASE_IDX 0 +#define mmDIDT_IND_DATA 0x1281 +#define mmDIDT_IND_DATA_BASE_IDX 0 + + +// addressBlock: gc_gccacdec +// base address: 0xca10 +#define mmGC_CAC_CTRL_1 0x1284 +#define mmGC_CAC_CTRL_1_BASE_IDX 0 +#define mmGC_CAC_CTRL_2 0x1285 +#define mmGC_CAC_CTRL_2_BASE_IDX 0 +#define mmGC_CAC_CGTT_CLK_CTRL 0x1286 +#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmGC_CAC_AGGR_LOWER 0x1287 +#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 +#define mmGC_CAC_AGGR_UPPER 0x1288 +#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 +#define mmGC_CAC_PG_AGGR_LOWER 0x128b +#define mmGC_CAC_PG_AGGR_LOWER_BASE_IDX 0 +#define mmGC_CAC_PG_AGGR_UPPER 0x128c +#define mmGC_CAC_PG_AGGR_UPPER_BASE_IDX 0 +#define mmGC_CAC_SOFT_CTRL 0x128d +#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 +#define mmGC_DIDT_CTRL0 0x128e +#define mmGC_DIDT_CTRL0_BASE_IDX 0 +#define mmGC_DIDT_CTRL1 0x128f +#define mmGC_DIDT_CTRL1_BASE_IDX 0 +#define mmGC_DIDT_CTRL2 0x1290 +#define mmGC_DIDT_CTRL2_BASE_IDX 0 +#define mmGC_DIDT_WEIGHT 0x1291 +#define mmGC_DIDT_WEIGHT_BASE_IDX 0 +#define mmGC_EDC_CTRL 0x1293 +#define mmGC_EDC_CTRL_BASE_IDX 0 +#define mmGC_EDC_THRESHOLD 0x1294 +#define mmGC_EDC_THRESHOLD_BASE_IDX 0 +#define mmGC_EDC_STATUS 0x1295 +#define mmGC_EDC_STATUS_BASE_IDX 0 +#define mmGC_EDC_OVERFLOW 0x1296 +#define mmGC_EDC_OVERFLOW_BASE_IDX 0 +#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297 +#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 +#define mmGC_DIDT_DROOP_CTRL 0x1298 +#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0 +#define mmGC_EDC_DROOP_CTRL 0x1299 +#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0 +#define mmGC_CAC_IND_INDEX 0x129a +#define mmGC_CAC_IND_INDEX_BASE_IDX 0 +#define mmGC_CAC_IND_DATA 0x129b +#define mmGC_CAC_IND_DATA_BASE_IDX 0 +#define mmSE_CAC_CGTT_CLK_CTRL 0x129c +#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmSE_CAC_IND_INDEX 0x129d +#define mmSE_CAC_IND_INDEX_BASE_IDX 0 +#define mmSE_CAC_IND_DATA 0x129e +#define mmSE_CAC_IND_DATA_BASE_IDX 0 + + +// addressBlock: gc_tcpdec +// base address: 0xca80 +#define mmTCP_WATCH0_ADDR_H 0x12a0 +#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define mmTCP_WATCH0_ADDR_L 0x12a1 +#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define mmTCP_WATCH0_CNTL 0x12a2 +#define mmTCP_WATCH0_CNTL_BASE_IDX 0 +#define mmTCP_WATCH1_ADDR_H 0x12a3 +#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define mmTCP_WATCH1_ADDR_L 0x12a4 +#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define mmTCP_WATCH1_CNTL 0x12a5 +#define mmTCP_WATCH1_CNTL_BASE_IDX 0 +#define mmTCP_WATCH2_ADDR_H 0x12a6 +#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define mmTCP_WATCH2_ADDR_L 0x12a7 +#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define mmTCP_WATCH2_CNTL 0x12a8 +#define mmTCP_WATCH2_CNTL_BASE_IDX 0 +#define mmTCP_WATCH3_ADDR_H 0x12a9 +#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define mmTCP_WATCH3_ADDR_L 0x12aa +#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define mmTCP_WATCH3_CNTL 0x12ab +#define mmTCP_WATCH3_CNTL_BASE_IDX 0 +#define mmTCP_GATCL1_CNTL 0x12b0 +#define mmTCP_GATCL1_CNTL_BASE_IDX 0 +#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1 +#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 +#define mmTCP_GATCL1_DSM_CNTL 0x12b2 +#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0 +#define mmTCP_CNTL2 0x12b4 +#define mmTCP_CNTL2_BASE_IDX 0 +#define mmTCP_UTCL1_CNTL1 0x12b5 +#define mmTCP_UTCL1_CNTL1_BASE_IDX 0 +#define mmTCP_UTCL1_CNTL2 0x12b6 +#define mmTCP_UTCL1_CNTL2_BASE_IDX 0 +#define mmTCP_UTCL1_STATUS 0x12b7 +#define mmTCP_UTCL1_STATUS_BASE_IDX 0 +#define mmTCP_PERFCOUNTER_FILTER 0x12b9 +#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 +#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba +#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 + + +// addressBlock: gc_gdspdec +// base address: 0xcc00 +#define mmGDS_VMID0_BASE 0x1300 +#define mmGDS_VMID0_BASE_BASE_IDX 0 +#define mmGDS_VMID0_SIZE 0x1301 +#define mmGDS_VMID0_SIZE_BASE_IDX 0 +#define mmGDS_VMID1_BASE 0x1302 +#define mmGDS_VMID1_BASE_BASE_IDX 0 +#define mmGDS_VMID1_SIZE 0x1303 +#define mmGDS_VMID1_SIZE_BASE_IDX 0 +#define mmGDS_VMID2_BASE 0x1304 +#define mmGDS_VMID2_BASE_BASE_IDX 0 +#define mmGDS_VMID2_SIZE 0x1305 +#define mmGDS_VMID2_SIZE_BASE_IDX 0 +#define mmGDS_VMID3_BASE 0x1306 +#define mmGDS_VMID3_BASE_BASE_IDX 0 +#define mmGDS_VMID3_SIZE 0x1307 +#define mmGDS_VMID3_SIZE_BASE_IDX 0 +#define mmGDS_VMID4_BASE 0x1308 +#define mmGDS_VMID4_BASE_BASE_IDX 0 +#define mmGDS_VMID4_SIZE 0x1309 +#define mmGDS_VMID4_SIZE_BASE_IDX 0 +#define mmGDS_VMID5_BASE 0x130a +#define mmGDS_VMID5_BASE_BASE_IDX 0 +#define mmGDS_VMID5_SIZE 0x130b +#define mmGDS_VMID5_SIZE_BASE_IDX 0 +#define mmGDS_VMID6_BASE 0x130c +#define mmGDS_VMID6_BASE_BASE_IDX 0 +#define mmGDS_VMID6_SIZE 0x130d +#define mmGDS_VMID6_SIZE_BASE_IDX 0 +#define mmGDS_VMID7_BASE 0x130e +#define mmGDS_VMID7_BASE_BASE_IDX 0 +#define mmGDS_VMID7_SIZE 0x130f +#define mmGDS_VMID7_SIZE_BASE_IDX 0 +#define mmGDS_VMID8_BASE 0x1310 +#define mmGDS_VMID8_BASE_BASE_IDX 0 +#define mmGDS_VMID8_SIZE 0x1311 +#define mmGDS_VMID8_SIZE_BASE_IDX 0 +#define mmGDS_VMID9_BASE 0x1312 +#define mmGDS_VMID9_BASE_BASE_IDX 0 +#define mmGDS_VMID9_SIZE 0x1313 +#define mmGDS_VMID9_SIZE_BASE_IDX 0 +#define mmGDS_VMID10_BASE 0x1314 +#define mmGDS_VMID10_BASE_BASE_IDX 0 +#define mmGDS_VMID10_SIZE 0x1315 +#define mmGDS_VMID10_SIZE_BASE_IDX 0 +#define mmGDS_VMID11_BASE 0x1316 +#define mmGDS_VMID11_BASE_BASE_IDX 0 +#define mmGDS_VMID11_SIZE 0x1317 +#define mmGDS_VMID11_SIZE_BASE_IDX 0 +#define mmGDS_VMID12_BASE 0x1318 +#define mmGDS_VMID12_BASE_BASE_IDX 0 +#define mmGDS_VMID12_SIZE 0x1319 +#define mmGDS_VMID12_SIZE_BASE_IDX 0 +#define mmGDS_VMID13_BASE 0x131a +#define mmGDS_VMID13_BASE_BASE_IDX 0 +#define mmGDS_VMID13_SIZE 0x131b +#define mmGDS_VMID13_SIZE_BASE_IDX 0 +#define mmGDS_VMID14_BASE 0x131c +#define mmGDS_VMID14_BASE_BASE_IDX 0 +#define mmGDS_VMID14_SIZE 0x131d +#define mmGDS_VMID14_SIZE_BASE_IDX 0 +#define mmGDS_VMID15_BASE 0x131e +#define mmGDS_VMID15_BASE_BASE_IDX 0 +#define mmGDS_VMID15_SIZE 0x131f +#define mmGDS_VMID15_SIZE_BASE_IDX 0 +#define mmGDS_GWS_VMID0 0x1320 +#define mmGDS_GWS_VMID0_BASE_IDX 0 +#define mmGDS_GWS_VMID1 0x1321 +#define mmGDS_GWS_VMID1_BASE_IDX 0 +#define mmGDS_GWS_VMID2 0x1322 +#define mmGDS_GWS_VMID2_BASE_IDX 0 +#define mmGDS_GWS_VMID3 0x1323 +#define mmGDS_GWS_VMID3_BASE_IDX 0 +#define mmGDS_GWS_VMID4 0x1324 +#define mmGDS_GWS_VMID4_BASE_IDX 0 +#define mmGDS_GWS_VMID5 0x1325 +#define mmGDS_GWS_VMID5_BASE_IDX 0 +#define mmGDS_GWS_VMID6 0x1326 +#define mmGDS_GWS_VMID6_BASE_IDX 0 +#define mmGDS_GWS_VMID7 0x1327 +#define mmGDS_GWS_VMID7_BASE_IDX 0 +#define mmGDS_GWS_VMID8 0x1328 +#define mmGDS_GWS_VMID8_BASE_IDX 0 +#define mmGDS_GWS_VMID9 0x1329 +#define mmGDS_GWS_VMID9_BASE_IDX 0 +#define mmGDS_GWS_VMID10 0x132a +#define mmGDS_GWS_VMID10_BASE_IDX 0 +#define mmGDS_GWS_VMID11 0x132b +#define mmGDS_GWS_VMID11_BASE_IDX 0 +#define mmGDS_GWS_VMID12 0x132c +#define mmGDS_GWS_VMID12_BASE_IDX 0 +#define mmGDS_GWS_VMID13 0x132d +#define mmGDS_GWS_VMID13_BASE_IDX 0 +#define mmGDS_GWS_VMID14 0x132e +#define mmGDS_GWS_VMID14_BASE_IDX 0 +#define mmGDS_GWS_VMID15 0x132f +#define mmGDS_GWS_VMID15_BASE_IDX 0 +#define mmGDS_OA_VMID0 0x1330 +#define mmGDS_OA_VMID0_BASE_IDX 0 +#define mmGDS_OA_VMID1 0x1331 +#define mmGDS_OA_VMID1_BASE_IDX 0 +#define mmGDS_OA_VMID2 0x1332 +#define mmGDS_OA_VMID2_BASE_IDX 0 +#define mmGDS_OA_VMID3 0x1333 +#define mmGDS_OA_VMID3_BASE_IDX 0 +#define mmGDS_OA_VMID4 0x1334 +#define mmGDS_OA_VMID4_BASE_IDX 0 +#define mmGDS_OA_VMID5 0x1335 +#define mmGDS_OA_VMID5_BASE_IDX 0 +#define mmGDS_OA_VMID6 0x1336 +#define mmGDS_OA_VMID6_BASE_IDX 0 +#define mmGDS_OA_VMID7 0x1337 +#define mmGDS_OA_VMID7_BASE_IDX 0 +#define mmGDS_OA_VMID8 0x1338 +#define mmGDS_OA_VMID8_BASE_IDX 0 +#define mmGDS_OA_VMID9 0x1339 +#define mmGDS_OA_VMID9_BASE_IDX 0 +#define mmGDS_OA_VMID10 0x133a +#define mmGDS_OA_VMID10_BASE_IDX 0 +#define mmGDS_OA_VMID11 0x133b +#define mmGDS_OA_VMID11_BASE_IDX 0 +#define mmGDS_OA_VMID12 0x133c +#define mmGDS_OA_VMID12_BASE_IDX 0 +#define mmGDS_OA_VMID13 0x133d +#define mmGDS_OA_VMID13_BASE_IDX 0 +#define mmGDS_OA_VMID14 0x133e +#define mmGDS_OA_VMID14_BASE_IDX 0 +#define mmGDS_OA_VMID15 0x133f +#define mmGDS_OA_VMID15_BASE_IDX 0 +#define mmGDS_GWS_RESET0 0x1344 +#define mmGDS_GWS_RESET0_BASE_IDX 0 +#define mmGDS_GWS_RESET1 0x1345 +#define mmGDS_GWS_RESET1_BASE_IDX 0 +#define mmGDS_GWS_RESOURCE_RESET 0x1346 +#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 +#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348 +#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 +#define mmGDS_OA_RESET_MASK 0x1349 +#define mmGDS_OA_RESET_MASK_BASE_IDX 0 +#define mmGDS_OA_RESET 0x134a +#define mmGDS_OA_RESET_BASE_IDX 0 +#define mmGDS_ENHANCE 0x134b +#define mmGDS_ENHANCE_BASE_IDX 0 +#define mmGDS_OA_CGPG_RESTORE 0x134c +#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 +#define mmGDS_CS_CTXSW_STATUS 0x134d +#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 +#define mmGDS_CS_CTXSW_CNT0 0x134e +#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_CS_CTXSW_CNT1 0x134f +#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_CS_CTXSW_CNT2 0x1350 +#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_CS_CTXSW_CNT3 0x1351 +#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_GFX_CTXSW_STATUS 0x1352 +#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 +#define mmGDS_VS_CTXSW_CNT0 0x1353 +#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_VS_CTXSW_CNT1 0x1354 +#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_VS_CTXSW_CNT2 0x1355 +#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_VS_CTXSW_CNT3 0x1356 +#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS0_CTXSW_CNT0 0x1357 +#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS0_CTXSW_CNT1 0x1358 +#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS0_CTXSW_CNT2 0x1359 +#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS0_CTXSW_CNT3 0x135a +#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS1_CTXSW_CNT0 0x135b +#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS1_CTXSW_CNT1 0x135c +#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS1_CTXSW_CNT2 0x135d +#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS1_CTXSW_CNT3 0x135e +#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS2_CTXSW_CNT0 0x135f +#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS2_CTXSW_CNT1 0x1360 +#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS2_CTXSW_CNT2 0x1361 +#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS2_CTXSW_CNT3 0x1362 +#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS3_CTXSW_CNT0 0x1363 +#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS3_CTXSW_CNT1 0x1364 +#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS3_CTXSW_CNT2 0x1365 +#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS3_CTXSW_CNT3 0x1366 +#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS4_CTXSW_CNT0 0x1367 +#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS4_CTXSW_CNT1 0x1368 +#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS4_CTXSW_CNT2 0x1369 +#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS4_CTXSW_CNT3 0x136a +#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS5_CTXSW_CNT0 0x136b +#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS5_CTXSW_CNT1 0x136c +#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS5_CTXSW_CNT2 0x136d +#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS5_CTXSW_CNT3 0x136e +#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS6_CTXSW_CNT0 0x136f +#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS6_CTXSW_CNT1 0x1370 +#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS6_CTXSW_CNT2 0x1371 +#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS6_CTXSW_CNT3 0x1372 +#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_PS7_CTXSW_CNT0 0x1373 +#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_PS7_CTXSW_CNT1 0x1374 +#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_PS7_CTXSW_CNT2 0x1375 +#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_PS7_CTXSW_CNT3 0x1376 +#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0 +#define mmGDS_GS_CTXSW_CNT0 0x1377 +#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 +#define mmGDS_GS_CTXSW_CNT1 0x1378 +#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 +#define mmGDS_GS_CTXSW_CNT2 0x1379 +#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 +#define mmGDS_GS_CTXSW_CNT3 0x137a +#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 + + +// addressBlock: gc_rasdec +// base address: 0xce00 +#define mmRAS_SIGNATURE_CONTROL 0x1380 +#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0 +#define mmRAS_SIGNATURE_MASK 0x1381 +#define mmRAS_SIGNATURE_MASK_BASE_IDX 0 +#define mmRAS_SX_SIGNATURE0 0x1382 +#define mmRAS_SX_SIGNATURE0_BASE_IDX 0 +#define mmRAS_SX_SIGNATURE1 0x1383 +#define mmRAS_SX_SIGNATURE1_BASE_IDX 0 +#define mmRAS_SX_SIGNATURE2 0x1384 +#define mmRAS_SX_SIGNATURE2_BASE_IDX 0 +#define mmRAS_SX_SIGNATURE3 0x1385 +#define mmRAS_SX_SIGNATURE3_BASE_IDX 0 +#define mmRAS_DB_SIGNATURE0 0x138b +#define mmRAS_DB_SIGNATURE0_BASE_IDX 0 +#define mmRAS_PA_SIGNATURE0 0x138c +#define mmRAS_PA_SIGNATURE0_BASE_IDX 0 +#define mmRAS_VGT_SIGNATURE0 0x138d +#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0 +#define mmRAS_SQ_SIGNATURE0 0x138e +#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE0 0x138f +#define mmRAS_SC_SIGNATURE0_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE1 0x1390 +#define mmRAS_SC_SIGNATURE1_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE2 0x1391 +#define mmRAS_SC_SIGNATURE2_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE3 0x1392 +#define mmRAS_SC_SIGNATURE3_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE4 0x1393 +#define mmRAS_SC_SIGNATURE4_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE5 0x1394 +#define mmRAS_SC_SIGNATURE5_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE6 0x1395 +#define mmRAS_SC_SIGNATURE6_BASE_IDX 0 +#define mmRAS_SC_SIGNATURE7 0x1396 +#define mmRAS_SC_SIGNATURE7_BASE_IDX 0 +#define mmRAS_IA_SIGNATURE0 0x1397 +#define mmRAS_IA_SIGNATURE0_BASE_IDX 0 +#define mmRAS_IA_SIGNATURE1 0x1398 +#define mmRAS_IA_SIGNATURE1_BASE_IDX 0 +#define mmRAS_SPI_SIGNATURE0 0x1399 +#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0 +#define mmRAS_SPI_SIGNATURE1 0x139a +#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0 +#define mmRAS_TA_SIGNATURE0 0x139b +#define mmRAS_TA_SIGNATURE0_BASE_IDX 0 +#define mmRAS_TD_SIGNATURE0 0x139c +#define mmRAS_TD_SIGNATURE0_BASE_IDX 0 +#define mmRAS_CB_SIGNATURE0 0x139d +#define mmRAS_CB_SIGNATURE0_BASE_IDX 0 +#define mmRAS_BCI_SIGNATURE0 0x139e +#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0 +#define mmRAS_BCI_SIGNATURE1 0x139f +#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0 +#define mmRAS_TA_SIGNATURE1 0x13a0 +#define mmRAS_TA_SIGNATURE1_BASE_IDX 0 + + +// addressBlock: gc_gfxdec0 +// base address: 0x28000 +#define mmDB_RENDER_CONTROL 0x0000 +#define mmDB_RENDER_CONTROL_BASE_IDX 1 +#define mmDB_COUNT_CONTROL 0x0001 +#define mmDB_COUNT_CONTROL_BASE_IDX 1 +#define mmDB_DEPTH_VIEW 0x0002 +#define mmDB_DEPTH_VIEW_BASE_IDX 1 +#define mmDB_RENDER_OVERRIDE 0x0003 +#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 +#define mmDB_RENDER_OVERRIDE2 0x0004 +#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define mmDB_HTILE_DATA_BASE 0x0005 +#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 +#define mmDB_HTILE_DATA_BASE_HI 0x0006 +#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 +#define mmDB_DEPTH_SIZE 0x0007 +#define mmDB_DEPTH_SIZE_BASE_IDX 1 +#define mmDB_DEPTH_BOUNDS_MIN 0x0008 +#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define mmDB_DEPTH_BOUNDS_MAX 0x0009 +#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define mmDB_STENCIL_CLEAR 0x000a +#define mmDB_STENCIL_CLEAR_BASE_IDX 1 +#define mmDB_DEPTH_CLEAR 0x000b +#define mmDB_DEPTH_CLEAR_BASE_IDX 1 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c +#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d +#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define mmDB_Z_INFO 0x000e +#define mmDB_Z_INFO_BASE_IDX 1 +#define mmDB_STENCIL_INFO 0x000f +#define mmDB_STENCIL_INFO_BASE_IDX 1 +#define mmDB_Z_READ_BASE 0x0010 +#define mmDB_Z_READ_BASE_BASE_IDX 1 +#define mmDB_Z_READ_BASE_HI 0x0011 +#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 +#define mmDB_STENCIL_READ_BASE 0x0012 +#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 +#define mmDB_STENCIL_READ_BASE_HI 0x0013 +#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define mmDB_Z_WRITE_BASE 0x0014 +#define mmDB_Z_WRITE_BASE_BASE_IDX 1 +#define mmDB_Z_WRITE_BASE_HI 0x0015 +#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define mmDB_STENCIL_WRITE_BASE 0x0016 +#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define mmDB_STENCIL_WRITE_BASE_HI 0x0017 +#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define mmDB_DFSM_CONTROL 0x0018 +#define mmDB_DFSM_CONTROL_BASE_IDX 1 +#define mmDB_RENDER_FILTER 0x0019 +#define mmDB_RENDER_FILTER_BASE_IDX 1 +#define mmDB_Z_INFO2 0x001a +#define mmDB_Z_INFO2_BASE_IDX 1 +#define mmDB_STENCIL_INFO2 0x001b +#define mmDB_STENCIL_INFO2_BASE_IDX 1 +#define mmTA_BC_BASE_ADDR 0x0020 +#define mmTA_BC_BASE_ADDR_BASE_IDX 1 +#define mmTA_BC_BASE_ADDR_HI 0x0021 +#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 +#define mmCOHER_DEST_BASE_HI_0 0x007a +#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define mmCOHER_DEST_BASE_HI_1 0x007b +#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define mmCOHER_DEST_BASE_HI_2 0x007c +#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define mmCOHER_DEST_BASE_HI_3 0x007d +#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define mmCOHER_DEST_BASE_2 0x007e +#define mmCOHER_DEST_BASE_2_BASE_IDX 1 +#define mmCOHER_DEST_BASE_3 0x007f +#define mmCOHER_DEST_BASE_3_BASE_IDX 1 +#define mmPA_SC_WINDOW_OFFSET 0x0080 +#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_RULE 0x0083 +#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_0_TL 0x0084 +#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_0_BR 0x0085 +#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_1_TL 0x0086 +#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_1_BR 0x0087 +#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_2_TL 0x0088 +#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_2_BR 0x0089 +#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_3_TL 0x008a +#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define mmPA_SC_CLIPRECT_3_BR 0x008b +#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define mmPA_SC_EDGERULE 0x008c +#define mmPA_SC_EDGERULE_BASE_IDX 1 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define mmCB_TARGET_MASK 0x008e +#define mmCB_TARGET_MASK_BASE_IDX 1 +#define mmCB_SHADER_MASK 0x008f +#define mmCB_SHADER_MASK_BASE_IDX 1 +#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define mmCOHER_DEST_BASE_0 0x0092 +#define mmCOHER_DEST_BASE_0_BASE_IDX 1 +#define mmCOHER_DEST_BASE_1 0x0093 +#define mmCOHER_DEST_BASE_1_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_0 0x00b4 +#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_0 0x00b5 +#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_1 0x00b6 +#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_1 0x00b7 +#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_2 0x00b8 +#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_2 0x00b9 +#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_3 0x00ba +#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_3 0x00bb +#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_4 0x00bc +#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_4 0x00bd +#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_5 0x00be +#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_5 0x00bf +#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_6 0x00c0 +#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_6 0x00c1 +#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_7 0x00c2 +#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_7 0x00c3 +#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_8 0x00c4 +#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_8 0x00c5 +#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_9 0x00c6 +#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_9 0x00c7 +#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_10 0x00c8 +#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_10 0x00c9 +#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_11 0x00ca +#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_11 0x00cb +#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_12 0x00cc +#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_12 0x00cd +#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_13 0x00ce +#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_13 0x00cf +#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_14 0x00d0 +#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_14 0x00d1 +#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMIN_15 0x00d2 +#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define mmPA_SC_VPORT_ZMAX_15 0x00d3 +#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define mmPA_SC_RASTER_CONFIG 0x00d4 +#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define mmPA_SC_RASTER_CONFIG_1 0x00d5 +#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define mmCP_PERFMON_CNTX_CNTL 0x00d8 +#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define mmCP_PIPEID 0x00d9 +#define mmCP_PIPEID_BASE_IDX 1 +#define mmCP_RINGID 0x00d9 +#define mmCP_RINGID_BASE_IDX 1 +#define mmCP_VMID 0x00da +#define mmCP_VMID_BASE_IDX 1 +#define mmPA_SC_RIGHT_VERT_GRID 0x00e8 +#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 +#define mmPA_SC_LEFT_VERT_GRID 0x00e9 +#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 +#define mmPA_SC_HORIZ_GRID 0x00ea +#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 +#define mmPA_SC_FOV_WINDOW_LR 0x00eb +#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1 +#define mmPA_SC_FOV_WINDOW_TB 0x00ec +#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define mmCB_BLEND_RED 0x0105 +#define mmCB_BLEND_RED_BASE_IDX 1 +#define mmCB_BLEND_GREEN 0x0106 +#define mmCB_BLEND_GREEN_BASE_IDX 1 +#define mmCB_BLEND_BLUE 0x0107 +#define mmCB_BLEND_BLUE_BASE_IDX 1 +#define mmCB_BLEND_ALPHA 0x0108 +#define mmCB_BLEND_ALPHA_BASE_IDX 1 +#define mmCB_DCC_CONTROL 0x0109 +#define mmCB_DCC_CONTROL_BASE_IDX 1 +#define mmDB_STENCIL_CONTROL 0x010b +#define mmDB_STENCIL_CONTROL_BASE_IDX 1 +#define mmDB_STENCILREFMASK 0x010c +#define mmDB_STENCILREFMASK_BASE_IDX 1 +#define mmDB_STENCILREFMASK_BF 0x010d +#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE 0x010f +#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET 0x0110 +#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE 0x0111 +#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET 0x0112 +#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE 0x0113 +#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET 0x0114 +#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_1 0x0115 +#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_1 0x0116 +#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_1 0x0117 +#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_1 0x0118 +#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_1 0x0119 +#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_1 0x011a +#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_2 0x011b +#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_2 0x011c +#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_2 0x011d +#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_2 0x011e +#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_2 0x011f +#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 +#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_3 0x0121 +#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_3 0x0122 +#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_3 0x0123 +#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_3 0x0124 +#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_3 0x0125 +#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 +#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_4 0x0127 +#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_4 0x0128 +#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_4 0x0129 +#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_4 0x012a +#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_4 0x012b +#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_4 0x012c +#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_5 0x012d +#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_5 0x012e +#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_5 0x012f +#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_5 0x0130 +#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_5 0x0131 +#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 +#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_6 0x0133 +#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_6 0x0134 +#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_6 0x0135 +#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_6 0x0136 +#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_6 0x0137 +#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 +#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_7 0x0139 +#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_7 0x013a +#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_7 0x013b +#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_7 0x013c +#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_7 0x013d +#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_7 0x013e +#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_8 0x013f +#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_8 0x0140 +#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_8 0x0141 +#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_8 0x0142 +#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_8 0x0143 +#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 +#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_9 0x0145 +#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_9 0x0146 +#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_9 0x0147 +#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_9 0x0148 +#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_9 0x0149 +#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_9 0x014a +#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_10 0x014b +#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_10 0x014c +#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_10 0x014d +#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_10 0x014e +#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_10 0x014f +#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 +#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_11 0x0151 +#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_11 0x0152 +#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_11 0x0153 +#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_11 0x0154 +#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_11 0x0155 +#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 +#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_12 0x0157 +#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_12 0x0158 +#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_12 0x0159 +#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_12 0x015a +#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_12 0x015b +#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_12 0x015c +#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_13 0x015d +#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_13 0x015e +#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_13 0x015f +#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_13 0x0160 +#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_13 0x0161 +#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 +#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_14 0x0163 +#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_14 0x0164 +#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_14 0x0165 +#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_14 0x0166 +#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_14 0x0167 +#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 +#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define mmPA_CL_VPORT_XSCALE_15 0x0169 +#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define mmPA_CL_VPORT_XOFFSET_15 0x016a +#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define mmPA_CL_VPORT_YSCALE_15 0x016b +#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define mmPA_CL_VPORT_YOFFSET_15 0x016c +#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define mmPA_CL_VPORT_ZSCALE_15 0x016d +#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define mmPA_CL_VPORT_ZOFFSET_15 0x016e +#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define mmPA_CL_UCP_0_X 0x016f +#define mmPA_CL_UCP_0_X_BASE_IDX 1 +#define mmPA_CL_UCP_0_Y 0x0170 +#define mmPA_CL_UCP_0_Y_BASE_IDX 1 +#define mmPA_CL_UCP_0_Z 0x0171 +#define mmPA_CL_UCP_0_Z_BASE_IDX 1 +#define mmPA_CL_UCP_0_W 0x0172 +#define mmPA_CL_UCP_0_W_BASE_IDX 1 +#define mmPA_CL_UCP_1_X 0x0173 +#define mmPA_CL_UCP_1_X_BASE_IDX 1 +#define mmPA_CL_UCP_1_Y 0x0174 +#define mmPA_CL_UCP_1_Y_BASE_IDX 1 +#define mmPA_CL_UCP_1_Z 0x0175 +#define mmPA_CL_UCP_1_Z_BASE_IDX 1 +#define mmPA_CL_UCP_1_W 0x0176 +#define mmPA_CL_UCP_1_W_BASE_IDX 1 +#define mmPA_CL_UCP_2_X 0x0177 +#define mmPA_CL_UCP_2_X_BASE_IDX 1 +#define mmPA_CL_UCP_2_Y 0x0178 +#define mmPA_CL_UCP_2_Y_BASE_IDX 1 +#define mmPA_CL_UCP_2_Z 0x0179 +#define mmPA_CL_UCP_2_Z_BASE_IDX 1 +#define mmPA_CL_UCP_2_W 0x017a +#define mmPA_CL_UCP_2_W_BASE_IDX 1 +#define mmPA_CL_UCP_3_X 0x017b +#define mmPA_CL_UCP_3_X_BASE_IDX 1 +#define mmPA_CL_UCP_3_Y 0x017c +#define mmPA_CL_UCP_3_Y_BASE_IDX 1 +#define mmPA_CL_UCP_3_Z 0x017d +#define mmPA_CL_UCP_3_Z_BASE_IDX 1 +#define mmPA_CL_UCP_3_W 0x017e +#define mmPA_CL_UCP_3_W_BASE_IDX 1 +#define mmPA_CL_UCP_4_X 0x017f +#define mmPA_CL_UCP_4_X_BASE_IDX 1 +#define mmPA_CL_UCP_4_Y 0x0180 +#define mmPA_CL_UCP_4_Y_BASE_IDX 1 +#define mmPA_CL_UCP_4_Z 0x0181 +#define mmPA_CL_UCP_4_Z_BASE_IDX 1 +#define mmPA_CL_UCP_4_W 0x0182 +#define mmPA_CL_UCP_4_W_BASE_IDX 1 +#define mmPA_CL_UCP_5_X 0x0183 +#define mmPA_CL_UCP_5_X_BASE_IDX 1 +#define mmPA_CL_UCP_5_Y 0x0184 +#define mmPA_CL_UCP_5_Y_BASE_IDX 1 +#define mmPA_CL_UCP_5_Z 0x0185 +#define mmPA_CL_UCP_5_Z_BASE_IDX 1 +#define mmPA_CL_UCP_5_W 0x0186 +#define mmPA_CL_UCP_5_W_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_0 0x0191 +#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_1 0x0192 +#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_2 0x0193 +#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_3 0x0194 +#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_4 0x0195 +#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_5 0x0196 +#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_6 0x0197 +#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_7 0x0198 +#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_8 0x0199 +#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_9 0x019a +#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_10 0x019b +#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_11 0x019c +#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_12 0x019d +#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_13 0x019e +#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_14 0x019f +#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_15 0x01a0 +#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_16 0x01a1 +#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_17 0x01a2 +#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_18 0x01a3 +#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_19 0x01a4 +#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_20 0x01a5 +#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_21 0x01a6 +#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_22 0x01a7 +#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_23 0x01a8 +#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_24 0x01a9 +#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_25 0x01aa +#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_26 0x01ab +#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_27 0x01ac +#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_28 0x01ad +#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_29 0x01ae +#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_30 0x01af +#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define mmSPI_PS_INPUT_CNTL_31 0x01b0 +#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define mmSPI_VS_OUT_CONFIG 0x01b1 +#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 +#define mmSPI_PS_INPUT_ENA 0x01b3 +#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 +#define mmSPI_PS_INPUT_ADDR 0x01b4 +#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define mmSPI_INTERP_CONTROL_0 0x01b5 +#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define mmSPI_PS_IN_CONTROL 0x01b6 +#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 +#define mmSPI_BARYC_CNTL 0x01b8 +#define mmSPI_BARYC_CNTL_BASE_IDX 1 +#define mmSPI_TMPRING_SIZE 0x01ba +#define mmSPI_TMPRING_SIZE_BASE_IDX 1 +#define mmSPI_SHADER_POS_FORMAT 0x01c3 +#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define mmSPI_SHADER_Z_FORMAT 0x01c4 +#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define mmSPI_SHADER_COL_FORMAT 0x01c5 +#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define mmSX_PS_DOWNCONVERT 0x01d5 +#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 +#define mmSX_BLEND_OPT_EPSILON 0x01d6 +#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define mmSX_BLEND_OPT_CONTROL 0x01d7 +#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define mmSX_MRT0_BLEND_OPT 0x01d8 +#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT1_BLEND_OPT 0x01d9 +#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT2_BLEND_OPT 0x01da +#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT3_BLEND_OPT 0x01db +#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT4_BLEND_OPT 0x01dc +#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT5_BLEND_OPT 0x01dd +#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT6_BLEND_OPT 0x01de +#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define mmSX_MRT7_BLEND_OPT 0x01df +#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define mmCB_BLEND0_CONTROL 0x01e0 +#define mmCB_BLEND0_CONTROL_BASE_IDX 1 +#define mmCB_BLEND1_CONTROL 0x01e1 +#define mmCB_BLEND1_CONTROL_BASE_IDX 1 +#define mmCB_BLEND2_CONTROL 0x01e2 +#define mmCB_BLEND2_CONTROL_BASE_IDX 1 +#define mmCB_BLEND3_CONTROL 0x01e3 +#define mmCB_BLEND3_CONTROL_BASE_IDX 1 +#define mmCB_BLEND4_CONTROL 0x01e4 +#define mmCB_BLEND4_CONTROL_BASE_IDX 1 +#define mmCB_BLEND5_CONTROL 0x01e5 +#define mmCB_BLEND5_CONTROL_BASE_IDX 1 +#define mmCB_BLEND6_CONTROL 0x01e6 +#define mmCB_BLEND6_CONTROL_BASE_IDX 1 +#define mmCB_BLEND7_CONTROL 0x01e7 +#define mmCB_BLEND7_CONTROL_BASE_IDX 1 +#define mmCB_MRT0_EPITCH 0x01e8 +#define mmCB_MRT0_EPITCH_BASE_IDX 1 +#define mmCB_MRT1_EPITCH 0x01e9 +#define mmCB_MRT1_EPITCH_BASE_IDX 1 +#define mmCB_MRT2_EPITCH 0x01ea +#define mmCB_MRT2_EPITCH_BASE_IDX 1 +#define mmCB_MRT3_EPITCH 0x01eb +#define mmCB_MRT3_EPITCH_BASE_IDX 1 +#define mmCB_MRT4_EPITCH 0x01ec +#define mmCB_MRT4_EPITCH_BASE_IDX 1 +#define mmCB_MRT5_EPITCH 0x01ed +#define mmCB_MRT5_EPITCH_BASE_IDX 1 +#define mmCB_MRT6_EPITCH 0x01ee +#define mmCB_MRT6_EPITCH_BASE_IDX 1 +#define mmCB_MRT7_EPITCH 0x01ef +#define mmCB_MRT7_EPITCH_BASE_IDX 1 +#define mmCS_COPY_STATE 0x01f3 +#define mmCS_COPY_STATE_BASE_IDX 1 +#define mmGFX_COPY_STATE 0x01f4 +#define mmGFX_COPY_STATE_BASE_IDX 1 +#define mmPA_CL_POINT_X_RAD 0x01f5 +#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 +#define mmPA_CL_POINT_Y_RAD 0x01f6 +#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define mmPA_CL_POINT_SIZE 0x01f7 +#define mmPA_CL_POINT_SIZE_BASE_IDX 1 +#define mmPA_CL_POINT_CULL_RAD 0x01f8 +#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define mmVGT_DMA_BASE_HI 0x01f9 +#define mmVGT_DMA_BASE_HI_BASE_IDX 1 +#define mmVGT_DMA_BASE 0x01fa +#define mmVGT_DMA_BASE_BASE_IDX 1 +#define mmVGT_DRAW_INITIATOR 0x01fc +#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 +#define mmVGT_IMMED_DATA 0x01fd +#define mmVGT_IMMED_DATA_BASE_IDX 1 +#define mmVGT_EVENT_ADDRESS_REG 0x01fe +#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define mmDB_DEPTH_CONTROL 0x0200 +#define mmDB_DEPTH_CONTROL_BASE_IDX 1 +#define mmDB_EQAA 0x0201 +#define mmDB_EQAA_BASE_IDX 1 +#define mmCB_COLOR_CONTROL 0x0202 +#define mmCB_COLOR_CONTROL_BASE_IDX 1 +#define mmDB_SHADER_CONTROL 0x0203 +#define mmDB_SHADER_CONTROL_BASE_IDX 1 +#define mmPA_CL_CLIP_CNTL 0x0204 +#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 +#define mmPA_SU_SC_MODE_CNTL 0x0205 +#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define mmPA_CL_VTE_CNTL 0x0206 +#define mmPA_CL_VTE_CNTL_BASE_IDX 1 +#define mmPA_CL_VS_OUT_CNTL 0x0207 +#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define mmPA_CL_NANINF_CNTL 0x0208 +#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 +#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a +#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define mmPA_SU_PRIM_FILTER_CNTL 0x020b +#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d +#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 +#define mmPA_CL_NGG_CNTL 0x020e +#define mmPA_CL_NGG_CNTL_BASE_IDX 1 +#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define mmPA_SU_POINT_SIZE 0x0280 +#define mmPA_SU_POINT_SIZE_BASE_IDX 1 +#define mmPA_SU_POINT_MINMAX 0x0281 +#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 +#define mmPA_SU_LINE_CNTL 0x0282 +#define mmPA_SU_LINE_CNTL_BASE_IDX 1 +#define mmPA_SC_LINE_STIPPLE 0x0283 +#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define mmVGT_OUTPUT_PATH_CNTL 0x0284 +#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 +#define mmVGT_HOS_CNTL 0x0285 +#define mmVGT_HOS_CNTL_BASE_IDX 1 +#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define mmVGT_HOS_REUSE_DEPTH 0x0288 +#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 +#define mmVGT_GROUP_PRIM_TYPE 0x0289 +#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 +#define mmVGT_GROUP_FIRST_DECR 0x028a +#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 +#define mmVGT_GROUP_DECR 0x028b +#define mmVGT_GROUP_DECR_BASE_IDX 1 +#define mmVGT_GROUP_VECT_0_CNTL 0x028c +#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 +#define mmVGT_GROUP_VECT_1_CNTL 0x028d +#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e +#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f +#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 +#define mmVGT_GS_MODE 0x0290 +#define mmVGT_GS_MODE_BASE_IDX 1 +#define mmVGT_GS_ONCHIP_CNTL 0x0291 +#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 +#define mmPA_SC_MODE_CNTL_0 0x0292 +#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define mmPA_SC_MODE_CNTL_1 0x0293 +#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define mmVGT_ENHANCE 0x0294 +#define mmVGT_ENHANCE_BASE_IDX 1 +#define mmVGT_GS_PER_ES 0x0295 +#define mmVGT_GS_PER_ES_BASE_IDX 1 +#define mmVGT_ES_PER_GS 0x0296 +#define mmVGT_ES_PER_GS_BASE_IDX 1 +#define mmVGT_GS_PER_VS 0x0297 +#define mmVGT_GS_PER_VS_BASE_IDX 1 +#define mmVGT_GSVS_RING_OFFSET_1 0x0298 +#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 +#define mmVGT_GSVS_RING_OFFSET_2 0x0299 +#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 +#define mmVGT_GSVS_RING_OFFSET_3 0x029a +#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 +#define mmVGT_GS_OUT_PRIM_TYPE 0x029b +#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define mmIA_ENHANCE 0x029c +#define mmIA_ENHANCE_BASE_IDX 1 +#define mmVGT_DMA_SIZE 0x029d +#define mmVGT_DMA_SIZE_BASE_IDX 1 +#define mmVGT_DMA_MAX_SIZE 0x029e +#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define mmVGT_DMA_INDEX_TYPE 0x029f +#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define mmWD_ENHANCE 0x02a0 +#define mmWD_ENHANCE_BASE_IDX 1 +#define mmVGT_PRIMITIVEID_EN 0x02a1 +#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define mmVGT_DMA_NUM_INSTANCES 0x02a2 +#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define mmVGT_PRIMITIVEID_RESET 0x02a3 +#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 +#define mmVGT_EVENT_INITIATOR 0x02a4 +#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 +#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 +#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 +#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 +#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7 +#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1 +#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 +#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 +#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 +#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 +#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab +#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 +#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac +#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 +#define mmVGT_REUSE_OFF 0x02ad +#define mmVGT_REUSE_OFF_BASE_IDX 1 +#define mmVGT_VTX_CNT_EN 0x02ae +#define mmVGT_VTX_CNT_EN_BASE_IDX 1 +#define mmDB_HTILE_SURFACE 0x02af +#define mmDB_HTILE_SURFACE_BASE_IDX 1 +#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define mmDB_PRELOAD_CONTROL 0x02b2 +#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 +#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 +#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 +#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 +#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb +#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc +#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd +#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf +#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 +#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 +#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 +#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 +#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define mmVGT_GS_MAX_VERT_OUT 0x02ce +#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define mmVGT_TESS_DISTRIBUTION 0x02d4 +#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define mmVGT_SHADER_STAGES_EN 0x02d5 +#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define mmVGT_LS_HS_CONFIG 0x02d6 +#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 +#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 +#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 +#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 +#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 +#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 +#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 +#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da +#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 +#define mmVGT_TF_PARAM 0x02db +#define mmVGT_TF_PARAM_BASE_IDX 1 +#define mmDB_ALPHA_TO_MASK 0x02dc +#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 +#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd +#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df +#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define mmVGT_GS_INSTANCE_CNT 0x02e4 +#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define mmVGT_STRMOUT_CONFIG 0x02e5 +#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 +#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 +#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 +#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 +#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 +#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 +#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define mmPA_SC_LINE_CNTL 0x02f7 +#define mmPA_SC_LINE_CNTL_BASE_IDX 1 +#define mmPA_SC_AA_CONFIG 0x02f8 +#define mmPA_SC_AA_CONFIG_BASE_IDX 1 +#define mmPA_SU_VTX_CNTL 0x02f9 +#define mmPA_SU_VTX_CNTL_BASE_IDX 1 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa +#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb +#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc +#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd +#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define mmPA_SC_SHADER_CONTROL 0x0310 +#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define mmPA_SC_BINNER_CNTL_0 0x0311 +#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define mmPA_SC_BINNER_CNTL_1 0x0312 +#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 +#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define mmPA_SC_NGG_MODE_CNTL 0x0314 +#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 +#define mmVGT_OUT_DEALLOC_CNTL 0x0317 +#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 +#define mmCB_COLOR0_BASE 0x0318 +#define mmCB_COLOR0_BASE_BASE_IDX 1 +#define mmCB_COLOR0_BASE_EXT 0x0319 +#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR0_ATTRIB2 0x031a +#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR0_VIEW 0x031b +#define mmCB_COLOR0_VIEW_BASE_IDX 1 +#define mmCB_COLOR0_INFO 0x031c +#define mmCB_COLOR0_INFO_BASE_IDX 1 +#define mmCB_COLOR0_ATTRIB 0x031d +#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR0_DCC_CONTROL 0x031e +#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR0_CMASK 0x031f +#define mmCB_COLOR0_CMASK_BASE_IDX 1 +#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320 +#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR0_FMASK 0x0321 +#define mmCB_COLOR0_FMASK_BASE_IDX 1 +#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322 +#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR0_CLEAR_WORD0 0x0323 +#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR0_CLEAR_WORD1 0x0324 +#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR0_DCC_BASE 0x0325 +#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR0_DCC_BASE_EXT 0x0326 +#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR1_BASE 0x0327 +#define mmCB_COLOR1_BASE_BASE_IDX 1 +#define mmCB_COLOR1_BASE_EXT 0x0328 +#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR1_ATTRIB2 0x0329 +#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR1_VIEW 0x032a +#define mmCB_COLOR1_VIEW_BASE_IDX 1 +#define mmCB_COLOR1_INFO 0x032b +#define mmCB_COLOR1_INFO_BASE_IDX 1 +#define mmCB_COLOR1_ATTRIB 0x032c +#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR1_DCC_CONTROL 0x032d +#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR1_CMASK 0x032e +#define mmCB_COLOR1_CMASK_BASE_IDX 1 +#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f +#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR1_FMASK 0x0330 +#define mmCB_COLOR1_FMASK_BASE_IDX 1 +#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331 +#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR1_CLEAR_WORD0 0x0332 +#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR1_CLEAR_WORD1 0x0333 +#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR1_DCC_BASE 0x0334 +#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR1_DCC_BASE_EXT 0x0335 +#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR2_BASE 0x0336 +#define mmCB_COLOR2_BASE_BASE_IDX 1 +#define mmCB_COLOR2_BASE_EXT 0x0337 +#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR2_ATTRIB2 0x0338 +#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR2_VIEW 0x0339 +#define mmCB_COLOR2_VIEW_BASE_IDX 1 +#define mmCB_COLOR2_INFO 0x033a +#define mmCB_COLOR2_INFO_BASE_IDX 1 +#define mmCB_COLOR2_ATTRIB 0x033b +#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR2_DCC_CONTROL 0x033c +#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR2_CMASK 0x033d +#define mmCB_COLOR2_CMASK_BASE_IDX 1 +#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e +#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR2_FMASK 0x033f +#define mmCB_COLOR2_FMASK_BASE_IDX 1 +#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340 +#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR2_CLEAR_WORD0 0x0341 +#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR2_CLEAR_WORD1 0x0342 +#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR2_DCC_BASE 0x0343 +#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR2_DCC_BASE_EXT 0x0344 +#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR3_BASE 0x0345 +#define mmCB_COLOR3_BASE_BASE_IDX 1 +#define mmCB_COLOR3_BASE_EXT 0x0346 +#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR3_ATTRIB2 0x0347 +#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR3_VIEW 0x0348 +#define mmCB_COLOR3_VIEW_BASE_IDX 1 +#define mmCB_COLOR3_INFO 0x0349 +#define mmCB_COLOR3_INFO_BASE_IDX 1 +#define mmCB_COLOR3_ATTRIB 0x034a +#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR3_DCC_CONTROL 0x034b +#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR3_CMASK 0x034c +#define mmCB_COLOR3_CMASK_BASE_IDX 1 +#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d +#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR3_FMASK 0x034e +#define mmCB_COLOR3_FMASK_BASE_IDX 1 +#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f +#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR3_CLEAR_WORD0 0x0350 +#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR3_CLEAR_WORD1 0x0351 +#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR3_DCC_BASE 0x0352 +#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR3_DCC_BASE_EXT 0x0353 +#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR4_BASE 0x0354 +#define mmCB_COLOR4_BASE_BASE_IDX 1 +#define mmCB_COLOR4_BASE_EXT 0x0355 +#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR4_ATTRIB2 0x0356 +#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR4_VIEW 0x0357 +#define mmCB_COLOR4_VIEW_BASE_IDX 1 +#define mmCB_COLOR4_INFO 0x0358 +#define mmCB_COLOR4_INFO_BASE_IDX 1 +#define mmCB_COLOR4_ATTRIB 0x0359 +#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR4_DCC_CONTROL 0x035a +#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR4_CMASK 0x035b +#define mmCB_COLOR4_CMASK_BASE_IDX 1 +#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c +#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR4_FMASK 0x035d +#define mmCB_COLOR4_FMASK_BASE_IDX 1 +#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e +#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR4_CLEAR_WORD0 0x035f +#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR4_CLEAR_WORD1 0x0360 +#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR4_DCC_BASE 0x0361 +#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR4_DCC_BASE_EXT 0x0362 +#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR5_BASE 0x0363 +#define mmCB_COLOR5_BASE_BASE_IDX 1 +#define mmCB_COLOR5_BASE_EXT 0x0364 +#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR5_ATTRIB2 0x0365 +#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR5_VIEW 0x0366 +#define mmCB_COLOR5_VIEW_BASE_IDX 1 +#define mmCB_COLOR5_INFO 0x0367 +#define mmCB_COLOR5_INFO_BASE_IDX 1 +#define mmCB_COLOR5_ATTRIB 0x0368 +#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR5_DCC_CONTROL 0x0369 +#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR5_CMASK 0x036a +#define mmCB_COLOR5_CMASK_BASE_IDX 1 +#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b +#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR5_FMASK 0x036c +#define mmCB_COLOR5_FMASK_BASE_IDX 1 +#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d +#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR5_CLEAR_WORD0 0x036e +#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR5_CLEAR_WORD1 0x036f +#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR5_DCC_BASE 0x0370 +#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR5_DCC_BASE_EXT 0x0371 +#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR6_BASE 0x0372 +#define mmCB_COLOR6_BASE_BASE_IDX 1 +#define mmCB_COLOR6_BASE_EXT 0x0373 +#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR6_ATTRIB2 0x0374 +#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR6_VIEW 0x0375 +#define mmCB_COLOR6_VIEW_BASE_IDX 1 +#define mmCB_COLOR6_INFO 0x0376 +#define mmCB_COLOR6_INFO_BASE_IDX 1 +#define mmCB_COLOR6_ATTRIB 0x0377 +#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR6_DCC_CONTROL 0x0378 +#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR6_CMASK 0x0379 +#define mmCB_COLOR6_CMASK_BASE_IDX 1 +#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a +#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR6_FMASK 0x037b +#define mmCB_COLOR6_FMASK_BASE_IDX 1 +#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c +#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR6_CLEAR_WORD0 0x037d +#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR6_CLEAR_WORD1 0x037e +#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR6_DCC_BASE 0x037f +#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR6_DCC_BASE_EXT 0x0380 +#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR7_BASE 0x0381 +#define mmCB_COLOR7_BASE_BASE_IDX 1 +#define mmCB_COLOR7_BASE_EXT 0x0382 +#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR7_ATTRIB2 0x0383 +#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define mmCB_COLOR7_VIEW 0x0384 +#define mmCB_COLOR7_VIEW_BASE_IDX 1 +#define mmCB_COLOR7_INFO 0x0385 +#define mmCB_COLOR7_INFO_BASE_IDX 1 +#define mmCB_COLOR7_ATTRIB 0x0386 +#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 +#define mmCB_COLOR7_DCC_CONTROL 0x0387 +#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 +#define mmCB_COLOR7_CMASK 0x0388 +#define mmCB_COLOR7_CMASK_BASE_IDX 1 +#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389 +#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR7_FMASK 0x038a +#define mmCB_COLOR7_FMASK_BASE_IDX 1 +#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b +#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 +#define mmCB_COLOR7_CLEAR_WORD0 0x038c +#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 +#define mmCB_COLOR7_CLEAR_WORD1 0x038d +#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 +#define mmCB_COLOR7_DCC_BASE 0x038e +#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 +#define mmCB_COLOR7_DCC_BASE_EXT 0x038f +#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 + + +// addressBlock: gc_gfxudec +// base address: 0x30000 +#define mmCP_EOP_DONE_ADDR_LO 0x2000 +#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define mmCP_EOP_DONE_ADDR_HI 0x2001 +#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define mmCP_EOP_DONE_DATA_LO 0x2002 +#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define mmCP_EOP_DONE_DATA_HI 0x2003 +#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define mmCP_EOP_LAST_FENCE_LO 0x2004 +#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define mmCP_EOP_LAST_FENCE_HI 0x2005 +#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define mmCP_STREAM_OUT_ADDR_LO 0x2006 +#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 +#define mmCP_STREAM_OUT_ADDR_HI 0x2007 +#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 +#define mmCP_PIPE_STATS_ADDR_LO 0x2018 +#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define mmCP_PIPE_STATS_ADDR_HI 0x2019 +#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define mmCP_VGT_IAVERT_COUNT_LO 0x201a +#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_IAVERT_COUNT_HI 0x201b +#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c +#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d +#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e +#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f +#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_PA_CINVOC_COUNT_LO 0x2028 +#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_PA_CINVOC_COUNT_HI 0x2029 +#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_PA_CPRIM_COUNT_LO 0x202a +#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define mmCP_PA_CPRIM_COUNT_HI 0x202b +#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c +#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d +#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e +#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f +#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define mmCP_PIPE_STATS_CONTROL 0x203d +#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define mmCP_STREAM_OUT_CONTROL 0x203e +#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 +#define mmCP_STRMOUT_CNTL 0x203f +#define mmCP_STRMOUT_CNTL_BASE_IDX 1 +#define mmSCRATCH_REG0 0x2040 +#define mmSCRATCH_REG0_BASE_IDX 1 +#define mmSCRATCH_REG1 0x2041 +#define mmSCRATCH_REG1_BASE_IDX 1 +#define mmSCRATCH_REG2 0x2042 +#define mmSCRATCH_REG2_BASE_IDX 1 +#define mmSCRATCH_REG3 0x2043 +#define mmSCRATCH_REG3_BASE_IDX 1 +#define mmSCRATCH_REG4 0x2044 +#define mmSCRATCH_REG4_BASE_IDX 1 +#define mmSCRATCH_REG5 0x2045 +#define mmSCRATCH_REG5_BASE_IDX 1 +#define mmSCRATCH_REG6 0x2046 +#define mmSCRATCH_REG6_BASE_IDX 1 +#define mmSCRATCH_REG7 0x2047 +#define mmSCRATCH_REG7_BASE_IDX 1 +#define mmCP_APPEND_DATA_HI 0x204c +#define mmCP_APPEND_DATA_HI_BASE_IDX 1 +#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define mmSCRATCH_UMSK 0x2050 +#define mmSCRATCH_UMSK_BASE_IDX 1 +#define mmSCRATCH_ADDR 0x2051 +#define mmSCRATCH_ADDR_BASE_IDX 1 +#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define mmCP_APPEND_ADDR_LO 0x2058 +#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 +#define mmCP_APPEND_ADDR_HI 0x2059 +#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 +#define mmCP_APPEND_DATA_LO 0x205a +#define mmCP_APPEND_DATA_LO_BASE_IDX 1 +#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define mmCP_ATOMIC_PREOP_LO 0x205d +#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmCP_ME_ATOMIC_PREOP_LO 0x205d +#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmCP_ATOMIC_PREOP_HI 0x205e +#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmCP_ME_ATOMIC_PREOP_HI 0x205e +#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f +#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 +#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 +#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 +#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define mmCP_ME_MC_WADDR_LO 0x2069 +#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define mmCP_ME_MC_WADDR_HI 0x206a +#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define mmCP_ME_MC_WDATA_LO 0x206b +#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define mmCP_ME_MC_WDATA_HI 0x206c +#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define mmCP_ME_MC_RADDR_LO 0x206d +#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define mmCP_ME_MC_RADDR_HI 0x206e +#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define mmCP_SEM_WAIT_TIMER 0x206f +#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 +#define mmCP_SIG_SEM_ADDR_LO 0x2070 +#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 +#define mmCP_SIG_SEM_ADDR_HI 0x2071 +#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 +#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define mmCP_WAIT_SEM_ADDR_LO 0x2075 +#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 +#define mmCP_WAIT_SEM_ADDR_HI 0x2076 +#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 +#define mmCP_DMA_PFP_CONTROL 0x2077 +#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define mmCP_DMA_ME_CONTROL 0x2078 +#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 +#define mmCP_COHER_BASE_HI 0x2079 +#define mmCP_COHER_BASE_HI_BASE_IDX 1 +#define mmCP_COHER_START_DELAY 0x207b +#define mmCP_COHER_START_DELAY_BASE_IDX 1 +#define mmCP_COHER_CNTL 0x207c +#define mmCP_COHER_CNTL_BASE_IDX 1 +#define mmCP_COHER_SIZE 0x207d +#define mmCP_COHER_SIZE_BASE_IDX 1 +#define mmCP_COHER_BASE 0x207e +#define mmCP_COHER_BASE_BASE_IDX 1 +#define mmCP_COHER_STATUS 0x207f +#define mmCP_COHER_STATUS_BASE_IDX 1 +#define mmCP_DMA_ME_SRC_ADDR 0x2080 +#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define mmCP_DMA_ME_DST_ADDR 0x2082 +#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 +#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define mmCP_DMA_ME_COMMAND 0x2084 +#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 +#define mmCP_DMA_PFP_SRC_ADDR 0x2085 +#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define mmCP_DMA_PFP_DST_ADDR 0x2087 +#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define mmCP_DMA_PFP_COMMAND 0x2089 +#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define mmCP_DMA_CNTL 0x208a +#define mmCP_DMA_CNTL_BASE_IDX 1 +#define mmCP_DMA_READ_TAGS 0x208b +#define mmCP_DMA_READ_TAGS_BASE_IDX 1 +#define mmCP_COHER_SIZE_HI 0x208c +#define mmCP_COHER_SIZE_HI_BASE_IDX 1 +#define mmCP_PFP_IB_CONTROL 0x208d +#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 +#define mmCP_PFP_LOAD_CONTROL 0x208e +#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define mmCP_SCRATCH_INDEX 0x208f +#define mmCP_SCRATCH_INDEX_BASE_IDX 1 +#define mmCP_SCRATCH_DATA 0x2090 +#define mmCP_SCRATCH_DATA_BASE_IDX 1 +#define mmCP_RB_OFFSET 0x2091 +#define mmCP_RB_OFFSET_BASE_IDX 1 +#define mmCP_IB1_OFFSET 0x2092 +#define mmCP_IB1_OFFSET_BASE_IDX 1 +#define mmCP_IB2_OFFSET 0x2093 +#define mmCP_IB2_OFFSET_BASE_IDX 1 +#define mmCP_IB1_PREAMBLE_BEGIN 0x2094 +#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 +#define mmCP_IB1_PREAMBLE_END 0x2095 +#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1 +#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 +#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define mmCP_IB2_PREAMBLE_END 0x2097 +#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define mmCP_CE_IB1_OFFSET 0x2098 +#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 +#define mmCP_CE_IB2_OFFSET 0x2099 +#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 +#define mmCP_CE_COUNTER 0x209a +#define mmCP_CE_COUNTER_BASE_IDX 1 +#define mmCP_CE_RB_OFFSET 0x209b +#define mmCP_CE_RB_OFFSET_BASE_IDX 1 +#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd +#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_CE_IB1_CMD_BUFSZ 0x20be +#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf +#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_IB1_CMD_BUFSZ 0x20c0 +#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_IB2_CMD_BUFSZ 0x20c1 +#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_ST_CMD_BUFSZ 0x20c2 +#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_CE_INIT_BASE_LO 0x20c3 +#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 +#define mmCP_CE_INIT_BASE_HI 0x20c4 +#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 +#define mmCP_CE_INIT_BUFSZ 0x20c5 +#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 +#define mmCP_CE_IB1_BASE_LO 0x20c6 +#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 +#define mmCP_CE_IB1_BASE_HI 0x20c7 +#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 +#define mmCP_CE_IB1_BUFSZ 0x20c8 +#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 +#define mmCP_CE_IB2_BASE_LO 0x20c9 +#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 +#define mmCP_CE_IB2_BASE_HI 0x20ca +#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 +#define mmCP_CE_IB2_BUFSZ 0x20cb +#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 +#define mmCP_IB1_BASE_LO 0x20cc +#define mmCP_IB1_BASE_LO_BASE_IDX 1 +#define mmCP_IB1_BASE_HI 0x20cd +#define mmCP_IB1_BASE_HI_BASE_IDX 1 +#define mmCP_IB1_BUFSZ 0x20ce +#define mmCP_IB1_BUFSZ_BASE_IDX 1 +#define mmCP_IB2_BASE_LO 0x20cf +#define mmCP_IB2_BASE_LO_BASE_IDX 1 +#define mmCP_IB2_BASE_HI 0x20d0 +#define mmCP_IB2_BASE_HI_BASE_IDX 1 +#define mmCP_IB2_BUFSZ 0x20d1 +#define mmCP_IB2_BUFSZ_BASE_IDX 1 +#define mmCP_ST_BASE_LO 0x20d2 +#define mmCP_ST_BASE_LO_BASE_IDX 1 +#define mmCP_ST_BASE_HI 0x20d3 +#define mmCP_ST_BASE_HI_BASE_IDX 1 +#define mmCP_ST_BUFSZ 0x20d4 +#define mmCP_ST_BUFSZ_BASE_IDX 1 +#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 +#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define mmCP_EOP_DONE_CNTX_ID 0x20d7 +#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define mmCP_PFP_COMPLETION_STATUS 0x20ec +#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define mmCP_CE_COMPLETION_STATUS 0x20ed +#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 +#define mmCP_PRED_NOT_VISIBLE 0x20ee +#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 +#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 +#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 +#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define mmCP_DISPATCH_INDR_ADDR 0x20f6 +#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define mmCP_INDEX_BASE_ADDR 0x20f8 +#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 +#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define mmCP_INDEX_TYPE 0x20fa +#define mmCP_INDEX_TYPE_BASE_IDX 1 +#define mmCP_GDS_BKUP_ADDR 0x20fb +#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 +#define mmCP_GDS_BKUP_ADDR_HI 0x20fc +#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 +#define mmCP_SAMPLE_STATUS 0x20fd +#define mmCP_SAMPLE_STATUS_BASE_IDX 1 +#define mmCP_ME_COHER_CNTL 0x20fe +#define mmCP_ME_COHER_CNTL_BASE_IDX 1 +#define mmCP_ME_COHER_SIZE 0x20ff +#define mmCP_ME_COHER_SIZE_BASE_IDX 1 +#define mmCP_ME_COHER_SIZE_HI 0x2100 +#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define mmCP_ME_COHER_BASE 0x2101 +#define mmCP_ME_COHER_BASE_BASE_IDX 1 +#define mmCP_ME_COHER_BASE_HI 0x2102 +#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define mmCP_ME_COHER_STATUS 0x2103 +#define mmCP_ME_COHER_STATUS_BASE_IDX 1 +#define mmRLC_GPM_PERF_COUNT_0 0x2140 +#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define mmRLC_GPM_PERF_COUNT_1 0x2141 +#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define mmGRBM_GFX_INDEX 0x2200 +#define mmGRBM_GFX_INDEX_BASE_IDX 1 +#define mmVGT_GSVS_RING_SIZE 0x2241 +#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1 +#define mmVGT_PRIMITIVE_TYPE 0x2242 +#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define mmVGT_INDEX_TYPE 0x2243 +#define mmVGT_INDEX_TYPE_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 +#define mmVGT_MAX_VTX_INDX 0x2248 +#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 +#define mmVGT_MIN_VTX_INDX 0x2249 +#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 +#define mmVGT_INDX_OFFSET 0x224a +#define mmVGT_INDX_OFFSET_BASE_IDX 1 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b +#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define mmVGT_NUM_INDICES 0x224c +#define mmVGT_NUM_INDICES_BASE_IDX 1 +#define mmVGT_NUM_INSTANCES 0x224d +#define mmVGT_NUM_INSTANCES_BASE_IDX 1 +#define mmVGT_TF_RING_SIZE 0x224e +#define mmVGT_TF_RING_SIZE_BASE_IDX 1 +#define mmVGT_HS_OFFCHIP_PARAM 0x224f +#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define mmVGT_TF_MEMORY_BASE 0x2250 +#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define mmVGT_TF_MEMORY_BASE_HI 0x2251 +#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define mmWD_POS_BUF_BASE 0x2252 +#define mmWD_POS_BUF_BASE_BASE_IDX 1 +#define mmWD_POS_BUF_BASE_HI 0x2253 +#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 +#define mmWD_CNTL_SB_BUF_BASE 0x2254 +#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 +#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 +#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 +#define mmWD_INDEX_BUF_BASE 0x2256 +#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 +#define mmWD_INDEX_BUF_BASE_HI 0x2257 +#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 +#define mmIA_MULTI_VGT_PARAM 0x2258 +#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 +#define mmVGT_OBJECT_ID 0x2259 +#define mmVGT_OBJECT_ID_BASE_IDX 1 +#define mmVGT_INSTANCE_BASE_ID 0x225a +#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 +#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define mmPA_SC_TRAP_SCREEN_H 0x22b1 +#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define mmPA_SC_TRAP_SCREEN_V 0x22b2 +#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_BASE 0x2330 +#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_SIZE 0x2331 +#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_MASK 0x2332 +#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333 +#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334 +#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_CTRL 0x2335 +#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_MODE 0x2336 +#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_BASE2 0x2337 +#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_WPTR 0x2339 +#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_STATUS 0x233a +#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_HIWATER 0x233b +#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_CNTR 0x233c +#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define mmSQC_CACHES 0x2348 +#define mmSQC_CACHES_BASE_IDX 1 +#define mmSQC_WRITEBACK 0x2349 +#define mmSQC_WRITEBACK_BASE_IDX 1 +#define mmTA_CS_BC_BASE_ADDR 0x2380 +#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 +#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 +#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 +#define mmTA_GRAD_ADJ_UCONFIG 0x2382 +#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 +#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 +#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 +#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 +#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define mmDB_ZPASS_COUNT_LOW 0x23fe +#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 +#define mmDB_ZPASS_COUNT_HI 0x23ff +#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 +#define mmGDS_RD_ADDR 0x2400 +#define mmGDS_RD_ADDR_BASE_IDX 1 +#define mmGDS_RD_DATA 0x2401 +#define mmGDS_RD_DATA_BASE_IDX 1 +#define mmGDS_RD_BURST_ADDR 0x2402 +#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 +#define mmGDS_RD_BURST_COUNT 0x2403 +#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 +#define mmGDS_RD_BURST_DATA 0x2404 +#define mmGDS_RD_BURST_DATA_BASE_IDX 1 +#define mmGDS_WR_ADDR 0x2405 +#define mmGDS_WR_ADDR_BASE_IDX 1 +#define mmGDS_WR_DATA 0x2406 +#define mmGDS_WR_DATA_BASE_IDX 1 +#define mmGDS_WR_BURST_ADDR 0x2407 +#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 +#define mmGDS_WR_BURST_DATA 0x2408 +#define mmGDS_WR_BURST_DATA_BASE_IDX 1 +#define mmGDS_WRITE_COMPLETE 0x2409 +#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 +#define mmGDS_ATOM_CNTL 0x240a +#define mmGDS_ATOM_CNTL_BASE_IDX 1 +#define mmGDS_ATOM_COMPLETE 0x240b +#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 +#define mmGDS_ATOM_BASE 0x240c +#define mmGDS_ATOM_BASE_BASE_IDX 1 +#define mmGDS_ATOM_SIZE 0x240d +#define mmGDS_ATOM_SIZE_BASE_IDX 1 +#define mmGDS_ATOM_OFFSET0 0x240e +#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 +#define mmGDS_ATOM_OFFSET1 0x240f +#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 +#define mmGDS_ATOM_DST 0x2410 +#define mmGDS_ATOM_DST_BASE_IDX 1 +#define mmGDS_ATOM_OP 0x2411 +#define mmGDS_ATOM_OP_BASE_IDX 1 +#define mmGDS_ATOM_SRC0 0x2412 +#define mmGDS_ATOM_SRC0_BASE_IDX 1 +#define mmGDS_ATOM_SRC0_U 0x2413 +#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 +#define mmGDS_ATOM_SRC1 0x2414 +#define mmGDS_ATOM_SRC1_BASE_IDX 1 +#define mmGDS_ATOM_SRC1_U 0x2415 +#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 +#define mmGDS_ATOM_READ0 0x2416 +#define mmGDS_ATOM_READ0_BASE_IDX 1 +#define mmGDS_ATOM_READ0_U 0x2417 +#define mmGDS_ATOM_READ0_U_BASE_IDX 1 +#define mmGDS_ATOM_READ1 0x2418 +#define mmGDS_ATOM_READ1_BASE_IDX 1 +#define mmGDS_ATOM_READ1_U 0x2419 +#define mmGDS_ATOM_READ1_U_BASE_IDX 1 +#define mmGDS_GWS_RESOURCE_CNTL 0x241a +#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 +#define mmGDS_GWS_RESOURCE 0x241b +#define mmGDS_GWS_RESOURCE_BASE_IDX 1 +#define mmGDS_GWS_RESOURCE_CNT 0x241c +#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 +#define mmGDS_OA_CNTL 0x241d +#define mmGDS_OA_CNTL_BASE_IDX 1 +#define mmGDS_OA_COUNTER 0x241e +#define mmGDS_OA_COUNTER_BASE_IDX 1 +#define mmGDS_OA_ADDRESS 0x241f +#define mmGDS_OA_ADDRESS_BASE_IDX 1 +#define mmGDS_OA_INCDEC 0x2420 +#define mmGDS_OA_INCDEC_BASE_IDX 1 +#define mmGDS_OA_RING_SIZE 0x2421 +#define mmGDS_OA_RING_SIZE_BASE_IDX 1 +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_CONFIG_CNTL_BASE_IDX 1 +#define mmSPI_CONFIG_CNTL_1 0x2441 +#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define mmSPI_CONFIG_CNTL_2 0x2442 +#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1 + + +// addressBlock: gc_perfddec +// base address: 0x34000 +#define mmCPG_PERFCOUNTER1_LO 0x3000 +#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmCPG_PERFCOUNTER1_HI 0x3001 +#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmCPG_PERFCOUNTER0_LO 0x3002 +#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmCPG_PERFCOUNTER0_HI 0x3003 +#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmCPC_PERFCOUNTER1_LO 0x3004 +#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmCPC_PERFCOUNTER1_HI 0x3005 +#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmCPC_PERFCOUNTER0_LO 0x3006 +#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmCPC_PERFCOUNTER0_HI 0x3007 +#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmCPF_PERFCOUNTER1_LO 0x3008 +#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmCPF_PERFCOUNTER1_HI 0x3009 +#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmCPF_PERFCOUNTER0_LO 0x300a +#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmCPF_PERFCOUNTER0_HI 0x300b +#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmCPF_LATENCY_STATS_DATA 0x300c +#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define mmCPG_LATENCY_STATS_DATA 0x300d +#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define mmCPC_LATENCY_STATS_DATA 0x300e +#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER0_LO 0x3040 +#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER0_HI 0x3041 +#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER1_LO 0x3043 +#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER1_HI 0x3044 +#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 +#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 +#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 +#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 +#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 +#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 +#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 +#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 +#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 +#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a +#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 +#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b +#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 +#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c +#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 +#define mmWD_PERFCOUNTER0_LO 0x3080 +#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmWD_PERFCOUNTER0_HI 0x3081 +#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmWD_PERFCOUNTER1_LO 0x3082 +#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmWD_PERFCOUNTER1_HI 0x3083 +#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmWD_PERFCOUNTER2_LO 0x3084 +#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmWD_PERFCOUNTER2_HI 0x3085 +#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmWD_PERFCOUNTER3_LO 0x3086 +#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmWD_PERFCOUNTER3_HI 0x3087 +#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmIA_PERFCOUNTER0_LO 0x3088 +#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmIA_PERFCOUNTER0_HI 0x3089 +#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmIA_PERFCOUNTER1_LO 0x308a +#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmIA_PERFCOUNTER1_HI 0x308b +#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmIA_PERFCOUNTER2_LO 0x308c +#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmIA_PERFCOUNTER2_HI 0x308d +#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmIA_PERFCOUNTER3_LO 0x308e +#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmIA_PERFCOUNTER3_HI 0x308f +#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmVGT_PERFCOUNTER0_LO 0x3090 +#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmVGT_PERFCOUNTER0_HI 0x3091 +#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmVGT_PERFCOUNTER1_LO 0x3092 +#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmVGT_PERFCOUNTER1_HI 0x3093 +#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmVGT_PERFCOUNTER2_LO 0x3094 +#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmVGT_PERFCOUNTER2_HI 0x3095 +#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmVGT_PERFCOUNTER3_LO 0x3096 +#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmVGT_PERFCOUNTER3_HI 0x3097 +#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER0_LO 0x3100 +#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER0_HI 0x3101 +#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER1_LO 0x3102 +#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER1_HI 0x3103 +#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER2_LO 0x3104 +#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER2_HI 0x3105 +#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER3_LO 0x3106 +#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER3_HI 0x3107 +#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER0_LO 0x3140 +#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER0_HI 0x3141 +#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER1_LO 0x3142 +#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER1_HI 0x3143 +#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER2_LO 0x3144 +#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER2_HI 0x3145 +#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER3_LO 0x3146 +#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER3_HI 0x3147 +#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER4_LO 0x3148 +#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER4_HI 0x3149 +#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER5_LO 0x314a +#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER5_HI 0x314b +#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER6_LO 0x314c +#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER6_HI 0x314d +#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER7_LO 0x314e +#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER7_HI 0x314f +#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER0_HI 0x3180 +#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER0_LO 0x3181 +#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmSPI_PERFCOUNTER1_HI 0x3182 +#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER1_LO 0x3183 +#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmSPI_PERFCOUNTER2_HI 0x3184 +#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER2_LO 0x3185 +#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmSPI_PERFCOUNTER3_HI 0x3186 +#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER3_LO 0x3187 +#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmSPI_PERFCOUNTER4_HI 0x3188 +#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER4_LO 0x3189 +#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define mmSPI_PERFCOUNTER5_HI 0x318a +#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define mmSPI_PERFCOUNTER5_LO 0x318b +#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER0_LO 0x31c0 +#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER0_HI 0x31c1 +#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER1_LO 0x31c2 +#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER1_HI 0x31c3 +#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER2_LO 0x31c4 +#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER2_HI 0x31c5 +#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER3_LO 0x31c6 +#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER3_HI 0x31c7 +#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER4_LO 0x31c8 +#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER4_HI 0x31c9 +#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER5_LO 0x31ca +#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER5_HI 0x31cb +#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER6_LO 0x31cc +#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER6_HI 0x31cd +#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER7_LO 0x31ce +#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER7_HI 0x31cf +#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER8_LO 0x31d0 +#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER8_HI 0x31d1 +#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER9_LO 0x31d2 +#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER9_HI 0x31d3 +#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER10_LO 0x31d4 +#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER10_HI 0x31d5 +#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER11_LO 0x31d6 +#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER11_HI 0x31d7 +#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER12_LO 0x31d8 +#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER12_HI 0x31d9 +#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER13_LO 0x31da +#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER13_HI 0x31db +#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER14_LO 0x31dc +#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER14_HI 0x31dd +#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 +#define mmSQ_PERFCOUNTER15_LO 0x31de +#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 +#define mmSQ_PERFCOUNTER15_HI 0x31df +#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 +#define mmSX_PERFCOUNTER0_LO 0x3240 +#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmSX_PERFCOUNTER0_HI 0x3241 +#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmSX_PERFCOUNTER1_LO 0x3242 +#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmSX_PERFCOUNTER1_HI 0x3243 +#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmSX_PERFCOUNTER2_LO 0x3244 +#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmSX_PERFCOUNTER2_HI 0x3245 +#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmSX_PERFCOUNTER3_LO 0x3246 +#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmSX_PERFCOUNTER3_HI 0x3247 +#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmGDS_PERFCOUNTER0_LO 0x3280 +#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmGDS_PERFCOUNTER0_HI 0x3281 +#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmGDS_PERFCOUNTER1_LO 0x3282 +#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmGDS_PERFCOUNTER1_HI 0x3283 +#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmGDS_PERFCOUNTER2_LO 0x3284 +#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmGDS_PERFCOUNTER2_HI 0x3285 +#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmGDS_PERFCOUNTER3_LO 0x3286 +#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmGDS_PERFCOUNTER3_HI 0x3287 +#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmTA_PERFCOUNTER0_LO 0x32c0 +#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmTA_PERFCOUNTER0_HI 0x32c1 +#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmTA_PERFCOUNTER1_LO 0x32c2 +#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmTA_PERFCOUNTER1_HI 0x32c3 +#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmTD_PERFCOUNTER0_LO 0x3300 +#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmTD_PERFCOUNTER0_HI 0x3301 +#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmTD_PERFCOUNTER1_LO 0x3302 +#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmTD_PERFCOUNTER1_HI 0x3303 +#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmTCP_PERFCOUNTER0_LO 0x3340 +#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmTCP_PERFCOUNTER0_HI 0x3341 +#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmTCP_PERFCOUNTER1_LO 0x3342 +#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmTCP_PERFCOUNTER1_HI 0x3343 +#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmTCP_PERFCOUNTER2_LO 0x3344 +#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmTCP_PERFCOUNTER2_HI 0x3345 +#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmTCP_PERFCOUNTER3_LO 0x3346 +#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmTCP_PERFCOUNTER3_HI 0x3347 +#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmTCC_PERFCOUNTER0_LO 0x3380 +#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmTCC_PERFCOUNTER0_HI 0x3381 +#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmTCC_PERFCOUNTER1_LO 0x3382 +#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmTCC_PERFCOUNTER1_HI 0x3383 +#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmTCC_PERFCOUNTER2_LO 0x3384 +#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmTCC_PERFCOUNTER2_HI 0x3385 +#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmTCC_PERFCOUNTER3_LO 0x3386 +#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmTCC_PERFCOUNTER3_HI 0x3387 +#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmTCA_PERFCOUNTER0_LO 0x3390 +#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmTCA_PERFCOUNTER0_HI 0x3391 +#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmTCA_PERFCOUNTER1_LO 0x3392 +#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmTCA_PERFCOUNTER1_HI 0x3393 +#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmTCA_PERFCOUNTER2_LO 0x3394 +#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmTCA_PERFCOUNTER2_HI 0x3395 +#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmTCA_PERFCOUNTER3_LO 0x3396 +#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmTCA_PERFCOUNTER3_HI 0x3397 +#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmCB_PERFCOUNTER0_LO 0x3406 +#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmCB_PERFCOUNTER0_HI 0x3407 +#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmCB_PERFCOUNTER1_LO 0x3408 +#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmCB_PERFCOUNTER1_HI 0x3409 +#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmCB_PERFCOUNTER2_LO 0x340a +#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmCB_PERFCOUNTER2_HI 0x340b +#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmCB_PERFCOUNTER3_LO 0x340c +#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmCB_PERFCOUNTER3_HI 0x340d +#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmDB_PERFCOUNTER0_LO 0x3440 +#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmDB_PERFCOUNTER0_HI 0x3441 +#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmDB_PERFCOUNTER1_LO 0x3442 +#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmDB_PERFCOUNTER1_HI 0x3443 +#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmDB_PERFCOUNTER2_LO 0x3444 +#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmDB_PERFCOUNTER2_HI 0x3445 +#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmDB_PERFCOUNTER3_LO 0x3446 +#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmDB_PERFCOUNTER3_HI 0x3447 +#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define mmRLC_PERFCOUNTER0_LO 0x3480 +#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmRLC_PERFCOUNTER0_HI 0x3481 +#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmRLC_PERFCOUNTER1_LO 0x3482 +#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmRLC_PERFCOUNTER1_HI 0x3483 +#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmRMI_PERFCOUNTER0_LO 0x34c0 +#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define mmRMI_PERFCOUNTER0_HI 0x34c1 +#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define mmRMI_PERFCOUNTER1_LO 0x34c2 +#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define mmRMI_PERFCOUNTER1_HI 0x34c3 +#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define mmRMI_PERFCOUNTER2_LO 0x34c4 +#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define mmRMI_PERFCOUNTER2_HI 0x34c5 +#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define mmRMI_PERFCOUNTER3_LO 0x34c6 +#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define mmRMI_PERFCOUNTER3_HI 0x34c7 +#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: gc_utcl2_atcl2pfcntrdec +// base address: 0x35400 +#define mmATC_L2_PERFCOUNTER_LO 0x3500 +#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmATC_L2_PERFCOUNTER_HI 0x3501 +#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vml2prdec +// base address: 0x35420 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508 +#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509 +#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: gc_perfsdec +// base address: 0x36000 +#define mmCPG_PERFCOUNTER1_SELECT 0x3800 +#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 +#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmCPG_PERFCOUNTER0_SELECT 0x3802 +#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmCPC_PERFCOUNTER1_SELECT 0x3803 +#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 +#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmCPF_PERFCOUNTER1_SELECT 0x3805 +#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 +#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmCPF_PERFCOUNTER0_SELECT 0x3807 +#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmCP_PERFMON_CNTL 0x3808 +#define mmCP_PERFMON_CNTL_BASE_IDX 1 +#define mmCPC_PERFCOUNTER0_SELECT 0x3809 +#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define mmCPF_LATENCY_STATS_SELECT 0x380c +#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define mmCPG_LATENCY_STATS_SELECT 0x380d +#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define mmCPC_LATENCY_STATS_SELECT 0x380e +#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define mmCP_DRAW_OBJECT 0x3810 +#define mmCP_DRAW_OBJECT_BASE_IDX 1 +#define mmCP_DRAW_OBJECT_COUNTER 0x3811 +#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 +#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define mmCP_DRAW_WINDOW_HI 0x3813 +#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define mmCP_DRAW_WINDOW_LO 0x3814 +#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define mmCP_DRAW_WINDOW_CNTL 0x3815 +#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 +#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 +#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 +#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 +#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 +#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 +#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 +#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 +#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 +#define mmWD_PERFCOUNTER0_SELECT 0x3880 +#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmWD_PERFCOUNTER1_SELECT 0x3881 +#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmWD_PERFCOUNTER2_SELECT 0x3882 +#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmWD_PERFCOUNTER3_SELECT 0x3883 +#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmIA_PERFCOUNTER0_SELECT 0x3884 +#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmIA_PERFCOUNTER1_SELECT 0x3885 +#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmIA_PERFCOUNTER2_SELECT 0x3886 +#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmIA_PERFCOUNTER3_SELECT 0x3887 +#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmIA_PERFCOUNTER0_SELECT1 0x3888 +#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmVGT_PERFCOUNTER0_SELECT 0x388c +#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmVGT_PERFCOUNTER1_SELECT 0x388d +#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmVGT_PERFCOUNTER2_SELECT 0x388e +#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmVGT_PERFCOUNTER3_SELECT 0x388f +#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmVGT_PERFCOUNTER0_SELECT1 0x3890 +#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmVGT_PERFCOUNTER1_SELECT1 0x3891 +#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894 +#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905 +#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER0_SELECT 0x3980 +#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER1_SELECT 0x3981 +#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER2_SELECT 0x3982 +#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER3_SELECT 0x3983 +#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 +#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 +#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 +#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 +#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define mmSPI_PERFCOUNTER4_SELECT 0x3988 +#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER5_SELECT 0x3989 +#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define mmSPI_PERFCOUNTER_BINS 0x398a +#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 +#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 +#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 +#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 +#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 +#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 +#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 +#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 +#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 +#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 +#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER10_SELECT 0x39ca +#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER11_SELECT 0x39cb +#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER12_SELECT 0x39cc +#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER13_SELECT 0x39cd +#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER14_SELECT 0x39ce +#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER15_SELECT 0x39cf +#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define mmSQ_PERFCOUNTER_CTRL 0x39e0 +#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define mmSQ_PERFCOUNTER_MASK 0x39e1 +#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1 +#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 +#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define mmSX_PERFCOUNTER0_SELECT 0x3a40 +#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmSX_PERFCOUNTER1_SELECT 0x3a41 +#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmSX_PERFCOUNTER2_SELECT 0x3a42 +#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmSX_PERFCOUNTER3_SELECT 0x3a43 +#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 +#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 +#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 +#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 +#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 +#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 +#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 +#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 +#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 +#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmTD_PERFCOUNTER0_SELECT 0x3b00 +#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 +#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTD_PERFCOUNTER1_SELECT 0x3b02 +#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 +#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 +#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 +#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 +#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmTCC_PERFCOUNTER0_SELECT 0x3b80 +#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81 +#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTCC_PERFCOUNTER1_SELECT 0x3b82 +#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83 +#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmTCC_PERFCOUNTER2_SELECT 0x3b84 +#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmTCC_PERFCOUNTER3_SELECT 0x3b85 +#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmTCA_PERFCOUNTER0_SELECT 0x3b90 +#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91 +#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmTCA_PERFCOUNTER1_SELECT 0x3b92 +#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93 +#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmTCA_PERFCOUNTER2_SELECT 0x3b94 +#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmTCA_PERFCOUNTER3_SELECT 0x3b95 +#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmCB_PERFCOUNTER_FILTER 0x3c00 +#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define mmCB_PERFCOUNTER0_SELECT 0x3c01 +#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 +#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmCB_PERFCOUNTER1_SELECT 0x3c03 +#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmCB_PERFCOUNTER2_SELECT 0x3c04 +#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmCB_PERFCOUNTER3_SELECT 0x3c05 +#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmDB_PERFCOUNTER0_SELECT 0x3c40 +#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 +#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmDB_PERFCOUNTER1_SELECT 0x3c42 +#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 +#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define mmDB_PERFCOUNTER2_SELECT 0x3c44 +#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmDB_PERFCOUNTER3_SELECT 0x3c46 +#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmRLC_SPM_PERFMON_CNTL 0x3c80 +#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85 +#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86 +#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define mmRLC_SPM_RING_RDPTR 0x3c9d +#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e +#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 +#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define mmRLC_PERFMON_CLK_CNTL 0x3cbf +#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 +#define mmRLC_PERFMON_CNTL 0x3cc0 +#define mmRLC_PERFMON_CNTL_BASE_IDX 1 +#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 +#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 +#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 +#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 +#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define mmRMI_PERF_COUNTER_CNTL 0x3d06 +#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_atcl2pfcntldec +// base address: 0x37500 +#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40 +#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41 +#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vml2pldec +// base address: 0x37530 +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c +#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d +#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e +#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f +#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 +#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 +#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 +#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 +#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: gc_rlcpdec +// base address: 0x3b000 +#define mmRLC_CNTL 0x4c00 +#define mmRLC_CNTL_BASE_IDX 1 +#define mmRLC_STAT 0x4c04 +#define mmRLC_STAT_BASE_IDX 1 +#define mmRLC_SAFE_MODE 0x4c05 +#define mmRLC_SAFE_MODE_BASE_IDX 1 +#define mmRLC_MEM_SLP_CNTL 0x4c06 +#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define mmSMU_RLC_RESPONSE 0x4c07 +#define mmSMU_RLC_RESPONSE_BASE_IDX 1 +#define mmRLC_RLCV_SAFE_MODE 0x4c08 +#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define mmRLC_SMU_SAFE_MODE 0x4c09 +#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define mmRLC_RLCV_COMMAND 0x4c0a +#define mmRLC_RLCV_COMMAND_BASE_IDX 1 +#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define mmRLC_GPM_TIMER_INT_0 0x4c0e +#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define mmRLC_GPM_TIMER_INT_1 0x4c0f +#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define mmRLC_GPM_TIMER_INT_2 0x4c10 +#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define mmRLC_GPM_TIMER_CTRL 0x4c11 +#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define mmRLC_LB_CNTR_MAX 0x4c12 +#define mmRLC_LB_CNTR_MAX_BASE_IDX 1 +#define mmRLC_GPM_TIMER_STAT 0x4c13 +#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define mmRLC_GPM_TIMER_INT_3 0x4c15 +#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 +#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 +#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 +#define mmRLC_INT_STAT 0x4c18 +#define mmRLC_INT_STAT_BASE_IDX 1 +#define mmRLC_LB_CNTL 0x4c19 +#define mmRLC_LB_CNTL_BASE_IDX 1 +#define mmRLC_MGCG_CTRL 0x4c1a +#define mmRLC_MGCG_CTRL_BASE_IDX 1 +#define mmRLC_LB_CNTR_INIT 0x4c1b +#define mmRLC_LB_CNTR_INIT_BASE_IDX 1 +#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c +#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 +#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e +#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define mmRLC_PG_DELAY_2 0x4c1f +#define mmRLC_PG_DELAY_2_BASE_IDX 1 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define mmRLC_UCODE_CNTL 0x4c27 +#define mmRLC_UCODE_CNTL_BASE_IDX 1 +#define mmRLC_GPM_THREAD_RESET 0x4c28 +#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define mmRLC_FIREWALL_VIOLATION 0x4c2b +#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1 +#define mmRLC_GPM_STAT 0x4c40 +#define mmRLC_GPM_STAT_BASE_IDX 1 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define mmRLC_GPU_CLOCK_32 0x4c42 +#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 +#define mmRLC_PG_CNTL 0x4c43 +#define mmRLC_PG_CNTL_BASE_IDX 1 +#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 +#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define mmRLC_GPM_THREAD_ENABLE 0x4c45 +#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define mmRLC_CGCG_CGLS_CTRL 0x4c49 +#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define mmRLC_CGCG_RAMP_CTRL 0x4c4a +#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define mmRLC_DYN_PG_STATUS 0x4c4b +#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 +#define mmRLC_DYN_PG_REQUEST 0x4c4c +#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define mmRLC_PG_DELAY 0x4c4d +#define mmRLC_PG_DELAY_BASE_IDX 1 +#define mmRLC_CU_STATUS 0x4c4e +#define mmRLC_CU_STATUS_BASE_IDX 1 +#define mmRLC_LB_INIT_CU_MASK 0x4c4f +#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1 +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 +#define mmRLC_LB_PARAMS 0x4c51 +#define mmRLC_LB_PARAMS_BASE_IDX 1 +#define mmRLC_THREAD1_DELAY 0x4c52 +#define mmRLC_THREAD1_DELAY_BASE_IDX 1 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 +#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 +#define mmRLC_MAX_PG_CU 0x4c54 +#define mmRLC_MAX_PG_CU_BASE_IDX 1 +#define mmRLC_AUTO_PG_CTRL 0x4c55 +#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59 +#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 +#define mmRLC_SERDES_RD_DATA_0 0x4c5a +#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define mmRLC_SERDES_RD_DATA_1 0x4c5b +#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define mmRLC_SERDES_RD_DATA_2 0x4c5c +#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d +#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 +#define mmRLC_SERDES_WR_CTRL 0x4c5f +#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1 +#define mmRLC_SERDES_WR_DATA 0x4c60 +#define mmRLC_SERDES_WR_DATA_BASE_IDX 1 +#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61 +#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 +#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 +#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_0 0x4c63 +#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_1 0x4c64 +#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_2 0x4c65 +#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_3 0x4c66 +#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_4 0x4c67 +#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_5 0x4c68 +#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_6 0x4c69 +#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_7 0x4c6a +#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 +#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c +#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define mmRLC_GPM_SCRATCH_DATA 0x4c6d +#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define mmRLC_STATIC_PG_STATUS 0x4c6e +#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define mmRLC_SPM_MC_CNTL 0x4c71 +#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 +#define mmRLC_SPM_INT_CNTL 0x4c72 +#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 +#define mmRLC_SPM_INT_STATUS 0x4c73 +#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 +#define mmRLC_SMU_MESSAGE 0x4c76 +#define mmRLC_SMU_MESSAGE_BASE_IDX 1 +#define mmRLC_GPM_LOG_SIZE 0x4c77 +#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 +#define mmRLC_PG_DELAY_3 0x4c78 +#define mmRLC_PG_DELAY_3_BASE_IDX 1 +#define mmRLC_GPR_REG1 0x4c79 +#define mmRLC_GPR_REG1_BASE_IDX 1 +#define mmRLC_GPR_REG2 0x4c7a +#define mmRLC_GPR_REG2_BASE_IDX 1 +#define mmRLC_GPM_LOG_CONT 0x4c7b +#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 +#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define mmRLC_GPM_INT_DISABLE_TH1 0x4c7d +#define mmRLC_GPM_INT_DISABLE_TH1_BASE_IDX 1 +#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e +#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f +#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 +#define mmRLC_SRM_CNTL 0x4c80 +#define mmRLC_SRM_CNTL_BASE_IDX 1 +#define mmRLC_SRM_ARAM_ADDR 0x4c83 +#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define mmRLC_SRM_ARAM_DATA 0x4c84 +#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define mmRLC_SRM_DRAM_ADDR 0x4c85 +#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define mmRLC_SRM_DRAM_DATA 0x4c86 +#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define mmRLC_SRM_GPM_COMMAND 0x4c87 +#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define mmRLC_SRM_RLCV_COMMAND 0x4c89 +#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 +#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a +#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define mmRLC_SRM_STAT 0x4c9b +#define mmRLC_SRM_STAT_BASE_IDX 1 +#define mmRLC_SRM_GPM_ABORT 0x4c9c +#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define mmRLC_CSIB_ADDR_LO 0x4ca2 +#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define mmRLC_CSIB_ADDR_HI 0x4ca3 +#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define mmRLC_CSIB_LENGTH 0x4ca4 +#define mmRLC_CSIB_LENGTH_BASE_IDX 1 +#define mmRLC_SMU_COMMAND 0x4ca9 +#define mmRLC_SMU_COMMAND_BASE_IDX 1 +#define mmRLC_CP_SCHEDULERS 0x4caa +#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 +#define mmRLC_SMU_ARGUMENT_1 0x4cab +#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define mmRLC_SMU_ARGUMENT_2 0x4cac +#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_8 0x4cad +#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_9 0x4cae +#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_10 0x4caf +#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_11 0x4cb0 +#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 +#define mmRLC_GPM_GENERAL_12 0x4cb1 +#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 +#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 +#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 +#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 +#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define mmRLC_UTCL1_STATUS_2 0x4cb6 +#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define mmRLC_LB_THR_CONFIG_2 0x4cb8 +#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1 +#define mmRLC_LB_THR_CONFIG_3 0x4cb9 +#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1 +#define mmRLC_LB_THR_CONFIG_4 0x4cba +#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1 +#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define mmRLC_LB_THR_CONFIG_1 0x4cbf +#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 +#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 +#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 +#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 +#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 +#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 +#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 +#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 +#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 +#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 +#define mmRLC_SEMAPHORE_0 0x4cc7 +#define mmRLC_SEMAPHORE_0_BASE_IDX 1 +#define mmRLC_SEMAPHORE_1 0x4cc8 +#define mmRLC_SEMAPHORE_1_BASE_IDX 1 +#define mmRLC_CP_EOF_INT 0x4cca +#define mmRLC_CP_EOF_INT_BASE_IDX 1 +#define mmRLC_CP_EOF_INT_CNT 0x4ccb +#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 +#define mmRLC_SPARE_INT 0x4ccc +#define mmRLC_SPARE_INT_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd +#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce +#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf +#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 +#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 +#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 +#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 +#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 +#define mmRLC_DSM_TRIG 0x4cd3 +#define mmRLC_DSM_TRIG_BASE_IDX 1 +#define mmRLC_UTCL1_STATUS 0x4cd4 +#define mmRLC_UTCL1_STATUS_BASE_IDX 1 +#define mmRLC_R2I_CNTL_0 0x4cd5 +#define mmRLC_R2I_CNTL_0_BASE_IDX 1 +#define mmRLC_R2I_CNTL_1 0x4cd6 +#define mmRLC_R2I_CNTL_1_BASE_IDX 1 +#define mmRLC_R2I_CNTL_2 0x4cd7 +#define mmRLC_R2I_CNTL_2_BASE_IDX 1 +#define mmRLC_R2I_CNTL_3 0x4cd8 +#define mmRLC_R2I_CNTL_3_BASE_IDX 1 +#define mmRLC_UTCL2_CNTL 0x4cd9 +#define mmRLC_UTCL2_CNTL_BASE_IDX 1 +#define mmRLC_LBPW_CU_STAT 0x4cda +#define mmRLC_LBPW_CU_STAT_BASE_IDX 1 +#define mmRLC_DS_CNTL 0x4cdb +#define mmRLC_DS_CNTL_BASE_IDX 1 +#define mmRLC_RLCV_SPARE_INT 0x4f30 +#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 + + +// addressBlock: gc_pwrdec +// base address: 0x3c000 +#define mmCGTS_SM_CTRL_REG 0x5000 +#define mmCGTS_SM_CTRL_REG_BASE_IDX 1 +#define mmCGTS_RD_CTRL_REG 0x5001 +#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 +#define mmCGTS_RD_REG 0x5002 +#define mmCGTS_RD_REG_BASE_IDX 1 +#define mmCGTS_TCC_DISABLE 0x5003 +#define mmCGTS_TCC_DISABLE_BASE_IDX 1 +#define mmCGTS_USER_TCC_DISABLE 0x5004 +#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 +#define mmCGTS_CU0_SP0_CTRL_REG 0x5008 +#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a +#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU0_SP1_CTRL_REG 0x500b +#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c +#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_SP0_CTRL_REG 0x500d +#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e +#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f +#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_SP1_CTRL_REG 0x5010 +#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011 +#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_SP0_CTRL_REG 0x5012 +#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014 +#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_SP1_CTRL_REG 0x5015 +#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016 +#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_SP0_CTRL_REG 0x5017 +#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019 +#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_SP1_CTRL_REG 0x501a +#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b +#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_SP0_CTRL_REG 0x501c +#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d +#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e +#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_SP1_CTRL_REG 0x501f +#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020 +#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_SP0_CTRL_REG 0x5021 +#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023 +#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_SP1_CTRL_REG 0x5024 +#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025 +#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_SP0_CTRL_REG 0x5026 +#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028 +#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_SP1_CTRL_REG 0x5029 +#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a +#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_SP0_CTRL_REG 0x502b +#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c +#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d +#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_SP1_CTRL_REG 0x502e +#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f +#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_SP0_CTRL_REG 0x5030 +#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032 +#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_SP1_CTRL_REG 0x5033 +#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034 +#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_SP0_CTRL_REG 0x5035 +#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037 +#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_SP1_CTRL_REG 0x5038 +#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039 +#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_SP0_CTRL_REG 0x503a +#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b +#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c +#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_SP1_CTRL_REG 0x503d +#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e +#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_SP0_CTRL_REG 0x503f +#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 +#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041 +#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_SP1_CTRL_REG 0x5042 +#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043 +#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_SP0_CTRL_REG 0x5044 +#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046 +#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_SP1_CTRL_REG 0x5047 +#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048 +#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_SP0_CTRL_REG 0x5049 +#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a +#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b +#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_SP1_CTRL_REG 0x504c +#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d +#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_SP0_CTRL_REG 0x504e +#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f +#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050 +#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_SP1_CTRL_REG 0x5051 +#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052 +#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_SP0_CTRL_REG 0x5053 +#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055 +#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_SP1_CTRL_REG 0x5056 +#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057 +#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058 +#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059 +#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a +#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b +#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c +#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d +#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e +#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f +#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060 +#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061 +#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062 +#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063 +#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064 +#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065 +#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066 +#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067 +#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 +#define mmCGTT_SPI_CLK_CTRL 0x5080 +#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_PC_CLK_CTRL 0x5081 +#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_BCI_CLK_CTRL 0x5082 +#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_VGT_CLK_CTRL 0x5084 +#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_IA_CLK_CTRL 0x5085 +#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_WD_CLK_CTRL 0x5086 +#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_PA_CLK_CTRL 0x5088 +#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_SC_CLK_CTRL0 0x5089 +#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define mmCGTT_SC_CLK_CTRL1 0x508a +#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define mmCGTT_SQ_CLK_CTRL 0x508c +#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_SQG_CLK_CTRL 0x508d +#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define mmSQ_ALU_CLK_CTRL 0x508e +#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define mmSQ_TEX_CLK_CTRL 0x508f +#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define mmSQ_LDS_CLK_CTRL 0x5090 +#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define mmSQ_POWER_THROTTLE 0x5091 +#define mmSQ_POWER_THROTTLE_BASE_IDX 1 +#define mmSQ_POWER_THROTTLE2 0x5092 +#define mmSQ_POWER_THROTTLE2_BASE_IDX 1 +#define mmCGTT_SX_CLK_CTRL0 0x5094 +#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 +#define mmCGTT_SX_CLK_CTRL1 0x5095 +#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 +#define mmCGTT_SX_CLK_CTRL2 0x5096 +#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 +#define mmCGTT_SX_CLK_CTRL3 0x5097 +#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 +#define mmCGTT_SX_CLK_CTRL4 0x5098 +#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 +#define mmTD_CGTT_CTRL 0x509c +#define mmTD_CGTT_CTRL_BASE_IDX 1 +#define mmTA_CGTT_CTRL 0x509d +#define mmTA_CGTT_CTRL_BASE_IDX 1 +#define mmCGTT_TCPI_CLK_CTRL 0x509e +#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_TCI_CLK_CTRL 0x509f +#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_GDS_CLK_CTRL 0x50a0 +#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 +#define mmDB_CGTT_CLK_CTRL_0 0x50a4 +#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define mmCB_CGTT_SCLK_CTRL 0x50a8 +#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 +#define mmTCC_CGTT_SCLK_CTRL 0x50ac +#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1 +#define mmTCA_CGTT_SCLK_CTRL 0x50ad +#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1 +#define mmCGTT_CP_CLK_CTRL 0x50b0 +#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_CPF_CLK_CTRL 0x50b1 +#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_CPC_CLK_CTRL 0x50b2 +#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define mmRLC_PWR_CTRL 0x50b4 +#define mmRLC_PWR_CTRL_BASE_IDX 1 +#define mmCGTT_RLC_CLK_CTRL 0x50b5 +#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define mmRLC_GFX_RM_CNTL 0x50b6 +#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 +#define mmRMI_CGTT_SCLK_CTRL 0x50c0 +#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 +#define mmCGTT_TCPF_CLK_CTRL 0x50c1 +#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_ea_pwrdec +// base address: 0x3c000 +#define mmGCEA_CGTT_CLK_CTRL 0x50c4 +#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_utcl2_vmsharedhvdec +// base address: 0x3ea00 +#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 +#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 +#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 +#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 +#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 +#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 +#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 +#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 +#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 +#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 +#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a +#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b +#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c +#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d +#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e +#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f +#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90 +#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_LO_0 0x5a91 +#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_LO_1 0x5a92 +#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_LO_2 0x5a93 +#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_LO_3 0x5a94 +#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_HI_0 0x5a95 +#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_HI_1 0x5a96 +#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_HI_2 0x5a97 +#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define mmMC_VM_MARC_BASE_HI_3 0x5a98 +#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_LO_0 0x5a99 +#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a +#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b +#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c +#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d +#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e +#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f +#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0 +#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_LO_0 0x5aa1 +#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_LO_1 0x5aa2 +#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_LO_2 0x5aa3 +#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_LO_3 0x5aa4 +#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_HI_0 0x5aa5 +#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_HI_1 0x5aa6 +#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_HI_2 0x5aa7 +#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define mmMC_VM_MARC_LEN_HI_3 0x5aa8 +#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9 +#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL 0x5aab +#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac +#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad +#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae +#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf +#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0 +#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1 +#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2 +#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3 +#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4 +#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5 +#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6 +#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7 +#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8 +#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9 +#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba +#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 +#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb +#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 +#define mmUTCL2_CGTT_CLK_CTRL 0x5abc +#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: gc_hypdec +// base address: 0x3e000 +#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 +#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define mmCP_PFP_UCODE_ADDR 0x5814 +#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define mmCP_HYP_PFP_UCODE_DATA 0x5815 +#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define mmCP_PFP_UCODE_DATA 0x5815 +#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 +#define mmCP_HYP_ME_UCODE_ADDR 0x5816 +#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define mmCP_ME_RAM_RADDR 0x5816 +#define mmCP_ME_RAM_RADDR_BASE_IDX 1 +#define mmCP_ME_RAM_WADDR 0x5816 +#define mmCP_ME_RAM_WADDR_BASE_IDX 1 +#define mmCP_HYP_ME_UCODE_DATA 0x5817 +#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define mmCP_ME_RAM_DATA 0x5817 +#define mmCP_ME_RAM_DATA_BASE_IDX 1 +#define mmCP_CE_UCODE_ADDR 0x5818 +#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 +#define mmCP_HYP_CE_UCODE_ADDR 0x5818 +#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 +#define mmCP_CE_UCODE_DATA 0x5819 +#define mmCP_CE_UCODE_DATA_BASE_IDX 1 +#define mmCP_HYP_CE_UCODE_DATA 0x5819 +#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 +#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a +#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define mmCP_MEC_ME1_UCODE_ADDR 0x581a +#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define mmCP_HYP_MEC1_UCODE_DATA 0x581b +#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define mmCP_MEC_ME1_UCODE_DATA 0x581b +#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c +#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 +#define mmCP_MEC_ME2_UCODE_ADDR 0x581c +#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 +#define mmCP_HYP_MEC2_UCODE_DATA 0x581d +#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 +#define mmCP_MEC_ME2_UCODE_DATA 0x581d +#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 +#define mmRLC_GPM_UCODE_ADDR 0x583c +#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define mmRLC_GPM_UCODE_DATA 0x583d +#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 +#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 +#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 +#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 +#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define mmGRBM_CAM_INDEX 0x5a04 +#define mmGRBM_CAM_INDEX_BASE_IDX 1 +#define mmGRBM_HYP_CAM_INDEX 0x5a04 +#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 +#define mmGRBM_CAM_DATA 0x5a05 +#define mmGRBM_CAM_DATA_BASE_IDX 1 +#define mmGRBM_HYP_CAM_DATA 0x5a05 +#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1 +#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define mmRLC_GFX_RM_CNTL_ADJ 0x5b01 +#define mmRLC_GFX_RM_CNTL_ADJ_BASE_IDX 1 +#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 +#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 +#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define mmRLC_RLCV_TIMER_INT_0 0x5b25 +#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 +#define mmRLC_RLCV_TIMER_CTRL 0x5b26 +#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 +#define mmRLC_RLCV_TIMER_STAT 0x5b27 +#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define mmRLC_GPU_IOV_VF_MASK 0x5b2d +#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define mmRLC_HYP_SEMAPHORE_2 0x5b2e +#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define mmRLC_HYP_SEMAPHORE_3 0x5b2f +#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define mmRLC_CLK_CNTL 0x5b31 +#define mmRLC_CLK_CNTL_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 +#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 +#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCH_0 0x5b38 +#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 +#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCH_3 0x5b3a +#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCH_1 0x5b3b +#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCH_2 0x5b3c +#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42 +#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 +#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43 +#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 +#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 +#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45 +#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 +#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 +#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 +#define mmRLC_GPU_IOV_F32_RESET 0x5b47 +#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 +#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48 +#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49 +#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c +#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 +#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e +#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 +#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f +#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 +#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 +#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 +#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: gccacind +// base address: 0x0 +#define ixGC_CAC_CNTL 0x0000 +#define ixGC_CAC_OVR_SEL 0x0001 +#define ixGC_CAC_OVR_VAL 0x0002 +#define ixGC_CAC_WEIGHT_BCI_0 0x0003 +#define ixGC_CAC_WEIGHT_CB_0 0x0004 +#define ixGC_CAC_WEIGHT_CB_1 0x0005 +#define ixGC_CAC_WEIGHT_CP_0 0x0008 +#define ixGC_CAC_WEIGHT_CP_1 0x0009 +#define ixGC_CAC_WEIGHT_DB_0 0x000a +#define ixGC_CAC_WEIGHT_DB_1 0x000b +#define ixGC_CAC_WEIGHT_GDS_0 0x000e +#define ixGC_CAC_WEIGHT_GDS_1 0x000f +#define ixGC_CAC_WEIGHT_IA_0 0x0010 +#define ixGC_CAC_WEIGHT_LDS_0 0x0011 +#define ixGC_CAC_WEIGHT_LDS_1 0x0012 +#define ixGC_CAC_WEIGHT_PA_0 0x0013 +#define ixGC_CAC_WEIGHT_PC_0 0x0014 +#define ixGC_CAC_WEIGHT_SC_0 0x0015 +#define ixGC_CAC_WEIGHT_SPI_0 0x0016 +#define ixGC_CAC_WEIGHT_SPI_1 0x0017 +#define ixGC_CAC_WEIGHT_SPI_2 0x0018 +#define ixGC_CAC_WEIGHT_SQ_0 0x001a +#define ixGC_CAC_WEIGHT_SQ_1 0x001b +#define ixGC_CAC_WEIGHT_SQ_2 0x001c +#define ixGC_CAC_WEIGHT_SQ_3 0x001d +#define ixGC_CAC_WEIGHT_SQ_4 0x001e +#define ixGC_CAC_WEIGHT_SX_0 0x001f +#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 +#define ixGC_CAC_WEIGHT_TA_0 0x0021 +#define ixGC_CAC_WEIGHT_TCC_0 0x0022 +#define ixGC_CAC_WEIGHT_TCC_1 0x0023 +#define ixGC_CAC_WEIGHT_TCC_2 0x0024 +#define ixGC_CAC_WEIGHT_TCP_0 0x0025 +#define ixGC_CAC_WEIGHT_TCP_1 0x0026 +#define ixGC_CAC_WEIGHT_TCP_2 0x0027 +#define ixGC_CAC_WEIGHT_TD_0 0x0028 +#define ixGC_CAC_WEIGHT_TD_1 0x0029 +#define ixGC_CAC_WEIGHT_TD_2 0x002a +#define ixGC_CAC_WEIGHT_VGT_0 0x002b +#define ixGC_CAC_WEIGHT_VGT_1 0x002c +#define ixGC_CAC_WEIGHT_WD_0 0x002d +#define ixGC_CAC_WEIGHT_CU_0 0x0032 +#define ixGC_CAC_WEIGHT_CU_1 0x0033 +#define ixGC_CAC_WEIGHT_CU_2 0x0034 +#define ixGC_CAC_WEIGHT_CU_3 0x0035 +#define ixGC_CAC_WEIGHT_CU_4 0x0036 +#define ixGC_CAC_WEIGHT_CU_5 0x0037 +#define ixGC_CAC_ACC_BCI0 0x0042 +#define ixGC_CAC_ACC_CB0 0x0043 +#define ixGC_CAC_ACC_CB1 0x0044 +#define ixGC_CAC_ACC_CB2 0x0045 +#define ixGC_CAC_ACC_CB3 0x0046 +#define ixGC_CAC_ACC_CP0 0x004b +#define ixGC_CAC_ACC_CP1 0x004c +#define ixGC_CAC_ACC_CP2 0x004d +#define ixGC_CAC_ACC_DB0 0x004e +#define ixGC_CAC_ACC_DB1 0x004f +#define ixGC_CAC_ACC_DB2 0x0050 +#define ixGC_CAC_ACC_DB3 0x0051 +#define ixGC_CAC_ACC_GDS0 0x0056 +#define ixGC_CAC_ACC_GDS1 0x0057 +#define ixGC_CAC_ACC_GDS2 0x0058 +#define ixGC_CAC_ACC_GDS3 0x0059 +#define ixGC_CAC_ACC_IA0 0x005a +#define ixGC_CAC_ACC_LDS0 0x005b +#define ixGC_CAC_ACC_LDS1 0x005c +#define ixGC_CAC_ACC_LDS2 0x005d +#define ixGC_CAC_ACC_LDS3 0x005e +#define ixGC_CAC_ACC_PA0 0x005f +#define ixGC_CAC_ACC_PA1 0x0060 +#define ixGC_CAC_ACC_PC0 0x0061 +#define ixGC_CAC_ACC_SC0 0x0062 +#define ixGC_CAC_ACC_SPI0 0x0063 +#define ixGC_CAC_ACC_SPI1 0x0064 +#define ixGC_CAC_ACC_SPI2 0x0065 +#define ixGC_CAC_ACC_SPI3 0x0066 +#define ixGC_CAC_ACC_SPI4 0x0067 +#define ixGC_CAC_ACC_SPI5 0x0068 +#define ixGC_CAC_WEIGHT_PG_0 0x0069 +#define ixGC_CAC_ACC_PG0 0x006a +#define ixGC_CAC_OVRD_PG 0x006b +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f +#define ixGC_CAC_ACC_EA0 0x0070 +#define ixGC_CAC_ACC_EA1 0x0071 +#define ixGC_CAC_ACC_EA2 0x0072 +#define ixGC_CAC_ACC_EA3 0x0073 +#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 +#define ixGC_CAC_OVRD_EA 0x0075 +#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 +#define ixGC_CAC_WEIGHT_EA_0 0x0077 +#define ixGC_CAC_WEIGHT_EA_1 0x0078 +#define ixGC_CAC_WEIGHT_RMI_0 0x0079 +#define ixGC_CAC_ACC_RMI0 0x007a +#define ixGC_CAC_OVRD_RMI 0x007b +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c +#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d +#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e +#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f +#define ixGC_CAC_ACC_EA4 0x0080 +#define ixGC_CAC_ACC_EA5 0x0081 +#define ixGC_CAC_WEIGHT_EA_2 0x0082 +#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 +#define ixGC_CAC_ACC_SQ0_UPPER 0x008a +#define ixGC_CAC_ACC_SQ1_LOWER 0x008b +#define ixGC_CAC_ACC_SQ1_UPPER 0x008c +#define ixGC_CAC_ACC_SQ2_LOWER 0x008d +#define ixGC_CAC_ACC_SQ2_UPPER 0x008e +#define ixGC_CAC_ACC_SQ3_LOWER 0x008f +#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 +#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 +#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 +#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 +#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 +#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 +#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 +#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 +#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 +#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 +#define ixGC_CAC_ACC_SQ8_UPPER 0x009a +#define ixGC_CAC_ACC_SX0 0x009b +#define ixGC_CAC_ACC_SXRB0 0x009c +#define ixGC_CAC_ACC_SXRB1 0x009d +#define ixGC_CAC_ACC_TA0 0x009e +#define ixGC_CAC_ACC_TCC0 0x009f +#define ixGC_CAC_ACC_TCC1 0x00a0 +#define ixGC_CAC_ACC_TCC2 0x00a1 +#define ixGC_CAC_ACC_TCC3 0x00a2 +#define ixGC_CAC_ACC_TCC4 0x00a3 +#define ixGC_CAC_ACC_TCP0 0x00a4 +#define ixGC_CAC_ACC_TCP1 0x00a5 +#define ixGC_CAC_ACC_TCP2 0x00a6 +#define ixGC_CAC_ACC_TCP3 0x00a7 +#define ixGC_CAC_ACC_TCP4 0x00a8 +#define ixGC_CAC_ACC_TD0 0x00a9 +#define ixGC_CAC_ACC_TD1 0x00aa +#define ixGC_CAC_ACC_TD2 0x00ab +#define ixGC_CAC_ACC_TD3 0x00ac +#define ixGC_CAC_ACC_TD4 0x00ad +#define ixGC_CAC_ACC_TD5 0x00ae +#define ixGC_CAC_ACC_VGT0 0x00af +#define ixGC_CAC_ACC_VGT1 0x00b0 +#define ixGC_CAC_ACC_VGT2 0x00b1 +#define ixGC_CAC_ACC_WD0 0x00b2 +#define ixGC_CAC_ACC_CU0 0x00ba +#define ixGC_CAC_ACC_CU1 0x00bb +#define ixGC_CAC_ACC_CU2 0x00bc +#define ixGC_CAC_ACC_CU3 0x00bd +#define ixGC_CAC_ACC_CU4 0x00be +#define ixGC_CAC_ACC_CU5 0x00bf +#define ixGC_CAC_ACC_CU6 0x00c0 +#define ixGC_CAC_ACC_CU7 0x00c1 +#define ixGC_CAC_ACC_CU8 0x00c2 +#define ixGC_CAC_ACC_CU9 0x00c3 +#define ixGC_CAC_ACC_CU10 0x00c4 +#define ixGC_CAC_OVRD_BCI 0x00da +#define ixGC_CAC_OVRD_CB 0x00db +#define ixGC_CAC_OVRD_CP 0x00dd +#define ixGC_CAC_OVRD_DB 0x00de +#define ixGC_CAC_OVRD_GDS 0x00e0 +#define ixGC_CAC_OVRD_IA 0x00e1 +#define ixGC_CAC_OVRD_LDS 0x00e2 +#define ixGC_CAC_OVRD_PA 0x00e3 +#define ixGC_CAC_OVRD_PC 0x00e4 +#define ixGC_CAC_OVRD_SC 0x00e5 +#define ixGC_CAC_OVRD_SPI 0x00e6 +#define ixGC_CAC_OVRD_CU 0x00e7 +#define ixGC_CAC_OVRD_SQ 0x00e8 +#define ixGC_CAC_OVRD_SX 0x00e9 +#define ixGC_CAC_OVRD_SXRB 0x00ea +#define ixGC_CAC_OVRD_TA 0x00eb +#define ixGC_CAC_OVRD_TCC 0x00ec +#define ixGC_CAC_OVRD_TCP 0x00ed +#define ixGC_CAC_OVRD_TD 0x00ee +#define ixGC_CAC_OVRD_VGT 0x00ef +#define ixGC_CAC_OVRD_WD 0x00f0 +#define ixGC_CAC_ACC_BCI1 0x00ff +#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 +#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 +#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 +#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 +#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a +#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b +#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c +#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d +#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e +#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f +#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 +#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 +#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 +#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 +#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 +#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 +#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 +#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 +#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 +#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 +#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c +#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d +#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e +#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f +#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 +#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 +#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 +#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 + + +// addressBlock: secacind +// base address: 0x0 +#define ixSE_CAC_CNTL 0x0000 +#define ixSE_CAC_OVR_SEL 0x0001 +#define ixSE_CAC_OVR_VAL 0x0002 + + +// addressBlock: sqind +// base address: 0x0 +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_INST_DW0 0x001a +#define ixSQ_WAVE_INST_DW1 0x001b +#define ixSQ_WAVE_IB_DBG0 0x001c +#define ixSQ_WAVE_IB_DBG1 0x001d +#define ixSQ_WAVE_FLUSH_IB 0x001e +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP2 0x026e +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027c +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f +#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 + + +// addressBlock: didtind +// base address: 0x0 +#define ixDIDT_SQ_CTRL0 0x0000 +#define ixDIDT_SQ_CTRL1 0x0001 +#define ixDIDT_SQ_CTRL2 0x0002 +#define ixDIDT_SQ_STALL_CTRL 0x0004 +#define ixDIDT_SQ_TUNING_CTRL 0x0005 +#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 +#define ixDIDT_SQ_CTRL3 0x0007 +#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 +#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 +#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a +#define ixDIDT_SQ_STALL_PATTERN_7 0x000b +#define ixDIDT_SQ_WEIGHT0_3 0x0010 +#define ixDIDT_SQ_WEIGHT4_7 0x0011 +#define ixDIDT_SQ_WEIGHT8_11 0x0012 +#define ixDIDT_SQ_EDC_CTRL 0x0013 +#define ixDIDT_SQ_EDC_THRESHOLD 0x0014 +#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 +#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 +#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 +#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 +#define ixDIDT_SQ_EDC_STATUS 0x0019 +#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a +#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b +#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c +#define ixDIDT_SQ_EDC_OVERFLOW 0x001e +#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f +#define ixDIDT_DB_CTRL0 0x0020 +#define ixDIDT_DB_CTRL1 0x0021 +#define ixDIDT_DB_CTRL2 0x0022 +#define ixDIDT_DB_STALL_CTRL 0x0024 +#define ixDIDT_DB_TUNING_CTRL 0x0025 +#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 +#define ixDIDT_DB_CTRL3 0x0027 +#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 +#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 +#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a +#define ixDIDT_DB_STALL_PATTERN_7 0x002b +#define ixDIDT_DB_WEIGHT0_3 0x0030 +#define ixDIDT_DB_WEIGHT4_7 0x0031 +#define ixDIDT_DB_WEIGHT8_11 0x0032 +#define ixDIDT_DB_EDC_CTRL 0x0033 +#define ixDIDT_DB_EDC_THRESHOLD 0x0034 +#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 +#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 +#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 +#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 +#define ixDIDT_DB_EDC_STATUS 0x0039 +#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a +#define ixDIDT_DB_EDC_OVERFLOW 0x003e +#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f +#define ixDIDT_TD_CTRL0 0x0040 +#define ixDIDT_TD_CTRL1 0x0041 +#define ixDIDT_TD_CTRL2 0x0042 +#define ixDIDT_TD_STALL_CTRL 0x0044 +#define ixDIDT_TD_TUNING_CTRL 0x0045 +#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 +#define ixDIDT_TD_CTRL3 0x0047 +#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 +#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 +#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a +#define ixDIDT_TD_STALL_PATTERN_7 0x004b +#define ixDIDT_TD_WEIGHT0_3 0x0050 +#define ixDIDT_TD_WEIGHT4_7 0x0051 +#define ixDIDT_TD_WEIGHT8_11 0x0052 +#define ixDIDT_TD_EDC_CTRL 0x0053 +#define ixDIDT_TD_EDC_THRESHOLD 0x0054 +#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 +#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 +#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 +#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 +#define ixDIDT_TD_EDC_STATUS 0x0059 +#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a +#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b +#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c +#define ixDIDT_TD_EDC_OVERFLOW 0x005e +#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f +#define ixDIDT_TCP_CTRL0 0x0060 +#define ixDIDT_TCP_CTRL1 0x0061 +#define ixDIDT_TCP_CTRL2 0x0062 +#define ixDIDT_TCP_STALL_CTRL 0x0064 +#define ixDIDT_TCP_TUNING_CTRL 0x0065 +#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 +#define ixDIDT_TCP_CTRL3 0x0067 +#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 +#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 +#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a +#define ixDIDT_TCP_STALL_PATTERN_7 0x006b +#define ixDIDT_TCP_WEIGHT0_3 0x0070 +#define ixDIDT_TCP_WEIGHT4_7 0x0071 +#define ixDIDT_TCP_WEIGHT8_11 0x0072 +#define ixDIDT_TCP_EDC_CTRL 0x0073 +#define ixDIDT_TCP_EDC_THRESHOLD 0x0074 +#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 +#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 +#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 +#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 +#define ixDIDT_TCP_EDC_STATUS 0x0079 +#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a +#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b +#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c +#define ixDIDT_TCP_EDC_OVERFLOW 0x007e +#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f +#define ixDIDT_DBR_CTRL0 0x0080 +#define ixDIDT_DBR_CTRL1 0x0081 +#define ixDIDT_DBR_CTRL2 0x0082 +#define ixDIDT_DBR_STALL_CTRL 0x0084 +#define ixDIDT_DBR_TUNING_CTRL 0x0085 +#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL 0x0086 +#define ixDIDT_DBR_CTRL3 0x0087 +#define ixDIDT_DBR_STALL_PATTERN_1_2 0x0088 +#define ixDIDT_DBR_STALL_PATTERN_3_4 0x0089 +#define ixDIDT_DBR_STALL_PATTERN_5_6 0x008a +#define ixDIDT_DBR_STALL_PATTERN_7 0x008b +#define ixDIDT_DBR_WEIGHT0_3 0x0090 +#define ixDIDT_DBR_WEIGHT4_7 0x0091 +#define ixDIDT_DBR_WEIGHT8_11 0x0092 +#define ixDIDT_DBR_EDC_CTRL 0x0093 +#define ixDIDT_DBR_EDC_THRESHOLD 0x0094 +#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2 0x0095 +#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4 0x0096 +#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097 +#define ixDIDT_DBR_EDC_STALL_PATTERN_7 0x0098 +#define ixDIDT_DBR_EDC_STATUS 0x0099 +#define ixDIDT_DBR_EDC_STALL_DELAY_1 0x009a +#define ixDIDT_DBR_EDC_OVERFLOW 0x009e +#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA 0x009f +#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 +#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 +#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 +#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 +#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h new file mode 100644 index 000000000000..ab0a25eba483 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h @@ -0,0 +1,31191 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _gc_9_1_SH_MASK_HEADER +#define _gc_9_1_SH_MASK_HEADER + + +// addressBlock: gc_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L +#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L +#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L +#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +//GRBM_CGTT_CLK_CNTL +#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_STATUS_SE2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE3 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_DSM_BYPASS +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_IOV_ERROR +#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 +#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 +#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a +#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b +#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f +#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL +#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L +#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L +#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L +#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +//GRBM_RSMU_CFG +#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 +#define GRBM_RSMU_CFG__QOS__SHIFT 0xc +#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 +#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL +#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L +#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_RSMU_READ_ERROR +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L +//GRBM_CHICKEN_BITS +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL + + +// addressBlock: gc_cpdec +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MEC_ME2_HEADER_DUMP +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_PRT_LOD_STATS_CNTL0 +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL +//CP_PRT_LOD_STATS_CNTL1 +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL +//CP_PRT_LOD_STATS_CNTL2 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL +//CP_PRT_LOD_STATS_CNTL3 +#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2 +#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa +#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12 +#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13 +#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17 +#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c +#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL +#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L +#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L +#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L +#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L +#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L +//CP_CE_COMPARE_COUNT +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_DE_COUNT +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_CE_COUNT +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_LAST_INVAL_COUNT +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL +//CP_DE_DE_COUNT +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +//CP_STAT +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_CE_HEADER_DUMP +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CE_INSTR_PNTR +#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC1_INSTR_PNTR +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC2_INSTR_PNTR +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_ROQ_THRESHOLDS +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L +//CP_MEQ_STQ_THRESHOLD +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL +//CP_RB2_RPTR +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB1_RPTR +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_CEQ1_AVAIL +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L +//CP_CEQ2_AVAIL +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL +//CP_CE_ROQ_RB_STAT +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_CE_ROQ_IB1_STAT +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_CE_ROQ_IB2_STAT +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L + + +// addressBlock: gc_padec +//VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L +//VGT_CACHE_INVALIDATION +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L +//VGT_STRMOUT_DELAY +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L +//VGT_FIFO_DEPTHS +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L +//VGT_GS_VERTEX_REUSE +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_CNTL_STATUS +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L +//VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L +//WD_CNTL_STATUS +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L +//CC_GC_PRIM_CONFIG +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//GC_USER_PRIM_CONFIG +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//WD_QOS +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x00000001L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//VGT_SYS_CONFIG +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +//VGT_VS_MAX_WAVE_ID +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//VGT_DMA_PRIMITIVE_TYPE +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_DMA_CONTROL +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 +#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L +#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L +#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L +//VGT_DMA_LS_HS_CONFIG +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +//WD_BUF_RESOURCE_1 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L +//WD_BUF_RESOURCE_2 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL +#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_UTCL1_CNTL1 +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//PA_UTCL1_CNTL2 +#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 +#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd +#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b +#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL +#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L +#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L +//PA_SIDEBAND_REQUEST_DELAYS +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L + + +// addressBlock: gc_sqdec +//SQ_CONFIG +#define SQ_CONFIG__UNUSED__SHIFT 0x0 +#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f +#define SQ_CONFIG__UNUSED_MASK 0x0000007FL +#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 +#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 +#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L +#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L +#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L +//LDS_CONFIG +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L +//SQ_REG_CREDITS +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 +#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc +#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L +#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L +#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L +//CC_GC_SHADER_RATE_CONFIG +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//GC_USER_SHADER_RATE_CONFIG +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_UTCL1_CNTL1 +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 +#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L +#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQ_UTCL1_CNTL2 +#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c +#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L +//SQ_UTCL1_STATUS +#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 +#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L +#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL +//SQC_DSM_CNTL +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//SQC_DSM_CNTLA +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTLB +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTL2 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//SQC_DSM_CNTL2A +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_DSM_CNTL2B +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_EDC_FUE_CNTL +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQC_EDC_CNT2 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L +//SQC_EDC_CNT3 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L +//SQ_REG_TIMESTAMP +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_CMD_TIMESTAMP +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL +#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L +#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L +#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L +#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x00000007L +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x000F0000L +#define SQ_CMD__SIMD_ID_MASK 0x00300000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L +//SQ_TIME_HI +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL +//SQ_TIME_LO +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL +//SQ_DS_0 +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS__SHIFT 0x10 +#define SQ_DS_0__OP__SHIFT 0x11 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_DS_0__OFFSET0_MASK 0x000000FFL +#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L +#define SQ_DS_0__GDS_MASK 0x00010000L +#define SQ_DS_0__OP_MASK 0x01FE0000L +#define SQ_DS_0__ENCODING_MASK 0xFC000000L +//SQ_DS_1 +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0x000000FFL +#define SQ_DS_1__DATA0_MASK 0x0000FF00L +#define SQ_DS_1__DATA1_MASK 0x00FF0000L +#define SQ_DS_1__VDST_MASK 0xFF000000L +//SQ_EXP_0 +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_EXP_0__EN_MASK 0x0000000FL +#define SQ_EXP_0__TGT_MASK 0x000003F0L +#define SQ_EXP_0__COMPR_MASK 0x00000400L +#define SQ_EXP_0__DONE_MASK 0x00000800L +#define SQ_EXP_0__VM_MASK 0x00001000L +#define SQ_EXP_0__ENCODING_MASK 0xFC000000L +//SQ_EXP_1 +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0x000000FFL +#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L +#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L +#define SQ_EXP_1__VSRC3_MASK 0xFF000000L +//SQ_FLAT_0 +#define SQ_FLAT_0__OFFSET__SHIFT 0x0 +#define SQ_FLAT_0__LDS__SHIFT 0xd +#define SQ_FLAT_0__SEG__SHIFT 0xe +#define SQ_FLAT_0__GLC__SHIFT 0x10 +#define SQ_FLAT_0__SLC__SHIFT 0x11 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL +#define SQ_FLAT_0__LDS_MASK 0x00002000L +#define SQ_FLAT_0__SEG_MASK 0x0000C000L +#define SQ_FLAT_0__GLC_MASK 0x00010000L +#define SQ_FLAT_0__SLC_MASK 0x00020000L +#define SQ_FLAT_0__OP_MASK 0x01FC0000L +#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L +//SQ_FLAT_1 +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__SADDR__SHIFT 0x10 +#define SQ_FLAT_1__NV__SHIFT 0x17 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_FLAT_1__ADDR_MASK 0x000000FFL +#define SQ_FLAT_1__DATA_MASK 0x0000FF00L +#define SQ_FLAT_1__SADDR_MASK 0x007F0000L +#define SQ_FLAT_1__NV_MASK 0x00800000L +#define SQ_FLAT_1__VDST_MASK 0xFF000000L +//SQ_GLBL_0 +#define SQ_GLBL_0__OFFSET__SHIFT 0x0 +#define SQ_GLBL_0__LDS__SHIFT 0xd +#define SQ_GLBL_0__SEG__SHIFT 0xe +#define SQ_GLBL_0__GLC__SHIFT 0x10 +#define SQ_GLBL_0__SLC__SHIFT 0x11 +#define SQ_GLBL_0__OP__SHIFT 0x12 +#define SQ_GLBL_0__ENCODING__SHIFT 0x1a +#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL +#define SQ_GLBL_0__LDS_MASK 0x00002000L +#define SQ_GLBL_0__SEG_MASK 0x0000C000L +#define SQ_GLBL_0__GLC_MASK 0x00010000L +#define SQ_GLBL_0__SLC_MASK 0x00020000L +#define SQ_GLBL_0__OP_MASK 0x01FC0000L +#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L +//SQ_GLBL_1 +#define SQ_GLBL_1__ADDR__SHIFT 0x0 +#define SQ_GLBL_1__DATA__SHIFT 0x8 +#define SQ_GLBL_1__SADDR__SHIFT 0x10 +#define SQ_GLBL_1__NV__SHIFT 0x17 +#define SQ_GLBL_1__VDST__SHIFT 0x18 +#define SQ_GLBL_1__ADDR_MASK 0x000000FFL +#define SQ_GLBL_1__DATA_MASK 0x0000FF00L +#define SQ_GLBL_1__SADDR_MASK 0x007F0000L +#define SQ_GLBL_1__NV_MASK 0x00800000L +#define SQ_GLBL_1__VDST_MASK 0xFF000000L +//SQ_INST +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL +//SQ_MIMG_0 +#define SQ_MIMG_0__OPM__SHIFT 0x0 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__GLC__SHIFT 0xd +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__A16__SHIFT 0xf +#define SQ_MIMG_0__TFE__SHIFT 0x10 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__SLC__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_MIMG_0__OPM_MASK 0x00000001L +#define SQ_MIMG_0__DMASK_MASK 0x00000F00L +#define SQ_MIMG_0__UNORM_MASK 0x00001000L +#define SQ_MIMG_0__GLC_MASK 0x00002000L +#define SQ_MIMG_0__DA_MASK 0x00004000L +#define SQ_MIMG_0__A16_MASK 0x00008000L +#define SQ_MIMG_0__TFE_MASK 0x00010000L +#define SQ_MIMG_0__LWE_MASK 0x00020000L +#define SQ_MIMG_0__OP_MASK 0x01FC0000L +#define SQ_MIMG_0__SLC_MASK 0x02000000L +#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L +//SQ_MIMG_1 +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_MIMG_1__D16__SHIFT 0x1f +#define SQ_MIMG_1__VADDR_MASK 0x000000FFL +#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L +#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L +#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L +#define SQ_MIMG_1__D16_MASK 0x80000000L +//SQ_MTBUF_0 +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__GLC__SHIFT 0xe +#define SQ_MTBUF_0__OP__SHIFT 0xf +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MTBUF_0__GLC_MASK 0x00004000L +#define SQ_MTBUF_0__OP_MASK 0x00078000L +#define SQ_MTBUF_0__DFMT_MASK 0x00780000L +#define SQ_MTBUF_0__NFMT_MASK 0x03800000L +#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MTBUF_1 +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SLC__SHIFT 0x16 +#define SQ_MTBUF_1__TFE__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MTBUF_1__SLC_MASK 0x00400000L +#define SQ_MTBUF_1__TFE_MASK 0x00800000L +#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_MUBUF_0 +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__GLC__SHIFT 0xe +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__SLC__SHIFT 0x11 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MUBUF_0__GLC_MASK 0x00004000L +#define SQ_MUBUF_0__LDS_MASK 0x00010000L +#define SQ_MUBUF_0__SLC_MASK 0x00020000L +#define SQ_MUBUF_0__OP_MASK 0x01FC0000L +#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MUBUF_1 +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__TFE__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MUBUF_1__TFE_MASK 0x00800000L +#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_SCRATCH_0 +#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 +#define SQ_SCRATCH_0__LDS__SHIFT 0xd +#define SQ_SCRATCH_0__SEG__SHIFT 0xe +#define SQ_SCRATCH_0__GLC__SHIFT 0x10 +#define SQ_SCRATCH_0__SLC__SHIFT 0x11 +#define SQ_SCRATCH_0__OP__SHIFT 0x12 +#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a +#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL +#define SQ_SCRATCH_0__LDS_MASK 0x00002000L +#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L +#define SQ_SCRATCH_0__GLC_MASK 0x00010000L +#define SQ_SCRATCH_0__SLC_MASK 0x00020000L +#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L +#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L +//SQ_SCRATCH_1 +#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 +#define SQ_SCRATCH_1__DATA__SHIFT 0x8 +#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 +#define SQ_SCRATCH_1__NV__SHIFT 0x17 +#define SQ_SCRATCH_1__VDST__SHIFT 0x18 +#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL +#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L +#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L +#define SQ_SCRATCH_1__NV_MASK 0x00800000L +#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L +//SQ_SMEM_0 +#define SQ_SMEM_0__SBASE__SHIFT 0x0 +#define SQ_SMEM_0__SDATA__SHIFT 0x6 +#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe +#define SQ_SMEM_0__NV__SHIFT 0xf +#define SQ_SMEM_0__GLC__SHIFT 0x10 +#define SQ_SMEM_0__IMM__SHIFT 0x11 +#define SQ_SMEM_0__OP__SHIFT 0x12 +#define SQ_SMEM_0__ENCODING__SHIFT 0x1a +#define SQ_SMEM_0__SBASE_MASK 0x0000003FL +#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L +#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L +#define SQ_SMEM_0__NV_MASK 0x00008000L +#define SQ_SMEM_0__GLC_MASK 0x00010000L +#define SQ_SMEM_0__IMM_MASK 0x00020000L +#define SQ_SMEM_0__OP_MASK 0x03FC0000L +#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L +//SQ_SMEM_1 +#define SQ_SMEM_1__OFFSET__SHIFT 0x0 +#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 +#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL +#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L +//SQ_SOP1 +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOP1__SSRC0_MASK 0x000000FFL +#define SQ_SOP1__OP_MASK 0x0000FF00L +#define SQ_SOP1__SDST_MASK 0x007F0000L +#define SQ_SOP1__ENCODING_MASK 0xFF800000L +//SQ_SOP2 +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_SOP2__SSRC0_MASK 0x000000FFL +#define SQ_SOP2__SSRC1_MASK 0x0000FF00L +#define SQ_SOP2__SDST_MASK 0x007F0000L +#define SQ_SOP2__OP_MASK 0x3F800000L +#define SQ_SOP2__ENCODING_MASK 0xC0000000L +//SQ_SOPC +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0x000000FFL +#define SQ_SOPC__SSRC1_MASK 0x0000FF00L +#define SQ_SOPC__OP_MASK 0x007F0000L +#define SQ_SOPC__ENCODING_MASK 0xFF800000L +//SQ_SOPK +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPK__SDST_MASK 0x007F0000L +#define SQ_SOPK__OP_MASK 0x0F800000L +#define SQ_SOPK__ENCODING_MASK 0xF0000000L +//SQ_SOPP +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPP__OP_MASK 0x007F0000L +#define SQ_SOPP__ENCODING_MASK 0xFF800000L +//SQ_VINTRP +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define SQ_VINTRP__VSRC_MASK 0x000000FFL +#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L +#define SQ_VINTRP__ATTR_MASK 0x0000FC00L +#define SQ_VINTRP__OP_MASK 0x00030000L +#define SQ_VINTRP__VDST_MASK 0x03FC0000L +#define SQ_VINTRP__ENCODING_MASK 0xFC000000L +//SQ_VOP1 +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_VOP1__SRC0_MASK 0x000001FFL +#define SQ_VOP1__OP_MASK 0x0001FE00L +#define SQ_VOP1__VDST_MASK 0x01FE0000L +#define SQ_VOP1__ENCODING_MASK 0xFE000000L +//SQ_VOP2 +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_VOP2__SRC0_MASK 0x000001FFL +#define SQ_VOP2__VSRC1_MASK 0x0001FE00L +#define SQ_VOP2__VDST_MASK 0x01FE0000L +#define SQ_VOP2__OP_MASK 0x7E000000L +#define SQ_VOP2__ENCODING_MASK 0x80000000L +//SQ_VOP3P_0 +#define SQ_VOP3P_0__VDST__SHIFT 0x0 +#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 +#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe +#define SQ_VOP3P_0__CLAMP__SHIFT 0xf +#define SQ_VOP3P_0__OP__SHIFT 0x10 +#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 +#define SQ_VOP3P_0__VDST_MASK 0x000000FFL +#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L +#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L +#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L +#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3P_0__OP_MASK 0x007F0000L +#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L +//SQ_VOP3P_1 +#define SQ_VOP3P_1__SRC0__SHIFT 0x0 +#define SQ_VOP3P_1__SRC1__SHIFT 0x9 +#define SQ_VOP3P_1__SRC2__SHIFT 0x12 +#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b +#define SQ_VOP3P_1__NEG__SHIFT 0x1d +#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L +#define SQ_VOP3P_1__NEG_MASK 0xE0000000L +//SQ_VOP3_0 +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3_0__CLAMP__SHIFT 0xf +#define SQ_VOP3_0__OP__SHIFT 0x10 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0__VDST_MASK 0x000000FFL +#define SQ_VOP3_0__ABS_MASK 0x00000700L +#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L +#define SQ_VOP3_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0__OP_MASK 0x03FF0000L +#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L +//SQ_VOP3_0_SDST_ENC +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L +//SQ_VOP3_1 +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_VOP3_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3_1__OMOD_MASK 0x18000000L +#define SQ_VOP3_1__NEG_MASK 0xE0000000L +//SQ_VOPC +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VOPC__SRC0_MASK 0x000001FFL +#define SQ_VOPC__VSRC1_MASK 0x0001FE00L +#define SQ_VOPC__OP_MASK 0x01FE0000L +#define SQ_VOPC__ENCODING_MASK 0xFE000000L +//SQ_VOP_DPP +#define SQ_VOP_DPP__SRC0__SHIFT 0x0 +#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 +#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 +#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 +#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 +#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 +#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c +#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL +#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L +#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L +#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L +#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L +#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L +#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L +//SQ_VOP_SDWA +#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 +#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb +#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd +#define SQ_VOP_SDWA__OMOD__SHIFT 0xe +#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA__S0__SHIFT 0x17 +#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA__S1__SHIFT 0x1f +#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L +#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L +#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L +#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L +#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA__S0_MASK 0x00800000L +#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA__S1_MASK 0x80000000L +//SQ_VOP_SDWA_SDST_ENC +#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f +#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L +//SQ_LB_CTR_CTRL +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +//SQ_LB_DATA0 +#define SQ_LB_DATA0__DATA__SHIFT 0x0 +#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA1 +#define SQ_LB_DATA1__DATA__SHIFT 0x0 +#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA2 +#define SQ_LB_DATA2__DATA__SHIFT 0x0 +#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA3 +#define SQ_LB_DATA3__DATA__SHIFT 0x0 +#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL +//SQ_LB_CTR_SEL +#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 +#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 +#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 +#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc +#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL +#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L +#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L +#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L +//SQ_LB_CTR0_CU +#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR1_CU +#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR2_CU +#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR3_CU +#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L +//SQC_EDC_CNT +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L +//SQ_EDC_SEC_CNT +#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL +#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L +#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L +//SQ_EDC_DED_CNT +#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL +#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L +#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L +//SQ_EDC_INFO +#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 +#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 +#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL +#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L +#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L +#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L +//SQ_EDC_CNT +#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 +#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 +#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 +#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 +#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 +#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa +#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc +#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe +#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 +#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 +#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 +#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 +#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 +#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a +#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L +#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL +#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L +#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L +#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L +#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L +#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L +#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L +#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L +#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L +#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L +#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L +#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L +#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L +//SQ_EDC_FUE_CNTL +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_CMN +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L +//SQ_THREAD_TRACE_WORD_EVENT +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L +//SQ_THREAD_TRACE_WORD_INST +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L +//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_ISSUE +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L +//SQ_THREAD_TRACE_WORD_MISC +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L +//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L +//SQ_THREAD_TRACE_WORD_REG_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_WAVE +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L +//SQ_THREAD_TRACE_WORD_WAVE_START +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L +//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL +//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL +//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L +//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL +//SQ_WREXEC_EXEC_HI +#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a +#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b +#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c +#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f +#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L +#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L +#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L +#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L +//SQ_WREXEC_EXEC_LO +#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD1 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L +//SQ_BUF_RSRC_WORD2 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L +#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L +//SQ_IMG_RSRC_WORD0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_RSRC_WORD1 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L +#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L +#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L +//SQ_IMG_RSRC_WORD2 +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L +//SQ_IMG_RSRC_WORD3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L +#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD4 +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L +//SQ_IMG_RSRC_WORD5 +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 +#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L +#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L +#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD6 +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD7 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_SAMP_WORD0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L +//SQ_IMG_SAMP_WORD1 +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L +//SQ_IMG_SAMP_WORD2 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L +//SQ_IMG_SAMP_WORD3 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L +//SQ_FLAT_SCRATCH_WORD0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL +//SQ_FLAT_SCRATCH_WORD1 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL +//SQ_M0_GPR_IDX_WORD +#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe +#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf +#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L +#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L +//SQC_ICACHE_UTCL1_CNTL1 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_ICACHE_UTCL1_CNTL2 +#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_DCACHE_UTCL1_CNTL1 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_DCACHE_UTCL1_CNTL2 +#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_ICACHE_UTCL1_STATUS +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//SQC_DCACHE_UTCL1_STATUS +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L + + +// addressBlock: gc_shsdec +//SX_DEBUG_1 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__PC_CFG__SHIFT 0xd +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L +#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_START_PHASE +#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 +#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 +#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 +#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L +#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL +#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 +#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L +#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_1 +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_6 +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_7 +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_8 +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_9 +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_1 +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_3 +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_5 +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_8 +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_10 +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_12 +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_CU_MASK +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_CU_MASK +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_4 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_5 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_6 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_7 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_HSGS +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_VSPS +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_CS +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L + + +// addressBlock: gc_tpdec +//TD_CNTL +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 +#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18 +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L +#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L +#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_DSM_CNTL +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//TD_DSM_CNTL2 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_CNTL +#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 +#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL +#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L +#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 +#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc +#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd +#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe +#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c +#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d +#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L +#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L +#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L +#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L +#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L +#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L +#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L +//TA_RESERVED_010C +#define TA_RESERVED_010C__Unused__SHIFT 0x0 +#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL +//TA_GRAD_ADJ +#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0 +#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8 +#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10 +#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18 +#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL +#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L +#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L +#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gdsdec +//GDS_CONFIG +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L +//GDS_CNTL_STATUS +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L +//GDS_ENHANCE2 +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 +#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L +//GDS_PROTECTION_FAULT +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_VM_PROTECTION_FAULT +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L +#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_EDC_CNT +#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 +#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 +#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 +#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L +#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL +#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L +//GDS_EDC_GRBM_CNT +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 +#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 +#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L +#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL +#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L +//GDS_EDC_OA_DED +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L +//GDS_DSM_CNTL +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//GDS_EDC_OA_PHY_CNT +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 +#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L +#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L +//GDS_EDC_OA_PIPE_CNT +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe +#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L +#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_DSM_CNTL2 +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L +//GDS_WD_GDS_CSB +#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 +#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd +#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL +#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L + + +// addressBlock: gc_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +//DB_DEBUG2 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__RESERVED__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L +#define DB_DEBUG2__RESERVED_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe +#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L +#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L +//DB_SUBTILE_CONTROL +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_RMI_CACHE_POLICY +#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 +#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 +#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 +#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 +#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 +#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb +#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 +#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 +#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 +#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 +#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 +#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 +#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a +#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b +#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L +#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L +#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L +#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L +#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L +#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L +#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L +#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L +#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L +#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L +#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L +#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L +#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L +#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L +//DB_DFSM_CONFIG +#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 +#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 +#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 +#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L +#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L +#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L +//DB_DFSM_WATERMARK +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L +//DB_DFSM_TILES_IN_FLIGHT +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_PRIMS_IN_FLIGHT +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_WATCHDOG +#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 +#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL +//DB_DFSM_FLUSH_ENABLE +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L +//DB_DFSM_FLUSH_AUX_EVENT +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L +//CC_RB_REDUNDANCY +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L +//GB_ADDR_CONFIG +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//CC_RB_DAISY_CHAIN +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L +//GB_TILE_MODE0 +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE1 +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE2 +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE3 +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE4 +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE5 +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE6 +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE7 +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE8 +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE9 +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE10 +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE11 +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE12 +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE13 +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE14 +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE15 +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE16 +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE17 +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE18 +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE19 +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE20 +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE21 +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE22 +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE23 +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE24 +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE25 +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE26 +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE27 +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE28 +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE29 +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE30 +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE31 +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L +//GB_MACROTILE_MODE0 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE1 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE2 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE4 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE5 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE6 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE7 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE8 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE9 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE10 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE11 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE12 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE13 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE14 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE15 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L +//CB_HW_CONTROL +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L +#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L +//CB_HW_MEM_ARBITER_RD +#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_HW_MEM_ARBITER_WR +#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_DCC_CONFIG +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L +//GC_USER_RB_REDUNDANCY +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L + + +// addressBlock: gc_ea_gceadec2 +//GCEA_EDC_CNT +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//GCEA_EDC_CNT2 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//GCEA_DSM_CNTL +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//GCEA_DSM_CNTLA +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//GCEA_DSM_CNTLB +//GCEA_DSM_CNTL2 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//GCEA_DSM_CNTL2A +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//GCEA_DSM_CNTL2B +//GCEA_TCC_XBR_CREDITS +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L +//GCEA_TCC_XBR_MAXBURST +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 +#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 +#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL +#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L +#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L +//GCEA_PROBE_CNTL +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L +//GCEA_PROBE_MAP +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf +#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L +#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L +//GCEA_ERR_STATUS +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 +#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L +#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L +//GCEA_MISC2 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +//GCEA_SDP_BACKDOOR_CMDCREDITS0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL +//GCEA_SDP_BACKDOOR_CMDCREDITS1 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL +//GCEA_SDP_BACKDOOR_DATACREDITS0 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL +//GCEA_SDP_BACKDOOR_DATACREDITS1 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL +//GCEA_SDP_BACKDOOR_MISCCREDITS +#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL +#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L +//GCEA_SDP_ENABLE +#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L + + +// addressBlock: gc_rmi_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//RMI_UTC_UNIT_CONFIG +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_SPARE +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 +#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 +#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L +#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L +#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 +#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 +#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 +#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 +#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 +#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 +#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 +#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 +#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L +#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L +#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L +#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L +#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L +#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L +#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L +#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L +#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L +#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L + + +// addressBlock: gc_dbgu_gfx_dbgudec +//port_a_addr +#define port_a_addr__Index__SHIFT 0x0 +#define port_a_addr__Reserved__SHIFT 0x8 +#define port_a_addr__ReadEnable__SHIFT 0x1f +#define port_a_addr__Index_MASK 0x000000FFL +#define port_a_addr__Reserved_MASK 0x7FFFFF00L +#define port_a_addr__ReadEnable_MASK 0x80000000L +//port_a_data_lo +#define port_a_data_lo__Data__SHIFT 0x0 +#define port_a_data_lo__Data_MASK 0xFFFFFFFFL +//port_a_data_hi +#define port_a_data_hi__Data__SHIFT 0x0 +#define port_a_data_hi__Data_MASK 0xFFFFFFFFL +//port_b_addr +#define port_b_addr__Index__SHIFT 0x0 +#define port_b_addr__Reserved__SHIFT 0x8 +#define port_b_addr__ReadEnable__SHIFT 0x1f +#define port_b_addr__Index_MASK 0x000000FFL +#define port_b_addr__Reserved_MASK 0x7FFFFF00L +#define port_b_addr__ReadEnable_MASK 0x80000000L +//port_b_data_lo +#define port_b_data_lo__Data__SHIFT 0x0 +#define port_b_data_lo__Data_MASK 0xFFFFFFFFL +//port_b_data_hi +#define port_b_data_hi__Data__SHIFT 0x0 +#define port_b_data_hi__Data_MASK 0xFFFFFFFFL +//port_c_addr +#define port_c_addr__Index__SHIFT 0x0 +#define port_c_addr__Reserved__SHIFT 0x8 +#define port_c_addr__ReadEnable__SHIFT 0x1f +#define port_c_addr__Index_MASK 0x000000FFL +#define port_c_addr__Reserved_MASK 0x7FFFFF00L +#define port_c_addr__ReadEnable_MASK 0x80000000L +//port_c_data_lo +#define port_c_data_lo__Data__SHIFT 0x0 +#define port_c_data_lo__Data_MASK 0xFFFFFFFFL +//port_c_data_hi +#define port_c_data_hi__Data__SHIFT 0x0 +#define port_c_data_hi__Data_MASK 0xFFFFFFFFL +//port_d_addr +#define port_d_addr__Index__SHIFT 0x0 +#define port_d_addr__Reserved__SHIFT 0x8 +#define port_d_addr__ReadEnable__SHIFT 0x1f +#define port_d_addr__Index_MASK 0x000000FFL +#define port_d_addr__Reserved_MASK 0x7FFFFF00L +#define port_d_addr__ReadEnable_MASK 0x80000000L +//port_d_data_lo +#define port_d_data_lo__Data__SHIFT 0x0 +#define port_d_data_lo__Data_MASK 0xFFFFFFFFL +//port_d_data_hi +#define port_d_data_hi__Data__SHIFT 0x0 +#define port_d_data_hi__Data_MASK 0xFFFFFFFFL + + +// addressBlock: gc_utcl2_atcl2dec +//ATC_L2_CNTL +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +//ATC_L2_CNTL2 +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L +//ATC_L2_CACHE_DATA0 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATC_L2_CACHE_DATA1 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA2 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CNTL3 +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L +//ATC_L2_STATUS +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL +//ATC_L2_STATUS2 +#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//ATC_L2_MISC_CG +#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATC_L2_MEM_POWER_LS +#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATC_L2_CGTT_CLK_CTRL +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: gc_utcl2_vml2pfdec +//VM_L2_CNTL +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VM_L2_CNTL2 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_CNTL3 +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_STATUS +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VM_DUMMY_PAGE_FAULT_CNTL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_CNTL +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VM_L2_PROTECTION_FAULT_CNTL2 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_STATUS +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +//VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VM_L2_CNTL4 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +//VM_L2_MM_GROUP_RT_CLASSES +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VM_L2_BANK_SELECT_RESERVED_CID +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_BANK_SELECT_RESERVED_CID2 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_CACHE_PARITY_CNTL +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VM_L2_CGTT_CLK_CTRL +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: gc_utcl2_vml2vcdec +//VM_CONTEXT0_CNTL +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT1_CNTL +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT2_CNTL +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT3_CNTL +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT4_CNTL +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT5_CNTL +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT6_CNTL +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT7_CNTL +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT8_CNTL +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT9_CNTL +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT10_CNTL +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT11_CNTL +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT12_CNTL +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT13_CNTL +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT14_CNTL +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT15_CNTL +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXTS_DISABLE +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_INVALIDATE_ENG0_SEM +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG1_SEM +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG2_SEM +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG3_SEM +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG4_SEM +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG5_SEM +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG6_SEM +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG7_SEM +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG8_SEM +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG9_SEM +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG10_SEM +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG11_SEM +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG12_SEM +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG13_SEM +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG14_SEM +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG15_SEM +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG16_SEM +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG17_SEM +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG0_REQ +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG1_REQ +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG2_REQ +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG3_REQ +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG4_REQ +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG5_REQ +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG6_REQ +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG7_REQ +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG8_REQ +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG9_REQ +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG10_REQ +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG11_REQ +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG12_REQ +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG13_REQ +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG14_REQ +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG15_REQ +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG16_REQ +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG17_REQ +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG0_ACK +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG1_ACK +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG2_ACK +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG3_ACK +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG4_ACK +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG5_ACK +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG6_ACK +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG7_ACK +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG8_ACK +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG9_ACK +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG10_ACK +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG11_ACK +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG12_ACK +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG13_ACK +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG14_ACK +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG15_ACK +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG16_ACK +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG17_ACK +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: gc_utcl2_vmsharedpfdec +//MC_VM_NB_MMIOBASE +#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MC_VM_NB_MMIOLIMIT +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MC_VM_NB_PCI_CTRL +#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MC_VM_NB_PCI_ARB +#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//MC_VM_FB_OFFSET +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MC_VM_STEERING +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MC_SHARED_VIRT_RESET_REQ +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MC_MEM_POWER_LS +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MC_VM_APT_CNTL +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +//MC_VM_LOCAL_HBM_ADDRESS_START +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_END +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L + + +// addressBlock: gc_utcl2_vmsharedvcdec +//MC_VM_FB_LOCATION_BASE +#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MC_VM_FB_LOCATION_TOP +#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_TOP +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_BOT +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MC_VM_AGP_BASE +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_MX_L1_TLB_CNTL +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: gc_ea_gceadec +//GCEA_DRAM_RD_CLI2GRP_MAP0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_CLI2GRP_MAP1 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP1 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_GRP2VC_MAP +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_WR_GRP2VC_MAP +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_RD_LAZY +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//GCEA_DRAM_WR_LAZY +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//GCEA_DRAM_RD_CAM_CNTL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//GCEA_DRAM_WR_CAM_CNTL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//GCEA_DRAM_PAGE_BURST +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_AGE +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_WR_PRI_AGE +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_RD_PRI_QUEUING +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_QUEUING +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_FIXED +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_FIXED +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_URGENCY +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_WR_PRI_URGENCY +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_RD_PRI_QUANT_PRI1 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI2 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI3 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI1 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI2 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI3 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_ADDRNORM_BASE_ADDR0 +#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L +#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L +#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR0 +#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa +#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL +#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L +#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_BASE_ADDR1 +#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 +#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L +#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L +#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_LIMIT_ADDR1 +#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa +#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL +#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L +#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//GCEA_ADDRNORM_OFFSET_ADDR1 +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//GCEA_ADDRNORM_HOLE_CNTL +#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//GCEA_ADDRDEC_BANK_CFG +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL +#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L +#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L +//GCEA_ADDRDEC_MISC_CFG +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L +#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L +#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L +#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L +#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L +//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_PC +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//GCEA_ADDRDECDRAM_ADDR_HASH_PC2 +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL +//GCEA_ADDRDECDRAM_ADDR_HASH_CS0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//GCEA_ADDRDECDRAM_ADDR_HASH_CS1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//GCEA_ADDRDECDRAM_HARVEST_ENABLE +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +//GCEA_ADDRDEC0_BASE_ADDR_CS0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS2 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_CS3 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_CS01 +#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_CS23 +#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC0_ADDR_CFG_CS01 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//GCEA_ADDRDEC0_ADDR_CFG_CS23 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//GCEA_ADDRDEC0_ADDR_SEL_CS01 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC0_ADDR_SEL_CS23 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_LO_CS01 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_LO_CS23 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_HI_CS01 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC0_COL_SEL_HI_CS23 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC0_RM_SEL_CS01 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_CS23 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_SECCS01 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC0_RM_SEL_SECCS23 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_BASE_ADDR_CS0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS2 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_CS3 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_CS01 +#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_CS23 +#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//GCEA_ADDRDEC1_ADDR_CFG_CS01 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//GCEA_ADDRDEC1_ADDR_CFG_CS23 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//GCEA_ADDRDEC1_ADDR_SEL_CS01 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC1_ADDR_SEL_CS23 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_LO_CS01 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_LO_CS23 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_HI_CS01 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC1_COL_SEL_HI_CS23 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//GCEA_ADDRDEC1_RM_SEL_CS01 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_CS23 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_SECCS01 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_ADDRDEC1_RM_SEL_SECCS23 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//GCEA_IO_RD_CLI2GRP_MAP0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_CLI2GRP_MAP1 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP1 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_COMBINE_FLUSH +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//GCEA_IO_WR_COMBINE_FLUSH +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//GCEA_IO_GROUP_BURST +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_IO_RD_PRI_AGE +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_WR_PRI_AGE +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_RD_PRI_QUEUING +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_QUEUING +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_FIXED +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_FIXED +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_URGENCY +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_WR_PRI_URGENCY +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_RD_PRI_URGENCY_MASK +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//GCEA_IO_WR_PRI_URGENCY_MASK +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//GCEA_IO_RD_PRI_QUANT_PRI1 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI2 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI3 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI1 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI2 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI3 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_SDP_ARB_DRAM +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +//GCEA_SDP_ARB_FINAL +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +//GCEA_SDP_DRAM_PRIORITY +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//GCEA_SDP_IO_PRIORITY +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//GCEA_SDP_CREDITS +#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 +#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L +//GCEA_SDP_TAG_RESERVE0 +#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//GCEA_SDP_TAG_RESERVE1 +#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//GCEA_SDP_VCC_RESERVE0 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GCEA_SDP_VCC_RESERVE1 +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GCEA_SDP_VCD_RESERVE0 +#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GCEA_SDP_VCD_RESERVE1 +#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GCEA_SDP_REQ_CNTL +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L +//GCEA_MISC +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//GCEA_LATENCY_SAMPLING +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//GCEA_PERFCOUNTER_LO +#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER_HI +#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCEA_PERFCOUNTER0_CFG +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER1_CFG +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER_RSLT_CNTL +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_tcdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_STATUS__VM_BUSY__SHIFT 0x8 +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L +#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L +#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L +#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L +#define TCP_STATUS__READ_BUSY_MASK 0x00000040L +#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L +#define TCP_STATUS__VM_BUSY_MASK 0x00000100L +//TCP_CNTL +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__L1_SIZE__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L +//TCP_CHAN_STEER_LO +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L +//TCP_CHAN_STEER_HI +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L +#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L +#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L +#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L +#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L +#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L +//TCP_ADDR_CONFIG +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L +//TCP_CREDIT +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L +#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L +//TCP_BUFFER_ADDR_HASH_CNTL +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L +//TCP_EDC_CNT +#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL +#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L +#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L +//TC_CFG_L1_LOAD_POLICY0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_LOAD_POLICY1 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L1_STORE_POLICY +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L +//TC_CFG_L2_LOAD_POLICY0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_LOAD_POLICY1 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY1 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_ATOMIC_POLICY +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_VOLATILE +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL +//TC_CFG_L2_VOLATILE +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL +//TCI_STATUS +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L +//TCI_CNTL_1 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L +//TCI_CNTL_2 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL +//TCC_CTRL +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 +#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 +#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c +#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L +#define TCC_CTRL__RATE_MASK 0x0000000CL +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L +#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L +#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L +#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L +//TCC_CTRL2 +#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 +#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL +//TCC_EDC_CNT +#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 +#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 +#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 +#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 +#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa +#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc +#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe +#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 +#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 +#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14 +#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16 +#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18 +#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a +#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c +#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e +#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L +#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL +#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L +#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L +#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L +#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L +#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L +#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L +#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L +#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L +#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L +#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L +#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L +#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L +#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L +#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L +//TCC_EDC_CNT2 +#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2 +#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4 +#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6 +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8 +#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L +#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL +#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L +#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L +#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L +//TCC_REDUNDANCY +#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 +#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 +#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L +#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L +//TCC_EXE_DISABLE +#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 +#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L +//TCC_DSM_CNTL +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTLA +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTL2 +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCC_DSM_CNTL2A +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L +//TCC_DSM_CNTL2B +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +//TCC_WBINVL2 +#define TCC_WBINVL2__DONE__SHIFT 0x4 +#define TCC_WBINVL2__DONE_MASK 0x00000010L +//TCC_SOFT_RESET +#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 +#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L +//TCA_CTRL +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 +#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL +#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L +#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L +//TCA_BURST_MASK +#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 +#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL +//TCA_BURST_CTRL +#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 +#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3 +#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 +#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 +#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 +#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 +#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8 +#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9 +#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa +#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb +#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc +#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd +#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe +#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L +#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L +#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L +#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L +#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L +#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L +#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L +#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L +#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L +#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L +#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L +#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L +#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L +//TCA_DSM_CNTL +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +//TCA_DSM_CNTL2 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCA_EDC_CNT +#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0 +#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2 +#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L +#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL + + +// addressBlock: gc_shdec +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_VS +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_LATE_ALLOC_VS +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL +//SPI_SHADER_PGM_LO_VS +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_VS +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_VS +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_VS +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_VS_0 +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_1 +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_2 +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_3 +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_4 +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_5 +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_6 +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_7 +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_8 +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_9 +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_10 +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_11 +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_12 +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_13 +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_14 +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_15 +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_16 +#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_17 +#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_18 +#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_19 +#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_20 +#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_21 +#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_22 +#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_23 +#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_24 +#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_25 +#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_26 +#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_27 +#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_28 +#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_29 +#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_30 +#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_31 +#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC2_GS_VS +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_ES_0 +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_1 +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_2 +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_3 +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_4 +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_5 +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_6 +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_7 +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_8 +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_9 +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_10 +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_11 +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_12 +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_13 +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_14 +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_15 +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_16 +#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_17 +#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_18 +#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_19 +#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_20 +#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_21 +#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_22 +#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_23 +#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_24 +#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_25 +#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_26 +#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_27 +#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_28 +#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_29 +#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_30 +#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_31 +#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_LS_0 +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_1 +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_2 +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_3 +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_4 +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_5 +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_6 +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_7 +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_8 +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_9 +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_10 +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_11 +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_12 +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_13 +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_14 +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_15 +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_16 +#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_17 +#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_18 +#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_19 +#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_20 +#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_21 +#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_22 +#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_23 +#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_24 +#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_25 +#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_26 +#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_27 +#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_28 +#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_29 +#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_30 +#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_31 +#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_1 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_2 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_3 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_4 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_5 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_6 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_7 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_8 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_9 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_10 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_11 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_12 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_13 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_14 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_15 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_16 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_17 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_18 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_19 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_20 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_21 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_22 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_23 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_24 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_25 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_26 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_27 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_28 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_29 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_30 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_31 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 +#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L +#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L +#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_cppdec +//CP_DFY_CNTL +#define CP_DFY_CNTL__POLICY__SHIFT 0x0 +#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 +#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_CNTL__POLICY_MASK 0x00000001L +#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL +#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L +#define CP_DFY_CNTL__MODE_MASK 0x60000000L +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L +//CP_DFY_STAT +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L +#define CP_DFY_STAT__BUSY_MASK 0x80000000L +//CP_DFY_ADDR_HI +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_DFY_ADDR_LO +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CP_DFY_DATA_0 +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_1 +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_2 +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_3 +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_4 +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_5 +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_6 +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_7 +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_8 +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_9 +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_10 +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_11 +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_12 +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_13 +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_14 +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_15 +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL +//CP_DFY_CMD +#define CP_DFY_CMD__OFFSET__SHIFT 0x0 +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL +#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 +#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +//CP_GFX_ERROR +#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 +#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f +#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L +#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//GC_PRIV_MODE +//CP_INT_CNTL +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE1_PRIORITY +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING1_PRIORITY +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE2_PRIORITY +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING2_PRIORITY +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_ME0_PIPE1_VMID +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR_HI +#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB2_WPTR +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CP_RB1_BASE +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB1_CNTL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB1_RPTR_ADDR +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB1_RPTR_ADDR_HI +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB2_BASE +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB2_CNTL +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB2_RPTR_ADDR +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB2_RPTR_ADDR_HI +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING1 +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING2 +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING1 +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING2 +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +//CP_MEM_SLP_CNTL +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING1 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING2 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE0_INT_CNTL +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE1_INT_CNTL +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE2_INT_CNTL +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE3_INT_CNTL +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE0_INT_STATUS +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE1_INT_STATUS +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE2_INT_STATUS +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE3_INT_STATUS +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE_PRIORITY_CNTS +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME2_PIPE0_PRIORITY +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE1_PRIORITY +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE2_PRIORITY +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE3_PRIORITY +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_CE_PRGRM_CNTR_START +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_MEC2_PRGRM_CNTR_START +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_CE_INTR_ROUTINE_START +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_MEC2_INTR_ROUTINE_START +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_RB1_BASE_HI +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_MEC1_F32_INT_DIS +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INT_DIS +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L + + +// addressBlock: gc_cppdec2 +//CP_RB_DOORBELL_CONTROL_SCH_0 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_1 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_3 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_4 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_5 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_6 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_7 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 +#define CP_SD_CNTL__WD_EN__SHIFT 0x5 +#define CP_SD_CNTL__IA_EN__SHIFT 0x6 +#define CP_SD_CNTL__PA_EN__SHIFT 0x7 +#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L +#define CP_SD_CNTL__WD_EN_MASK 0x00000020L +#define CP_SD_CNTL__IA_EN_MASK 0x00000040L +#define CP_SD_CNTL__PA_EN_MASK 0x00000080L +#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: gc_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L + + +// addressBlock: gc_cpphqddec +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_SEMA_CMD +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL +#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_didtdec +//DIDT_IND_INDEX +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL +//DIDT_IND_DATA +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gccacdec +//GC_CAC_CTRL_1 +#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 +#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL +#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L +//GC_CAC_CTRL_2 +#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 +#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2 +#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L +#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL +//GC_CAC_CGTT_CLK_CTRL +#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//GC_CAC_AGGR_LOWER +#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 +#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_UPPER +#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 +#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL +//GC_CAC_PG_AGGR_LOWER +#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_PG_AGGR_UPPER +#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_CAC_SOFT_CTRL +#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 +#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 +#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L +#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL +//GC_DIDT_CTRL0 +#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 +#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 +#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L +#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L +//GC_DIDT_CTRL1 +#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 +#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 +#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//GC_DIDT_CTRL2 +#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe +#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a +#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f +#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L +#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L +#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L +//GC_DIDT_WEIGHT +#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 +#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 +#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 +#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 +#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL +#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L +#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L +#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L +//GC_EDC_CTRL +#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 +#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa +#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L +#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L +//GC_EDC_THRESHOLD +#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//GC_EDC_STATUS +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 +#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3 +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L +#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L +//GC_EDC_OVERFLOW +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11 +#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12 +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L +#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L +//GC_EDC_ROLLING_POWER_DELTA +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//GC_DIDT_DROOP_CTRL +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0 +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1 +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf +#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13 +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L +#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L +#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L +//GC_EDC_DROOP_CTRL +#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0 +#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1 +#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf +#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14 +#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15 +#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L +#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL +#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L +#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L +#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L +//GC_CAC_IND_INDEX +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//GC_CAC_IND_DATA +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL +//SE_CAC_CGTT_CLK_CTRL +#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//SE_CAC_IND_INDEX +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//SE_CAC_IND_DATA +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: gc_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L +//TCP_GATCL1_CNTL +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_ATC_EDC_GATCL1_CNT +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL +//TCP_GATCL1_DSM_CNTL +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L +//TCP_CNTL2 +#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 +#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL +//TCP_UTCL1_CNTL1 +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_UTCL1_CNTL2 +#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//TCP_UTCL1_STATUS +#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 +#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L +#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L +#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L + + +// addressBlock: gc_gdspdec +//GDS_VMID0_BASE +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID0_SIZE +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID1_BASE +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID1_SIZE +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID2_BASE +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID2_SIZE +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID3_BASE +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID3_SIZE +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID4_BASE +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID4_SIZE +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID5_BASE +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID5_SIZE +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID6_BASE +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID6_SIZE +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID7_BASE +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID7_SIZE +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID8_BASE +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID8_SIZE +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID9_BASE +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID9_SIZE +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID10_BASE +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID10_SIZE +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID11_BASE +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID11_SIZE +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID12_BASE +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID12_SIZE +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID13_BASE +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID13_SIZE +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID14_BASE +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID14_SIZE +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID15_BASE +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID15_SIZE +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_GWS_VMID0 +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID1 +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID2 +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID3 +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID4 +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID5 +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID6 +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID7 +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID8 +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID9 +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID10 +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID11 +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID12 +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID13 +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID14 +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID15 +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L +//GDS_OA_VMID0 +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID1 +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID2 +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID3 +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID4 +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID5 +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID6 +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID7 +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID8 +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID9 +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID10 +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID11 +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID12 +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID13 +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID14 +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID15 +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L +//GDS_GWS_RESET0 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L +//GDS_GWS_RESET1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L +//GDS_GWS_RESOURCE_RESET +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GDS_OA_RESET_MASK +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L +//GDS_OA_RESET +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_OA_RESET__RESET_MASK 0x00000001L +#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L +//GDS_ENHANCE +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 +#define GDS_ENHANCE__UNUSED__SHIFT 0x16 +#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L +#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L +#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L +//GDS_OA_CGPG_RESTORE +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L +//GDS_CS_CTXSW_STATUS +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_CS_CTXSW_CNT0 +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT1 +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT2 +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT3 +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GFX_CTXSW_STATUS +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_VS_CTXSW_CNT0 +#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT1 +#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT2 +#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT3 +#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT0 +#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT1 +#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT2 +#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT3 +#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT0 +#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT1 +#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT2 +#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT3 +#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT0 +#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT1 +#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT2 +#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT3 +#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT0 +#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT1 +#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT2 +#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT3 +#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT0 +#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT1 +#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT2 +#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT3 +#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT0 +#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT1 +#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT2 +#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT3 +#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT0 +#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT1 +#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT2 +#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT3 +#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT0 +#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT1 +#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT2 +#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT3 +#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT0 +#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT1 +#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT2 +#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT3 +#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L + + +// addressBlock: gc_rasdec +//RAS_SIGNATURE_CONTROL +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L +//RAS_SIGNATURE_MASK +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE0 +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE1 +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE2 +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE3 +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_DB_SIGNATURE0 +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_PA_SIGNATURE0 +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_VGT_SIGNATURE0 +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SQ_SIGNATURE0 +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE0 +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE1 +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE2 +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE3 +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE4 +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE5 +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE6 +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE7 +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_IA_SIGNATURE0 +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_IA_SIGNATURE1 +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SPI_SIGNATURE0 +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SPI_SIGNATURE1 +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TA_SIGNATURE0 +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TD_SIGNATURE0 +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_CB_SIGNATURE0 +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_BCI_SIGNATURE0 +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_BCI_SIGNATURE1 +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TA_SIGNATURE1 +#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL + + +// addressBlock: gc_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +//DB_HTILE_DATA_BASE +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_HTILE_DATA_BASE_HI +#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DEPTH_SIZE +#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL +#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_STENCIL_CLEAR +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL +//DB_DEPTH_CLEAR +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_Z_INFO__MAXMIP__SHIFT 0x10 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DFSM_CONTROL +#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 +#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L +//DB_RENDER_FILTER +#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0 +#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL +//DB_Z_INFO2 +#define DB_Z_INFO2__EPITCH__SHIFT 0x0 +#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL +//DB_STENCIL_INFO2 +#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 +#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL +//TA_BC_BASE_ADDR +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_BC_BASE_ADDR_HI +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 +#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L +#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//PA_SC_RIGHT_VERT_GRID +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_LEFT_VERT_GRID +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_HORIZ_GRID +#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 +#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 +#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 +#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 +#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL +#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L +#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L +#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L +//PA_SC_FOV_WINDOW_LR +#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0 +#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8 +#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10 +#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18 +#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL +#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L +#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L +#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L +//PA_SC_FOV_WINDOW_TB +#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0 +#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8 +#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL +#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//CB_DCC_CONTROL +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_STENCILREFMASK +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L +//DB_STENCILREFMASK_BF +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_VS_OUT_CONFIG +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//SX_PS_DOWNCONVERT +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL +#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L +#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L +#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L +#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L +#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L +#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L +//SX_BLEND_OPT_EPSILON +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L +//SX_BLEND_OPT_CONTROL +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L +//SX_MRT0_BLEND_OPT +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT1_BLEND_OPT +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT2_BLEND_OPT +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT3_BLEND_OPT +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT4_BLEND_OPT +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT5_BLEND_OPT +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT6_BLEND_OPT +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT7_BLEND_OPT +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_MRT0_EPITCH +#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT1_EPITCH +#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT2_EPITCH +#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT3_EPITCH +#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT4_EPITCH +#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT5_EPITCH +#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT6_EPITCH +#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT7_EPITCH +#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL +//CS_COPY_STATE +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +//DB_EQAA +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L +//PA_CL_OBJPRIM_ID_CNTL +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +//VGT_OUTPUT_PATH_CNTL +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L +//VGT_HOS_CNTL +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_REUSE_DEPTH +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL +//VGT_GROUP_PRIM_TYPE +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L +//VGT_GROUP_FIRST_DECR +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL +//VGT_GROUP_DECR +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL +//VGT_GROUP_VECT_0_CNTL +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_1_CNTL +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_0_FMT_CNTL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GROUP_VECT_1_FMT_CNTL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GS_MODE +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe +#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf +#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_MODE__MODE_MASK 0x00000007L +#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L +#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L +#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L +#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L +#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L +#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L +#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L +#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L +//VGT_GS_ONCHIP_CNTL +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_GS_PER_ES +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL +//VGT_ES_PER_GS +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL +//VGT_GS_PER_VS +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL +//VGT_GSVS_RING_OFFSET_1 +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_2 +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_3 +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L +//IA_ENHANCE +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +//WD_ENHANCE +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_GS_MAX_PRIMS_PER_SUBGROUP +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L +//VGT_INDEX_PAYLOAD_CNTL +#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0 +#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L +//VGT_INSTANCE_STEP_RATE_0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL +//VGT_INSTANCE_STEP_RATE_1 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL +//VGT_ESGS_RING_ITEMSIZE +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GSVS_RING_ITEMSIZE +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//VGT_VTX_CNT_EN +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 +#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L +#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +//DB_PRELOAD_CONTROL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L +//VGT_STRMOUT_BUFFER_SIZE_0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_1 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_1 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_1 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_2 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_2 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_2 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_3 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_3 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_3 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L +//VGT_GS_VERT_ITEMSIZE +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_1 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_2 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_3 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L +#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//VGT_DISPATCH_DRAW_INDEX +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL +//VGT_STRMOUT_CONFIG +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L +//VGT_STRMOUT_BUFFER_CONFIG +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L +//VGT_DMA_EVENT_INITIATOR +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +//VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL +//VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR0_DCC_CONTROL +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR0_CMASK +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_CMASK_BASE_EXT +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_FMASK +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_FMASK_BASE_EXT +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_CLEAR_WORD0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR0_CLEAR_WORD1 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE_EXT +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR1_DCC_CONTROL +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR1_CMASK +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_CMASK_BASE_EXT +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_FMASK +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_FMASK_BASE_EXT +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_CLEAR_WORD0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR1_CLEAR_WORD1 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE_EXT +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR2_DCC_CONTROL +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR2_CMASK +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_CMASK_BASE_EXT +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_FMASK +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_FMASK_BASE_EXT +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_CLEAR_WORD0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR2_CLEAR_WORD1 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE_EXT +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR3_DCC_CONTROL +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR3_CMASK +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_CMASK_BASE_EXT +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_FMASK +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_FMASK_BASE_EXT +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_CLEAR_WORD0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR3_CLEAR_WORD1 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE_EXT +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR4_DCC_CONTROL +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR4_CMASK +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_CMASK_BASE_EXT +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_FMASK +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_FMASK_BASE_EXT +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_CLEAR_WORD0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR4_CLEAR_WORD1 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE_EXT +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR5_DCC_CONTROL +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR5_CMASK +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_CMASK_BASE_EXT +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_FMASK +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_FMASK_BASE_EXT +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_CLEAR_WORD0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR5_CLEAR_WORD1 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE_EXT +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR6_DCC_CONTROL +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR6_CMASK +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_CMASK_BASE_EXT +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_FMASK +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_FMASK_BASE_EXT +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_CLEAR_WORD0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR6_CLEAR_WORD1 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE_EXT +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR7_DCC_CONTROL +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +//CB_COLOR7_CMASK +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_CMASK_BASE_EXT +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_FMASK +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_FMASK_BASE_EXT +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_CLEAR_WORD0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR7_CLEAR_WORD1 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE_EXT +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL + + +// addressBlock: gc_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_STREAM_OUT_ADDR_LO +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL +//CP_STREAM_OUT_ADDR_HI +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_LO +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_HI +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_LO +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_HI +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_LO +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_HI +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_LO +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_HI +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_LO +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_HI +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_LO +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_HI +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_LO +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_HI +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_LO +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_HI +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STREAM_OUT_CONTROL +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STRMOUT_CNTL +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//SCRATCH_UMSK +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L +//SCRATCH_ADDR +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_LO +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_HI +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_LO +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_HI +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_LO +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_LO +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_HI +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_HI +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_LO +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_LO +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_HI +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_HI +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_SEM_WAIT_TIMER +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL +//CP_SIG_SEM_ADDR_LO +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_SIG_SEM_ADDR_HI +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_WAIT_SEM_ADDR_LO +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_WAIT_SEM_ADDR_HI +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_COHER_BASE_HI +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_COHER_START_DELAY +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL +//CP_COHER_CNTL +#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 +#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e +#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L +#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L +//CP_COHER_SIZE +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_COHER_BASE +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_COHER_STATUS +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_COHER_STATUS__MEID_MASK 0x03000000L +#define CP_COHER_STATUS__STATUS_MASK 0x80000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_COHER_SIZE_HI +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB1_OFFSET +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_BEGIN +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_END +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_CE_IB1_OFFSET +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_CE_IB2_OFFSET +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_CE_COUNTER +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_RB_OFFSET +#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_CE_INIT_CMD_BUFSZ +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL +//CP_CE_IB1_CMD_BUFSZ +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_IB2_CMD_BUFSZ +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_INIT_BASE_LO +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L +//CP_CE_INIT_BASE_HI +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL +//CP_CE_INIT_BUFSZ +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL +//CP_CE_IB1_BASE_LO +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB1_BASE_HI +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB1_BUFSZ +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_CE_IB2_BASE_LO +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB2_BASE_HI +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB2_BUFSZ +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_IB1_BASE_LO +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB1_BASE_HI +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_CE_COMPLETION_STATUS +#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_CE_METADATA_BASE_ADDR +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_CE_METADATA_BASE_ADDR_HI +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_GDS_BKUP_ADDR +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_GDS_BKUP_ADDR_HI +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//VGT_GSVS_RING_SIZE +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//VGT_MULTI_PRIM_IB_RESET_EN +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_POS_BUF_BASE +#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 +#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_POS_BUF_BASE_HI +#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_CNTL_SB_BUF_BASE +#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_CNTL_SB_BUF_BASE_HI +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_INDEX_BUF_BASE +#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 +#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_INDEX_BUF_BASE_HI +#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//IA_MULTI_VGT_PARAM +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L +//VGT_OBJECT_ID +#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0 +#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_BASE +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_SIZE +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L +//SQ_THREAD_TRACE_PERF_MASK +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L +//SQ_THREAD_TRACE_MODE +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L +//SQ_THREAD_TRACE_BASE2 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL +//SQ_THREAD_TRACE_TOKEN_MASK2 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L +//SQ_THREAD_TRACE_HIWATER +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L +//SQ_THREAD_TRACE_CNTR +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__WRITEBACK__SHIFT 0x3 +#define SQC_CACHES__VOL__SHIFT 0x4 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__WRITEBACK_MASK 0x00000008L +#define SQC_CACHES__VOL_MASK 0x00000010L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//SQC_WRITEBACK +#define SQC_WRITEBACK__DWB__SHIFT 0x0 +#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 +#define SQC_WRITEBACK__DWB_MASK 0x00000001L +#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L +//TA_CS_BC_BASE_ADDR +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_CS_BC_BASE_ADDR_HI +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//TA_GRAD_ADJ_UCONFIG +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0 +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8 +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10 +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18 +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L +#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_ZPASS_COUNT_LOW +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_ZPASS_COUNT_HI +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL +//GDS_RD_ADDR +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_DATA +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL +//GDS_RD_BURST_ADDR +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_BURST_COUNT +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL +//GDS_RD_BURST_DATA +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL +//GDS_WR_ADDR +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_DATA +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WR_BURST_ADDR +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_BURST_DATA +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WRITE_COMPLETE +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL +//GDS_ATOM_CNTL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L +//GDS_ATOM_COMPLETE +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL +//GDS_ATOM_BASE +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL +#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_SIZE +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL +#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_OFFSET0 +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_OFFSET1 +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_DST +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL +//GDS_ATOM_OP +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OP__OP_MASK 0x000000FFL +#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_SRC0 +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC0_U +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1 +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1_U +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0 +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0_U +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1 +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1_U +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL +//GDS_GWS_RESOURCE_CNTL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L +//GDS_GWS_RESOURCE +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd +#define GDS_GWS_RESOURCE__DED__SHIFT 0xe +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d +#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L +#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L +#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L +//GDS_GWS_RESOURCE_CNT +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_OA_CNTL +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL +#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L +//GDS_OA_COUNTER +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL +//GDS_OA_ADDRESS +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL +#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L +//GDS_OA_INCDEC +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L +//GDS_OA_RING_SIZE +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L + + +// addressBlock: gc_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_LO +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_HI +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_LO +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_HI +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_LO +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_HI +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_LO +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_HI +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_LO +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_HI +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_LO +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_HI +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_LO +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_HI +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_LO +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_HI +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_LO +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_HI +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_LO +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_HI +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_LO +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_HI +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_LO +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_HI +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_LO +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_LO +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_LO +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_LO +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_HI +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_HI +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_HI +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_HI +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_LO +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_HI +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_LO +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_HI +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_LO +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_HI +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_LO +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_HI +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_LO +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_HI +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_LO +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_HI +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_LO +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_HI +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_LO +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_HI +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_LO +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_HI +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_LO +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_HI +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_LO +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_HI +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_LO +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_HI +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_LO +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_HI +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_LO +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_HI +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_LO +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_HI +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_LO +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_HI +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_LO +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_HI +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_LO +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_HI +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_LO +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_HI +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_LO +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_HI +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: gc_utcl2_atcl2pfcntrdec +//ATC_L2_PERFCOUNTER_LO +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_L2_PERFCOUNTER_HI +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_utcl2_vml2prdec +//MC_VM_L2_PERFCOUNTER_LO +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_L2_PERFCOUNTER_HI +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: gc_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_SE0_PERFCOUNTER_SELECT +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE1_PERFCOUNTER_SELECT +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE2_PERFCOUNTER_SELECT +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE3_PERFCOUNTER_SELECT +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//WD_PERFCOUNTER0_SELECT +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER1_SELECT +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER2_SELECT +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER3_SELECT +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER1_SELECT +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER2_SELECT +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER3_SELECT +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT1 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT1 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT1 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER_SEID_MASK +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L +//SQ_PERFCOUNTER_MASK +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L +//GDS_PERFCOUNTER0_SELECT +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +//GDS_PERFCOUNTER1_SELECT +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +//GDS_PERFCOUNTER2_SELECT +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +//GDS_PERFCOUNTER3_SELECT +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +//GDS_PERFCOUNTER0_SELECT1 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT1 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT1 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER2_SELECT +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER3_SELECT +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT1 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT1 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER2_SELECT +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER3_SELECT +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_DB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_IA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TD_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SX_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL +//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_PERFMON_CLK_CNTL +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L + + +// addressBlock: gc_utcl2_atcl2pfcntldec +//ATC_L2_PERFCOUNTER0_CFG +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER1_CFG +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_utcl2_vml2pldec +//MC_VM_L2_PERFCOUNTER0_CFG +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER1_CFG +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER2_CFG +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER3_CFG +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER4_CFG +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER5_CFG +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER6_CFG +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER7_CFG +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: gc_rlcpdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__RESERVED__SHIFT 0x4 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RESERVED__SHIFT 0x8 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//SMU_RLC_RESPONSE +#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 +#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SMU_SAFE_MODE +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L +//RLC_LB_CNTR_MAX +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4 +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK_1 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L +//RLC_SERDES_NONCU_MASTER_BUSY_1 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_LB_CNTL +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L +#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L +//RLC_LB_CNTR_INIT +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL +//RLC_LOAD_BALANCE_CNTR +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_FIREWALL_VIOLATION +#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 +#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__RESERVED__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_CU_STATUS +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL +//RLC_LB_INIT_CU_MASK +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_ALWAYS_ACTIVE_CU_MASK +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_PARAMS +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_THREAD1_DELAY +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L +#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L +//RLC_PG_ALWAYS_ON_CU_MASK +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_CU +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL +#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SMU_GRBM_REG_SAVE_CTRL +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL +//RLC_SERDES_RD_MASTER_INDEX +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_CU_MASTER_MASK +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L +//RLC_SERDES_WR_CTRL +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf +#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L +#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L +#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L +//RLC_SERDES_WR_DATA +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_CU_MASTER_BUSY +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL +//RLC_SERDES_NONCU_MASTER_BUSY +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_MESSAGE +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL +//RLC_GPM_LOG_SIZE +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL +#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_LOG_CONT +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH1 +#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH1 +#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L +#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_RLCV_COMMAND +#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 +#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL +#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L +#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L +#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_RLCV_COMMAND_STATUS +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_SMU_COMMAND +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 +#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L +#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L +//RLC_SMU_ARGUMENT_1 +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_2 +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_1 +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L +//RLC_GPM_UTCL1_CNTL_2 +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L +//RLC_LB_THR_CONFIG_2 +#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_3 +#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_4 +#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_LB_THR_CONFIG_1 +#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH1_ERROR_1 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH1_ERROR_2 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH2_ERROR_1 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH2_ERROR_2 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_CGCG_CGLS_CTRL_3D +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL_3D +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNT +#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL +//RLC_SPARE_INT +#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_PREWALKER_UTCL1_CNTL +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L +//RLC_PREWALKER_UTCL1_TRIG +#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 +#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f +#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L +#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L +#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L +//RLC_PREWALKER_UTCL1_ADDR_LSB +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_ADDR_MSB +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL +//RLC_PREWALKER_UTCL1_SIZE_LSB +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_SIZE_MSB +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L +//RLC_DSM_TRIG +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_UTCL2_CNTL +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_LBPW_CU_STAT +#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 +#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 +#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL +#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L +//RLC_DS_CNTL +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 +#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 +#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L +#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L +#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: gc_pwrdec +//CGTS_SM_CTRL_REG +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L +//CGTS_RD_CTRL_REG +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L +//CGTS_RD_REG +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL +//CGTS_TCC_DISABLE +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_USER_TCC_DISABLE +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_CU0_SP0_CTRL_REG +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_LDS_SQ_CTRL_REG +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TA_SQC_CTRL_REG +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_SP1_CTRL_REG +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TD_TCP_CTRL_REG +#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_SP0_CTRL_REG +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_LDS_SQ_CTRL_REG +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_TA_SQC_CTRL_REG +#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU1_SP1_CTRL_REG +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_TD_TCP_CTRL_REG +#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_SP0_CTRL_REG +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_LDS_SQ_CTRL_REG +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_TA_SQC_CTRL_REG +#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU2_SP1_CTRL_REG +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_TD_TCP_CTRL_REG +#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_SP0_CTRL_REG +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_LDS_SQ_CTRL_REG +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_TA_SQC_CTRL_REG +#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_SP1_CTRL_REG +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_TD_TCP_CTRL_REG +#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_SP0_CTRL_REG +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_LDS_SQ_CTRL_REG +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_TA_SQC_CTRL_REG +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU4_SP1_CTRL_REG +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_TD_TCP_CTRL_REG +#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_SP0_CTRL_REG +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_LDS_SQ_CTRL_REG +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_TA_SQC_CTRL_REG +#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU5_SP1_CTRL_REG +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_TD_TCP_CTRL_REG +#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP0_CTRL_REG +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_LDS_SQ_CTRL_REG +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_TA_SQC_CTRL_REG +#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP1_CTRL_REG +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_TD_TCP_CTRL_REG +#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_SP0_CTRL_REG +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_LDS_SQ_CTRL_REG +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_TA_SQC_CTRL_REG +#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU7_SP1_CTRL_REG +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_TD_TCP_CTRL_REG +#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_SP0_CTRL_REG +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_LDS_SQ_CTRL_REG +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_TA_SQC_CTRL_REG +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU8_SP1_CTRL_REG +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_TD_TCP_CTRL_REG +#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_SP0_CTRL_REG +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_LDS_SQ_CTRL_REG +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_TA_SQC_CTRL_REG +#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_SP1_CTRL_REG +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_TD_TCP_CTRL_REG +#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_SP0_CTRL_REG +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_LDS_SQ_CTRL_REG +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_TA_SQC_CTRL_REG +#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU10_SP1_CTRL_REG +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_TD_TCP_CTRL_REG +#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_SP0_CTRL_REG +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_LDS_SQ_CTRL_REG +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_TA_SQC_CTRL_REG +#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU11_SP1_CTRL_REG +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_TD_TCP_CTRL_REG +#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP0_CTRL_REG +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_LDS_SQ_CTRL_REG +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_TA_SQC_CTRL_REG +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP1_CTRL_REG +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_TD_TCP_CTRL_REG +#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_SP0_CTRL_REG +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_LDS_SQ_CTRL_REG +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_TA_SQC_CTRL_REG +#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU13_SP1_CTRL_REG +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_TD_TCP_CTRL_REG +#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_SP0_CTRL_REG +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_LDS_SQ_CTRL_REG +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_TA_SQC_CTRL_REG +#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU14_SP1_CTRL_REG +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_TD_TCP_CTRL_REG +#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_SP0_CTRL_REG +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_LDS_SQ_CTRL_REG +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_TA_SQC_CTRL_REG +#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_SP1_CTRL_REG +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_TD_TCP_CTRL_REG +#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TCPI_CTRL_REG +#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU1_TCPI_CTRL_REG +#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU2_TCPI_CTRL_REG +#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU3_TCPI_CTRL_REG +#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU4_TCPI_CTRL_REG +#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU5_TCPI_CTRL_REG +#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU6_TCPI_CTRL_REG +#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU7_TCPI_CTRL_REG +#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU8_TCPI_CTRL_REG +#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU9_TCPI_CTRL_REG +#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU10_TCPI_CTRL_REG +#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU11_TCPI_CTRL_REG +#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU12_TCPI_CTRL_REG +#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU13_TCPI_CTRL_REG +#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU14_TCPI_CTRL_REG +#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU15_TCPI_CTRL_REG +#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTT_SPI_CLK_CTRL +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PC_CLK_CTRL +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_BCI_CLK_CTRL +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_VGT_CLK_CTRL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a +#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L +#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_IA_CLK_CTRL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_WD_CLK_CTRL +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L +#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SQ_CLK_CTRL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_POWER_THROTTLE +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L +//SQ_POWER_THROTTLE2 +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L +//CGTT_SX_CLK_CTRL0 +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL1 +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL2 +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL3 +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_SX_CLK_CTRL4 +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L +//TD_CGTT_CTRL +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TA_CGTT_CTRL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCPI_CLK_CTRL +#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCI_CLK_CTRL +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_GDS_CLK_CTRL +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L +//CB_CGTT_SCLK_CTRL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCC_CGTT_SCLK_CTRL +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCA_CGTT_SCLK_CTRL +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPF_CLK_CTRL +#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//RLC_PWR_CTRL +#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0 +#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1 +#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8 +#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L +#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL +#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//RLC_GFX_RM_CNTL +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 +#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L +#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RMI_CGTT_SCLK_CTRL +#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCPF_CLK_CTRL +#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L + + +// addressBlock: gc_ea_pwrdec +//GCEA_CGTT_CLK_CTRL +#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L + + +// addressBlock: gc_utcl2_vmsharedhvdec +//MC_VM_FB_SIZE_OFFSET_VF0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF1 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF2 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF3 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF4 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF5 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF6 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF7 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF8 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF9 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF11 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF12 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF13 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF14 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF15 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//VM_IOMMU_MMIO_CNTRL_1 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L +//MC_VM_MARC_BASE_LO_0 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_1 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_2 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_3 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_HI_0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_1 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_2 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_3 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_LO_0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_2 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_3 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_HI_0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_1 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_2 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_3 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_LO_0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_1 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_2 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_3 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_HI_0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_1 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_2 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_3 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VM_IOMMU_CONTROL_REGISTER +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//VM_PCIE_ATS_CNTL +#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_0 +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_1 +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_2 +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_3 +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_4 +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_5 +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_6 +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_7 +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_8 +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_9 +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_10 +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_11 +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_12 +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_13 +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_14 +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_15 +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//UTCL2_CGTT_CLK_CTRL +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: gc_hypdec +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_CE_UCODE_ADDR +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_HYP_CE_UCODE_ADDR +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_CE_UCODE_DATA +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_CE_UCODE_DATA +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC2_UCODE_ADDR +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME2_UCODE_ADDR +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC2_UCODE_DATA +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME2_UCODE_DATA +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_HYP_CAM_INDEX +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_HYP_CAM_DATA +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_GFX_RM_CNTL_ADJ +#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0 +#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1 +#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L +#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_0 +#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_CTRL +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_TIMER_STAT +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_ACTIVE_FCN_ID +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_UCODE_ADDR +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_GPU_IOV_UCODE_DATA +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCRATCH_ADDR +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPU_IOV_SCRATCH_DATA +#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_F32_CNTL +#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_F32_RESET +#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 +#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L +#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SMU_RESPONSE +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VIRT_RESET_REQ +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_DISABLE +#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_FORCE +#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: gccacind +//GC_CAC_CNTL +#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 +#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 +#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 +#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f +#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL +#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L +#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L +#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L +//GC_CAC_OVR_SEL +#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 +#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL +#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 +#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_BCI_0 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CB_0 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CB_1 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_1 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_DB_0 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_DB_1 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GDS_1 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_IA_0 +#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_LDS_0 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_LDS_1 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PA_0 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_PC_0 +#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SC_0 +#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SPI_0 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SPI_1 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SPI_2 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_0 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_1 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_2 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_3 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SQ_4 +#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SX_0 +#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SXRB_0 +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TA_0 +#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCC_0 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCC_1 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCC_2 +#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCP_0 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCP_1 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TCP_2 +#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TD_0 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TD_1 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_TD_2 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_VGT_0 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_VGT_1 +#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_WD_0 +#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10 +#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_1 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_2 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_3 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_4 +#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CU_5 +#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L +//GC_CAC_ACC_BCI0 +#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB0 +#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB1 +#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB2 +#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CB3 +#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP1 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CP2 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB0 +#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB1 +#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB2 +#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_DB3 +#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS1 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS2 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_GDS3 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_IA0 +#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS0 +#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS1 +#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS2 +#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_LDS3 +#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PA0 +#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PA1 +#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_PC0 +#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SC0 +#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI0 +#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI1 +#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI2 +#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI3 +#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI4 +#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SPI5 +#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_PG_0 +#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10 +#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L +//GC_CAC_ACC_PG0 +#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_PG +#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10 +#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL +#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ATCL2_0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L +//GC_CAC_ACC_EA0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA1 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA2 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA3 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL20 +#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_EA +#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_UTCL2_ATCL2 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_WEIGHT_EA_0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_EA_1 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_RMI_0 +#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10 +#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L +//GC_CAC_ACC_RMI0 +#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_RMI +#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_WEIGHT_UTCL2_ATCL2_1 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L +//GC_CAC_ACC_UTCL2_ATCL21 +#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL22 +#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ATCL23 +#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA4 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_EA5 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_EA_2 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L +//GC_CAC_ACC_SQ0_LOWER +#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ0_UPPER +#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ1_LOWER +#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ1_UPPER +#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ2_LOWER +#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ2_UPPER +#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ3_LOWER +#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ3_UPPER +#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ4_LOWER +#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ4_UPPER +#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ5_LOWER +#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ5_UPPER +#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ6_LOWER +#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ6_UPPER +#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ7_LOWER +#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ7_UPPER +#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SQ8_LOWER +#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SQ8_UPPER +#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 +#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 +#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL +#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L +//GC_CAC_ACC_SX0 +#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SXRB0 +#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_SXRB1 +#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TA0 +#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC0 +#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC1 +#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC2 +#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC3 +#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCC4 +#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP0 +#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP1 +#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP2 +#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP3 +#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TCP4 +#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD0 +#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD1 +#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD2 +#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD3 +#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD4 +#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_TD5 +#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT0 +#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT1 +#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_VGT2 +#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_WD0 +#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU0 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU1 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU2 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU3 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU4 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU5 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU6 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU7 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU8 +#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU9 +#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_CU10 +#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_BCI +#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 +#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L +#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL +//GC_CAC_OVRD_CB +#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_CP +#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 +#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L +#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L +//GC_CAC_OVRD_DB +#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_GDS +#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_IA +#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_LDS +#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 +#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL +#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L +//GC_CAC_OVRD_PA +#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 +#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L +#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL +//GC_CAC_OVRD_PC +#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SC +#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SPI +#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_CU +#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SQ +#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 +#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL +#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L +//GC_CAC_OVRD_SX +#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_SXRB +#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_TA +#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_OVRD_TCC +#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_OVRD_TCP +#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_OVRD_TD +#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 +#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL +#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L +//GC_CAC_OVRD_VGT +#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 +#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L +#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L +//GC_CAC_OVRD_WD +#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 +#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L +#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L +//GC_CAC_ACC_BCI1 +#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_WEIGHT_UTCL2_ATCL2_2 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_1 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_2 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_3 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_ROUTER_4 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_1 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_VML2_2 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L +//GC_CAC_ACC_UTCL2_ATCL24 +#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER1 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER2 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER3 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER4 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER5 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER6 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER7 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER8 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_ROUTER9 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML20 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML21 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML22 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML23 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_VML24 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_UTCL2_ROUTER +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL +#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L +//GC_CAC_OVRD_UTCL2_VML2 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L +//GC_CAC_WEIGHT_UTCL2_WALKER_0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_1 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_UTCL2_WALKER_2 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L +//GC_CAC_ACC_UTCL2_WALKER0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER1 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER2 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER3 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_ACC_UTCL2_WALKER4 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_OVRD_UTCL2_WALKER +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL +#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L + + +// addressBlock: secacind +//SE_CAC_CNTL +#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 +#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 +#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 +#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 +#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f +#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L +#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL +#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L +#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L +#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L +//SE_CAC_OVR_SEL +#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 +#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL +//SE_CAC_OVR_VAL +#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 +#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL + + +// addressBlock: sqind +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 +#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a +#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L +#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L +#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L +#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +//SQ_WAVE_TRAPSTS +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb +#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L +#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L +#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L +#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L +#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L +#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf +#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 +#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L +#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L +#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L +#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL +//SQ_WAVE_INST_DW0 +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL +//SQ_WAVE_INST_DW1 +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL +//SQ_WAVE_IB_DBG0 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 +#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 +#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 +#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb +#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L +#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L +#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L +#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L +#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP2 +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL +//SQ_INTERRUPT_WORD_AUTO_CTXID +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_AUTO_HI +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_AUTO_LO +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L +//SQ_INTERRUPT_WORD_CMN_CTXID +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_CMN_HI +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_CTXID +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_WAVE_HI +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_LO +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L + + + + + + + + +// addressBlock: didtind +//DIDT_SQ_CTRL0 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L +//DIDT_SQ_CTRL1 +#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_SQ_CTRL2 +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L +//DIDT_SQ_STALL_CTRL +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18 +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L +//DIDT_SQ_TUNING_CTRL +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_SQ_STALL_AUTO_RELEASE_CTRL +#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_SQ_CTRL3 +#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_SQ_STALL_PATTERN_1_2 +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_STALL_PATTERN_3_4 +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_STALL_PATTERN_5_6 +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_STALL_PATTERN_7 +#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_SQ_WEIGHT0_3 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_SQ_WEIGHT4_7 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_SQ_WEIGHT8_11 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_SQ_EDC_CTRL +#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17 +#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L +//DIDT_SQ_EDC_THRESHOLD +#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_SQ_EDC_STALL_PATTERN_1_2 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_EDC_STALL_PATTERN_3_4 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_EDC_STALL_PATTERN_5_6 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_SQ_EDC_STALL_PATTERN_7 +#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_SQ_EDC_STATUS +#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_SQ_EDC_STALL_DELAY_1 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 +#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L +#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L +#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L +//DIDT_SQ_EDC_STALL_DELAY_2 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 +#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L +#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L +#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L +//DIDT_SQ_EDC_STALL_DELAY_3 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc +#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L +#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L +#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L +//DIDT_SQ_EDC_OVERFLOW +#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_SQ_EDC_ROLLING_POWER_DELTA +#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_DB_CTRL0 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b +#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L +//DIDT_DB_CTRL1 +#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_DB_CTRL2 +#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L +//DIDT_DB_STALL_CTRL +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18 +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L +//DIDT_DB_TUNING_CTRL +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_DB_STALL_AUTO_RELEASE_CTRL +#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_DB_CTRL3 +#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_DB_STALL_PATTERN_1_2 +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_DB_STALL_PATTERN_3_4 +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_DB_STALL_PATTERN_5_6 +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_DB_STALL_PATTERN_7 +#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_DB_WEIGHT0_3 +#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_DB_WEIGHT4_7 +#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_DB_WEIGHT8_11 +#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_DB_EDC_CTRL +#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17 +#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L +//DIDT_DB_EDC_THRESHOLD +#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_DB_EDC_STALL_PATTERN_1_2 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_DB_EDC_STALL_PATTERN_3_4 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_DB_EDC_STALL_PATTERN_5_6 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_DB_EDC_STALL_PATTERN_7 +#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_DB_EDC_STATUS +#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_DB_EDC_STALL_DELAY_1 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3 +#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6 +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L +#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L +#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L +//DIDT_DB_EDC_OVERFLOW +#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_DB_EDC_ROLLING_POWER_DELTA +#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_TD_CTRL0 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b +#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L +//DIDT_TD_CTRL1 +#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_TD_CTRL2 +#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L +//DIDT_TD_STALL_CTRL +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18 +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L +//DIDT_TD_TUNING_CTRL +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_TD_STALL_AUTO_RELEASE_CTRL +#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_TD_CTRL3 +#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_TD_STALL_PATTERN_1_2 +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_TD_STALL_PATTERN_3_4 +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_TD_STALL_PATTERN_5_6 +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_TD_STALL_PATTERN_7 +#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_TD_WEIGHT0_3 +#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_TD_WEIGHT4_7 +#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_TD_WEIGHT8_11 +#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_TD_EDC_CTRL +#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17 +#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L +//DIDT_TD_EDC_THRESHOLD +#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_TD_EDC_STALL_PATTERN_1_2 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_TD_EDC_STALL_PATTERN_3_4 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_TD_EDC_STALL_PATTERN_5_6 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_TD_EDC_STALL_PATTERN_7 +#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_TD_EDC_STATUS +#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_TD_EDC_STALL_DELAY_1 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 +#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L +#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L +#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L +//DIDT_TD_EDC_STALL_DELAY_2 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 +#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L +#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L +#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L +//DIDT_TD_EDC_STALL_DELAY_3 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc +#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L +#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L +#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L +//DIDT_TD_EDC_OVERFLOW +#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_TD_EDC_ROLLING_POWER_DELTA +#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_TCP_CTRL0 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L +//DIDT_TCP_CTRL1 +#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_TCP_CTRL2 +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L +//DIDT_TCP_STALL_CTRL +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18 +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L +//DIDT_TCP_TUNING_CTRL +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_TCP_STALL_AUTO_RELEASE_CTRL +#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_TCP_CTRL3 +#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_TCP_STALL_PATTERN_1_2 +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_STALL_PATTERN_3_4 +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_STALL_PATTERN_5_6 +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_STALL_PATTERN_7 +#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_TCP_WEIGHT0_3 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_TCP_WEIGHT4_7 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_TCP_WEIGHT8_11 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_TCP_EDC_CTRL +#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17 +#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L +//DIDT_TCP_EDC_THRESHOLD +#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_TCP_EDC_STALL_PATTERN_1_2 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_EDC_STALL_PATTERN_3_4 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_EDC_STALL_PATTERN_5_6 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_TCP_EDC_STALL_PATTERN_7 +#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_TCP_EDC_STATUS +#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +//DIDT_TCP_EDC_STALL_DELAY_1 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 +#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L +#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L +#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L +//DIDT_TCP_EDC_STALL_DELAY_2 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 +#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L +#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L +#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L +//DIDT_TCP_EDC_STALL_DELAY_3 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc +#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L +#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L +#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L +//DIDT_TCP_EDC_OVERFLOW +#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_TCP_EDC_ROLLING_POWER_DELTA +#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_DBR_CTRL0 +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1 +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 +#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 +#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 +#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 +#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 +#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 +#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 +#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a +#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L +#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L +#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L +#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L +#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L +#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L +#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L +#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L +#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L +#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L +//DIDT_DBR_CTRL1 +#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL +#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L +//DIDT_DBR_CTRL2 +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L +//DIDT_DBR_STALL_CTRL +#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 +#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 +#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc +#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 +#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18 +#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL +#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L +#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L +#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L +#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L +//DIDT_DBR_TUNING_CTRL +#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe +#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL +#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L +//DIDT_DBR_STALL_AUTO_RELEASE_CTRL +#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 +#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL +//DIDT_DBR_CTRL3 +#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 +#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 +#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2 +#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 +#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe +#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 +#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 +#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 +#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b +#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c +#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L +#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L +#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL +#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L +#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L +#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L +#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L +#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L +#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L +#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L +//DIDT_DBR_STALL_PATTERN_1_2 +#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_STALL_PATTERN_3_4 +#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_STALL_PATTERN_5_6 +#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_STALL_PATTERN_7 +#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_DBR_WEIGHT0_3 +#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL +#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L +#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L +#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L +//DIDT_DBR_WEIGHT4_7 +#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL +#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L +#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L +#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L +//DIDT_DBR_WEIGHT8_11 +#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL +#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L +#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L +#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L +//DIDT_DBR_EDC_CTRL +#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 +#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 +#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 +#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 +#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 +#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 +#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17 +#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L +#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L +#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L +#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L +#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L +#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L +#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L +#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L +//DIDT_DBR_EDC_THRESHOLD +#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_DBR_EDC_STALL_PATTERN_1_2 +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_EDC_STALL_PATTERN_3_4 +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_EDC_STALL_PATTERN_5_6 +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L +//DIDT_DBR_EDC_STALL_PATTERN_7 +#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf +#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L +//DIDT_DBR_EDC_STATUS +#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4 +#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L +//DIDT_DBR_EDC_STALL_DELAY_1 +#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0 +#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1 +#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L +#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL +//DIDT_DBR_EDC_OVERFLOW +#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_DBR_EDC_ROLLING_POWER_DELTA +#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_SQ_STALL_EVENT_COUNTER +#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DB_STALL_EVENT_COUNTER +#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TD_STALL_EVENT_COUNTER +#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_TCP_STALL_EVENT_COUNTER +#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//DIDT_DBR_STALL_EVENT_COUNTER +#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 +#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL + + + + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h new file mode 100644 index 000000000000..392ef7721f53 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h @@ -0,0 +1,1028 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_1_DEFAULT_HEADER +#define _mmhub_9_1_DEFAULT_HEADER + + +// addressBlock: mmhub_dagbdec +#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI19_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI20_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI21_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI22_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI23_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI24_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI25_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI26_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI27_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI28_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI29_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI30_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI31_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f +#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 +#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 +#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI19_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI20_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI21_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI22_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI23_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI24_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI25_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI26_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI27_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI28_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI29_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI30_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI31_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f +#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_DEFAULT 0x00000000 +#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 +#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 +#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 +#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff +#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB0_RESERVE0_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE1_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE2_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE3_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE4_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE5_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE6_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE7_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE8_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE9_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE10_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE11_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE12_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE13_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE14_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE15_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE16_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE17_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE18_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE19_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE20_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE21_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE22_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE23_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE24_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE25_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE26_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE27_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE28_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE29_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE30_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE31_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE32_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE33_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE34_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE35_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE36_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE37_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE38_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE39_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE40_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE41_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE42_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE43_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE44_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE45_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE46_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE47_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE48_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE49_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE50_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE51_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE52_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE53_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE54_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE55_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE56_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE57_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE58_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE59_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE60_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE61_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE62_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE63_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE64_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE65_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE66_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE67_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE68_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE69_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE70_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE71_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE72_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE73_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE74_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE75_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE76_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE77_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE78_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE79_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE80_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE81_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE82_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE83_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE84_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE85_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE86_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE87_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE88_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE89_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE90_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE91_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE92_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE93_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE94_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE95_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE96_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE97_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE98_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE99_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE100_DEFAULT 0x00000000 +#define mmDAGB0_RESERVE101_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 +#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 +#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef +#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 +#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf +#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f +#define mmMMEA0_MISC_DEFAULT 0x00180130 +#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 +#define mmMMEA0_MISC2_DEFAULT 0x00000000 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 +#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 +#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef +#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 +#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf +#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f +#define mmMMEA1_MISC_DEFAULT 0x00180130 +#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 +#define mmMMEA1_MISC2_DEFAULT 0x00000000 + + +// addressBlock: mmhub_pctldec +#define mmPCTL_MISC_DEFAULT 0x00000889 +#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 +#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 +#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 +#define mmPCTL_PG_DAGB_DEFAULT 0x00000000 +#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_MISC_DEFAULT 0x00001000 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_MISC_DEFAULT 0x00000800 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL2_MISC_DEFAULT 0x00000800 +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff + + +// addressBlock: mmhub_l1tlb_vml1dec +#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 + + +// addressBlock: mmhub_l1tlb_vml1pldec +#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_l1tlb_vml1prdec +#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_l1tlb_vmtlspfdec +#define mmVM_L2_SAW_CNTL_DEFAULT 0x0c0b8602 +#define mmVM_L2_SAW_CNTL2_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CNTL3_DEFAULT 0x80100004 +#define mmVM_L2_SAW_CNTL4_DEFAULT 0x00000001 +#define mmVM_L2_SAW_CONTEXT0_CNTL_DEFAULT 0x00fffed8 +#define mmVM_L2_SAW_CONTEXT0_CNTL2_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_SAW_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define mmVM_L2_SAW_PIPES_BUSY_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2dec +#define mmATC_L2_CNTL_DEFAULT 0x000001c9 +#define mmATC_L2_CNTL2_DEFAULT 0x00000100 +#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 +#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 +#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 +#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 +#define mmATC_L2_STATUS_DEFAULT 0x00000000 +#define mmATC_L2_STATUS2_DEFAULT 0x00000000 +#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 +#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: mmhub_utcl2_vml2pfdec +#define mmVM_L2_CNTL_DEFAULT 0x00080602 +#define mmVM_L2_CNTL2_DEFAULT 0x00000000 +#define mmVM_L2_CNTL3_DEFAULT 0x80100007 +#define mmVM_L2_STATUS_DEFAULT 0x00000000 +#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc +#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff +#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 +#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 +#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 +#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 +#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 +#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 +#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: mmhub_utcl2_vml2vcdec +#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 +#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 +#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vml2pldec +#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_utcl2_vml2prdec +#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 +#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 +#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 +#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 +#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 +#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 +#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 +#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 +#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmMC_VM_STEERING_DEFAULT 0x00000001 +#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 +#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 +#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 +#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 +#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 +#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 +#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h new file mode 100644 index 000000000000..4b6fc7242277 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h @@ -0,0 +1,1999 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_1_OFFSET_HEADER +#define _mmhub_9_1_OFFSET_HEADER + + + +// addressBlock: mmhub_dagbdec +// base address: 0x68000 +#define mmDAGB0_RDCLI0 0x0000 +#define mmDAGB0_RDCLI0_BASE_IDX 0 +#define mmDAGB0_RDCLI1 0x0001 +#define mmDAGB0_RDCLI1_BASE_IDX 0 +#define mmDAGB0_RDCLI2 0x0002 +#define mmDAGB0_RDCLI2_BASE_IDX 0 +#define mmDAGB0_RDCLI3 0x0003 +#define mmDAGB0_RDCLI3_BASE_IDX 0 +#define mmDAGB0_RDCLI4 0x0004 +#define mmDAGB0_RDCLI4_BASE_IDX 0 +#define mmDAGB0_RDCLI5 0x0005 +#define mmDAGB0_RDCLI5_BASE_IDX 0 +#define mmDAGB0_RDCLI6 0x0006 +#define mmDAGB0_RDCLI6_BASE_IDX 0 +#define mmDAGB0_RDCLI7 0x0007 +#define mmDAGB0_RDCLI7_BASE_IDX 0 +#define mmDAGB0_RDCLI8 0x0008 +#define mmDAGB0_RDCLI8_BASE_IDX 0 +#define mmDAGB0_RDCLI9 0x0009 +#define mmDAGB0_RDCLI9_BASE_IDX 0 +#define mmDAGB0_RDCLI10 0x000a +#define mmDAGB0_RDCLI10_BASE_IDX 0 +#define mmDAGB0_RDCLI11 0x000b +#define mmDAGB0_RDCLI11_BASE_IDX 0 +#define mmDAGB0_RDCLI12 0x000c +#define mmDAGB0_RDCLI12_BASE_IDX 0 +#define mmDAGB0_RDCLI13 0x000d +#define mmDAGB0_RDCLI13_BASE_IDX 0 +#define mmDAGB0_RDCLI14 0x000e +#define mmDAGB0_RDCLI14_BASE_IDX 0 +#define mmDAGB0_RDCLI15 0x000f +#define mmDAGB0_RDCLI15_BASE_IDX 0 +#define mmDAGB0_RDCLI16 0x0010 +#define mmDAGB0_RDCLI16_BASE_IDX 0 +#define mmDAGB0_RDCLI17 0x0011 +#define mmDAGB0_RDCLI17_BASE_IDX 0 +#define mmDAGB0_RDCLI18 0x0012 +#define mmDAGB0_RDCLI18_BASE_IDX 0 +#define mmDAGB0_RDCLI19 0x0013 +#define mmDAGB0_RDCLI19_BASE_IDX 0 +#define mmDAGB0_RDCLI20 0x0014 +#define mmDAGB0_RDCLI20_BASE_IDX 0 +#define mmDAGB0_RDCLI21 0x0015 +#define mmDAGB0_RDCLI21_BASE_IDX 0 +#define mmDAGB0_RDCLI22 0x0016 +#define mmDAGB0_RDCLI22_BASE_IDX 0 +#define mmDAGB0_RDCLI23 0x0017 +#define mmDAGB0_RDCLI23_BASE_IDX 0 +#define mmDAGB0_RDCLI24 0x0018 +#define mmDAGB0_RDCLI24_BASE_IDX 0 +#define mmDAGB0_RDCLI25 0x0019 +#define mmDAGB0_RDCLI25_BASE_IDX 0 +#define mmDAGB0_RDCLI26 0x001a +#define mmDAGB0_RDCLI26_BASE_IDX 0 +#define mmDAGB0_RDCLI27 0x001b +#define mmDAGB0_RDCLI27_BASE_IDX 0 +#define mmDAGB0_RDCLI28 0x001c +#define mmDAGB0_RDCLI28_BASE_IDX 0 +#define mmDAGB0_RDCLI29 0x001d +#define mmDAGB0_RDCLI29_BASE_IDX 0 +#define mmDAGB0_RDCLI30 0x001e +#define mmDAGB0_RDCLI30_BASE_IDX 0 +#define mmDAGB0_RDCLI31 0x001f +#define mmDAGB0_RDCLI31_BASE_IDX 0 +#define mmDAGB0_RD_CNTL 0x0020 +#define mmDAGB0_RD_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_GMI_CNTL 0x0021 +#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB 0x0022 +#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0023 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0024 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0025 +#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0026 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0027 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0028 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0029 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x002a +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x002b +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x002c +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x002d +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002e +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 0 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002f +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 0 +#define mmDAGB0_RD_VC0_CNTL 0x0030 +#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC1_CNTL 0x0031 +#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC2_CNTL 0x0032 +#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC3_CNTL 0x0033 +#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC4_CNTL 0x0034 +#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC5_CNTL 0x0035 +#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC6_CNTL 0x0036 +#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_VC7_CNTL 0x0037 +#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 +#define mmDAGB0_RD_CNTL_MISC 0x0038 +#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 +#define mmDAGB0_RD_TLB_CREDIT 0x0039 +#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 +#define mmDAGB0_RDCLI_ASK_PENDING 0x003a +#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 +#define mmDAGB0_RDCLI_GO_PENDING 0x003b +#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 +#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x003c +#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define mmDAGB0_RDCLI_TLB_PENDING 0x003d +#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 +#define mmDAGB0_RDCLI_OARB_PENDING 0x003e +#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 +#define mmDAGB0_RDCLI_OSD_PENDING 0x003f +#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI0 0x0040 +#define mmDAGB0_WRCLI0_BASE_IDX 0 +#define mmDAGB0_WRCLI1 0x0041 +#define mmDAGB0_WRCLI1_BASE_IDX 0 +#define mmDAGB0_WRCLI2 0x0042 +#define mmDAGB0_WRCLI2_BASE_IDX 0 +#define mmDAGB0_WRCLI3 0x0043 +#define mmDAGB0_WRCLI3_BASE_IDX 0 +#define mmDAGB0_WRCLI4 0x0044 +#define mmDAGB0_WRCLI4_BASE_IDX 0 +#define mmDAGB0_WRCLI5 0x0045 +#define mmDAGB0_WRCLI5_BASE_IDX 0 +#define mmDAGB0_WRCLI6 0x0046 +#define mmDAGB0_WRCLI6_BASE_IDX 0 +#define mmDAGB0_WRCLI7 0x0047 +#define mmDAGB0_WRCLI7_BASE_IDX 0 +#define mmDAGB0_WRCLI8 0x0048 +#define mmDAGB0_WRCLI8_BASE_IDX 0 +#define mmDAGB0_WRCLI9 0x0049 +#define mmDAGB0_WRCLI9_BASE_IDX 0 +#define mmDAGB0_WRCLI10 0x004a +#define mmDAGB0_WRCLI10_BASE_IDX 0 +#define mmDAGB0_WRCLI11 0x004b +#define mmDAGB0_WRCLI11_BASE_IDX 0 +#define mmDAGB0_WRCLI12 0x004c +#define mmDAGB0_WRCLI12_BASE_IDX 0 +#define mmDAGB0_WRCLI13 0x004d +#define mmDAGB0_WRCLI13_BASE_IDX 0 +#define mmDAGB0_WRCLI14 0x004e +#define mmDAGB0_WRCLI14_BASE_IDX 0 +#define mmDAGB0_WRCLI15 0x004f +#define mmDAGB0_WRCLI15_BASE_IDX 0 +#define mmDAGB0_WRCLI16 0x0050 +#define mmDAGB0_WRCLI16_BASE_IDX 0 +#define mmDAGB0_WRCLI17 0x0051 +#define mmDAGB0_WRCLI17_BASE_IDX 0 +#define mmDAGB0_WRCLI18 0x0052 +#define mmDAGB0_WRCLI18_BASE_IDX 0 +#define mmDAGB0_WRCLI19 0x0053 +#define mmDAGB0_WRCLI19_BASE_IDX 0 +#define mmDAGB0_WRCLI20 0x0054 +#define mmDAGB0_WRCLI20_BASE_IDX 0 +#define mmDAGB0_WRCLI21 0x0055 +#define mmDAGB0_WRCLI21_BASE_IDX 0 +#define mmDAGB0_WRCLI22 0x0056 +#define mmDAGB0_WRCLI22_BASE_IDX 0 +#define mmDAGB0_WRCLI23 0x0057 +#define mmDAGB0_WRCLI23_BASE_IDX 0 +#define mmDAGB0_WRCLI24 0x0058 +#define mmDAGB0_WRCLI24_BASE_IDX 0 +#define mmDAGB0_WRCLI25 0x0059 +#define mmDAGB0_WRCLI25_BASE_IDX 0 +#define mmDAGB0_WRCLI26 0x005a +#define mmDAGB0_WRCLI26_BASE_IDX 0 +#define mmDAGB0_WRCLI27 0x005b +#define mmDAGB0_WRCLI27_BASE_IDX 0 +#define mmDAGB0_WRCLI28 0x005c +#define mmDAGB0_WRCLI28_BASE_IDX 0 +#define mmDAGB0_WRCLI29 0x005d +#define mmDAGB0_WRCLI29_BASE_IDX 0 +#define mmDAGB0_WRCLI30 0x005e +#define mmDAGB0_WRCLI30_BASE_IDX 0 +#define mmDAGB0_WRCLI31 0x005f +#define mmDAGB0_WRCLI31_BASE_IDX 0 +#define mmDAGB0_WR_CNTL 0x0060 +#define mmDAGB0_WR_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_GMI_CNTL 0x0061 +#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB 0x0062 +#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0063 +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0064 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 +#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0065 +#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0066 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0067 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0068 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0069 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x006a +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x006b +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x006c +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x006d +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x006e +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 0 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006f +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB 0x0070 +#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0071 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0072 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0073 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0074 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0075 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0076 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0077 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 0 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0078 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 0 +#define mmDAGB0_WR_VC0_CNTL 0x0079 +#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC1_CNTL 0x007a +#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC2_CNTL 0x007b +#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC3_CNTL 0x007c +#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC4_CNTL 0x007d +#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC5_CNTL 0x007e +#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC6_CNTL 0x007f +#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_VC7_CNTL 0x0080 +#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 +#define mmDAGB0_WR_CNTL_MISC 0x0081 +#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 +#define mmDAGB0_WR_TLB_CREDIT 0x0082 +#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 +#define mmDAGB0_WR_DATA_CREDIT 0x0083 +#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 +#define mmDAGB0_WR_MISC_CREDIT 0x0084 +#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 +#define mmDAGB0_WRCLI_ASK_PENDING 0x0085 +#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_GO_PENDING 0x0086 +#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x0087 +#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_TLB_PENDING 0x0088 +#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_OARB_PENDING 0x0089 +#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_OSD_PENDING 0x008a +#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x008b +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x008c +#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define mmDAGB0_DAGB_DLY 0x008d +#define mmDAGB0_DAGB_DLY_BASE_IDX 0 +#define mmDAGB0_CNTL_MISC 0x008e +#define mmDAGB0_CNTL_MISC_BASE_IDX 0 +#define mmDAGB0_CNTL_MISC2 0x008f +#define mmDAGB0_CNTL_MISC2_BASE_IDX 0 +#define mmDAGB0_FIFO_EMPTY 0x0090 +#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 +#define mmDAGB0_FIFO_FULL 0x0091 +#define mmDAGB0_FIFO_FULL_BASE_IDX 0 +#define mmDAGB0_WR_CREDITS_FULL 0x0092 +#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 +#define mmDAGB0_RD_CREDITS_FULL 0x0093 +#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER_LO 0x0094 +#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER_HI 0x0095 +#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER0_CFG 0x0096 +#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER1_CFG 0x0097 +#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER2_CFG 0x0098 +#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0099 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmDAGB0_RESERVE0 0x009a +#define mmDAGB0_RESERVE0_BASE_IDX 0 +#define mmDAGB0_RESERVE1 0x009b +#define mmDAGB0_RESERVE1_BASE_IDX 0 +#define mmDAGB0_RESERVE2 0x009c +#define mmDAGB0_RESERVE2_BASE_IDX 0 +#define mmDAGB0_RESERVE3 0x009d +#define mmDAGB0_RESERVE3_BASE_IDX 0 +#define mmDAGB0_RESERVE4 0x009e +#define mmDAGB0_RESERVE4_BASE_IDX 0 +#define mmDAGB0_RESERVE5 0x009f +#define mmDAGB0_RESERVE5_BASE_IDX 0 +#define mmDAGB0_RESERVE6 0x00a0 +#define mmDAGB0_RESERVE6_BASE_IDX 0 +#define mmDAGB0_RESERVE7 0x00a1 +#define mmDAGB0_RESERVE7_BASE_IDX 0 +#define mmDAGB0_RESERVE8 0x00a2 +#define mmDAGB0_RESERVE8_BASE_IDX 0 +#define mmDAGB0_RESERVE9 0x00a3 +#define mmDAGB0_RESERVE9_BASE_IDX 0 +#define mmDAGB0_RESERVE10 0x00a4 +#define mmDAGB0_RESERVE10_BASE_IDX 0 +#define mmDAGB0_RESERVE11 0x00a5 +#define mmDAGB0_RESERVE11_BASE_IDX 0 +#define mmDAGB0_RESERVE12 0x00a6 +#define mmDAGB0_RESERVE12_BASE_IDX 0 +#define mmDAGB0_RESERVE13 0x00a7 +#define mmDAGB0_RESERVE13_BASE_IDX 0 +#define mmDAGB0_RESERVE14 0x00a8 +#define mmDAGB0_RESERVE14_BASE_IDX 0 +#define mmDAGB0_RESERVE15 0x00a9 +#define mmDAGB0_RESERVE15_BASE_IDX 0 +#define mmDAGB0_RESERVE16 0x00aa +#define mmDAGB0_RESERVE16_BASE_IDX 0 +#define mmDAGB0_RESERVE17 0x00ab +#define mmDAGB0_RESERVE17_BASE_IDX 0 +#define mmDAGB0_RESERVE18 0x00ac +#define mmDAGB0_RESERVE18_BASE_IDX 0 +#define mmDAGB0_RESERVE19 0x00ad +#define mmDAGB0_RESERVE19_BASE_IDX 0 +#define mmDAGB0_RESERVE20 0x00ae +#define mmDAGB0_RESERVE20_BASE_IDX 0 +#define mmDAGB0_RESERVE21 0x00af +#define mmDAGB0_RESERVE21_BASE_IDX 0 +#define mmDAGB0_RESERVE22 0x00b0 +#define mmDAGB0_RESERVE22_BASE_IDX 0 +#define mmDAGB0_RESERVE23 0x00b1 +#define mmDAGB0_RESERVE23_BASE_IDX 0 +#define mmDAGB0_RESERVE24 0x00b2 +#define mmDAGB0_RESERVE24_BASE_IDX 0 +#define mmDAGB0_RESERVE25 0x00b3 +#define mmDAGB0_RESERVE25_BASE_IDX 0 +#define mmDAGB0_RESERVE26 0x00b4 +#define mmDAGB0_RESERVE26_BASE_IDX 0 +#define mmDAGB0_RESERVE27 0x00b5 +#define mmDAGB0_RESERVE27_BASE_IDX 0 +#define mmDAGB0_RESERVE28 0x00b6 +#define mmDAGB0_RESERVE28_BASE_IDX 0 +#define mmDAGB0_RESERVE29 0x00b7 +#define mmDAGB0_RESERVE29_BASE_IDX 0 +#define mmDAGB0_RESERVE30 0x00b8 +#define mmDAGB0_RESERVE30_BASE_IDX 0 +#define mmDAGB0_RESERVE31 0x00b9 +#define mmDAGB0_RESERVE31_BASE_IDX 0 +#define mmDAGB0_RESERVE32 0x00ba +#define mmDAGB0_RESERVE32_BASE_IDX 0 +#define mmDAGB0_RESERVE33 0x00bb +#define mmDAGB0_RESERVE33_BASE_IDX 0 +#define mmDAGB0_RESERVE34 0x00bc +#define mmDAGB0_RESERVE34_BASE_IDX 0 +#define mmDAGB0_RESERVE35 0x00bd +#define mmDAGB0_RESERVE35_BASE_IDX 0 +#define mmDAGB0_RESERVE36 0x00be +#define mmDAGB0_RESERVE36_BASE_IDX 0 +#define mmDAGB0_RESERVE37 0x00bf +#define mmDAGB0_RESERVE37_BASE_IDX 0 +#define mmDAGB0_RESERVE38 0x00c0 +#define mmDAGB0_RESERVE38_BASE_IDX 0 +#define mmDAGB0_RESERVE39 0x00c1 +#define mmDAGB0_RESERVE39_BASE_IDX 0 +#define mmDAGB0_RESERVE40 0x00c2 +#define mmDAGB0_RESERVE40_BASE_IDX 0 +#define mmDAGB0_RESERVE41 0x00c3 +#define mmDAGB0_RESERVE41_BASE_IDX 0 +#define mmDAGB0_RESERVE42 0x00c4 +#define mmDAGB0_RESERVE42_BASE_IDX 0 +#define mmDAGB0_RESERVE43 0x00c5 +#define mmDAGB0_RESERVE43_BASE_IDX 0 +#define mmDAGB0_RESERVE44 0x00c6 +#define mmDAGB0_RESERVE44_BASE_IDX 0 +#define mmDAGB0_RESERVE45 0x00c7 +#define mmDAGB0_RESERVE45_BASE_IDX 0 +#define mmDAGB0_RESERVE46 0x00c8 +#define mmDAGB0_RESERVE46_BASE_IDX 0 +#define mmDAGB0_RESERVE47 0x00c9 +#define mmDAGB0_RESERVE47_BASE_IDX 0 +#define mmDAGB0_RESERVE48 0x00ca +#define mmDAGB0_RESERVE48_BASE_IDX 0 +#define mmDAGB0_RESERVE49 0x00cb +#define mmDAGB0_RESERVE49_BASE_IDX 0 +#define mmDAGB0_RESERVE50 0x00cc +#define mmDAGB0_RESERVE50_BASE_IDX 0 +#define mmDAGB0_RESERVE51 0x00cd +#define mmDAGB0_RESERVE51_BASE_IDX 0 +#define mmDAGB0_RESERVE52 0x00ce +#define mmDAGB0_RESERVE52_BASE_IDX 0 +#define mmDAGB0_RESERVE53 0x00cf +#define mmDAGB0_RESERVE53_BASE_IDX 0 +#define mmDAGB0_RESERVE54 0x00d0 +#define mmDAGB0_RESERVE54_BASE_IDX 0 +#define mmDAGB0_RESERVE55 0x00d1 +#define mmDAGB0_RESERVE55_BASE_IDX 0 +#define mmDAGB0_RESERVE56 0x00d2 +#define mmDAGB0_RESERVE56_BASE_IDX 0 +#define mmDAGB0_RESERVE57 0x00d3 +#define mmDAGB0_RESERVE57_BASE_IDX 0 +#define mmDAGB0_RESERVE58 0x00d4 +#define mmDAGB0_RESERVE58_BASE_IDX 0 +#define mmDAGB0_RESERVE59 0x00d5 +#define mmDAGB0_RESERVE59_BASE_IDX 0 +#define mmDAGB0_RESERVE60 0x00d6 +#define mmDAGB0_RESERVE60_BASE_IDX 0 +#define mmDAGB0_RESERVE61 0x00d7 +#define mmDAGB0_RESERVE61_BASE_IDX 0 +#define mmDAGB0_RESERVE62 0x00d8 +#define mmDAGB0_RESERVE62_BASE_IDX 0 +#define mmDAGB0_RESERVE63 0x00d9 +#define mmDAGB0_RESERVE63_BASE_IDX 0 +#define mmDAGB0_RESERVE64 0x00da +#define mmDAGB0_RESERVE64_BASE_IDX 0 +#define mmDAGB0_RESERVE65 0x00db +#define mmDAGB0_RESERVE65_BASE_IDX 0 +#define mmDAGB0_RESERVE66 0x00dc +#define mmDAGB0_RESERVE66_BASE_IDX 0 +#define mmDAGB0_RESERVE67 0x00dd +#define mmDAGB0_RESERVE67_BASE_IDX 0 +#define mmDAGB0_RESERVE68 0x00de +#define mmDAGB0_RESERVE68_BASE_IDX 0 +#define mmDAGB0_RESERVE69 0x00df +#define mmDAGB0_RESERVE69_BASE_IDX 0 +#define mmDAGB0_RESERVE70 0x00e0 +#define mmDAGB0_RESERVE70_BASE_IDX 0 +#define mmDAGB0_RESERVE71 0x00e1 +#define mmDAGB0_RESERVE71_BASE_IDX 0 +#define mmDAGB0_RESERVE72 0x00e2 +#define mmDAGB0_RESERVE72_BASE_IDX 0 +#define mmDAGB0_RESERVE73 0x00e3 +#define mmDAGB0_RESERVE73_BASE_IDX 0 +#define mmDAGB0_RESERVE74 0x00e4 +#define mmDAGB0_RESERVE74_BASE_IDX 0 +#define mmDAGB0_RESERVE75 0x00e5 +#define mmDAGB0_RESERVE75_BASE_IDX 0 +#define mmDAGB0_RESERVE76 0x00e6 +#define mmDAGB0_RESERVE76_BASE_IDX 0 +#define mmDAGB0_RESERVE77 0x00e7 +#define mmDAGB0_RESERVE77_BASE_IDX 0 +#define mmDAGB0_RESERVE78 0x00e8 +#define mmDAGB0_RESERVE78_BASE_IDX 0 +#define mmDAGB0_RESERVE79 0x00e9 +#define mmDAGB0_RESERVE79_BASE_IDX 0 +#define mmDAGB0_RESERVE80 0x00ea +#define mmDAGB0_RESERVE80_BASE_IDX 0 +#define mmDAGB0_RESERVE81 0x00eb +#define mmDAGB0_RESERVE81_BASE_IDX 0 +#define mmDAGB0_RESERVE82 0x00ec +#define mmDAGB0_RESERVE82_BASE_IDX 0 +#define mmDAGB0_RESERVE83 0x00ed +#define mmDAGB0_RESERVE83_BASE_IDX 0 +#define mmDAGB0_RESERVE84 0x00ee +#define mmDAGB0_RESERVE84_BASE_IDX 0 +#define mmDAGB0_RESERVE85 0x00ef +#define mmDAGB0_RESERVE85_BASE_IDX 0 +#define mmDAGB0_RESERVE86 0x00f0 +#define mmDAGB0_RESERVE86_BASE_IDX 0 +#define mmDAGB0_RESERVE87 0x00f1 +#define mmDAGB0_RESERVE87_BASE_IDX 0 +#define mmDAGB0_RESERVE88 0x00f2 +#define mmDAGB0_RESERVE88_BASE_IDX 0 +#define mmDAGB0_RESERVE89 0x00f3 +#define mmDAGB0_RESERVE89_BASE_IDX 0 +#define mmDAGB0_RESERVE90 0x00f4 +#define mmDAGB0_RESERVE90_BASE_IDX 0 +#define mmDAGB0_RESERVE91 0x00f5 +#define mmDAGB0_RESERVE91_BASE_IDX 0 +#define mmDAGB0_RESERVE92 0x00f6 +#define mmDAGB0_RESERVE92_BASE_IDX 0 +#define mmDAGB0_RESERVE93 0x00f7 +#define mmDAGB0_RESERVE93_BASE_IDX 0 +#define mmDAGB0_RESERVE94 0x00f8 +#define mmDAGB0_RESERVE94_BASE_IDX 0 +#define mmDAGB0_RESERVE95 0x00f9 +#define mmDAGB0_RESERVE95_BASE_IDX 0 +#define mmDAGB0_RESERVE96 0x00fa +#define mmDAGB0_RESERVE96_BASE_IDX 0 +#define mmDAGB0_RESERVE97 0x00fb +#define mmDAGB0_RESERVE97_BASE_IDX 0 +#define mmDAGB0_RESERVE98 0x00fc +#define mmDAGB0_RESERVE98_BASE_IDX 0 +#define mmDAGB0_RESERVE99 0x00fd +#define mmDAGB0_RESERVE99_BASE_IDX 0 +#define mmDAGB0_RESERVE100 0x00fe +#define mmDAGB0_RESERVE100_BASE_IDX 0 +#define mmDAGB0_RESERVE101 0x00ff +#define mmDAGB0_RESERVE101_BASE_IDX 0 + + +// addressBlock: mmhub_ea_mmeadec +// base address: 0x68400 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_LAZY 0x0106 +#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_LAZY 0x0107 +#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 +#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 +#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define mmMMEA0_DRAM_PAGE_BURST 0x010a +#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b +#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c +#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d +#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e +#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f +#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 +#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 +#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 +#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0132 +#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0133 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0134 +#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0135 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0136 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define mmMMEA0_ADDRNORM_HOLE_CNTL 0x0141 +#define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX 0 +#define mmMMEA0_ADDRDEC_BANK_CFG 0x0142 +#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define mmMMEA0_ADDRDEC_MISC_CFG 0x0143 +#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0144 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x0145 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x0146 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x0147 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x0148 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x0149 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014a +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x014b +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x014c +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x014d +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0158 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0159 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015a +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x015b +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x015c +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x015d +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x015e +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x015f +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0160 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0161 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0162 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0163 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0164 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0165 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0166 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0167 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0168 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0169 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016a +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x016b +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x016c +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x016d +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x016e +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x016f +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0170 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0171 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0172 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0173 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0174 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0175 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0176 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0177 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0178 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0179 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017a +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x017b +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x017c +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x017d +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x017e +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x017f +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0180 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0181 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0182 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0183 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0184 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0185 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0186 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0187 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d0 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d1 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d2 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d3 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d4 +#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01d5 +#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define mmMMEA0_IO_GROUP_BURST 0x01d6 +#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_AGE 0x01d7 +#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_AGE 0x01d8 +#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_QUEUING 0x01d9 +#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_QUEUING 0x01da +#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_FIXED 0x01db +#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_FIXED 0x01dc +#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_URGENCY 0x01dd +#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_URGENCY 0x01de +#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01df +#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e0 +#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e1 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e2 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e3 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e4 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01e5 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01e6 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA0_SDP_ARB_DRAM 0x01e7 +#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 +#define mmMMEA0_SDP_ARB_FINAL 0x01e9 +#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 +#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ea +#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define mmMMEA0_SDP_IO_PRIORITY 0x01ec +#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 +#define mmMMEA0_SDP_CREDITS 0x01ed +#define mmMMEA0_SDP_CREDITS_BASE_IDX 0 +#define mmMMEA0_SDP_TAG_RESERVE0 0x01ee +#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 +#define mmMMEA0_SDP_TAG_RESERVE1 0x01ef +#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 +#define mmMMEA0_SDP_VCC_RESERVE0 0x01f0 +#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 +#define mmMMEA0_SDP_VCC_RESERVE1 0x01f1 +#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 +#define mmMMEA0_SDP_VCD_RESERVE0 0x01f2 +#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 +#define mmMMEA0_SDP_VCD_RESERVE1 0x01f3 +#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 +#define mmMMEA0_SDP_REQ_CNTL 0x01f4 +#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 +#define mmMMEA0_MISC 0x01f5 +#define mmMMEA0_MISC_BASE_IDX 0 +#define mmMMEA0_LATENCY_SAMPLING 0x01f6 +#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 +#define mmMMEA0_PERFCOUNTER_LO 0x01f7 +#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 +#define mmMMEA0_PERFCOUNTER_HI 0x01f8 +#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 +#define mmMMEA0_PERFCOUNTER0_CFG 0x01f9 +#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmMMEA0_PERFCOUNTER1_CFG 0x01fa +#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x01fb +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmMMEA0_EDC_CNT 0x0201 +#define mmMMEA0_EDC_CNT_BASE_IDX 0 +#define mmMMEA0_EDC_CNT2 0x0202 +#define mmMMEA0_EDC_CNT2_BASE_IDX 0 +#define mmMMEA0_DSM_CNTL 0x0203 +#define mmMMEA0_DSM_CNTL_BASE_IDX 0 +#define mmMMEA0_DSM_CNTLA 0x0204 +#define mmMMEA0_DSM_CNTLA_BASE_IDX 0 +#define mmMMEA0_DSM_CNTLB 0x0205 +#define mmMMEA0_DSM_CNTLB_BASE_IDX 0 +#define mmMMEA0_DSM_CNTL2 0x0206 +#define mmMMEA0_DSM_CNTL2_BASE_IDX 0 +#define mmMMEA0_DSM_CNTL2A 0x0207 +#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 +#define mmMMEA0_DSM_CNTL2B 0x0208 +#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 +#define mmMMEA0_CGTT_CLK_CTRL 0x020a +#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmMMEA0_EDC_MODE 0x020b +#define mmMMEA0_EDC_MODE_BASE_IDX 0 +#define mmMMEA0_ERR_STATUS 0x020c +#define mmMMEA0_ERR_STATUS_BASE_IDX 0 +#define mmMMEA0_MISC2 0x020d +#define mmMMEA0_MISC2_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_LAZY 0x0246 +#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_LAZY 0x0247 +#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248 +#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249 +#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define mmMMEA1_DRAM_PAGE_BURST 0x024a +#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b +#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c +#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d +#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e +#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f +#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250 +#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251 +#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252 +#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0272 +#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0273 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0274 +#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0275 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0276 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 +#define mmMMEA1_ADDRNORM_HOLE_CNTL 0x0281 +#define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX 0 +#define mmMMEA1_ADDRDEC_BANK_CFG 0x0282 +#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 +#define mmMMEA1_ADDRDEC_MISC_CFG 0x0283 +#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0284 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x0285 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x0286 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x0287 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x0288 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x0289 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028a +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x028b +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x028c +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x028d +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x0298 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0299 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029a +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x029b +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x029c +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x029d +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x029e +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x029f +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a0 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a1 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a2 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a3 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a4 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02a5 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02a6 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02a7 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02a8 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02a9 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02aa +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02ab +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02ac +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02ad +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02ae +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02af +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b2 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b3 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b4 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02b5 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02b6 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02b7 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02b8 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02b9 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02ba +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02bb +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02bc +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02bd +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02be +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02bf +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c0 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c1 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c2 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c3 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c4 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02c5 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02c6 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02c7 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0310 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0311 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0312 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0313 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0314 +#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x0315 +#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define mmMMEA1_IO_GROUP_BURST 0x0316 +#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_AGE 0x0317 +#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_AGE 0x0318 +#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_QUEUING 0x0319 +#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_QUEUING 0x031a +#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_FIXED 0x031b +#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_FIXED 0x031c +#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_URGENCY 0x031d +#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_URGENCY 0x031e +#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x031f +#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0320 +#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0321 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0322 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0323 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0324 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x0325 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x0326 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define mmMMEA1_SDP_ARB_DRAM 0x0327 +#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0 +#define mmMMEA1_SDP_ARB_FINAL 0x0329 +#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0 +#define mmMMEA1_SDP_DRAM_PRIORITY 0x032a +#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define mmMMEA1_SDP_IO_PRIORITY 0x032c +#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 +#define mmMMEA1_SDP_CREDITS 0x032d +#define mmMMEA1_SDP_CREDITS_BASE_IDX 0 +#define mmMMEA1_SDP_TAG_RESERVE0 0x032e +#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 +#define mmMMEA1_SDP_TAG_RESERVE1 0x032f +#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 +#define mmMMEA1_SDP_VCC_RESERVE0 0x0330 +#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 +#define mmMMEA1_SDP_VCC_RESERVE1 0x0331 +#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 +#define mmMMEA1_SDP_VCD_RESERVE0 0x0332 +#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 +#define mmMMEA1_SDP_VCD_RESERVE1 0x0333 +#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 +#define mmMMEA1_SDP_REQ_CNTL 0x0334 +#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0 +#define mmMMEA1_MISC 0x0335 +#define mmMMEA1_MISC_BASE_IDX 0 +#define mmMMEA1_LATENCY_SAMPLING 0x0336 +#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0 +#define mmMMEA1_PERFCOUNTER_LO 0x0337 +#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0 +#define mmMMEA1_PERFCOUNTER_HI 0x0338 +#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0 +#define mmMMEA1_PERFCOUNTER0_CFG 0x0339 +#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmMMEA1_PERFCOUNTER1_CFG 0x033a +#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x033b +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmMMEA1_EDC_CNT 0x0341 +#define mmMMEA1_EDC_CNT_BASE_IDX 0 +#define mmMMEA1_EDC_CNT2 0x0342 +#define mmMMEA1_EDC_CNT2_BASE_IDX 0 +#define mmMMEA1_DSM_CNTL 0x0343 +#define mmMMEA1_DSM_CNTL_BASE_IDX 0 +#define mmMMEA1_DSM_CNTLA 0x0344 +#define mmMMEA1_DSM_CNTLA_BASE_IDX 0 +#define mmMMEA1_DSM_CNTLB 0x0345 +#define mmMMEA1_DSM_CNTLB_BASE_IDX 0 +#define mmMMEA1_DSM_CNTL2 0x0346 +#define mmMMEA1_DSM_CNTL2_BASE_IDX 0 +#define mmMMEA1_DSM_CNTL2A 0x0347 +#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0 +#define mmMMEA1_DSM_CNTL2B 0x0348 +#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0 +#define mmMMEA1_CGTT_CLK_CTRL 0x034a +#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 +#define mmMMEA1_EDC_MODE 0x034b +#define mmMMEA1_EDC_MODE_BASE_IDX 0 +#define mmMMEA1_ERR_STATUS 0x034c +#define mmMMEA1_ERR_STATUS_BASE_IDX 0 +#define mmMMEA1_MISC2 0x034d +#define mmMMEA1_MISC2_BASE_IDX 0 + + +// addressBlock: mmhub_pctldec +// base address: 0x68e00 +#define mmPCTL_MISC 0x0380 +#define mmPCTL_MISC_BASE_IDX 0 +#define mmPCTL_MMHUB_DEEPSLEEP 0x0381 +#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 +#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 +#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 +#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 +#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 +#define mmPCTL_PG_DAGB 0x0384 +#define mmPCTL_PG_DAGB_BASE_IDX 0 +#define mmPCTL0_RENG_RAM_INDEX 0x0385 +#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 +#define mmPCTL0_RENG_RAM_DATA 0x0386 +#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 +#define mmPCTL0_RENG_EXECUTE 0x0387 +#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 +#define mmPCTL0_MISC 0x0388 +#define mmPCTL0_MISC_BASE_IDX 0 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b +#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038c +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038d +#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define mmPCTL1_RENG_RAM_INDEX 0x038e +#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 +#define mmPCTL1_RENG_RAM_DATA 0x038f +#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 +#define mmPCTL1_RENG_EXECUTE 0x0390 +#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 +#define mmPCTL1_MISC 0x0391 +#define mmPCTL1_MISC_BASE_IDX 0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0392 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0393 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0394 +#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0395 +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0396 +#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define mmPCTL2_RENG_RAM_INDEX 0x0397 +#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 +#define mmPCTL2_RENG_RAM_DATA 0x0398 +#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 +#define mmPCTL2_RENG_EXECUTE 0x0399 +#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 +#define mmPCTL2_MISC 0x039a +#define mmPCTL2_MISC_BASE_IDX 0 +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d +#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x039e +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039f +#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1dec +// base address: 0x69600 +#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588 +#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589 +#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a +#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b +#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c +#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d +#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e +#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f +#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1pldec +// base address: 0x69650 +#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 +#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 +#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 +#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 +#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 +#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vml1prdec +// base address: 0x69670 +#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c +#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 +#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d +#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_vmtlspfdec +// base address: 0x69680 +#define mmVM_L2_SAW_CNTL 0x0600 +#define mmVM_L2_SAW_CNTL_BASE_IDX 0 +#define mmVM_L2_SAW_CNTL2 0x0601 +#define mmVM_L2_SAW_CNTL2_BASE_IDX 0 +#define mmVM_L2_SAW_CNTL3 0x0602 +#define mmVM_L2_SAW_CNTL3_BASE_IDX 0 +#define mmVM_L2_SAW_CNTL4 0x0603 +#define mmVM_L2_SAW_CNTL4_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_CNTL 0x0604 +#define mmVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_CNTL2 0x0605 +#define mmVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0606 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0607 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0608 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0609 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x060a +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x060b +#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_SAW_CONTEXTS_DISABLE 0x060c +#define mmVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 0 +#define mmVM_L2_SAW_PIPES_BUSY 0x060d +#define mmVM_L2_SAW_PIPES_BUSY_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2dec +// base address: 0x69900 +#define mmATC_L2_CNTL 0x0640 +#define mmATC_L2_CNTL_BASE_IDX 0 +#define mmATC_L2_CNTL2 0x0641 +#define mmATC_L2_CNTL2_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA0 0x0644 +#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA1 0x0645 +#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 +#define mmATC_L2_CACHE_DATA2 0x0646 +#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 +#define mmATC_L2_CNTL3 0x0647 +#define mmATC_L2_CNTL3_BASE_IDX 0 +#define mmATC_L2_STATUS 0x0648 +#define mmATC_L2_STATUS_BASE_IDX 0 +#define mmATC_L2_STATUS2 0x0649 +#define mmATC_L2_STATUS2_BASE_IDX 0 +#define mmATC_L2_MISC_CG 0x064a +#define mmATC_L2_MISC_CG_BASE_IDX 0 +#define mmATC_L2_MEM_POWER_LS 0x064b +#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define mmATC_L2_CGTT_CLK_CTRL 0x064c +#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2pfdec +// base address: 0x69a00 +#define mmVM_L2_CNTL 0x0680 +#define mmVM_L2_CNTL_BASE_IDX 0 +#define mmVM_L2_CNTL2 0x0681 +#define mmVM_L2_CNTL2_BASE_IDX 0 +#define mmVM_L2_CNTL3 0x0682 +#define mmVM_L2_CNTL3_BASE_IDX 0 +#define mmVM_L2_STATUS 0x0683 +#define mmVM_L2_STATUS_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684 +#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 +#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687 +#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688 +#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a +#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b +#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c +#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d +#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f +#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define mmVM_L2_CNTL4 0x0697 +#define mmVM_L2_CNTL4_BASE_IDX 0 +#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698 +#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699 +#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a +#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define mmVM_L2_CACHE_PARITY_CNTL 0x069b +#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define mmVM_L2_CGTT_CLK_CTRL 0x069e +#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2vcdec +// base address: 0x69b00 +#define mmVM_CONTEXT0_CNTL 0x06c0 +#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT1_CNTL 0x06c1 +#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT2_CNTL 0x06c2 +#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT3_CNTL 0x06c3 +#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT4_CNTL 0x06c4 +#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT5_CNTL 0x06c5 +#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT6_CNTL 0x06c6 +#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT7_CNTL 0x06c7 +#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT8_CNTL 0x06c8 +#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT9_CNTL 0x06c9 +#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT10_CNTL 0x06ca +#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT11_CNTL 0x06cb +#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT12_CNTL 0x06cc +#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT13_CNTL 0x06cd +#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT14_CNTL 0x06ce +#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 +#define mmVM_CONTEXT15_CNTL 0x06cf +#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 +#define mmVM_CONTEXTS_DISABLE 0x06d0 +#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_SEM 0x06d1 +#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_SEM 0x06d2 +#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_SEM 0x06d3 +#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_SEM 0x06d4 +#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_SEM 0x06d5 +#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_SEM 0x06d6 +#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_SEM 0x06d7 +#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_SEM 0x06d8 +#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_SEM 0x06d9 +#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_SEM 0x06da +#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_SEM 0x06db +#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_SEM 0x06dc +#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_SEM 0x06dd +#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_SEM 0x06de +#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_SEM 0x06df +#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_SEM 0x06e0 +#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_SEM 0x06e1 +#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_SEM 0x06e2 +#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_REQ 0x06e3 +#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_REQ 0x06e4 +#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_REQ 0x06e5 +#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_REQ 0x06e6 +#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_REQ 0x06e7 +#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_REQ 0x06e8 +#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_REQ 0x06e9 +#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_REQ 0x06ea +#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_REQ 0x06eb +#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_REQ 0x06ec +#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_REQ 0x06ed +#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_REQ 0x06ee +#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_REQ 0x06ef +#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_REQ 0x06f0 +#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_REQ 0x06f1 +#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_REQ 0x06f2 +#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_REQ 0x06f3 +#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_REQ 0x06f4 +#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ACK 0x06f5 +#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ACK 0x06f6 +#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ACK 0x06f7 +#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ACK 0x06f8 +#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ACK 0x06f9 +#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ACK 0x06fa +#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ACK 0x06fb +#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ACK 0x06fc +#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ACK 0x06fd +#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ACK 0x06fe +#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ACK 0x06ff +#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ACK 0x0700 +#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ACK 0x0701 +#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ACK 0x0702 +#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ACK 0x0703 +#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ACK 0x0704 +#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ACK 0x0705 +#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ACK 0x0706 +#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 +#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a +#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c +#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e +#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 +#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 +#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 +#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 +#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 +#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a +#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c +#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e +#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 +#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 +#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 +#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 +#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 +#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a +#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 +#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 +#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 +#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 +#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 +#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a +#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c +#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e +#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 +#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 +#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 +#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 +#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 +#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a +#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 +#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 +#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 +#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 +#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 +#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a +#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c +#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e +#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 +#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 +#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 +#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 +#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 +#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a +#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2pldec +// base address: 0x69e90 +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 +#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 +#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 +#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 +#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 +#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 +#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa +#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab +#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vml2prdec +// base address: 0x69ee0 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8 +#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9 +#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +// base address: 0x69f30 +#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc +#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd +#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce +#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf +#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 +#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 +#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 +#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 +#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 +#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 +#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 +#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 +#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 +#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 +#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da +#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 +#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db +#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 +#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc +#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_LO_0 0x07dd +#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_LO_1 0x07de +#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_LO_2 0x07df +#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_LO_3 0x07e0 +#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_HI_0 0x07e1 +#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_HI_1 0x07e2 +#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_HI_2 0x07e3 +#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0 +#define mmMC_VM_MARC_BASE_HI_3 0x07e4 +#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_LO_0 0x07e5 +#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_LO_1 0x07e6 +#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_LO_2 0x07e7 +#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_LO_3 0x07e8 +#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_HI_0 0x07e9 +#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_HI_1 0x07ea +#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_HI_2 0x07eb +#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 +#define mmMC_VM_MARC_RELOC_HI_3 0x07ec +#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_LO_0 0x07ed +#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_LO_1 0x07ee +#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_LO_2 0x07ef +#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_LO_3 0x07f0 +#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_HI_0 0x07f1 +#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_HI_1 0x07f2 +#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_HI_2 0x07f3 +#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0 +#define mmMC_VM_MARC_LEN_HI_3 0x07f4 +#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0 +#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5 +#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6 +#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL 0x07f7 +#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8 +#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9 +#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa +#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb +#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc +#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd +#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe +#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff +#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800 +#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801 +#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802 +#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803 +#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804 +#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805 +#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806 +#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 +#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807 +#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 +#define mmUTCL2_CGTT_CLK_CTRL 0x0808 +#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +// base address: 0x6a040 +#define mmMC_VM_NB_MMIOBASE 0x0810 +#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 +#define mmMC_VM_NB_MMIOLIMIT 0x0811 +#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 +#define mmMC_VM_NB_PCI_CTRL 0x0812 +#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 +#define mmMC_VM_NB_PCI_ARB 0x0813 +#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 +#define mmMC_VM_FB_OFFSET 0x0817 +#define mmMC_VM_FB_OFFSET_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define mmMC_VM_STEERING 0x081a +#define mmMC_VM_STEERING_BASE_IDX 0 +#define mmMC_SHARED_VIRT_RESET_REQ 0x081b +#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define mmMC_MEM_POWER_LS 0x081c +#define mmMC_MEM_POWER_LS_BASE_IDX 0 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e +#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define mmMC_VM_APT_CNTL 0x081f +#define mmMC_VM_APT_CNTL_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820 +#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821 +#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822 +#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +// base address: 0x6a0b0 +#define mmMC_VM_FB_LOCATION_BASE 0x082c +#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define mmMC_VM_FB_LOCATION_TOP 0x082d +#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define mmMC_VM_AGP_TOP 0x082e +#define mmMC_VM_AGP_TOP_BASE_IDX 0 +#define mmMC_VM_AGP_BOT 0x082f +#define mmMC_VM_AGP_BOT_BASE_IDX 0 +#define mmMC_VM_AGP_BASE 0x0830 +#define mmMC_VM_AGP_BASE_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831 +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832 +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define mmMC_VM_MX_L1_TLB_CNTL 0x0833 +#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +// base address: 0x6a100 +#define mmATC_L2_PERFCOUNTER_LO 0x0840 +#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define mmATC_L2_PERFCOUNTER_HI 0x0841 +#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +// base address: 0x6a120 +#define mmATC_L2_PERFCOUNTER0_CFG 0x0848 +#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmATC_L2_PERFCOUNTER1_CFG 0x0849 +#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a +#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h new file mode 100644 index 000000000000..8effec70a3c0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h @@ -0,0 +1,9790 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_1_SH_MASK_HEADER +#define _mmhub_9_1_SH_MASK_HEADER + + +// addressBlock: mmhub_dagbdec +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI16 +#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI17 +#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI18 +#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI19 +#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI20 +#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI21 +#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI22 +#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI23 +#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI24 +#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI25 +#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI26 +#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI27 +#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI28 +#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI29 +#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI30 +#define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI31 +#define DAGB0_RDCLI31__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI31__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI31__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI31__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI31__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI31__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI31__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI31__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI31__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI31__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI31__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI31__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI31__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI31__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST3 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC6_CNTL +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC7_CNTL +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI16 +#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI17 +#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI18 +#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI19 +#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI20 +#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI21 +#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI22 +#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI23 +#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI24 +#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI25 +#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI26 +#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI27 +#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI28 +#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI29 +#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI30 +#define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI31 +#define DAGB0_WRCLI31__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI31__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI31__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI31__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI31__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI31__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI31__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI31__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI31__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI31__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI31__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI31__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI31__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI31__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST2 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST3 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST2 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST3 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER3 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC6_CNTL +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC7_CNTL +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_RESERVE0 +#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE5 +#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE6 +#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE7 +#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE8 +#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE9 +#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE10 +#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE11 +#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE12 +#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE13 +#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE14 +#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE15 +#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE16 +#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE17 +#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE18 +#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE19 +#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE20 +#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE21 +#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE22 +#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE23 +#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE24 +#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE25 +#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE26 +#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE27 +#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE28 +#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE29 +#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE30 +#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE31 +#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE32 +#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE33 +#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE34 +#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE35 +#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE36 +#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE37 +#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE38 +#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE39 +#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE40 +#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE41 +#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE42 +#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE43 +#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE44 +#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE45 +#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE46 +#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE47 +#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE48 +#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE49 +#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE50 +#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE51 +#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE52 +#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE53 +#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE54 +#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE55 +#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE56 +#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE57 +#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE58 +#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE59 +#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE60 +#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE61 +#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE62 +#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE63 +#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE64 +#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE65 +#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE66 +#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE67 +#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE68 +#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE69 +#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE70 +#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE71 +#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE72 +#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE73 +#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE74 +#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE75 +#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE76 +#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE77 +#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE78 +#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE79 +#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE80 +#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE81 +#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE82 +#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE83 +#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE84 +#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE85 +#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE86 +#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE87 +#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE88 +#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE89 +#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE90 +#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE91 +#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE92 +#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE93 +#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE94 +#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE95 +#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE96 +#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE97 +#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE98 +#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE99 +#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE100 +#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE101 +#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_ea_mmeadec +//MMEA0_DRAM_RD_CLI2GRP_MAP0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_CLI2GRP_MAP1 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP1 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_GRP2VC_MAP +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_WR_GRP2VC_MAP +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_RD_LAZY +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//MMEA0_DRAM_WR_LAZY +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//MMEA0_DRAM_RD_CAM_CNTL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//MMEA0_DRAM_WR_CAM_CNTL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//MMEA0_DRAM_PAGE_BURST +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_AGE +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_WR_PRI_AGE +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_RD_PRI_QUEUING +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_QUEUING +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_FIXED +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_FIXED +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_URGENCY +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_WR_PRI_URGENCY +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_ADDRNORM_BASE_ADDR0 +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL +#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR1 +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR1 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL +#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR1 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA0_ADDRNORM_HOLE_CNTL +#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA0_ADDRDEC_BANK_CFG +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L +//MMEA0_ADDRDEC_MISC_CFG +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL +//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +//MMEA0_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//MMEA0_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_RM_SEL_CS01 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_CS23 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//MMEA0_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_RM_SEL_CS01 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_CS23 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_IO_RD_CLI2GRP_MAP0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_CLI2GRP_MAP1 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP1 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_COMBINE_FLUSH +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//MMEA0_IO_WR_COMBINE_FLUSH +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//MMEA0_IO_GROUP_BURST +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_AGE +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_WR_PRI_AGE +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_RD_PRI_QUEUING +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_QUEUING +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_FIXED +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_FIXED +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_URGENCY +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_WR_PRI_URGENCY +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_RD_PRI_URGENCY_MASK +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_WR_PRI_URGENCY_MASK +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_RD_PRI_QUANT_PRI1 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI2 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI3 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI1 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI2 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI3 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_SDP_ARB_DRAM +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +//MMEA0_SDP_ARB_FINAL +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +//MMEA0_SDP_DRAM_PRIORITY +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_IO_PRIORITY +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_CREDITS +#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA0_SDP_TAG_RESERVE0 +#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA0_SDP_TAG_RESERVE1 +#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA0_SDP_VCC_RESERVE0 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCC_RESERVE1 +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_VCD_RESERVE0 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCD_RESERVE1 +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_REQ_CNTL +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L +//MMEA0_MISC +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 +#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L +#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L +//MMEA0_LATENCY_SAMPLING +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA0_PERFCOUNTER_LO +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA0_PERFCOUNTER_HI +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA0_PERFCOUNTER0_CFG +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER1_CFG +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER_RSLT_CNTL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA0_EDC_CNT +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA0_EDC_CNT2 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA0_DSM_CNTL +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA0_DSM_CNTLA +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA0_DSM_CNTLB +//MMEA0_DSM_CNTL2 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA0_DSM_CNTL2A +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA0_DSM_CNTL2B +//MMEA0_CGTT_CLK_CTRL +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA0_EDC_MODE +#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA0_ERR_STATUS +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L +//MMEA0_MISC2 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +//MMEA1_DRAM_RD_CLI2GRP_MAP0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_CLI2GRP_MAP1 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP1 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_GRP2VC_MAP +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_WR_GRP2VC_MAP +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_RD_LAZY +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//MMEA1_DRAM_WR_LAZY +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +//MMEA1_DRAM_RD_CAM_CNTL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//MMEA1_DRAM_WR_CAM_CNTL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +//MMEA1_DRAM_PAGE_BURST +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_AGE +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_WR_PRI_AGE +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_RD_PRI_QUEUING +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_QUEUING +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_FIXED +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_FIXED +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_URGENCY +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_WR_PRI_URGENCY +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_ADDRNORM_BASE_ADDR0 +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL +#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR1 +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR1 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL +#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR1 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA1_ADDRNORM_HOLE_CNTL +#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA1_ADDRDEC_BANK_CFG +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L +//MMEA1_ADDRDEC_MISC_CFG +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL +//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +//MMEA1_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//MMEA1_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_RM_SEL_CS01 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_CS23 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +//MMEA1_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_RM_SEL_CS01 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_CS23 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_IO_RD_CLI2GRP_MAP0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_CLI2GRP_MAP1 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP1 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_COMBINE_FLUSH +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//MMEA1_IO_WR_COMBINE_FLUSH +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +//MMEA1_IO_GROUP_BURST +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_AGE +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_WR_PRI_AGE +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_RD_PRI_QUEUING +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_QUEUING +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_FIXED +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_FIXED +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_URGENCY +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_WR_PRI_URGENCY +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_RD_PRI_URGENCY_MASK +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_WR_PRI_URGENCY_MASK +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_RD_PRI_QUANT_PRI1 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI2 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI3 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI1 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI2 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI3 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_SDP_ARB_DRAM +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +//MMEA1_SDP_ARB_FINAL +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +//MMEA1_SDP_DRAM_PRIORITY +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_IO_PRIORITY +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_CREDITS +#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA1_SDP_TAG_RESERVE0 +#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA1_SDP_TAG_RESERVE1 +#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA1_SDP_VCC_RESERVE0 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCC_RESERVE1 +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_VCD_RESERVE0 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCD_RESERVE1 +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_REQ_CNTL +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L +//MMEA1_MISC +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 +#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L +#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L +//MMEA1_LATENCY_SAMPLING +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA1_PERFCOUNTER_LO +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA1_PERFCOUNTER_HI +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA1_PERFCOUNTER0_CFG +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER1_CFG +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER_RSLT_CNTL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA1_EDC_CNT +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA1_EDC_CNT2 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA1_DSM_CNTL +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA1_DSM_CNTLA +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA1_DSM_CNTLB +//MMEA1_DSM_CNTL2 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA1_DSM_CNTL2A +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA1_DSM_CNTL2B +//MMEA1_CGTT_CLK_CTRL +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA1_EDC_MODE +#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA1_ERR_STATUS +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L +//MMEA1_MISC2 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L + + +// addressBlock: mmhub_pctldec +//PCTL_MISC +#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 +#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 +#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 +#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb +#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc +#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd +#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe +#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L +#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L +#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L +#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L +#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L +#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L +#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L +//PCTL_MMHUB_DEEPSLEEP +#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f +#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +//PCTL_PG_IGNORE_DEEPSLEEP +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L +//PCTL_PG_DAGB +#define PCTL_PG_DAGB__DS0__SHIFT 0x0 +#define PCTL_PG_DAGB__DS1__SHIFT 0x1 +#define PCTL_PG_DAGB__DS2__SHIFT 0x2 +#define PCTL_PG_DAGB__DS3__SHIFT 0x3 +#define PCTL_PG_DAGB__DS4__SHIFT 0x4 +#define PCTL_PG_DAGB__DS5__SHIFT 0x5 +#define PCTL_PG_DAGB__DS6__SHIFT 0x6 +#define PCTL_PG_DAGB__DS7__SHIFT 0x7 +#define PCTL_PG_DAGB__DS8__SHIFT 0x8 +#define PCTL_PG_DAGB__DS9__SHIFT 0x9 +#define PCTL_PG_DAGB__DS10__SHIFT 0xa +#define PCTL_PG_DAGB__DS11__SHIFT 0xb +#define PCTL_PG_DAGB__DS12__SHIFT 0xc +#define PCTL_PG_DAGB__DS13__SHIFT 0xd +#define PCTL_PG_DAGB__DS14__SHIFT 0xe +#define PCTL_PG_DAGB__DS15__SHIFT 0xf +#define PCTL_PG_DAGB__DS16__SHIFT 0x10 +#define PCTL_PG_DAGB__DS0_MASK 0x00000001L +#define PCTL_PG_DAGB__DS1_MASK 0x00000002L +#define PCTL_PG_DAGB__DS2_MASK 0x00000004L +#define PCTL_PG_DAGB__DS3_MASK 0x00000008L +#define PCTL_PG_DAGB__DS4_MASK 0x00000010L +#define PCTL_PG_DAGB__DS5_MASK 0x00000020L +#define PCTL_PG_DAGB__DS6_MASK 0x00000040L +#define PCTL_PG_DAGB__DS7_MASK 0x00000080L +#define PCTL_PG_DAGB__DS8_MASK 0x00000100L +#define PCTL_PG_DAGB__DS9_MASK 0x00000200L +#define PCTL_PG_DAGB__DS10_MASK 0x00000400L +#define PCTL_PG_DAGB__DS11_MASK 0x00000800L +#define PCTL_PG_DAGB__DS12_MASK 0x00001000L +#define PCTL_PG_DAGB__DS13_MASK 0x00002000L +#define PCTL_PG_DAGB__DS14_MASK 0x00004000L +#define PCTL_PG_DAGB__DS15_MASK 0x00008000L +#define PCTL_PG_DAGB__DS16_MASK 0x00010000L +//PCTL0_RENG_RAM_INDEX +#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL0_RENG_RAM_DATA +#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_RENG_EXECUTE +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L +#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L +//PCTL0_MISC +#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL1_RENG_RAM_INDEX +#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_RENG_RAM_DATA +#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_RENG_EXECUTE +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L +#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L +//PCTL1_MISC +#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL2_RENG_RAM_INDEX +#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL2_RENG_RAM_DATA +#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL2_RENG_EXECUTE +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L +#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L +//PCTL2_MISC +#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L + + +// addressBlock: mmhub_l1tlb_vml1dec +//MC_VM_MX_L1_TLB0_STATUS +#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB1_STATUS +#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB2_STATUS +#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB3_STATUS +#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB4_STATUS +#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB5_STATUS +#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB6_STATUS +#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MC_VM_MX_L1_TLB7_STATUS +#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L + + +// addressBlock: mmhub_l1tlb_vml1pldec +//MC_VM_MX_L1_PERFCOUNTER0_CFG +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER1_CFG +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER2_CFG +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER3_CFG +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_vml1prdec +//MC_VM_MX_L1_PERFCOUNTER_LO +#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_MX_L1_PERFCOUNTER_HI +#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_l1tlb_vmtlspfdec +//VM_L2_SAW_CNTL +#define VM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define VM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L +#define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L +//VM_L2_SAW_CNTL2 +#define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L +#define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_SAW_CNTL3 +#define VM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_SAW_CNTL4 +#define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 +#define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 +#define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L +#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L +#define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L +//VM_L2_SAW_CONTEXT0_CNTL +#define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L +//VM_L2_SAW_CONTEXT0_CNTL2 +#define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_SAW_CONTEXTS_DISABLE +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_L2_SAW_PIPES_BUSY +#define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY__SHIFT 0x0 +#define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_utcl2_atcl2dec +//ATC_L2_CNTL +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +//ATC_L2_CNTL2 +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L +//ATC_L2_CACHE_DATA0 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATC_L2_CACHE_DATA1 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA2 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CNTL3 +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L +//ATC_L2_STATUS +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL +//ATC_L2_STATUS2 +#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//ATC_L2_MISC_CG +#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATC_L2_MEM_POWER_LS +#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATC_L2_CGTT_CLK_CTRL +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: mmhub_utcl2_vml2pfdec +//VM_L2_CNTL +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VM_L2_CNTL2 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_CNTL3 +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_STATUS +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VM_DUMMY_PAGE_FAULT_CNTL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_CNTL +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VM_L2_PROTECTION_FAULT_CNTL2 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_STATUS +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +//VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VM_L2_CNTL4 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +//VM_L2_MM_GROUP_RT_CLASSES +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VM_L2_BANK_SELECT_RESERVED_CID +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_BANK_SELECT_RESERVED_CID2 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_CACHE_PARITY_CNTL +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VM_L2_CGTT_CLK_CTRL +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: mmhub_utcl2_vml2vcdec +//VM_CONTEXT0_CNTL +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT1_CNTL +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT2_CNTL +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT3_CNTL +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT4_CNTL +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT5_CNTL +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT6_CNTL +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT7_CNTL +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT8_CNTL +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT9_CNTL +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT10_CNTL +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT11_CNTL +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT12_CNTL +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT13_CNTL +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT14_CNTL +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXT15_CNTL +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VM_CONTEXTS_DISABLE +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_INVALIDATE_ENG0_SEM +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG1_SEM +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG2_SEM +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG3_SEM +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG4_SEM +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG5_SEM +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG6_SEM +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG7_SEM +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG8_SEM +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG9_SEM +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG10_SEM +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG11_SEM +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG12_SEM +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG13_SEM +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG14_SEM +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG15_SEM +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG16_SEM +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG17_SEM +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG0_REQ +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG1_REQ +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG2_REQ +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG3_REQ +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG4_REQ +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG5_REQ +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG6_REQ +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG7_REQ +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG8_REQ +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG9_REQ +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG10_REQ +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG11_REQ +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG12_REQ +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG13_REQ +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG14_REQ +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG15_REQ +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG16_REQ +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG17_REQ +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VM_INVALIDATE_ENG0_ACK +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG1_ACK +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG2_ACK +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG3_ACK +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG4_ACK +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG5_ACK +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG6_ACK +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG7_ACK +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG8_ACK +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG9_ACK +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG10_ACK +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG11_ACK +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG12_ACK +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG13_ACK +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG14_ACK +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG15_ACK +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG16_ACK +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG17_ACK +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: mmhub_utcl2_vml2pldec +//MC_VM_L2_PERFCOUNTER0_CFG +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER1_CFG +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER2_CFG +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER3_CFG +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER4_CFG +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER5_CFG +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER6_CFG +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER7_CFG +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2prdec +//MC_VM_L2_PERFCOUNTER_LO +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_L2_PERFCOUNTER_HI +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +//MC_VM_FB_SIZE_OFFSET_VF0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF1 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF2 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF3 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF4 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF5 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF6 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF7 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF8 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF9 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF11 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF12 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF13 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF14 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF15 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//VM_IOMMU_MMIO_CNTRL_1 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L +//MC_VM_MARC_BASE_LO_0 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_1 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_2 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_3 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_HI_0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_1 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_2 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_3 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_LO_0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_2 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_3 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_HI_0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_1 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_2 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_3 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_LO_0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_1 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_2 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_3 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_HI_0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_1 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_2 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_3 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VM_IOMMU_CONTROL_REGISTER +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//VM_PCIE_ATS_CNTL +#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_0 +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_1 +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_2 +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_3 +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_4 +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_5 +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_6 +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_7 +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_8 +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_9 +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_10 +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_11 +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_12 +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_13 +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_14 +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_15 +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//UTCL2_CGTT_CLK_CTRL +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +//MC_VM_NB_MMIOBASE +#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MC_VM_NB_MMIOLIMIT +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MC_VM_NB_PCI_CTRL +#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MC_VM_NB_PCI_ARB +#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//MC_VM_FB_OFFSET +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MC_VM_STEERING +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MC_SHARED_VIRT_RESET_REQ +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MC_MEM_POWER_LS +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MC_VM_APT_CNTL +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +//MC_VM_LOCAL_HBM_ADDRESS_START +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_END +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +//MC_VM_FB_LOCATION_BASE +#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MC_VM_FB_LOCATION_TOP +#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_TOP +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_BOT +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MC_VM_AGP_BASE +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_MX_L1_TLB_CNTL +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +//ATC_L2_PERFCOUNTER_LO +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_L2_PERFCOUNTER_HI +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +//ATC_L2_PERFCOUNTER0_CFG +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER1_CFG +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h new file mode 100644 index 000000000000..f087a2bf3863 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_10_0_DEFAULT_HEADER +#define _mp_10_0_DEFAULT_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000 +#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000 +#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000 +#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000 +#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 + + +// addressBlock: mp_SmuMp1_SmnDec +#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000 +#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000 +#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000 +#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000 +#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 +#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h new file mode 100644 index 000000000000..1063e5e8ea0e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_10_0_OFFSET_HEADER +#define _mp_10_0_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define mmMP0_SMN_C2PMSG_32 0x0060 +#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_33 0x0061 +#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_34 0x0062 +#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_35 0x0063 +#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_36 0x0064 +#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_37 0x0065 +#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_38 0x0066 +#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_39 0x0067 +#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_40 0x0068 +#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_41 0x0069 +#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_42 0x006a +#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_43 0x006b +#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_44 0x006c +#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_45 0x006d +#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_46 0x006e +#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_47 0x006f +#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_48 0x0070 +#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_49 0x0071 +#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_50 0x0072 +#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_51 0x0073 +#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_52 0x0074 +#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_53 0x0075 +#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_54 0x0076 +#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_55 0x0077 +#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_56 0x0078 +#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_57 0x0079 +#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_58 0x007a +#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_59 0x007b +#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_60 0x007c +#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_61 0x007d +#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_62 0x007e +#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_63 0x007f +#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_64 0x0080 +#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_65 0x0081 +#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_66 0x0082 +#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_67 0x0083 +#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_68 0x0084 +#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_69 0x0085 +#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_70 0x0086 +#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_71 0x0087 +#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_72 0x0088 +#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_73 0x0089 +#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_74 0x008a +#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_75 0x008b +#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_76 0x008c +#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_77 0x008d +#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_78 0x008e +#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_79 0x008f +#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_80 0x0090 +#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_81 0x0091 +#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_82 0x0092 +#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_83 0x0093 +#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_84 0x0094 +#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_85 0x0095 +#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_86 0x0096 +#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_87 0x0097 +#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_88 0x0098 +#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_89 0x0099 +#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_90 0x009a +#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_91 0x009b +#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_92 0x009c +#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_93 0x009d +#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_94 0x009e +#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_95 0x009f +#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_96 0x00a0 +#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_97 0x00a1 +#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_98 0x00a2 +#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_99 0x00a3 +#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_100 0x00a4 +#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_101 0x00a5 +#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_102 0x00a6 +#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_103 0x00a7 +#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP0_SMN_IH_CREDIT 0x00c1 +#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT 0x00c2 +#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define mmMP1_SMN_C2PMSG_32 0x0260 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_33 0x0261 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_34 0x0262 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_35 0x0263 +#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_36 0x0264 +#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_37 0x0265 +#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_38 0x0266 +#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_39 0x0267 +#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_40 0x0268 +#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_41 0x0269 +#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_42 0x026a +#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_43 0x026b +#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_44 0x026c +#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_45 0x026d +#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_46 0x026e +#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_47 0x026f +#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_48 0x0270 +#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_49 0x0271 +#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_50 0x0272 +#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_51 0x0273 +#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_52 0x0274 +#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_55 0x0277 +#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_56 0x0278 +#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_57 0x0279 +#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_58 0x027a +#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_59 0x027b +#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_60 0x027c +#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_61 0x027d +#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_62 0x027e +#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_64 0x0280 +#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_65 0x0281 +#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_67 0x0283 +#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_68 0x0284 +#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_69 0x0285 +#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_70 0x0286 +#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_71 0x0287 +#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_72 0x0288 +#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_73 0x0289 +#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_74 0x028a +#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_76 0x028c +#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_77 0x028d +#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_78 0x028e +#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_79 0x028f +#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_80 0x0290 +#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_81 0x0291 +#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_83 0x0293 +#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_84 0x0294 +#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_85 0x0295 +#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_86 0x0296 +#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_87 0x0297 +#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_88 0x0298 +#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_89 0x0299 +#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_91 0x029b +#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_92 0x029c +#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_93 0x029d +#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_94 0x029e +#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_95 0x029f +#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_96 0x02a0 +#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_97 0x02a1 +#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_98 0x02a2 +#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_99 0x02a3 +#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_100 0x02a4 +#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_101 0x02a5 +#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_102 0x02a6 +#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_103 0x02a7 +#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP1_SMN_IH_CREDIT 0x02c1 +#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT 0x02c2 +#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define mmMP1_SMN_FPS_CNT 0x02c4 +#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h new file mode 100644 index 000000000000..9b0c8c575160 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h @@ -0,0 +1,886 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_10_0_SH_MASK_HEADER +#define _mp_10_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMp0Pub_CruDec +//MP0_ACTIVE_FCN_ID +#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_IH_CREDIT +#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_IH_SW_INT +#define MP0_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_IH_SW_INT_CTRL +#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MP1_C2PMSG_0 +#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_1 +#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_2 +#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_3 +#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_4 +#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_5 +#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_6 +#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_7 +#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_8 +#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_9 +#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_10 +#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_11 +#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_12 +#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_13 +#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_14 +#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_15 +#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_16 +#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_17 +#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_18 +#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_19 +#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_20 +#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_21 +#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_22 +#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_23 +#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_24 +#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_25 +#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_26 +#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_27 +#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_28 +#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_29 +#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_30 +#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_31 +#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_0 +#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_1 +#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_2 +#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_3 +#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_INTEN +#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP1_P2CMSG_INTSTS +#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_C2PMSG_32 +#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_33 +#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_34 +#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_35 +#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_36 +#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_37 +#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_38 +#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_39 +#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_40 +#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_41 +#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_42 +#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_43 +#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_44 +#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_45 +#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_46 +#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_47 +#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_48 +#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_49 +#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_50 +#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_51 +#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_52 +#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_53 +#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_54 +#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_55 +#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_56 +#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_57 +#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_58 +#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_59 +#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_60 +#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_61 +#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_62 +#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_63 +#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_64 +#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_65 +#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_66 +#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_67 +#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_68 +#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_69 +#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_70 +#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_71 +#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_72 +#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_73 +#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_74 +#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_75 +#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_76 +#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_77 +#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_78 +#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_79 +#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_80 +#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_81 +#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_82 +#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_83 +#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_84 +#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_85 +#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_86 +#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_87 +#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_88 +#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_89 +#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_90 +#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_91 +#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_92 +#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_93 +#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_94 +#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_95 +#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_96 +#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_97 +#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_98 +#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_99 +#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_100 +#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_101 +#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_102 +#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_103 +#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACTIVE_FCN_ID +#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_IH_CREDIT +#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_IH_SW_INT +#define MP1_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_IH_SW_INT_CTRL +#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_FPS_CNT +#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h new file mode 100644 index 000000000000..f5fc31ffcd73 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h @@ -0,0 +1,14865 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _nbio_7_0_DEFAULT_HEADER +#define _nbio_7_0_DEFAULT_HEADER + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +#define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_HEADER_DEFAULT 0x00000080 +#define cfgNB_NBCFG0_NB_ADAPTER_ID_DEFAULT 0x15d01022 +#define cfgNB_NBCFG0_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_HEADER_W_DEFAULT 0x00000080 +#define cfgNB_NBCFG0_NB_PCI_CTRL_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_0_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_0_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_0_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_2_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_3_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_4_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_PCI_ARB_DEFAULT 0x00000108 +#define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_2_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_2_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_3_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_3_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_4_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_4_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_5_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_5_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 +#define cfgNB_NBCFG0_NB_SMN_INDEX_6_DEFAULT 0x00000000 +#define cfgNB_NBCFG0_NB_SMN_DATA_6_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +#define cfgIOMMU_L2_0_IOMMU_VENDOR_ID_DEFAULT 0x00001022 +#define cfgIOMMU_L2_0_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 +#define cfgIOMMU_L2_0_IOMMU_COMMAND_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_STATUS_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_REVISION_ID_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_REGPROG_INF_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_SUB_CLASS_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_BASE_CODE_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CACHE_LINE_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_LATENCY_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_HEADER_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_BIST_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 +#define cfgIOMMU_L2_0_IOMMU_CAP_HEADER_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CAP_RANGE_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_DEFAULT 0x00003000 +#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 +#define cfgIOMMU_L2_0_IOMMU_MSI_CAP_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_MSI_DATA_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_CONTROL_W_DEFAULT 0x00002b01 +#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada +#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf +#define cfgIOMMU_L2_0_IOMMU_RANGE_W_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 +#define cfgIOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 +#define cfgIOMMU_L2_0_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 +#define cfgIOMMU_L2_0_SMMU_AIDR_W_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +#define cfgBIF_CFG_DEV0_RC0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_DEFAULT 0x00000042 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_DEFAULT 0x00002001 +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +#define cfgBIF_CFG_DEV1_RC0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIF_CFG_DEV1_RC0_INTERRUPT_PIN_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_DEFAULT 0x00000042 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV1_RC0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_LINK_STATUS_DEFAULT 0x00002001 +#define cfgBIF_CFG_DEV1_RC0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV1_RC0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV1_RC0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SSID_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +#define cfgNB_PCIEDUMMY0_0_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY0_0_STATUS_COMMAND_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY0_0_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY0_0_HEADER_TYPE_DEFAULT 0x00800000 +#define cfgNB_PCIEDUMMY0_0_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +#define cfgNB_PCIEDUMMY1_0_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY1_0_STATUS_COMMAND_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY1_0_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define cfgNB_PCIEDUMMY1_0_HEADER_TYPE_DEFAULT 0x00800000 +#define cfgNB_PCIEDUMMY1_0_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +#define cfgVENDOR_ID_DEFAULT 0x00000000 +#define cfgDEVICE_ID_DEFAULT 0x00000000 +#define cfgCOMMAND_DEFAULT 0x00000000 +#define cfgSTATUS_DEFAULT 0x00000000 +#define cfgREVISION_ID_DEFAULT 0x00000000 +#define cfgPROG_INTERFACE_DEFAULT 0x00000000 +#define cfgSUB_CLASS_DEFAULT 0x00000000 +#define cfgBASE_CLASS_DEFAULT 0x00000000 +#define cfgCACHE_LINE_DEFAULT 0x00000000 +#define cfgLATENCY_DEFAULT 0x00000000 +#define cfgHEADER_DEFAULT 0x00000000 +#define cfgBIST_DEFAULT 0x00000000 +#define cfgBASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBASE_ADDR_6_DEFAULT 0x00000000 +#define cfgADAPTER_ID_DEFAULT 0x00000000 +#define cfgROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgCAP_PTR_DEFAULT 0x00000000 +#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgINTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgMIN_GRANT_DEFAULT 0x00000000 +#define cfgMAX_LATENCY_DEFAULT 0x00000000 +#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgPMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgPMI_CAP_DEFAULT 0x00000000 +#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgPCIE_CAP_DEFAULT 0x00000002 +#define cfgDEVICE_CAP_DEFAULT 0x10000000 +#define cfgDEVICE_CNTL_DEFAULT 0x00002810 +#define cfgDEVICE_STATUS_DEFAULT 0x00000000 +#define cfgLINK_CAP_DEFAULT 0x00011c03 +#define cfgLINK_CNTL_DEFAULT 0x00000000 +#define cfgLINK_STATUS_DEFAULT 0x00000001 +#define cfgDEVICE_CAP2_DEFAULT 0x00000000 +#define cfgDEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgDEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgLINK_CAP2_DEFAULT 0x0000000e +#define cfgLINK_CNTL2_DEFAULT 0x00000003 +#define cfgLINK_STATUS2_DEFAULT 0x00000000 +#define cfgSLOT_CAP2_DEFAULT 0x00000000 +#define cfgSLOT_CNTL2_DEFAULT 0x00000000 +#define cfgSLOT_STATUS2_DEFAULT 0x00000000 +#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgMSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgMSI_MASK_DEFAULT 0x00000000 +#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgMSI_MASK_64_DEFAULT 0x00000000 +#define cfgMSI_PENDING_DEFAULT 0x00000000 +#define cfgMSI_PENDING_64_DEFAULT 0x00000000 +#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgMSIX_TABLE_DEFAULT 0x00000000 +#define cfgMSIX_PBA_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 +#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgPCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +#define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +#define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +#define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +#define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_HEADER_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MIN_GRANT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SBRN_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_FLADJ_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV1_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP_DEFAULT 0x10000000 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_PBA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +#define cfgBIFPLR0_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR0_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR0_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR0_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR0_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR0_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR0_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR0_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR0_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR0_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR0_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR0_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR0_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +#define cfgBIFPLR1_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR1_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR1_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR1_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR1_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR1_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR1_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR1_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR1_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR1_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR1_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR1_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR1_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +#define cfgBIFPLR2_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR2_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR2_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR2_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR2_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR2_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR2_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR2_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR2_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR2_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR2_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR2_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR2_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR2_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +#define cfgBIFPLR3_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR3_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR3_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR3_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR3_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR3_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR3_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR3_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR3_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR3_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR3_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR3_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR3_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR3_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR3_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +#define cfgBIFPLR4_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR4_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR4_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR4_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR4_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR4_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR4_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR4_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR4_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR4_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR4_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR4_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR4_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR4_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR4_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +#define cfgBIFPLR5_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR5_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR5_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR5_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR5_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR5_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR5_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR5_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR5_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR5_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR5_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR5_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR5_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR5_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR5_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +#define cfgBIFPLR6_0_VENDOR_ID_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_DEVICE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_COMMAND_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_REVISION_ID_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PROG_INTERFACE_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SUB_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_BASE_CLASS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_CACHE_LINE_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_HEADER_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_BIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SECONDARY_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_CAP_PTR_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_INTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgBIFPLR6_0_INTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PMI_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgBIFPLR6_0_PCIE_CAP_DEFAULT 0x00000002 +#define cfgBIFPLR6_0_DEVICE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_DEVICE_CNTL_DEFAULT 0x00002810 +#define cfgBIFPLR6_0_DEVICE_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_LINK_CAP_DEFAULT 0x00011c03 +#define cfgBIFPLR6_0_LINK_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_LINK_STATUS_DEFAULT 0x00000001 +#define cfgBIFPLR6_0_SLOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SLOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SLOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_ROOT_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_ROOT_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_ROOT_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_DEVICE_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_DEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_DEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_LINK_CAP2_DEFAULT 0x0000000e +#define cfgBIFPLR6_0_LINK_CNTL2_DEFAULT 0x00000003 +#define cfgBIFPLR6_0_LINK_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SLOT_CAP2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SLOT_CNTL2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SLOT_STATUS2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgBIFPLR6_0_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define cfgBIFPLR6_0_SSID_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MAP_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgBIFPLR6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define cfgBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define cfgBIFPLR6_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define cfgBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgBIFPLR6_0_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgBIFPLR6_0_PCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define cfgBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define cfgBIFPLR6_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_dbgu0_dbgudec +#define mmport_a_addr_DEFAULT 0x00000000 +#define mmport_a_data_lo_DEFAULT 0x00000000 +#define mmport_a_data_hi_DEFAULT 0x00000000 +#define mmport_b_addr_DEFAULT 0x00000000 +#define mmport_b_data_lo_DEFAULT 0x00000000 +#define mmport_b_data_hi_DEFAULT 0x00000000 +#define mmport_c_addr_DEFAULT 0x00000000 +#define mmport_c_data_lo_DEFAULT 0x00000000 +#define mmport_c_data_hi_DEFAULT 0x00000000 +#define mmport_d_addr_DEFAULT 0x00000000 +#define mmport_d_data_lo_DEFAULT 0x00000000 +#define mmport_d_data_hi_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +#define smnGDC0_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f +#define smnGDC0_SHUB_REGS_IF_CTL_DEFAULT 0x00000000 +#define smnGDC0_NGDC_RESERVED_0_DEFAULT 0x00000000 +#define smnGDC0_NGDC_RESERVED_1_DEFAULT 0x00000000 +#define smnGDC0_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f +#define smnGDC0_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC0_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC0_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC0_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC0_ATDMA_MISC_CNTL_DEFAULT 0x04040001 +#define smnGDC0_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 +#define smnGDC0_S2A_MISC_CNTL_DEFAULT 0x00000000 +#define smnGDC0_GDC_PG_MISC_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_syshub_mmreg_direct_syshubdirect +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL_DEFAULT 0x00082000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER_DEFAULT 0x00000100 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080 +#define smnSYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH_DEFAULT 0x00000040 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 +#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080 +#define smnSYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_nbif_sion_SIONDEC +#define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define smnSION_CNTL_REG0_DEFAULT 0x00000000 +#define smnSION_CNTL_REG1_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC +#define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000 +#define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000 +#define smnSHUB_LINK_RESET_DEFAULT 0x00000000 +#define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 +#define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b +#define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 +#define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000 +#define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001 + + +// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk +#define smnGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000080 +#define smnGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000080 +#define smnGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000080 +#define smnGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000080 +#define smnGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000080 +#define smnGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00002200 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EFR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EFR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1_DEFAULT 0x08000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSFX_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSCX_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSSX_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_ioapicmio_ioapic_miodec +#define smnIOAPICMIO_INDEX_DEFAULT 0x00000000 +#define smnIOAPICMIO_DATA_DEFAULT 0x00000000 +#define smnIRQ_PIN_ASSERTION_REGISTER_DEFAULT 0x00000000 +#define smnEOI_REGISTER_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_ioapicmioindex_ioapic_mioindexdec +#define smnIOAPIC_ID_REGISTER_DEFAULT 0x00000000 +#define smnIOAPIC_VERSION_REGISTER_DEFAULT 0x00000000 +#define smnIOAPIC_ARBITRATION_REGISTER_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_0_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_0_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_1_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_1_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_2_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_2_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_3_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_3_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_4_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_4_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_5_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_5_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_6_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_6_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_7_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_7_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_8_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_8_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_9_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_9_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_10_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_10_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_11_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_11_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_12_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_12_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_13_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_13_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_14_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_14_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_15_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_15_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_16_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_16_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_17_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_17_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_18_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_18_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_19_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_19_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_20_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_20_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_21_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_21_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_22_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_22_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_23_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_23_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_24_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_24_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_25_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_25_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_26_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_26_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_27_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_27_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_28_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_28_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_29_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_29_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_30_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_30_DEFAULT 0x00000000 +#define smnREDIRECTION_TABLE_ENTRY_LOW_31_DEFAULT 0x00010000 +#define smnREDIRECTION_TABLE_ENTRY_HIGH_31_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +#define smnBIF_CFG_DEV0_RC1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_RC1_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_RC1_PCIE_CAP_DEFAULT 0x00000042 +#define smnBIF_CFG_DEV0_RC1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_RC1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_RC1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_LINK_STATUS_DEFAULT 0x00002001 +#define smnBIF_CFG_DEV0_RC1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_RC1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_RC1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_RC1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SSID_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +#define smnBIF_CFG_DEV1_RC1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV1_RC1_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_RC1_PCIE_CAP_DEFAULT 0x00000042 +#define smnBIF_CFG_DEV1_RC1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_RC1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_RC1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_LINK_STATUS_DEFAULT 0x00002001 +#define smnBIF_CFG_DEV1_RC1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_RC1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_RC1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_RC1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SSID_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +#define smnBIF_BX_PF0_MM_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MM_DATA_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MM_INDEX_HI_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +#define smnBIF_BX_PF0_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SYSHUB_DATA_OVLP_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_PCIE_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_PCIE_DATA_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_PCIE_INDEX2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_PCIE_DATA2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_4_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_5_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_6_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_7_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_8_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_9_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_10_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_11_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_12_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_13_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_14_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIOS_SCRATCH_15_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +#define smnRCC_EP_DEV0_0_EP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define smnRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +#define smnRCC_DWN_DEV0_0_DN_PCIE_RESERVED_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_0_DN_PCIE_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +#define smnRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_DWNP_DEV0_0_PCIE_RX_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +#define smnBIF_BX_PF0_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_SCRATCH0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_SCRATCH1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BX_RESET_EN_DEFAULT 0x00010003 +#define smnBIF_BX_PF0_MM_CFGREGS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BX_RESET_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_INTERRUPT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0 +#define smnBIF_BX_PF0_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_DOORBELL_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_FB_EN_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f +#define smnBIF_BX_PF0_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BACO_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 +#define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 +#define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 +#define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 +#define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 +#define smnBIF_BX_PF0_MEM_TYPE_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 +#define smnBIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 +#define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc +#define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 +#define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c +#define smnBIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c +#define smnBIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 +#define smnBIF_BX_PF0_BIF_RB_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RB_BASE_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RB_RPTR_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RB_WPTR_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF0_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 +#define smnBIF_BX_PF0_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 +#define smnBIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 +#define smnBIF_BX_PF0_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +#define smnBIF_BX_PF0_BIF_BME_STATUS_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 +#define smnBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_TRANS_PENDING_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_CONTROL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +#define smnSHADOW_COMMAND_DEFAULT 0x00000000 +#define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnSUC_INDEX_DEFAULT 0x00000000 +#define smnSUC_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +#define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 +#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +#define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +#define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC +#define smnRCC_EP_DEV1_EP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_EP_DEV1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 +#define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnRCC_EP_DEV1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_EP_DEV1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define smnRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC +#define smnRCC_DWN_DEV1_DN_PCIE_RESERVED_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV1_DN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV1_DN_PCIE_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_DWN_DEV1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC +#define smnRCC_DWNP_DEV1_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_DWNP_DEV1_PCIE_RX_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV1_PCIE_LC_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal +#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd + + +// addressBlock: nbio_nbif0_bif_bx_pf_SUMDEC +#define smnSUM_INDEX_DEFAULT 0x00000000 +#define smnSUM_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk +#define smnMISC_SCRATCH_DEFAULT 0x00000000 +#define smnINTR_LINE_POLARITY_DEFAULT 0x00000000 +#define smnINTR_LINE_ENABLE_DEFAULT 0x00000000 +#define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf +#define smnBIFC_MISC_CTRL0_DEFAULT 0x08000004 +#define smnBIFC_MISC_CTRL1_DEFAULT 0xa0108c04 +#define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000 +#define smnBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5_DEFAULT 0x00000000 +#define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7_DEFAULT 0x00000000 +#define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000 +#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +#define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +#define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 +#define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 +#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 +#define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000080 +#define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 +#define smnSMN_MST_CNTL0_DEFAULT 0x00000001 +#define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000 +#define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000 +#define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +#define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +#define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 +#define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 +#define smnBME_DUMMY_CNTL_0_DEFAULT 0xaaaaaaaa +#define smnBIFC_THT_CNTL_DEFAULT 0x00000222 +#define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000 +#define smnBIFC_GSI_CNTL_DEFAULT 0x000017c0 +#define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 +#define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f +#define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 +#define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 +#define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 +#define smnNBIF_PGMST_CTRL_DEFAULT 0x00000000 +#define smnNBIF_PGSLV_CTRL_DEFAULT 0x00000004 +#define smnNBIF_PG_MISC_CTRL_DEFAULT 0x14006084 +#define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000 +#define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000 +#define smnSMN_MST_CNTL1_DEFAULT 0x00000000 +#define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000 +#define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f +#define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 +#define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00040404 +#define smnBIF_GMI_CPLBUF_WR_CTRL_DEFAULT 0x00008884 +#define smnBIF_GMI_CPLBUF_RD_CTRL_DEFAULT 0x00008008 + + +// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +#define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_psp_RCCPFCDEC +#define smnRCC_PFC_PSP_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_usb3_0_RCCPFCDEC +#define smnRCC_PFC_USB3_0_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_usb3_1_RCCPFCDEC +#define smnRCC_PFC_USB3_1_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_acp_RCCPFCDEC +#define smnRCC_PFC_ACP_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_az_RCCPFCDEC +#define smnRCC_PFC_AZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_mp2_RCCPFCDEC +#define smnRCC_PFC_MP2_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_sata_RCCPFCDEC +#define smnRCC_PFC_SATA_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_gbe0_RCCPFCDEC +#define smnRCC_PFC_GBE0_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_pfc_gbe1_RCCPFCDEC +#define smnRCC_PFC_GBE1_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define smnRCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk +#define smnHARD_RST_CTRL_DEFAULT 0xb0000055 +#define smnRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 +#define smnSELF_SOFT_RST_DEFAULT 0x00000000 +#define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000 +#define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648 +#define smnBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 +#define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900 +#define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9 +#define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 +#define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 +#define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 +#define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000 +#define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 +#define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 +#define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 +#define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x0000ffff +#define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000 +#define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 +#define smnBIF_PF_FLR_RST_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF0_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnDEV1_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 +#define smnBIF_DEV1_PF0_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF1_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF2_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF3_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF4_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF5_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF6_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_DEV1_PF7_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnDEV1_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnDEV1_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 +#define smnBIF_PORT1_DSTATE_VALUE_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk +#define smnBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000080 +#define smnBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000080 +#define smnBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000080 +#define smnBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 +#define smnBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 +#define smnBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF0_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF0_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF0_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF0_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF2_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF2_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF3_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF3_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF4_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF4_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF4_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF4_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF5_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF5_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF5_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF5_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF6_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF6_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF6_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF6_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF7_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF7_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF7_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF7_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF0_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF0_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF0_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF0_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF1_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF1_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF2_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF2_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF2_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF2_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXTDEC +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_psp_MSIXTDEC +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXTDEC +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXTDEC +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXTDEC +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXTDEC +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXTDEC +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXPDEC +#define smnPCIEMSIX_AMDGFX_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_psp_MSIXPDEC +#define smnPCIEMSIX_PSP_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXPDEC +#define smnPCIEMSIX_USB3_0_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXPDEC +#define smnPCIEMSIX_USB3_1_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXPDEC +#define smnPCIEMSIX_MP2_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXPDEC +#define smnPCIEMSIX_GBE0_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXPDEC +#define smnPCIEMSIX_GBE1_PCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +#define smnBIFPLR0_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR0_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR0_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR0_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR0_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR0_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR0_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR0_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR0_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR0_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR0_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR0_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR0_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR0_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR0_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR0_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR0_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR0_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR0_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR0_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR0_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR0_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR0_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR0_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +#define smnBIFPLR1_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR1_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR1_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR1_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR1_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR1_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR1_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR1_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR1_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR1_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR1_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR1_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR1_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR1_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR1_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR1_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR1_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR1_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR1_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR1_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR1_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR1_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR1_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR1_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +#define smnBIFPLR2_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR2_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR2_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR2_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR2_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR2_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR2_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR2_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR2_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR2_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR2_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR2_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR2_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR2_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR2_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR2_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR2_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR2_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR2_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR2_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR2_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR2_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR2_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR2_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR2_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR2_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR2_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +#define smnBIFPLR3_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR3_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR3_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR3_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR3_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR3_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR3_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR3_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR3_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR3_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR3_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR3_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR3_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR3_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR3_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR3_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR3_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR3_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR3_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR3_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR3_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR3_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR3_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR3_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR3_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR3_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR3_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR3_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +#define smnBIFPLR4_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR4_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR4_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR4_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR4_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR4_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR4_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR4_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR4_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR4_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR4_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR4_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR4_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR4_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR4_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR4_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR4_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR4_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR4_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR4_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR4_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR4_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR4_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR4_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR4_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR4_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR4_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR4_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +#define smnBIFPLR5_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR5_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR5_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR5_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR5_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR5_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR5_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR5_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR5_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR5_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR5_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR5_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR5_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR5_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR5_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR5_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR5_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR5_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR5_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR5_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR5_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR5_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR5_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR5_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR5_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR5_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR5_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR5_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +#define smnBIFPLR6_1_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_1_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_1_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR6_1_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR6_1_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR6_1_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR6_1_BIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR6_1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR6_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_1_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR6_1_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR6_1_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR6_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR6_1_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR6_1_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR6_1_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR6_1_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR6_1_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR6_1_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR6_1_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR6_1_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR6_1_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR6_1_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR6_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR6_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR6_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR6_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR6_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR6_1_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR6_1_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR6_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR6_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR6_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp0_pciedir_p +#define smnBIFP0_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP0_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP0_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP0_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP0_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP0_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP0_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP0_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP0_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP0_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP0_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP0_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP0_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP0_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP0_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP0_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP0_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP0_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP0_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP0_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP0_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP0_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP0_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP0_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP0_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP0_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp1_pciedir_p +#define smnBIFP1_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP1_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP1_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP1_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP1_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP1_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP1_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP1_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP1_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP1_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP1_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP1_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP1_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP1_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP1_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP1_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP1_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP1_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP1_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP1_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP1_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP1_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP1_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP1_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP1_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP1_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP1_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp2_pciedir_p +#define smnBIFP2_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP2_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP2_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP2_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP2_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP2_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP2_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP2_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP2_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP2_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP2_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP2_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP2_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP2_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP2_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP2_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP2_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP2_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP2_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP2_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP2_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP2_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP2_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP2_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP2_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP2_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP2_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp3_pciedir_p +#define smnBIFP3_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP3_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP3_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP3_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP3_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP3_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP3_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP3_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP3_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP3_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP3_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP3_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP3_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP3_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP3_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP3_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP3_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP3_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP3_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP3_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP3_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP3_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP3_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP3_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP3_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP3_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP3_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp4_pciedir_p +#define smnBIFP4_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP4_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP4_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP4_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP4_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP4_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP4_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP4_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP4_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP4_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP4_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP4_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP4_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP4_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP4_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP4_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP4_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP4_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP4_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP4_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP4_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP4_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP4_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP4_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP4_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP4_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP4_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp5_pciedir_p +#define smnBIFP5_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP5_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP5_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP5_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP5_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP5_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP5_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP5_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP5_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP5_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP5_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP5_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP5_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP5_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP5_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP5_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP5_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP5_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP5_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP5_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP5_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP5_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP5_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP5_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP5_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP5_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP5_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifp6_pciedir_p +#define smnBIFP6_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_SCRATCH_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_PORT_CNTL_DEFAULT 0x00010009 +#define smnBIFP6_PCIE_TX_CNTL_DEFAULT 0x00508000 +#define smnBIFP6_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 +#define smnBIFP6_PCIE_TX_SEQ_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_REPLAY_DEFAULT 0x00900003 +#define smnBIFP6_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 +#define smnBIFP6_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_FC_P_DEFAULT 0x00000208 +#define smnBIFP6_PCIE_FC_NP_DEFAULT 0x00000202 +#define smnBIFP6_PCIE_FC_CPL_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnBIFP6_PCIE_RX_CNTL_DEFAULT 0x01084000 +#define smnBIFP6_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_RX_CNTL3_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_CNTL_DEFAULT 0x40010030 +#define smnBIFP6_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 +#define smnBIFP6_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 +#define smnBIFP6_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c +#define smnBIFP6_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 +#define smnBIFP6_PCIE_LC_STATE0_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_STATE1_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_STATE2_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_STATE3_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_STATE4_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_STATE5_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_CNTL2_DEFAULT 0x96180280 +#define smnBIFP6_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 +#define smnBIFP6_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_CNTL3_DEFAULT 0x2850a020 +#define smnBIFP6_PCIE_LC_CNTL4_DEFAULT 0x0340048c +#define smnBIFP6_PCIE_LC_CNTL5_DEFAULT 0x40410b2c +#define smnBIFP6_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 +#define smnBIFP6_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_CNTL6_DEFAULT 0x8a000010 +#define smnBIFP6_PCIE_LC_CNTL7_DEFAULT 0x8000026e +#define smnBIFP6_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff +#define smnBIFP6_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_STRAP_LC_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 +#define smnBIFP6_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 +#define smnBIFP6_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 +#define smnBIFP6_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_HPGI_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 +#define smnBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_pciedir +#define smnPCIE_RESERVED_DEFAULT 0x00000000 +#define smnPCIE_SCRATCH_DEFAULT 0x00000000 +#define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000 +#define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000 +#define smnPCIE_CNTL_DEFAULT 0x80e31000 +#define smnPCIE_CONFIG_CNTL_DEFAULT 0x0800010f +#define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000 +#define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000 +#define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000 +#define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000 +#define smnPCIE_CNTL2_DEFAULT 0x0e000109 +#define smnPCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000 +#define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000 +#define smnPCIE_CI_CNTL_DEFAULT 0x00000010 +#define smnPCIE_BUS_CNTL_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE6_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE7_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE8_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE9_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE10_DEFAULT 0x00000000 +#define smnPCIE_LC_STATE11_DEFAULT 0x00000000 +#define smnPCIE_LC_STATUS1_DEFAULT 0x00000000 +#define smnPCIE_LC_STATUS2_DEFAULT 0x00000000 +#define smnPCIE_WPR_CNTL_DEFAULT 0x00000005 +#define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000 +#define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000 +#define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000 +#define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000 +#define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000 +#define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000 +#define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000 +#define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000 +#define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000 +#define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000 +#define smnPCIE_CFG_CNTL_DEFAULT 0x00000000 +#define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210 +#define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000 +#define smnPCIE_P_CNTL_DEFAULT 0x00010000 +#define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000 +#define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000 +#define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000 +#define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff +#define smnPCIE_RX_AD_DEFAULT 0x00000002 +#define smnPCIE_SDP_CTRL_DEFAULT 0x00000002 +#define smnNBIO_CLKREQb_MAP_CNTL_DEFAULT 0x00000000 +#define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000 +#define smnPCIE_SDP_RC_SLV_ATTR_CTRL_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_TXCLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_TXCLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_TXCLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_MST_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_MST_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_MST_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_MST_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_MST_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_MST_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_SLV_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_SLV_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_SLV_R_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_SLV_S_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL_DEFAULT 0x00000000 +#define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000 +#define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000 +#define smnPCIE_PRBS_CLR_DEFAULT 0x00000000 +#define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000 +#define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000 +#define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000 +#define smnPCIE_PRBS_MISC_DEFAULT 0x00000000 +#define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000 +#define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000 +#define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000 +#define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000 +#define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000 +#define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002 +#define smnSWRST_COMMAND_0_DEFAULT 0x00000000 +#define smnSWRST_COMMAND_1_DEFAULT 0x04000000 +#define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00 +#define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff +#define smnSWRST_CONTROL_2_DEFAULT 0x00000000 +#define smnSWRST_CONTROL_3_DEFAULT 0x00000000 +#define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01 +#define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff +#define smnSWRST_CONTROL_6_DEFAULT 0x000007ff +#define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000 +#define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500 +#define smnCPM_CONTROL_DEFAULT 0x0080da00 +#define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000 +#define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000 +#define smnRSMU_MASTER_CONTROL_DEFAULT 0x00000000 +#define smnRSMU_SLAVE_CONTROL_DEFAULT 0x00000001 +#define smnRSMU_POWER_GATING_CONTROL_DEFAULT 0x00000000 +#define smnRSMU_BIOS_TIMER_CMD_DEFAULT 0x00000000 +#define smnRSMU_BIOS_TIMER_CNTL_DEFAULT 0x00000064 +#define smnLNCNT_CONTROL_DEFAULT 0x00000000 +#define smnCFG_LNC_WINDOW_REGISTER_DEFAULT 0x00000000 +#define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000 +#define smnLNCNT_WEIGHT_DEFAULT 0x00000000 +#define smnLNC_TOTAL_WACC_REGISTER_DEFAULT 0x00000000 +#define smnLNC_BW_WACC_REGISTER_DEFAULT 0x00000000 +#define smnLNC_CMN_WACC_REGISTER_DEFAULT 0x00000000 +#define smnSMU_HP_STATUS_UPDATE_DEFAULT 0x00000000 +#define smnHP_SMU_COMMAND_UPDATE_DEFAULT 0x00000000 +#define smnSMU_HP_END_OF_INTERRUPT_DEFAULT 0x00000000 +#define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000 +#define smnPCIE_PGMST_CNTL_DEFAULT 0x00000000 +#define smnPCIE_PGSLV_CNTL_DEFAULT 0x00000004 +#define smnSMU_PCIE_FENCED1_REG_DEFAULT 0x00000000 +#define smnSMU_PCIE_FENCED2_REG_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +#define smnNB_NBCFG1_NB_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_DEVICE_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_COMMAND_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_STATUS_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_REVISION_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_REGPROG_INF_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SUB_CLASS_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_BASE_CODE_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_CACHE_LINE_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_LATENCY_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_HEADER_DEFAULT 0x00000080 +#define smnNB_NBCFG1_NB_ADAPTER_ID_DEFAULT 0x15d01022 +#define smnNB_NBCFG1_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_HEADER_W_DEFAULT 0x00000080 +#define smnNB_NBCFG1_NB_PCI_CTRL_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_0_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_0_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NBCFG_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NBCFG_SCRATCH_1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NBCFG_SCRATCH_2_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NBCFG_SCRATCH_3_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NBCFG_SCRATCH_4_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_PCI_ARB_DEFAULT 0x00000108 +#define smnNB_NBCFG1_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_2_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_2_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_3_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_3_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_4_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_4_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_INDEX_5_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_5_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 +#define smnNB_NBCFG1_NB_SMN_INDEX_6_DEFAULT 0x00000000 +#define smnNB_NBCFG1_NB_SMN_DATA_6_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_iommushadow_iommushadow_cfgdecp +#define smnSHADOW_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000000 +#define smnSHADOW_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnSHADOW_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW0_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW0_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW1_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW1_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW2_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW2_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW3_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW3_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW4_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW4_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW5_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW5_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp +#define smnNB_PCIE0SHADOW6_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0SHADOW6_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp +#define smnNB_NBIF1SHADOW0_COMMAND_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW0_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp +#define smnNB_NBIF1SHADOW1_COMMAND_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_SLOT_CAP_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_ROOT_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1SHADOW1_DEVICE_CNTL2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec +#define smnFASTREG_APERTURE_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_misc_misc_cfgdec +#define smnNB_CNTL_DEFAULT 0x00000000 +#define smnNB_SPARE1_DEFAULT 0x00000000 +#define smnNB_SPARE2_DEFAULT 0x00000000 +#define smnNB_REVID_DEFAULT 0x00000000 +#define smnIOHC_REFCLK_MODE_DEFAULT 0x00000002 +#define smnIOHC_PCIE_CRS_Count_DEFAULT 0x00000000 +#define smnIOHC_P2P_CNTL_DEFAULT 0x00000000 +#define smnCFG_IOHC_PCI_DEFAULT 0x00000001 +#define smnNB_BUS_NUM_CNTL_DEFAULT 0x00000000 +#define smnIOHC_AER_CNTL_DEFAULT 0x00000000 +#define smnNB_MMIOBASE_DEFAULT 0x00000000 +#define smnNB_MMIOLIMIT_DEFAULT 0x00000000 +#define smnNB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define smnNB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define smnNB_LOWER_DRAM2_BASE_DEFAULT 0x00000000 +#define smnNB_UPPER_DRAM2_BASE_DEFAULT 0x00000001 +#define smnSB_LOCATION_DEFAULT 0x00020001 +#define smnIOHC_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 +#define smnIOHC_GLUE_CG_LCLK_CTRL_1_DEFAULT 0xffc00000 +#define smnIOHC_GLUE_CG_LCLK_CTRL_2_DEFAULT 0xffc00000 +#define smnIOHC_PERF_CNTL_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT0_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT0_UPPER_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT1_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT1_UPPER_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT2_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT2_UPPER_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT3_DEFAULT 0x00000000 +#define smnIOHC_PERF_COUNT3_UPPER_DEFAULT 0x00000000 +#define smnNB_PROG_DEVICE_REMAP_PBr0_DEFAULT 0x00000009 +#define smnNB_PROG_DEVICE_REMAP_PBr1_DEFAULT 0x0000000a +#define smnNB_PROG_DEVICE_REMAP_PBr2_DEFAULT 0x0000000b +#define smnNB_PROG_DEVICE_REMAP_PBr3_DEFAULT 0x0000000c +#define smnNB_PROG_DEVICE_REMAP_PBr4_DEFAULT 0x0000000d +#define smnNB_PROG_DEVICE_REMAP_PBr5_DEFAULT 0x0000000e +#define smnNB_PROG_DEVICE_REMAP_PBr6_DEFAULT 0x0000000f +#define smnNB_PROG_DEVICE_REMAP_PBr7_DEFAULT 0x00000041 +#define smnNB_PROG_DEVICE_REMAP_PBr8_DEFAULT 0x00000042 +#define smnSW_NMI_CNTL_DEFAULT 0x00000000 +#define smnSW_SMI_CNTL_DEFAULT 0x00000000 +#define smnSW_SCI_CNTL_DEFAULT 0x00000000 +#define smnAPML_SW_STATUS_DEFAULT 0x00000000 +#define smnIOHC_FEATURE_CNTL_DEFAULT 0x00000003 +#define smnSW_GIC_SPI_CNTL_DEFAULT 0x00000000 +#define smnIOHC_INTERRUPT_EOI_DEFAULT 0x00000000 +#define smnSW_SYNCFLOOD_CNTL_DEFAULT 0x00000000 +#define smnIOHC_PIN_CNTL_DEFAULT 0x00000000 +#define smnIOHC_INTR_CNTL_DEFAULT 0x0000ff00 +#define smnIOHC_FEATURE_CNTL2_DEFAULT 0x00000000 +#define smnNB_TOP_OF_DRAM3_DEFAULT 0x00000000 +#define smnCAM_CONTROL_DEFAULT 0x00000000 +#define smnCAM_TARGET_INDEX_ADDR_BOTTOM_DEFAULT 0x00000000 +#define smnCAM_TARGET_INDEX_ADDR_TOP_DEFAULT 0x00000000 +#define smnCAM_TARGET_INDEX_DATA_DEFAULT 0x00000000 +#define smnCAM_TARGET_INDEX_DATA_MASK_DEFAULT 0x00000000 +#define smnCAM_TARGET_DATA_ADDR_BOTTOM_DEFAULT 0x00000000 +#define smnCAM_TARGET_DATA_ADDR_TOP_DEFAULT 0x00000000 +#define smnCAM_TARGET_DATA_DEFAULT 0x00000000 +#define smnCAM_TARGET_DATA_MASK_DEFAULT 0x00000000 +#define smnP_DMA_DROPPED_LOG_LOWER_DEFAULT 0x00000000 +#define smnP_DMA_DROPPED_LOG_UPPER_DEFAULT 0x00000000 +#define smnNP_DMA_DROPPED_LOG_LOWER_DEFAULT 0x00000000 +#define smnNP_DMA_DROPPED_LOG_UPPER_DEFAULT 0x00000000 +#define smnPCIE_VDM_NODE0_CTRL4_DEFAULT 0x00000000 +#define smnPCIE_VDM_CNTL2_DEFAULT 0x00000000 +#define smnPCIE_VDM_CNTL3_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT0_0_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT0_1_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT1_0_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT1_1_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT2_0_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT2_1_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT3_0_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT3_1_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT4_0_DEFAULT 0x00000000 +#define smnSTALL_CONTROL_XBARPORT4_1_DEFAULT 0x00000000 +#define smnNB_DRAM3_BASE_DEFAULT 0x00040000 +#define smnPSP_BASE_ADDR_LO_DEFAULT 0x00000000 +#define smnPSP_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnSMU_BASE_ADDR_LO_DEFAULT 0x00000000 +#define smnSMU_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnIOAPIC_BASE_ADDR_LO_DEFAULT 0xfec00000 +#define smnIOAPIC_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnFASTREG_BASE_ADDR_LO_DEFAULT 0x00000000 +#define smnFASTREG_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnFASTREGCNTL_BASE_ADDR_LO_DEFAULT 0x00000000 +#define smnFASTREGCNTL_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnSMMU_BASE_ADDR_LO_DEFAULT 0x00000000 +#define smnSMMU_BASE_ADDR_HI_DEFAULT 0x00000000 +#define smnIOHC_PGMST_CNTL_DEFAULT 0x0000000f +#define smnIOHC_SDP_PORT_CONTROL_DEFAULT 0x00000c8f +#define smnIOHC_SDP_PARITY_CONTROL_DEFAULT 0x00000000 +#define smnIOHC_PGSLV_CNTL_DEFAULT 0x00000004 +#define smnSCRATCH_4_DEFAULT 0x00000000 +#define smnSCRATCH_5_DEFAULT 0x00000000 +#define smnSMU_BLOCK_CPU_DEFAULT 0x00000000 +#define smnSMU_BLOCK_CPU_STATUS_DEFAULT 0x00000000 +#define smnTRAP_STATUS_DEFAULT 0x00000000 +#define smnTRAP_REQUEST0_DEFAULT 0x00000000 +#define smnTRAP_REQUEST1_DEFAULT 0x00000000 +#define smnTRAP_REQUEST2_DEFAULT 0x00000000 +#define smnTRAP_REQUEST3_DEFAULT 0x00000000 +#define smnTRAP_REQUEST4_DEFAULT 0x00000000 +#define smnTRAP_REQUEST5_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATASTRB0_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATASTRB1_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA0_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA1_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA2_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA3_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA4_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA5_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA6_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA7_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA8_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA9_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA10_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA11_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA12_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA13_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA14_DEFAULT 0x00000000 +#define smnTRAP_REQUEST_DATA15_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_CONTROL_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE0_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA0_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA1_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA2_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA3_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA4_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA5_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA6_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA7_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA8_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA9_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA10_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA11_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA12_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA13_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA14_DEFAULT 0x00000000 +#define smnTRAP_RESPONSE_DATA15_DEFAULT 0x00000000 +#define smnTRAP0_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP0_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP0_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP0_COMMAND_DEFAULT 0x00000000 +#define smnTRAP0_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP0_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP0_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP1_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP1_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP1_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP1_COMMAND_DEFAULT 0x00000000 +#define smnTRAP1_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP1_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP1_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP2_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP2_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP2_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP2_COMMAND_DEFAULT 0x00000000 +#define smnTRAP2_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP2_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP2_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP3_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP3_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP3_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP3_COMMAND_DEFAULT 0x00000000 +#define smnTRAP3_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP3_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP3_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP4_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP4_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP4_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP4_COMMAND_DEFAULT 0x00000000 +#define smnTRAP4_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP4_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP4_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP5_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP5_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP5_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP5_COMMAND_DEFAULT 0x00000000 +#define smnTRAP5_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP5_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP5_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP6_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP6_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP6_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP6_COMMAND_DEFAULT 0x00000000 +#define smnTRAP6_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP6_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP6_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP7_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP7_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP7_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP7_COMMAND_DEFAULT 0x00000000 +#define smnTRAP7_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP7_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP7_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP8_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP8_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP8_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP8_COMMAND_DEFAULT 0x00000000 +#define smnTRAP8_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP8_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP8_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP9_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP9_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP9_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP9_COMMAND_DEFAULT 0x00000000 +#define smnTRAP9_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP9_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP9_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP10_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP10_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP10_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP10_COMMAND_DEFAULT 0x00000000 +#define smnTRAP10_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP10_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP10_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP11_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP11_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP11_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP11_COMMAND_DEFAULT 0x00000000 +#define smnTRAP11_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP11_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP11_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP12_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP12_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP12_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP12_COMMAND_DEFAULT 0x00000000 +#define smnTRAP12_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP12_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP12_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP13_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP13_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP13_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP13_COMMAND_DEFAULT 0x00000000 +#define smnTRAP13_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP13_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP13_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP14_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP14_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP14_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP14_COMMAND_DEFAULT 0x00000000 +#define smnTRAP14_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP14_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP14_COMMAND_MASK_DEFAULT 0x00000000 +#define smnTRAP15_CONTROL0_DEFAULT 0x00000000 +#define smnTRAP15_ADDRESS_LO_DEFAULT 0x00000000 +#define smnTRAP15_ADDRESS_HI_DEFAULT 0x00000000 +#define smnTRAP15_COMMAND_DEFAULT 0x00000000 +#define smnTRAP15_ADDRESS_LO_MASK_DEFAULT 0x00000000 +#define smnTRAP15_ADDRESS_HI_MASK_DEFAULT 0x00000000 +#define smnTRAP15_COMMAND_MASK_DEFAULT 0x00000000 +#define smnIOHC_REQDECODE_OVERRIDE_DEFAULT 0x00000000 +#define smnIOHC_RSPDECODE_OVERRIDE_DEFAULT 0x00000000 +#define smnIOHC_RSPPASSPW_OVERRIDE_DEFAULT 0x00000000 +#define smnIOHC_USERBIT_BYPASS_DEFAULT 0x00000000 +#define smnIOHC_SMN_MASTER_CNTL_DEFAULT 0x00000000 +#define smnIOHC_SMN_MASTER_STATUS_DEFAULT 0x00000000 +#define smnSB_COMMAND_DEFAULT 0x00000000 +#define smnSB_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSB_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSB_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSB_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnSB_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnSB_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnSB_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnSB_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnSB_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnSB_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnSB_SLOT_CAP_DEFAULT 0x00000000 +#define smnSB_ROOT_CNTL_DEFAULT 0x00000000 +#define smnSB_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnIOHC_QOS_CONTROL_DEFAULT 0x00000000 +#define smnUSB_QoS_CNTL_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01000101 +#define smnIOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01000001 +#define smnIOHC_SION_Client0_DataPoolCredit_Alloc_Lower_DEFAULT 0x01000101 +#define smnIOHC_SION_Client0_DataPoolCredit_Alloc_Upper_DEFAULT 0x01000001 +#define smnIOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x00010101 +#define smnIOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client1_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_Client1_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_S0_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client2_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_Client2_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_S0_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client3_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_Client3_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_S0_Client4_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client4_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOHC_SION_Client4_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOHC_SION_LiveLock_WatchDog_Threshold_DEFAULT 0x00000014 + + +// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec +#define smnPARITY_CONTROL_0_DEFAULT 0x00010001 +#define smnPARITY_CONTROL_1_DEFAULT 0x80000000 +#define smnPARITY_SEVERITY_CONTROL_UNCORR_0_DEFAULT 0x00000000 +#define smnPARITY_SEVERITY_CONTROL_CORR_0_DEFAULT 0x00000000 +#define smnPARITY_SEVERITY_CONTROL_UCP_0_DEFAULT 0x00000000 +#define smnRAS_GLOBAL_STATUS_LO_DEFAULT 0x00000000 +#define smnRAS_GLOBAL_STATUS_HI_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UNCORR_GRP0_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UNCORR_GRP1_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UNCORR_GRP2_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UNCORR_GRP3_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UNCORR_GRP4_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_CORR_GRP0_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_CORR_GRP1_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_CORR_GRP2_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_CORR_GRP3_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_CORR_GRP4_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_CORR_GRP0_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_CORR_GRP1_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_CORR_GRP2_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_CORR_GRP3_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_CORR_GRP4_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UCP_GRP0_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UCP_GRP1_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UCP_GRP2_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UCP_GRP3_DEFAULT 0x00000000 +#define smnPARITY_ERROR_STATUS_UCP_GRP4_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_UCP_GRP0_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_UCP_GRP1_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_UCP_GRP2_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_UCP_GRP3_DEFAULT 0x00000000 +#define smnPARITY_COUNTER_UCP_GRP4_DEFAULT 0x00000000 +#define smnMISC_SEVERITY_CONTROL_DEFAULT 0x00000000 +#define smnMISC_RAS_CONTROL_DEFAULT 0x00000008 +#define smnRAS_SCRATCH_0_DEFAULT 0x00000000 +#define smnRAS_SCRATCH_1_DEFAULT 0x00000000 +#define smnErrEvent_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnParitySerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnParityFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnParityNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnParityCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortASerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortAParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortBParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortCParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortDParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortESerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortEParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortFParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPCIE0PortGParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortASerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortAParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBSerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnNBIF1PortBParityErr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnSYNCFLOOD_STATUS_DEFAULT 0x00000000 +#define smnNMI_STATUS_DEFAULT 0x00000000 +#define smnPOISON_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnINTERNAL_POISON_STATUS_DEFAULT 0x00000000 +#define smnINTERNAL_POISON_MASK_DEFAULT 0x00000000 +#define smnEGRESS_POISON_STATUS_LO_DEFAULT 0x00000000 +#define smnEGRESS_POISON_STATUS_HI_DEFAULT 0x00000000 +#define smnEGRESS_POISON_MASK_LO_DEFAULT 0x00000000 +#define smnEGRESS_POISON_MASK_HI_DEFAULT 0x00000000 +#define smnEGRESS_POISON_SEVERITY_DOWN_DEFAULT 0x00000000 +#define smnEGRESS_POISON_SEVERITY_UPPER_DEFAULT 0x00000000 +#define smnAPML_STATUS_DEFAULT 0x00000000 +#define smnAPML_CONTROL_DEFAULT 0x00000100 +#define smnAPML_TRIGGER_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec +#define smnPSP_SYNCFLOOD_STATUS_DEFAULT 0x00000000 +#define smnPSP_INTERNAL_POISON_STATUS_DEFAULT 0x00000000 +#define smnPSP_EGRESS_POISON_STATUS_LO_DEFAULT 0x00000000 +#define smnPSP_EGRESS_POISON_STATUS_HI_DEFAULT 0x00000000 +#define smnPSP_PARITY_CONTROL_0_DEFAULT 0x00010001 +#define smnPSP_PARITY_STATUS_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP0_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP1_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP2_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP3_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP4_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UCP_GRP0_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UCP_GRP1_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UCP_GRP2_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UCP_GRP3_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_UCP_GRP4_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_UCP_GRP0_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_UCP_GRP1_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_UCP_GRP2_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_UCP_GRP3_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_UCP_GRP4_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_CORR_GRP0_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_CORR_GRP1_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_CORR_GRP2_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_CORR_GRP3_DEFAULT 0x00000000 +#define smnPSP_PARITY_ERROR_STATUS_CORR_GRP4_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_CORR_GRP0_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_CORR_GRP1_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_CORR_GRP2_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_CORR_GRP3_DEFAULT 0x00000000 +#define smnPSP_PARITY_COUNTER_CORR_GRP4_DEFAULT 0x00000000 +#define smnPSP_ParitySerr_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPSP_ParityFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPSP_ParityNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 +#define smnPSP_ParityCorr_ACTION_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG1_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG2_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG3_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG4_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG5_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +#define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG6_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +#define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1devindcfg1_devind_cfgdecp +#define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG1_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +#define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 +#define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 +#define smnNB_INTSBDEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 +#define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +#define smnNB_PCIEDUMMY0_1_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_1_STATUS_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_1_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_1_HEADER_TYPE_DEFAULT 0x00800000 +#define smnNB_PCIEDUMMY0_1_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +#define smnNB_PCIEDUMMY1_1_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_1_STATUS_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_1_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_1_HEADER_TYPE_DEFAULT 0x00800000 +#define smnNB_PCIEDUMMY1_1_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_iommu_indcfg_iommuind_cfgdec +#define smnIOMMU_SMN_INDEX_0_DEFAULT 0x00000000 +#define smnIOMMU_SMN_DATA_0_DEFAULT 0x00000000 +#define smnIOMMU_SMN_INDEX_1_DEFAULT 0x00000000 +#define smnIOMMU_SMN_DATA_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_ioapic_indcfg_ioapicind_cfgdec +#define smnIOAPIC_MIO_INDEX_DEFAULT 0x00000000 +#define smnIOAPIC_MIO_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +#define smnNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +#define smnNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg1_pciercbdgind_cfgdec +#define smnNB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX_DEFAULT 0x00000000 +#define smnNB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +#define smnIOMMU_L2_1_IOMMU_VENDOR_ID_DEFAULT 0x00001022 +#define smnIOMMU_L2_1_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 +#define smnIOMMU_L2_1_IOMMU_COMMAND_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_STATUS_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_REVISION_ID_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_REGPROG_INF_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_SUB_CLASS_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_BASE_CODE_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CACHE_LINE_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_LATENCY_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_HEADER_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_BIST_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnIOMMU_L2_1_IOMMU_CAP_HEADER_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CAP_RANGE_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CAP_MISC_DEFAULT 0x00003000 +#define smnIOMMU_L2_1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 +#define smnIOMMU_L2_1_IOMMU_MSI_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_MSI_DATA_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_CONTROL_W_DEFAULT 0x00002b01 +#define smnIOMMU_L2_1_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada +#define smnIOMMU_L2_1_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf +#define smnIOMMU_L2_1_IOMMU_RANGE_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 +#define smnIOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf +#define smnIOMMU_L2_1_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 +#define smnIOMMU_L2_1_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 +#define smnIOMMU_L2_1_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_1_SMMU_AIDR_W_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2indx_l2indxcfg +#define smnL2_STATUS_1_DEFAULT 0x00000000 +#define smnL2_SB_LOCATION_DEFAULT 0x00000000 +#define smnL2_CONTROL_5_DEFAULT 0x01001001 +#define smnL2_CONTROL_6_DEFAULT 0x00010808 +#define smnL2_PDC_CONTROL_DEFAULT 0x00000200 +#define smnL2_PDC_HASH_CONTROL_DEFAULT 0x00000000 +#define smnL2_PDC_WAY_CONTROL_DEFAULT 0x00000000 +#define smnL2B_UPDATE_FILTER_CNTL_DEFAULT 0x00000007 +#define smnL2_TW_CONTROL_DEFAULT 0x00501000 +#define smnL2_CP_CONTROL_DEFAULT 0x00000004 +#define smnL2_CP_CONTROL_1_DEFAULT 0x00000000 +#define smnIOMMU_L2_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 +#define smnL2_TW_CONTROL_1_DEFAULT 0x00000000 +#define smnL2_TW_CONTROL_2_DEFAULT 0x00000000 +#define smnL2_TW_CONTROL_3_DEFAULT 0x00000000 +#define smnL2_CREDIT_CONTROL_0_DEFAULT 0x40000000 +#define smnL2_CREDIT_CONTROL_1_DEFAULT 0x00440404 +#define smnL2_ERR_RULE_CONTROL_0_DEFAULT 0x00000000 +#define smnL2_ERR_RULE_CONTROL_1_DEFAULT 0x00000000 +#define smnL2_ERR_RULE_CONTROL_2_DEFAULT 0x00000000 +#define smnL2_L2B_CK_GATE_CONTROL_DEFAULT 0x00000057 +#define smnPPR_CONTROL_DEFAULT 0x00000000 +#define smnL2_L2B_PGSIZE_CONTROL_DEFAULT 0x00000101 +#define smnL2_L2B_MEMPWR_GATE_1_DEFAULT 0x00000000 +#define smnL2_L2B_MEMPWR_GATE_2_DEFAULT 0x00000064 +#define smnL2_L2B_MEMPWR_GATE_3_DEFAULT 0x00000064 +#define smnL2_L2B_MEMPWR_GATE_4_DEFAULT 0x0000044c +#define smnL2_PERF_CNTL_2_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_4_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_5_DEFAULT 0x00000000 +#define smnL2_PERF_CNTL_3_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_6_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_7_DEFAULT 0x00000000 +#define smnL2_L2B_DVM_CTRL_0_DEFAULT 0x00000008 +#define smnL2_L2B_DVM_CTRL_1_DEFAULT 0x00000000 +#define smnL2B_SDP_MAXCRED_DEFAULT 0x08888888 +#define smnL2B_SDP_PARITY_ERROR_EN_DEFAULT 0x00000000 +#define smnL2_ECO_CNTRL_1_DEFAULT 0x00000000 +#define smnL2_L2B_MEMPWR_GATE_5_DEFAULT 0x00000001 +#define smnL2_L2B_MEMPWR_GATE_6_DEFAULT 0x00000001 +#define smnL2_L2B_MEMPWR_GATE_7_DEFAULT 0x00000001 +#define smnL2_L2B_MEMPWR_GATE_8_DEFAULT 0x00000006 +#define smnL2_L2B_MEMPWR_GATE_9_DEFAULT 0x00000001 +#define smnL2_L2B_MEMPWR_GATE_10_DEFAULT 0x00000006 + + +// addressBlock: nbio_iohub_iommu_l2bshdw_l2bshdw +#define smnSHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnSHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2bpsp_l2bpsp +#define smnL2BPSP_ERR_REP_ENABLE_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_STATUS_0_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_STATUS_1_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_LOWER_0_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_LOWER_1_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_UPPER_0_DEFAULT 0x00000000 +#define smnL2BPSP_HW_ERR_UPPER_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +#define smnFEATURES_ENABLE_DEFAULT 0x00000204 +#define smnIOAPIC_BR0_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR1_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR2_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR3_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR4_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR5_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR6_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR7_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_BR8_INTERRUPT_ROUTING_DEFAULT 0x00000000 +#define smnIOAPIC_SERIAL_IRQ_STATUS_DEFAULT 0x00000000 +#define smnIOAPIC_SCRATCH_0_DEFAULT 0x00000000 +#define smnIOAPIC_SCRATCH_1_DEFAULT 0x00000000 +#define smnIOAPIC_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 +#define smnIOAPIC_SDP_PORT_CONTROL_DEFAULT 0x0000000f +#define smnIOAPIC_PERF_CNTL_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT0_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT0_UPPER_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT1_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT1_UPPER_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT2_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT2_UPPER_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT3_DEFAULT 0x00000000 +#define smnIOAPIC_PERF_COUNT3_UPPER_DEFAULT 0x00000000 +#define smnIOAPIC_PGSLV_CONTROL_DEFAULT 0x00000004 + + +// addressBlock: nbio_iohub_nb_ioapicshdw_ioapic_shdwdec +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0_DEFAULT 0x00000009 +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1_DEFAULT 0x0000000a +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2_DEFAULT 0x0000000b +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3_DEFAULT 0x0000000c +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4_DEFAULT 0x0000000d +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5_DEFAULT 0x0000000e +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6_DEFAULT 0x0000000f +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7_DEFAULT 0x00000041 +#define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8_DEFAULT 0x00000042 + + +// addressBlock: nbio_iohub_iommu_l1_PCIE0_iommul1cfg +#define smnIOMMU_L1_PCIE0_L1_PERF_CNTL_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PERF_CNTL_B_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_B0_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_B1_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_SB_LOCATION_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_CNTRL_0_DEFAULT 0x00100a0c +#define smnIOMMU_L1_PCIE0_L1_CNTRL_1_DEFAULT 0x00000400 +#define smnIOMMU_L1_PCIE0_L1_CNTRL_2_DEFAULT 0x32000008 +#define smnIOMMU_L1_PCIE0_L1_CNTRL_3_DEFAULT 0x0000c350 +#define smnIOMMU_L1_PCIE0_L1_BANK_SEL_0_DEFAULT 0x00000001 +#define smnIOMMU_L1_PCIE0_L1_BANK_DISABLE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_2_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_3_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_FEATURE_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_5_DEFAULT 0x00000001 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_6_DEFAULT 0x00000001 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_7_DEFAULT 0x00000001 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_8_DEFAULT 0x00000006 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_9_DEFAULT 0x00000001 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_10_DEFAULT 0x00000006 +#define smnIOMMU_L1_PCIE0_L1_CNTRL_4_DEFAULT 0x24000000 +#define smnIOMMU_L1_PCIE0_L1_CLKCNTRL_0_DEFAULT 0x00020000 +#define smnIOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL_DEFAULT 0x0000001f +#define smnIOMMU_L1_PCIE0_L1_CNTRL_5_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_2_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_3_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_4_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL_DEFAULT 0x0000000b +#define smnIOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_PCIE0_L1_SDP_MAXCRED_0_DEFAULT 0x00000008 +#define smnIOMMU_L1_PCIE0_L1_ECO_CNTRL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l1shdw_PCIE0_l1shdw +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_iommu_l1psp_PCIE0_l1psp +#define smnIOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l1_IOAGR_iommul1cfg +#define smnIOMMU_L1_IOAGR_L1_PERF_CNTL_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PERF_CNTL_B_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_B0_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_B1_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_SB_LOCATION_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_CNTRL_0_DEFAULT 0x00100a0c +#define smnIOMMU_L1_IOAGR_L1_CNTRL_1_DEFAULT 0x00000400 +#define smnIOMMU_L1_IOAGR_L1_CNTRL_2_DEFAULT 0x32000008 +#define smnIOMMU_L1_IOAGR_L1_CNTRL_3_DEFAULT 0x0000c350 +#define smnIOMMU_L1_IOAGR_L1_BANK_SEL_0_DEFAULT 0x00000001 +#define smnIOMMU_L1_IOAGR_L1_BANK_DISABLE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_2_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_3_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_FEATURE_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_5_DEFAULT 0x00000001 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_6_DEFAULT 0x00000001 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_7_DEFAULT 0x00000001 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_8_DEFAULT 0x00000006 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_9_DEFAULT 0x00000001 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_10_DEFAULT 0x00000006 +#define smnIOMMU_L1_IOAGR_L1_CNTRL_4_DEFAULT 0x24000000 +#define smnIOMMU_L1_IOAGR_L1_CLKCNTRL_0_DEFAULT 0x00020000 +#define smnIOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL_DEFAULT 0x0000001f +#define smnIOMMU_L1_IOAGR_L1_CNTRL_5_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_1_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_2_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_3_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_4_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL_DEFAULT 0x0000000b +#define smnIOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L1_IOAGR_L1_SDP_MAXCRED_0_DEFAULT 0x00000008 +#define smnIOMMU_L1_IOAGR_L1_ECO_CNTRL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l1shdw_IOAGR_l1shdw +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_DEFAULT 0x00000000 +#define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 + + +// addressBlock: nbio_iohub_iommu_l1psp_IOAGR_l1psp +#define smnIOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1_DEFAULT 0x00000000 +#define smnIOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2a_l2acfg +#define smnL2_PERF_CNTL_0_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_0_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_1_DEFAULT 0x00000000 +#define smnL2_PERF_CNTL_1_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_2_DEFAULT 0x00000000 +#define smnL2_PERF_COUNT_3_DEFAULT 0x00000000 +#define smnL2_STATUS_0_DEFAULT 0x00000000 +#define smnL2_CONTROL_0_DEFAULT 0x00100000 +#define smnL2_CONTROL_1_DEFAULT 0x00010808 +#define smnL2_DTC_CONTROL_DEFAULT 0x00000200 +#define smnL2_DTC_HASH_CONTROL_DEFAULT 0x00000000 +#define smnL2_DTC_WAY_CONTROL_DEFAULT 0x00000000 +#define smnL2_ITC_CONTROL_DEFAULT 0x00000200 +#define smnL2_ITC_HASH_CONTROL_DEFAULT 0x00000000 +#define smnL2_ITC_WAY_CONTROL_DEFAULT 0x00000000 +#define smnL2_PTC_A_CONTROL_DEFAULT 0x00000200 +#define smnL2_PTC_A_HASH_CONTROL_DEFAULT 0x00000000 +#define smnL2_PTC_A_WAY_CONTROL_DEFAULT 0x00000000 +#define smnL2_CREDIT_CONTROL_2_DEFAULT 0x04000000 +#define smnL2A_UPDATE_FILTER_CNTL_DEFAULT 0x00000007 +#define smnL2_ERR_RULE_CONTROL_3_DEFAULT 0x00000000 +#define smnL2_ERR_RULE_CONTROL_4_DEFAULT 0x00000000 +#define smnL2_ERR_RULE_CONTROL_5_DEFAULT 0x00000000 +#define smnL2_L2A_CK_GATE_CONTROL_DEFAULT 0x00000057 +#define smnL2_L2A_PGSIZE_CONTROL_DEFAULT 0x00000101 +#define smnL2_L2A_MEMPWR_GATE_1_DEFAULT 0x00000000 +#define smnL2_L2A_MEMPWR_GATE_2_DEFAULT 0x00000064 +#define smnL2_L2A_MEMPWR_GATE_3_DEFAULT 0x00000064 +#define smnL2_L2A_MEMPWR_GATE_4_DEFAULT 0x0000044c +#define smnL2_L2A_MEMPWR_GATE_5_DEFAULT 0x00000001 +#define smnL2_L2A_MEMPWR_GATE_6_DEFAULT 0x00000001 +#define smnL2_L2A_MEMPWR_GATE_7_DEFAULT 0x00000001 +#define smnL2_L2A_MEMPWR_GATE_8_DEFAULT 0x00000006 +#define smnL2_L2A_MEMPWR_GATE_9_DEFAULT 0x00000001 +#define smnL2_PWRGATE_CNTRL_REG_0_DEFAULT 0x000003e8 +#define smnL2_L2A_MEMPWR_GATE_10_DEFAULT 0x00000006 +#define smnL2_PWRGATE_CNTRL_REG_3_DEFAULT 0x00000000 +#define smnL2_ECO_CNTRL_0_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 +#define smnSHDWL2A_SMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 +#define smnSHDWL2A_SMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 +#define smnSHDWL2A_SMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 +#define smnSHDWL2A_SMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_CAP_MISC_DEFAULT 0x00000000 +#define smnSHDWL2A_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 +#define smnSHDWL2A_IOMMU_CONTROL_W_DEFAULT 0x00000300 +#define smnSHDWL2A_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x00001a1a +#define smnSHDWL2A_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x000100cf + + +// addressBlock: nbio_iohub_smmu_mmio_smmummiocfg +#define smnSMMU_IDR0_DEFAULT 0x00000000 +#define smnSMMU_IDR1_DEFAULT 0x00000000 +#define smnSMMU_IDR2_DEFAULT 0x00000000 +#define smnSMMU_IDR3_DEFAULT 0x00000000 +#define smnSMMU_IDR4_DEFAULT 0x00000000 +#define smnSMMU_IDR5_DEFAULT 0x00000072 +#define smnSMMU_IIDR_DEFAULT 0x0000043b +#define smnSMMU_AIDR_DEFAULT 0x00000000 +#define smnSMMU_CR0_DEFAULT 0x00000000 +#define smnSMMU_CR0ACK_DEFAULT 0x00000000 +#define smnSMMU_CR2_DEFAULT 0x00000000 +#define smnSMMU_GBPA_DEFAULT 0x00000000 +#define smnSMMU_STRTAB_BASE_HI_DEFAULT 0x00000000 +#define smnSMMU_STRTAB_BASE_LO_DEFAULT 0x00000000 +#define smnSMMU_STRTAB_BASE_CFG_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_ioagrcfg_ioagr_cfgdec +#define smnIOAGR_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 +#define smnIOAGR_GLUE_CG_LCLK_CTRL_1_DEFAULT 0xffc00000 +#define smnIOAGR_REQDECODE_OVERRIDE_DEFAULT 0x00000000 +#define smnIOAGR_RSPDECODE_OVERRIDE_DEFAULT 0x00000000 +#define smnIOAGR_USERBIT_BYPASS_DEFAULT 0x00000000 +#define smnIOAGR_SDP_PORT_CONTROL_DEFAULT 0x0000000f +#define smnIOAGR_PERF_CNTL_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT0_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT0_UPPER_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT1_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT1_UPPER_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT2_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT2_UPPER_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT3_DEFAULT 0x00000000 +#define smnIOAGR_PERF_COUNT3_UPPER_DEFAULT 0x00000000 +#define smnIOAGR_PGMST_CNTL_DEFAULT 0x0000000f +#define smnIOAGR_PGSLV_CNTL_DEFAULT 0x00000004 +#define smnIOAGR_SION_S0_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010401 +#define smnIOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020902 +#define smnIOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_S0_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_S0_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_S0_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 +#define smnIOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 +#define smnIOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 +#define smnIOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 +#define smnIOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 +#define smnIOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 +#define smnIOAGR_SION_LiveLock_WatchDog_Threshold_DEFAULT 0x00000014 + + +// addressBlock: nbio_sst0_sst_core_sstcorecfg +#define smnSST_CORE0_SST_CLOCK_CTRL_DEFAULT 0x00014001 +#define smnSST_CORE0_SST_ENABLE_CTRL_DEFAULT 0x00000000 +#define smnSST_CORE0_SST_RSMU_HCID_DEFAULT 0x00002000 +#define smnSST_CORE0_SST_RSMU_SIID_DEFAULT 0x00002000 +#define smnSST_CORE0_SST_STATISTIC_0_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS_DEFAULT 0x000000ff +#define smnSST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE0_SST_BACKDOOR0_DEFAULT 0x00000000 +#define smnSST_CORE0_SST_BACKDOOR1_DEFAULT 0x00000000 +#define smnSST_CORE0_SST_BACKDOOR2_DEFAULT 0x00000000 + + +// addressBlock: nbio_sst1_sst_core_sstcorecfg +#define smnSST_CORE1_SST_CLOCK_CTRL_DEFAULT 0x00014001 +#define smnSST_CORE1_SST_ENABLE_CTRL_DEFAULT 0x00000000 +#define smnSST_CORE1_SST_RSMU_HCID_DEFAULT 0x00002000 +#define smnSST_CORE1_SST_RSMU_SIID_DEFAULT 0x00002000 +#define smnSST_CORE1_SST_STATISTIC_0_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS_DEFAULT 0x000000ff +#define smnSST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 +#define smnSST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 +#define smnSST_CORE1_SST_BACKDOOR0_DEFAULT 0x00000000 +#define smnSST_CORE1_SST_BACKDOOR1_DEFAULT 0x00000000 +#define smnSST_CORE1_SST_BACKDOOR2_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg +#define mmIOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_EVENT_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 +#define mmIOMMU_MMIO_CNTRL_1_DEFAULT 0x00002200 +#define mmIOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EFR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EFR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_HW_ERR_UPPER_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_HW_ERR_UPPER_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_HW_ERR_LOWER_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_HW_ERR_LOWER_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_HW_ERR_STATUS_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_HW_ERR_STATUS_1_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_0_1_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_1_1_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_2_1_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 +#define mmSMI_FILTER_REGISTER_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_LOG_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_LOG_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_EVENT_B_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_B_BASE_1_DEFAULT 0x08000000 +#define mmIOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_1_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_2_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DSFX_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DSCX_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DSSX_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CAP_MISC_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CAP_MISC_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_MSI_CAP_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_MSI_ADDR_LO_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_MSI_ADDR_HI_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_MSI_DATA_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_MSI_MAPPING_CAP_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CONTROL_W_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmIOMMU_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmIOMMU_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define mmIOMMU_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_STATUS_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_STATUS_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_AUTORESP_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_CONFIG_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_CONFIG_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_DEFAULT 0x00000000 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +#define smnNB_NBCFG2_NB_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_DEVICE_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_COMMAND_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_STATUS_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_REVISION_ID_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_REGPROG_INF_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SUB_CLASS_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_BASE_CODE_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_CACHE_LINE_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_LATENCY_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_HEADER_DEFAULT 0x00000080 +#define smnNB_NBCFG2_NB_ADAPTER_ID_DEFAULT 0x15d01022 +#define smnNB_NBCFG2_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_HEADER_W_DEFAULT 0x00000080 +#define smnNB_NBCFG2_NB_PCI_CTRL_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_0_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_0_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NBCFG_SCRATCH_0_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NBCFG_SCRATCH_1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NBCFG_SCRATCH_2_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NBCFG_SCRATCH_3_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NBCFG_SCRATCH_4_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_PCI_ARB_DEFAULT 0x00000108 +#define smnNB_NBCFG2_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_2_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_2_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_3_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_3_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_4_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_4_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_INDEX_5_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_5_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 +#define smnNB_NBCFG2_NB_SMN_INDEX_6_DEFAULT 0x00000000 +#define smnNB_NBCFG2_NB_SMN_DATA_6_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +#define smnIOMMU_L2_2_IOMMU_VENDOR_ID_DEFAULT 0x00001022 +#define smnIOMMU_L2_2_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 +#define smnIOMMU_L2_2_IOMMU_COMMAND_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_STATUS_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_REVISION_ID_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_REGPROG_INF_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_SUB_CLASS_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_BASE_CODE_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CACHE_LINE_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_LATENCY_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_HEADER_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_BIST_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnIOMMU_L2_2_IOMMU_CAP_HEADER_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CAP_RANGE_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CAP_MISC_DEFAULT 0x00003000 +#define smnIOMMU_L2_2_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 +#define smnIOMMU_L2_2_IOMMU_MSI_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_MSI_DATA_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_CONTROL_W_DEFAULT 0x00002b01 +#define smnIOMMU_L2_2_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada +#define smnIOMMU_L2_2_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf +#define smnIOMMU_L2_2_IOMMU_RANGE_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 +#define smnIOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf +#define smnIOMMU_L2_2_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 +#define smnIOMMU_L2_2_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 +#define smnIOMMU_L2_2_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 +#define smnIOMMU_L2_2_SMMU_AIDR_W_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +#define smnNB_PCIEDUMMY0_2_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_2_STATUS_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_2_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY0_2_HEADER_TYPE_DEFAULT 0x00800000 +#define smnNB_PCIEDUMMY0_2_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +#define smnBIFPLR0_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR0_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR0_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR0_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR0_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR0_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR0_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR0_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR0_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR0_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR0_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR0_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR0_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR0_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR0_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR0_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR0_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR0_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR0_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR0_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR0_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR0_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR0_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR0_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR0_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +#define smnBIFPLR1_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR1_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR1_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR1_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR1_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR1_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR1_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR1_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR1_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR1_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR1_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR1_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR1_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR1_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR1_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR1_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR1_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR1_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR1_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR1_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR1_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR1_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR1_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR1_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR1_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR1_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR1_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR1_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR1_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +#define smnBIFPLR2_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR2_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR2_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR2_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR2_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR2_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR2_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR2_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR2_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR2_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR2_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR2_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR2_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR2_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR2_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR2_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR2_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR2_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR2_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR2_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR2_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR2_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR2_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR2_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR2_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR2_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR2_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR2_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR2_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +#define smnBIFPLR3_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR3_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR3_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR3_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR3_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR3_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR3_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR3_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR3_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR3_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR3_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR3_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR3_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR3_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR3_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR3_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR3_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR3_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR3_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR3_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR3_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR3_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR3_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR3_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR3_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR3_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR3_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR3_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR3_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR3_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR3_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR3_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR3_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +#define smnBIFPLR4_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR4_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR4_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR4_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR4_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR4_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR4_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR4_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR4_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR4_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR4_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR4_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR4_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR4_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR4_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR4_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR4_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR4_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR4_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR4_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR4_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR4_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR4_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR4_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR4_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR4_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR4_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR4_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR4_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR4_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR4_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR4_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR4_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +#define smnBIFPLR5_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR5_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR5_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR5_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR5_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR5_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR5_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR5_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR5_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR5_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR5_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR5_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR5_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR5_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR5_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR5_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR5_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR5_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR5_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR5_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR5_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR5_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR5_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR5_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR5_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR5_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR5_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR5_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR5_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR5_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR5_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR5_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR5_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +#define smnBIFPLR6_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_2_COMMAND_DEFAULT 0x00000000 +#define smnBIFPLR6_2_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIFPLR6_2_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR6_2_HEADER_DEFAULT 0x00000000 +#define smnBIFPLR6_2_BIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIFPLR6_2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIFPLR6_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIFPLR6_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIFPLR6_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIFPLR6_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIFPLR6_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIFPLR6_2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIFPLR6_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIFPLR6_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIFPLR6_2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIFPLR6_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIFPLR6_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIFPLR6_2_MSI_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIFPLR6_2_SSID_CAP_LIST_DEFAULT 0x0000c800 +#define smnBIFPLR6_2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIFPLR6_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIFPLR6_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIFPLR6_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR6_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 +#define smnBIFPLR6_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 +#define smnBIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIFPLR6_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 +#define smnBIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIFPLR6_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f +#define smnBIFPLR6_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIFPLR6_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIFPLR6_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 +#define smnBIFPLR6_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 +#define smnBIFPLR6_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 +#define smnBIFPLR6_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +#define smnNB_PCIEDUMMY1_2_DEVICE_VENDOR_ID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_2_STATUS_COMMAND_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_2_CLASS_CODE_REVID_DEFAULT 0x00000000 +#define smnNB_PCIEDUMMY1_2_HEADER_TYPE_DEFAULT 0x00800000 +#define smnNB_PCIEDUMMY1_2_HEADER_TYPE_W_DEFAULT 0x00000080 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +#define smnBIF_CFG_DEV0_RC2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_RC2_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_RC2_PCIE_CAP_DEFAULT 0x00000042 +#define smnBIF_CFG_DEV0_RC2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_RC2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_RC2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_LINK_STATUS_DEFAULT 0x00002001 +#define smnBIF_CFG_DEV0_RC2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_RC2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_RC2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_RC2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SSID_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_RC2_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +#define smnBIF_CFG_DEV1_RC2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SECONDARY_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV1_RC2_INTERRUPT_PIN_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_RC2_PCIE_CAP_DEFAULT 0x00000042 +#define smnBIF_CFG_DEV1_RC2_DEVICE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_RC2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_RC2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_LINK_STATUS_DEFAULT 0x00002001 +#define smnBIF_CFG_DEV1_RC2_SLOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SLOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SLOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_ROOT_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_ROOT_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_ROOT_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_RC2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_RC2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_RC2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SSID_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_SSID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MAP_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f +#define smnBIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_RC2_PCIE_ACS_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF0_3_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF0_3_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF0_3_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF0_3_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF1_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE_DEFAULT 0x000000ff +#define smnBIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF1_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF1_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF1_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF2_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF2_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF2_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF2_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF2_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF3_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF3_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF3_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF3_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF3_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF4_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF4_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF4_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF4_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF4_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF5_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF5_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF5_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF5_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF5_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF6_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF6_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF6_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF6_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF6_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +#define smnBIF_CFG_DEV0_EPF7_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF7_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV0_EPF7_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV0_EPF7_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV0_EPF7_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF0_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF0_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF0_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF0_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF1_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF1_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF1_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF1_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF1_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +#define smnBIF_CFG_DEV1_EPF2_2_VENDOR_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_COMMAND_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_REVISION_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PROG_INTERFACE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SUB_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_CLASS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_CACHE_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_HEADER_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_ADAPTER_ID_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_CAP_PTR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MIN_GRANT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MAX_LATENCY_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PMI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SBRN_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_FLADJ_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF2_2_DBESL_DBESLD_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_CAP_DEFAULT 0x00000002 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CAP_DEFAULT 0x10000000 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CNTL_DEFAULT 0x00002810 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_LINK_CAP_DEFAULT 0x00011c03 +#define smnBIF_CFG_DEV1_EPF2_2_LINK_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_LINK_STATUS_DEFAULT 0x00000001 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_LINK_CAP2_DEFAULT 0x0000000e +#define smnBIF_CFG_DEV1_EPF2_2_LINK_CNTL2_DEFAULT 0x00000003 +#define smnBIF_CFG_DEV1_EPF2_2_LINK_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SLOT_CAP2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SLOT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SLOT_STATUS2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL_DEFAULT 0x00000080 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_MASK_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_PENDING_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSI_PENDING_64_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSIX_TABLE_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_MSIX_PBA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SATA_CAP_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SATA_CAP_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP_DEFAULT 0x00000000 +#define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +#define smnBIF_BX_PF1_MM_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MM_DATA_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MM_INDEX_HI_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +#define smnBIF_BX_PF1_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SYSHUB_DATA_OVLP_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_PCIE_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_PCIE_DATA_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_PCIE_INDEX2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_PCIE_DATA2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_4_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_5_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_6_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_7_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_8_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_9_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_10_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_11_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_12_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_13_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_14_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIOS_SCRATCH_15_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec +#define smnSYSHUB_MMREG_IND0_SYSHUB_INDEX_DEFAULT 0x00000000 +#define smnSYSHUB_MMREG_IND0_SYSHUB_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +#define smnRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +#define smnRCC_EP_DEV0_2_EP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define smnRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define smnRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +#define smnRCC_DWN_DEV0_2_DN_PCIE_RESERVED_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_2_DN_PCIE_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define smnRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +#define smnRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define smnRCC_DWNP_DEV0_2_PCIE_RX_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define smnRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +#define smnBIF_BX_PF1_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BUS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_SCRATCH0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_SCRATCH1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BX_RESET_EN_DEFAULT 0x00010003 +#define smnBIF_BX_PF1_MM_CFGREGS_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BX_RESET_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_INTERRUPT_CNTL2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0 +#define smnBIF_BX_PF1_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_DOORBELL_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_FB_EN_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f +#define smnBIF_BX_PF1_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BACO_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 +#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 +#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 +#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 +#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 +#define smnBIF_BX_PF1_MEM_TYPE_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 +#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 +#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc +#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 +#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c +#define smnBIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c +#define smnBIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 +#define smnBIF_BX_PF1_BIF_RB_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RB_BASE_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RB_RPTR_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RB_WPTR_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_INDEX_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define smnBIF_BX_PF1_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 +#define smnBIF_BX_PF1_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 +#define smnBIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 +#define smnBIF_BX_PF1_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +#define smnBIF_BX_PF1_BIF_BME_STATUS_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 +#define smnBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_TRANS_PENDING_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_CONTROL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000 +#define smnBIF_BX_PF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +#define smnGDC1_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f +#define smnGDC1_SHUB_REGS_IF_CTL_DEFAULT 0x00000000 +#define smnGDC1_NGDC_RESERVED_0_DEFAULT 0x00000000 +#define smnGDC1_NGDC_RESERVED_1_DEFAULT 0x00000000 +#define smnGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f +#define smnGDC1_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC1_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC1_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC1_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define smnGDC1_ATDMA_MISC_CNTL_DEFAULT 0x04040001 +#define smnGDC1_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 +#define smnGDC1_S2A_MISC_CNTL_DEFAULT 0x00000000 +#define smnGDC1_GDC_PG_MISC_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +#define mmMM_INDEX_DEFAULT 0x00000000 +#define mmMM_DATA_DEFAULT 0x00000000 +#define mmMM_INDEX_HI_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 +#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 +#define mmPCIE_INDEX_DEFAULT 0x00000000 +#define mmPCIE_DATA_DEFAULT 0x00000000 +#define mmPCIE_INDEX2_DEFAULT 0x00000000 +#define mmPCIE_DATA2_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 +#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 +#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 +#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec +#define mmSYSHUB_INDEX_DEFAULT 0x00000000 +#define mmSYSHUB_DATA_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define mmEP_PCIE_CNTL_DEFAULT 0x00000100 +#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 +#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define mmDN_PCIE_CNTL_DEFAULT 0x00000000 +#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 +#define mmPCIE_RX_CNTL_DEFAULT 0x00000000 +#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 +#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 +#define mmRCC_ERR_LOG_DEFAULT 0x00000000 +#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 +#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 +#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +#define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000 +#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 +#define mmRCC_RESET_EN_DEFAULT 0x00008000 +#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 +#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 +#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 +#define mmRCC_BUS_CNTL_DEFAULT 0x00000000 +#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 +#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 +#define mmRCC_XDMA_LO_DEFAULT 0x00000000 +#define mmRCC_XDMA_HI_DEFAULT 0x00000000 +#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 +#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 +#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 +#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000 +#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 +#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 +#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 +#define mmBUS_CNTL_DEFAULT 0x00000000 +#define mmBIF_SCRATCH0_DEFAULT 0x00000000 +#define mmBIF_SCRATCH1_DEFAULT 0x00000000 +#define mmBX_RESET_EN_DEFAULT 0x00010003 +#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 +#define mmBX_RESET_CNTL_DEFAULT 0x00000000 +#define mmINTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 +#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 +#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 +#define mmBIF_FB_EN_DEFAULT 0x00000000 +#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f +#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define mmBACO_CNTL_DEFAULT 0x00000000 +#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 +#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 +#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 +#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 +#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 +#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 +#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 +#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc +#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 +#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc +#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 +#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc +#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 +#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc +#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 +#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc +#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 +#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc +#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 +#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc +#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 +#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c +#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c +#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 +#define mmBIF_RB_CNTL_DEFAULT 0x00000000 +#define mmBIF_RB_BASE_DEFAULT 0x00000000 +#define mmBIF_RB_RPTR_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmMAILBOX_INDEX_DEFAULT 0x00000000 +#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 +#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 +#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 +#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +#define mmBIF_BME_STATUS_DEFAULT 0x00000000 +#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 +#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 +#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 +#define mmMAILBOX_CONTROL_DEFAULT 0x00000000 +#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 +#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f +#define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000 +#define mmNGDC_RESERVED_0_DEFAULT 0x00000000 +#define mmNGDC_RESERVED_1_DEFAULT 0x00000000 +#define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f +#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmATDMA_MISC_CNTL_DEFAULT 0x04040001 +#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 +#define mmS2A_MISC_CNTL_DEFAULT 0x00000000 +#define mmGDC_PG_MISC_CNTL_DEFAULT 0x00000000 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 +#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: syshub_mmreg_ind_syshubind +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 +#define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 +#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080 +#define ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH_DEFAULT 0x00000040 +#define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080 +#define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD_DEFAULT 0x00000000 +#define ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h new file mode 100644 index 000000000000..435462294fbc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h @@ -0,0 +1,4640 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _nbio_7_0_OFFSET_HEADER +#define _nbio_7_0_OFFSET_HEADER + + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +// base address: 0x0 +#define cfgNB_NBCFG0_NB_VENDOR_ID 0x0000 +#define cfgNB_NBCFG0_NB_DEVICE_ID 0x0002 +#define cfgNB_NBCFG0_NB_COMMAND 0x0004 +#define cfgNB_NBCFG0_NB_STATUS 0x0006 +#define cfgNB_NBCFG0_NB_REVISION_ID 0x0008 +#define cfgNB_NBCFG0_NB_REGPROG_INF 0x0009 +#define cfgNB_NBCFG0_NB_SUB_CLASS 0x000a +#define cfgNB_NBCFG0_NB_BASE_CODE 0x000b +#define cfgNB_NBCFG0_NB_CACHE_LINE 0x000c +#define cfgNB_NBCFG0_NB_LATENCY 0x000d +#define cfgNB_NBCFG0_NB_HEADER 0x000e +#define cfgNB_NBCFG0_NB_ADAPTER_ID 0x002c +#define cfgNB_NBCFG0_NB_CAPABILITIES_PTR 0x0034 +#define cfgNB_NBCFG0_NB_HEADER_W 0x0048 +#define cfgNB_NBCFG0_NB_PCI_CTRL 0x004c +#define cfgNB_NBCFG0_NB_ADAPTER_ID_W 0x0050 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 0x005c +#define cfgNB_NBCFG0_NB_SMN_INDEX_0 0x0060 +#define cfgNB_NBCFG0_NB_SMN_DATA_0 0x0064 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_0 0x0068 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_1 0x006c +#define cfgNB_NBCFG0_NBCFG_SCRATCH_2 0x0070 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_3 0x0074 +#define cfgNB_NBCFG0_NBCFG_SCRATCH_4 0x0078 +#define cfgNB_NBCFG0_NB_PCI_ARB 0x0084 +#define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE 0x0088 +#define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 0x0090 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 0x009c +#define cfgNB_NBCFG0_NB_SMN_INDEX_1 0x00a0 +#define cfgNB_NBCFG0_NB_SMN_DATA_1 0x00a4 +#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0 0x00a8 +#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1 0x00ac +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 0x00b4 +#define cfgNB_NBCFG0_NB_SMN_INDEX_2 0x00b8 +#define cfgNB_NBCFG0_NB_SMN_DATA_2 0x00bc +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 0x00c0 +#define cfgNB_NBCFG0_NB_SMN_INDEX_3 0x00c4 +#define cfgNB_NBCFG0_NB_SMN_DATA_3 0x00c8 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 0x00cc +#define cfgNB_NBCFG0_NB_SMN_INDEX_4 0x00d0 +#define cfgNB_NBCFG0_NB_SMN_DATA_4 0x00d4 +#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 0x00dc +#define cfgNB_NBCFG0_NB_SMN_INDEX_5 0x00e0 +#define cfgNB_NBCFG0_NB_SMN_DATA_5 0x00e4 +#define cfgNB_NBCFG0_NB_PERF_CNT_CTRL 0x00f4 +#define cfgNB_NBCFG0_NB_SMN_INDEX_6 0x00f8 +#define cfgNB_NBCFG0_NB_SMN_DATA_6 0x00fc + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +// base address: 0x0 +#define cfgIOMMU_L2_0_IOMMU_VENDOR_ID 0x0000 +#define cfgIOMMU_L2_0_IOMMU_DEVICE_ID 0x0002 +#define cfgIOMMU_L2_0_IOMMU_COMMAND 0x0004 +#define cfgIOMMU_L2_0_IOMMU_STATUS 0x0006 +#define cfgIOMMU_L2_0_IOMMU_REVISION_ID 0x0008 +#define cfgIOMMU_L2_0_IOMMU_REGPROG_INF 0x0009 +#define cfgIOMMU_L2_0_IOMMU_SUB_CLASS 0x000a +#define cfgIOMMU_L2_0_IOMMU_BASE_CODE 0x000b +#define cfgIOMMU_L2_0_IOMMU_CACHE_LINE 0x000c +#define cfgIOMMU_L2_0_IOMMU_LATENCY 0x000d +#define cfgIOMMU_L2_0_IOMMU_HEADER 0x000e +#define cfgIOMMU_L2_0_IOMMU_BIST 0x000f +#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID 0x002c +#define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR 0x0034 +#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE 0x003c +#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN 0x003d +#define cfgIOMMU_L2_0_IOMMU_CAP_HEADER 0x0040 +#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO 0x0044 +#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI 0x0048 +#define cfgIOMMU_L2_0_IOMMU_CAP_RANGE 0x004c +#define cfgIOMMU_L2_0_IOMMU_CAP_MISC 0x0050 +#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1 0x0054 +#define cfgIOMMU_L2_0_IOMMU_MSI_CAP 0x0064 +#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO 0x0068 +#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI 0x006c +#define cfgIOMMU_L2_0_IOMMU_MSI_DATA 0x0070 +#define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP 0x0074 +#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W 0x0078 +#define cfgIOMMU_L2_0_IOMMU_CONTROL_W 0x007c +#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W 0x0080 +#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W 0x0084 +#define cfgIOMMU_L2_0_IOMMU_RANGE_W 0x0088 +#define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL 0x008c +#define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0 0x0090 +#define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0 0x0094 +#define cfgIOMMU_L2_0_L2B_POISON_DVM_CNTRL 0x0098 +#define cfgIOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control 0x009c +#define cfgIOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control 0x00a0 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR0_W 0x00a4 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR1_W 0x00a8 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR2_W 0x00ac +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR3_W 0x00b0 +#define cfgIOMMU_L2_0_SMMU_MMIO_IDR5_W 0x00b8 +#define cfgIOMMU_L2_0_SMMU_MMIO_IIDR_W 0x00bc +#define cfgIOMMU_L2_0_SMMU_AIDR_W 0x00c0 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC0_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_RC0_ROOT_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_RC0_ROOT_CAP 0x0076 +#define cfgBIF_CFG_DEV0_RC0_ROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP 0x00ca +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x02a6 + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV1_RC0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV1_RC0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV1_RC0_STATUS 0x0006 +#define cfgBIF_CFG_DEV1_RC0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV1_RC0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV1_RC0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV1_RC0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV1_RC0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV1_RC0_LATENCY 0x000d +#define cfgBIF_CFG_DEV1_RC0_HEADER 0x000e +#define cfgBIF_CFG_DEV1_RC0_BIST 0x000f +#define cfgBIF_CFG_DEV1_RC0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV1_RC0_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV1_RC0_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV1_RC0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV1_RC0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV1_RC0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV1_RC0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV1_RC0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV1_RC0_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV1_RC0_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV1_RC0_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV1_RC0_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV1_RC0_ROOT_CNTL 0x0074 +#define cfgBIF_CFG_DEV1_RC0_ROOT_CAP 0x0076 +#define cfgBIF_CFG_DEV1_RC0_ROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV1_RC0_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV1_RC0_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV1_RC0_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV1_RC0_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV1_RC0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV1_RC0_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV1_RC0_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP 0x00ca +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL 0x02a6 + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +// base address: 0x0 +#define cfgNB_PCIEDUMMY0_0_DEVICE_VENDOR_ID 0x0000 +#define cfgNB_PCIEDUMMY0_0_STATUS_COMMAND 0x0004 +#define cfgNB_PCIEDUMMY0_0_CLASS_CODE_REVID 0x0008 +#define cfgNB_PCIEDUMMY0_0_HEADER_TYPE 0x000c +#define cfgNB_PCIEDUMMY0_0_HEADER_TYPE_W 0x0040 + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +// base address: 0x0 +#define cfgNB_PCIEDUMMY1_0_DEVICE_VENDOR_ID 0x0000 +#define cfgNB_PCIEDUMMY1_0_STATUS_COMMAND 0x0004 +#define cfgNB_PCIEDUMMY1_0_CLASS_CODE_REVID 0x0008 +#define cfgNB_PCIEDUMMY1_0_HEADER_TYPE 0x000c +#define cfgNB_PCIEDUMMY1_0_HEADER_TYPE_W 0x0040 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgVENDOR_ID 0x0000 +#define cfgDEVICE_ID 0x0002 +#define cfgCOMMAND 0x0004 +#define cfgSTATUS 0x0006 +#define cfgREVISION_ID 0x0008 +#define cfgPROG_INTERFACE 0x0009 +#define cfgSUB_CLASS 0x000a +#define cfgBASE_CLASS 0x000b +#define cfgCACHE_LINE 0x000c +#define cfgLATENCY 0x000d +#define cfgHEADER 0x000e +#define cfgBIST 0x000f +#define cfgBASE_ADDR_1 0x0010 +#define cfgBASE_ADDR_2 0x0014 +#define cfgBASE_ADDR_3 0x0018 +#define cfgBASE_ADDR_4 0x001c +#define cfgBASE_ADDR_5 0x0020 +#define cfgBASE_ADDR_6 0x0024 +#define cfgADAPTER_ID 0x002c +#define cfgROM_BASE_ADDR 0x0030 +#define cfgCAP_PTR 0x0034 +#define cfgINTERRUPT_LINE 0x003c +#define cfgINTERRUPT_PIN 0x003d +#define cfgMIN_GRANT 0x003e +#define cfgMAX_LATENCY 0x003f +#define cfgVENDOR_CAP_LIST 0x0048 +#define cfgADAPTER_ID_W 0x004c +#define cfgPMI_CAP_LIST 0x0050 +#define cfgPMI_CAP 0x0052 +#define cfgPMI_STATUS_CNTL 0x0054 +#define cfgPCIE_CAP_LIST 0x0064 +#define cfgPCIE_CAP 0x0066 +#define cfgDEVICE_CAP 0x0068 +#define cfgDEVICE_CNTL 0x006c +#define cfgDEVICE_STATUS 0x006e +#define cfgLINK_CAP 0x0070 +#define cfgLINK_CNTL 0x0074 +#define cfgLINK_STATUS 0x0076 +#define cfgDEVICE_CAP2 0x0088 +#define cfgDEVICE_CNTL2 0x008c +#define cfgDEVICE_STATUS2 0x008e +#define cfgLINK_CAP2 0x0090 +#define cfgLINK_CNTL2 0x0094 +#define cfgLINK_STATUS2 0x0096 +#define cfgSLOT_CAP2 0x0098 +#define cfgSLOT_CNTL2 0x009c +#define cfgSLOT_STATUS2 0x009e +#define cfgMSI_CAP_LIST 0x00a0 +#define cfgMSI_MSG_CNTL 0x00a2 +#define cfgMSI_MSG_ADDR_LO 0x00a4 +#define cfgMSI_MSG_ADDR_HI 0x00a8 +#define cfgMSI_MSG_DATA 0x00a8 +#define cfgMSI_MASK 0x00ac +#define cfgMSI_MSG_DATA_64 0x00ac +#define cfgMSI_MASK_64 0x00b0 +#define cfgMSI_PENDING 0x00b0 +#define cfgMSI_PENDING_64 0x00b4 +#define cfgMSIX_CAP_LIST 0x00c0 +#define cfgMSIX_MSG_CNTL 0x00c2 +#define cfgMSIX_TABLE 0x00c4 +#define cfgMSIX_PBA 0x00c8 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgPCIE_VENDOR_SPECIFIC2 0x010c +#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgPCIE_PORT_VC_CNTL 0x011c +#define cfgPCIE_PORT_VC_STATUS 0x011e +#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgPCIE_VC1_RESOURCE_CAP 0x012c +#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgPCIE_UNCORR_ERR_MASK 0x0158 +#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgPCIE_CORR_ERR_STATUS 0x0160 +#define cfgPCIE_CORR_ERR_MASK 0x0164 +#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgPCIE_HDR_LOG0 0x016c +#define cfgPCIE_HDR_LOG1 0x0170 +#define cfgPCIE_HDR_LOG2 0x0174 +#define cfgPCIE_HDR_LOG3 0x0178 +#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgPCIE_TLP_PREFIX_LOG1 0x018c +#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgPCIE_BAR1_CAP 0x0204 +#define cfgPCIE_BAR1_CNTL 0x0208 +#define cfgPCIE_BAR2_CAP 0x020c +#define cfgPCIE_BAR2_CNTL 0x0210 +#define cfgPCIE_BAR3_CAP 0x0214 +#define cfgPCIE_BAR3_CNTL 0x0218 +#define cfgPCIE_BAR4_CAP 0x021c +#define cfgPCIE_BAR4_CNTL 0x0220 +#define cfgPCIE_BAR5_CAP 0x0224 +#define cfgPCIE_BAR5_CNTL 0x0228 +#define cfgPCIE_BAR6_CAP 0x022c +#define cfgPCIE_BAR6_CNTL 0x0230 +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgPCIE_PWR_BUDGET_DATA 0x0248 +#define cfgPCIE_PWR_BUDGET_CAP 0x024c +#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgPCIE_DPA_CAP 0x0254 +#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgPCIE_DPA_STATUS 0x025c +#define cfgPCIE_DPA_CNTL 0x025e +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgPCIE_LINK_CNTL3 0x0274 +#define cfgPCIE_LANE_ERROR_STATUS 0x0278 +#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgPCIE_ACS_CAP 0x02a4 +#define cfgPCIE_ACS_CNTL 0x02a6 +#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgPCIE_ATS_CAP 0x02b4 +#define cfgPCIE_ATS_CNTL 0x02b6 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgPCIE_PASID_CAP 0x02d4 +#define cfgPCIE_PASID_CNTL 0x02d6 +#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 +#define cfgPCIE_TPH_REQR_CAP 0x02e4 +#define cfgPCIE_TPH_REQR_CNTL 0x02e8 +#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgPCIE_MC_CAP 0x02f4 +#define cfgPCIE_MC_CNTL 0x02f6 +#define cfgPCIE_MC_ADDR0 0x02f8 +#define cfgPCIE_MC_ADDR1 0x02fc +#define cfgPCIE_MC_RCV0 0x0300 +#define cfgPCIE_MC_RCV1 0x0304 +#define cfgPCIE_MC_BLOCK_ALL0 0x0308 +#define cfgPCIE_MC_BLOCK_ALL1 0x030c +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgPCIE_LTR_CAP 0x0324 +#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgPCIE_ARI_CAP 0x032c +#define cfgPCIE_ARI_CNTL 0x032e +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgPCIE_SRIOV_CAP 0x0334 +#define cfgPCIE_SRIOV_CONTROL 0x0338 +#define cfgPCIE_SRIOV_STATUS 0x033a +#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgPCIE_SRIOV_NUM_VFS 0x0340 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 +//#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +//#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +//#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +//#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +//#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +//#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +//#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +//#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +//#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +//#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +//#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +//#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +//#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +//#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +//#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +//#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +//#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +//#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +//#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +//#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 +//#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c +//#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +//#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +//#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +//#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +//#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +//#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +//#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +//#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +//#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +//#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +//#define cfgBIF_CFG_DEV0_EPF0_SLOT_CAP2 0x0098 +//#define cfgBIF_CFG_DEV0_EPF0_SLOT_CNTL2 0x009c +//#define cfgBIF_CFG_DEV0_EPF0_SLOT_STATUS2 0x009e +//#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +//#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +//#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +//#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +//#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +//#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +//#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL 0x02c4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS 0x02c6 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP 0x02e4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL 0x02e8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec +//#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF2_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF3_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF4_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF4_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF4_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF4_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF4_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF4_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF4_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF4_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF4_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF4_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF4_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF4_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF4_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF4_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF4_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF5_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF5_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF5_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF5_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF5_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF5_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF5_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF5_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF5_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF5_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF5_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF5_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF5_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF5_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF5_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF6_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF6_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF6_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF6_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF6_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF6_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF6_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF6_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF6_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF6_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF6_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF6_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF6_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF6_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF6_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF7_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF7_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF7_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF7_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF7_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF7_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF7_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF7_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF7_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF7_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF7_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF7_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF7_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV0_EPF7_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF7_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV1_EPF0_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV1_EPF0_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV1_EPF0_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV1_EPF0_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV1_EPF0_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV1_EPF0_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV1_EPF0_0_HEADER 0x000e +#define cfgBIF_CFG_DEV1_EPF0_0_BIST 0x000f +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV1_EPF0_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV1_EPF0_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV1_EPF0_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV1_EPF0_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV1_EPF0_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV1_EPF1_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV1_EPF1_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV1_EPF1_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV1_EPF1_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV1_EPF1_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV1_EPF1_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV1_EPF1_0_HEADER 0x000e +#define cfgBIF_CFG_DEV1_EPF1_0_BIST 0x000f +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV1_EPF1_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV1_EPF1_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV1_EPF1_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV1_EPF1_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV1_EPF1_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV1_EPF1_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV1_EPF1_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV1_EPF2_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV1_EPF2_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV1_EPF2_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV1_EPF2_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV1_EPF2_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV1_EPF2_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV1_EPF2_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV1_EPF2_0_HEADER 0x000e +#define cfgBIF_CFG_DEV1_EPF2_0_BIST 0x000f +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV1_EPF2_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV1_EPF2_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV1_EPF2_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV1_EPF2_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV1_EPF2_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV1_EPF2_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CAP2 0x0098 +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CNTL2 0x009c +#define cfgBIF_CFG_DEV1_EPF2_0_SLOT_STATUS2 0x009e +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV1_EPF2_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +// base address: 0x0 +#define cfgBIFPLR0_0_VENDOR_ID 0x0000 +#define cfgBIFPLR0_0_DEVICE_ID 0x0002 +#define cfgBIFPLR0_0_COMMAND 0x0004 +#define cfgBIFPLR0_0_STATUS 0x0006 +#define cfgBIFPLR0_0_REVISION_ID 0x0008 +#define cfgBIFPLR0_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR0_0_SUB_CLASS 0x000a +#define cfgBIFPLR0_0_BASE_CLASS 0x000b +#define cfgBIFPLR0_0_CACHE_LINE 0x000c +#define cfgBIFPLR0_0_LATENCY 0x000d +#define cfgBIFPLR0_0_HEADER 0x000e +#define cfgBIFPLR0_0_BIST 0x000f +#define cfgBIFPLR0_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR0_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR0_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR0_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR0_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR0_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR0_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR0_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR0_0_CAP_PTR 0x0034 +#define cfgBIFPLR0_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR0_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR0_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR0_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR0_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR0_0_PMI_CAP 0x0052 +#define cfgBIFPLR0_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR0_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR0_0_PCIE_CAP 0x005a +#define cfgBIFPLR0_0_DEVICE_CAP 0x005c +#define cfgBIFPLR0_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR0_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR0_0_LINK_CAP 0x0064 +#define cfgBIFPLR0_0_LINK_CNTL 0x0068 +#define cfgBIFPLR0_0_LINK_STATUS 0x006a +#define cfgBIFPLR0_0_SLOT_CAP 0x006c +#define cfgBIFPLR0_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR0_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR0_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR0_0_ROOT_CAP 0x0076 +#define cfgBIFPLR0_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR0_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR0_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR0_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR0_0_LINK_CAP2 0x0084 +#define cfgBIFPLR0_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR0_0_LINK_STATUS2 0x008a +#define cfgBIFPLR0_0_SLOT_CAP2 0x008c +#define cfgBIFPLR0_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR0_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR0_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR0_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR0_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR0_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR0_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR0_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR0_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR0_0_SSID_CAP 0x00c4 +#define cfgBIFPLR0_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR0_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR0_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR0_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR0_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR0_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR0_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR0_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR0_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR0_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR0_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR0_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR0_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR0_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR0_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR0_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR0_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR0_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR0_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR0_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR0_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR0_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR0_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR0_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR0_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR0_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR0_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR0_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR0_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR0_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR0_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR0_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR0_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR0_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR0_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR0_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR0_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR0_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR0_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR0_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +// base address: 0x0 +#define cfgBIFPLR1_0_VENDOR_ID 0x0000 +#define cfgBIFPLR1_0_DEVICE_ID 0x0002 +#define cfgBIFPLR1_0_COMMAND 0x0004 +#define cfgBIFPLR1_0_STATUS 0x0006 +#define cfgBIFPLR1_0_REVISION_ID 0x0008 +#define cfgBIFPLR1_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR1_0_SUB_CLASS 0x000a +#define cfgBIFPLR1_0_BASE_CLASS 0x000b +#define cfgBIFPLR1_0_CACHE_LINE 0x000c +#define cfgBIFPLR1_0_LATENCY 0x000d +#define cfgBIFPLR1_0_HEADER 0x000e +#define cfgBIFPLR1_0_BIST 0x000f +#define cfgBIFPLR1_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR1_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR1_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR1_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR1_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR1_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR1_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR1_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR1_0_CAP_PTR 0x0034 +#define cfgBIFPLR1_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR1_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR1_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR1_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR1_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR1_0_PMI_CAP 0x0052 +#define cfgBIFPLR1_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR1_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR1_0_PCIE_CAP 0x005a +#define cfgBIFPLR1_0_DEVICE_CAP 0x005c +#define cfgBIFPLR1_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR1_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR1_0_LINK_CAP 0x0064 +#define cfgBIFPLR1_0_LINK_CNTL 0x0068 +#define cfgBIFPLR1_0_LINK_STATUS 0x006a +#define cfgBIFPLR1_0_SLOT_CAP 0x006c +#define cfgBIFPLR1_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR1_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR1_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR1_0_ROOT_CAP 0x0076 +#define cfgBIFPLR1_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR1_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR1_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR1_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR1_0_LINK_CAP2 0x0084 +#define cfgBIFPLR1_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR1_0_LINK_STATUS2 0x008a +#define cfgBIFPLR1_0_SLOT_CAP2 0x008c +#define cfgBIFPLR1_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR1_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR1_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR1_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR1_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR1_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR1_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR1_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR1_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR1_0_SSID_CAP 0x00c4 +#define cfgBIFPLR1_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR1_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR1_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR1_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR1_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR1_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR1_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR1_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR1_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR1_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR1_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR1_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR1_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR1_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR1_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR1_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR1_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR1_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR1_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR1_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR1_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR1_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR1_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR1_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR1_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR1_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR1_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR1_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR1_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR1_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR1_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR1_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR1_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR1_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR1_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR1_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR1_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR1_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR1_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR1_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +// base address: 0x0 +#define cfgBIFPLR2_0_VENDOR_ID 0x0000 +#define cfgBIFPLR2_0_DEVICE_ID 0x0002 +#define cfgBIFPLR2_0_COMMAND 0x0004 +#define cfgBIFPLR2_0_STATUS 0x0006 +#define cfgBIFPLR2_0_REVISION_ID 0x0008 +#define cfgBIFPLR2_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR2_0_SUB_CLASS 0x000a +#define cfgBIFPLR2_0_BASE_CLASS 0x000b +#define cfgBIFPLR2_0_CACHE_LINE 0x000c +#define cfgBIFPLR2_0_LATENCY 0x000d +#define cfgBIFPLR2_0_HEADER 0x000e +#define cfgBIFPLR2_0_BIST 0x000f +#define cfgBIFPLR2_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR2_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR2_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR2_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR2_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR2_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR2_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR2_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR2_0_CAP_PTR 0x0034 +#define cfgBIFPLR2_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR2_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR2_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR2_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR2_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR2_0_PMI_CAP 0x0052 +#define cfgBIFPLR2_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR2_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR2_0_PCIE_CAP 0x005a +#define cfgBIFPLR2_0_DEVICE_CAP 0x005c +#define cfgBIFPLR2_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR2_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR2_0_LINK_CAP 0x0064 +#define cfgBIFPLR2_0_LINK_CNTL 0x0068 +#define cfgBIFPLR2_0_LINK_STATUS 0x006a +#define cfgBIFPLR2_0_SLOT_CAP 0x006c +#define cfgBIFPLR2_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR2_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR2_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR2_0_ROOT_CAP 0x0076 +#define cfgBIFPLR2_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR2_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR2_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR2_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR2_0_LINK_CAP2 0x0084 +#define cfgBIFPLR2_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR2_0_LINK_STATUS2 0x008a +#define cfgBIFPLR2_0_SLOT_CAP2 0x008c +#define cfgBIFPLR2_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR2_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR2_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR2_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR2_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR2_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR2_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR2_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR2_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR2_0_SSID_CAP 0x00c4 +#define cfgBIFPLR2_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR2_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR2_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR2_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR2_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR2_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR2_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR2_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR2_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR2_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR2_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR2_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR2_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR2_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR2_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR2_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR2_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR2_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR2_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR2_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR2_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR2_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR2_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR2_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR2_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR2_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR2_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR2_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR2_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR2_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR2_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR2_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR2_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR2_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR2_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR2_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR2_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR2_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR2_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR2_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR2_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +// base address: 0x0 +#define cfgBIFPLR3_0_VENDOR_ID 0x0000 +#define cfgBIFPLR3_0_DEVICE_ID 0x0002 +#define cfgBIFPLR3_0_COMMAND 0x0004 +#define cfgBIFPLR3_0_STATUS 0x0006 +#define cfgBIFPLR3_0_REVISION_ID 0x0008 +#define cfgBIFPLR3_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR3_0_SUB_CLASS 0x000a +#define cfgBIFPLR3_0_BASE_CLASS 0x000b +#define cfgBIFPLR3_0_CACHE_LINE 0x000c +#define cfgBIFPLR3_0_LATENCY 0x000d +#define cfgBIFPLR3_0_HEADER 0x000e +#define cfgBIFPLR3_0_BIST 0x000f +#define cfgBIFPLR3_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR3_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR3_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR3_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR3_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR3_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR3_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR3_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR3_0_CAP_PTR 0x0034 +#define cfgBIFPLR3_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR3_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR3_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR3_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR3_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR3_0_PMI_CAP 0x0052 +#define cfgBIFPLR3_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR3_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR3_0_PCIE_CAP 0x005a +#define cfgBIFPLR3_0_DEVICE_CAP 0x005c +#define cfgBIFPLR3_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR3_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR3_0_LINK_CAP 0x0064 +#define cfgBIFPLR3_0_LINK_CNTL 0x0068 +#define cfgBIFPLR3_0_LINK_STATUS 0x006a +#define cfgBIFPLR3_0_SLOT_CAP 0x006c +#define cfgBIFPLR3_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR3_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR3_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR3_0_ROOT_CAP 0x0076 +#define cfgBIFPLR3_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR3_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR3_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR3_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR3_0_LINK_CAP2 0x0084 +#define cfgBIFPLR3_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR3_0_LINK_STATUS2 0x008a +#define cfgBIFPLR3_0_SLOT_CAP2 0x008c +#define cfgBIFPLR3_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR3_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR3_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR3_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR3_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR3_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR3_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR3_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR3_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR3_0_SSID_CAP 0x00c4 +#define cfgBIFPLR3_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR3_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR3_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR3_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR3_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR3_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR3_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR3_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR3_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR3_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR3_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR3_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR3_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR3_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR3_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR3_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR3_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR3_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR3_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR3_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR3_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR3_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR3_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR3_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR3_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR3_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR3_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR3_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR3_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR3_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR3_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR3_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR3_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR3_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR3_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR3_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR3_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR3_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR3_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR3_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR3_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +// base address: 0x0 +#define cfgBIFPLR4_0_VENDOR_ID 0x0000 +#define cfgBIFPLR4_0_DEVICE_ID 0x0002 +#define cfgBIFPLR4_0_COMMAND 0x0004 +#define cfgBIFPLR4_0_STATUS 0x0006 +#define cfgBIFPLR4_0_REVISION_ID 0x0008 +#define cfgBIFPLR4_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR4_0_SUB_CLASS 0x000a +#define cfgBIFPLR4_0_BASE_CLASS 0x000b +#define cfgBIFPLR4_0_CACHE_LINE 0x000c +#define cfgBIFPLR4_0_LATENCY 0x000d +#define cfgBIFPLR4_0_HEADER 0x000e +#define cfgBIFPLR4_0_BIST 0x000f +#define cfgBIFPLR4_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR4_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR4_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR4_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR4_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR4_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR4_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR4_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR4_0_CAP_PTR 0x0034 +#define cfgBIFPLR4_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR4_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR4_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR4_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR4_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR4_0_PMI_CAP 0x0052 +#define cfgBIFPLR4_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR4_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR4_0_PCIE_CAP 0x005a +#define cfgBIFPLR4_0_DEVICE_CAP 0x005c +#define cfgBIFPLR4_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR4_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR4_0_LINK_CAP 0x0064 +#define cfgBIFPLR4_0_LINK_CNTL 0x0068 +#define cfgBIFPLR4_0_LINK_STATUS 0x006a +#define cfgBIFPLR4_0_SLOT_CAP 0x006c +#define cfgBIFPLR4_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR4_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR4_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR4_0_ROOT_CAP 0x0076 +#define cfgBIFPLR4_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR4_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR4_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR4_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR4_0_LINK_CAP2 0x0084 +#define cfgBIFPLR4_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR4_0_LINK_STATUS2 0x008a +#define cfgBIFPLR4_0_SLOT_CAP2 0x008c +#define cfgBIFPLR4_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR4_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR4_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR4_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR4_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR4_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR4_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR4_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR4_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR4_0_SSID_CAP 0x00c4 +#define cfgBIFPLR4_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR4_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR4_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR4_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR4_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR4_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR4_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR4_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR4_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR4_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR4_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR4_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR4_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR4_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR4_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR4_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR4_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR4_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR4_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR4_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR4_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR4_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR4_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR4_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR4_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR4_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR4_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR4_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR4_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR4_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR4_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR4_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR4_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR4_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR4_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR4_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR4_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR4_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR4_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR4_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR4_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +// base address: 0x0 +#define cfgBIFPLR5_0_VENDOR_ID 0x0000 +#define cfgBIFPLR5_0_DEVICE_ID 0x0002 +#define cfgBIFPLR5_0_COMMAND 0x0004 +#define cfgBIFPLR5_0_STATUS 0x0006 +#define cfgBIFPLR5_0_REVISION_ID 0x0008 +#define cfgBIFPLR5_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR5_0_SUB_CLASS 0x000a +#define cfgBIFPLR5_0_BASE_CLASS 0x000b +#define cfgBIFPLR5_0_CACHE_LINE 0x000c +#define cfgBIFPLR5_0_LATENCY 0x000d +#define cfgBIFPLR5_0_HEADER 0x000e +#define cfgBIFPLR5_0_BIST 0x000f +#define cfgBIFPLR5_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR5_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR5_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR5_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR5_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR5_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR5_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR5_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR5_0_CAP_PTR 0x0034 +#define cfgBIFPLR5_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR5_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR5_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR5_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR5_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR5_0_PMI_CAP 0x0052 +#define cfgBIFPLR5_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR5_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR5_0_PCIE_CAP 0x005a +#define cfgBIFPLR5_0_DEVICE_CAP 0x005c +#define cfgBIFPLR5_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR5_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR5_0_LINK_CAP 0x0064 +#define cfgBIFPLR5_0_LINK_CNTL 0x0068 +#define cfgBIFPLR5_0_LINK_STATUS 0x006a +#define cfgBIFPLR5_0_SLOT_CAP 0x006c +#define cfgBIFPLR5_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR5_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR5_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR5_0_ROOT_CAP 0x0076 +#define cfgBIFPLR5_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR5_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR5_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR5_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR5_0_LINK_CAP2 0x0084 +#define cfgBIFPLR5_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR5_0_LINK_STATUS2 0x008a +#define cfgBIFPLR5_0_SLOT_CAP2 0x008c +#define cfgBIFPLR5_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR5_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR5_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR5_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR5_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR5_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR5_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR5_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR5_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR5_0_SSID_CAP 0x00c4 +#define cfgBIFPLR5_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR5_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR5_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR5_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR5_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR5_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR5_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR5_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR5_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR5_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR5_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR5_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR5_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR5_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR5_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR5_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR5_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR5_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR5_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR5_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR5_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR5_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR5_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR5_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR5_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR5_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR5_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR5_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR5_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR5_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR5_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR5_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR5_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR5_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR5_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR5_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR5_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR5_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR5_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR5_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR5_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +// base address: 0x0 +#define cfgBIFPLR6_0_VENDOR_ID 0x0000 +#define cfgBIFPLR6_0_DEVICE_ID 0x0002 +#define cfgBIFPLR6_0_COMMAND 0x0004 +#define cfgBIFPLR6_0_STATUS 0x0006 +#define cfgBIFPLR6_0_REVISION_ID 0x0008 +#define cfgBIFPLR6_0_PROG_INTERFACE 0x0009 +#define cfgBIFPLR6_0_SUB_CLASS 0x000a +#define cfgBIFPLR6_0_BASE_CLASS 0x000b +#define cfgBIFPLR6_0_CACHE_LINE 0x000c +#define cfgBIFPLR6_0_LATENCY 0x000d +#define cfgBIFPLR6_0_HEADER 0x000e +#define cfgBIFPLR6_0_BIST 0x000f +#define cfgBIFPLR6_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIFPLR6_0_IO_BASE_LIMIT 0x001c +#define cfgBIFPLR6_0_SECONDARY_STATUS 0x001e +#define cfgBIFPLR6_0_MEM_BASE_LIMIT 0x0020 +#define cfgBIFPLR6_0_PREF_BASE_LIMIT 0x0024 +#define cfgBIFPLR6_0_PREF_BASE_UPPER 0x0028 +#define cfgBIFPLR6_0_PREF_LIMIT_UPPER 0x002c +#define cfgBIFPLR6_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIFPLR6_0_CAP_PTR 0x0034 +#define cfgBIFPLR6_0_INTERRUPT_LINE 0x003c +#define cfgBIFPLR6_0_INTERRUPT_PIN 0x003d +#define cfgBIFPLR6_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIFPLR6_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIFPLR6_0_PMI_CAP_LIST 0x0050 +#define cfgBIFPLR6_0_PMI_CAP 0x0052 +#define cfgBIFPLR6_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIFPLR6_0_PCIE_CAP_LIST 0x0058 +#define cfgBIFPLR6_0_PCIE_CAP 0x005a +#define cfgBIFPLR6_0_DEVICE_CAP 0x005c +#define cfgBIFPLR6_0_DEVICE_CNTL 0x0060 +#define cfgBIFPLR6_0_DEVICE_STATUS 0x0062 +#define cfgBIFPLR6_0_LINK_CAP 0x0064 +#define cfgBIFPLR6_0_LINK_CNTL 0x0068 +#define cfgBIFPLR6_0_LINK_STATUS 0x006a +#define cfgBIFPLR6_0_SLOT_CAP 0x006c +#define cfgBIFPLR6_0_SLOT_CNTL 0x0070 +#define cfgBIFPLR6_0_SLOT_STATUS 0x0072 +#define cfgBIFPLR6_0_ROOT_CNTL 0x0074 +#define cfgBIFPLR6_0_ROOT_CAP 0x0076 +#define cfgBIFPLR6_0_ROOT_STATUS 0x0078 +#define cfgBIFPLR6_0_DEVICE_CAP2 0x007c +#define cfgBIFPLR6_0_DEVICE_CNTL2 0x0080 +#define cfgBIFPLR6_0_DEVICE_STATUS2 0x0082 +#define cfgBIFPLR6_0_LINK_CAP2 0x0084 +#define cfgBIFPLR6_0_LINK_CNTL2 0x0088 +#define cfgBIFPLR6_0_LINK_STATUS2 0x008a +#define cfgBIFPLR6_0_SLOT_CAP2 0x008c +#define cfgBIFPLR6_0_SLOT_CNTL2 0x0090 +#define cfgBIFPLR6_0_SLOT_STATUS2 0x0092 +#define cfgBIFPLR6_0_MSI_CAP_LIST 0x00a0 +#define cfgBIFPLR6_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIFPLR6_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIFPLR6_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIFPLR6_0_MSI_MSG_DATA 0x00a8 +#define cfgBIFPLR6_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIFPLR6_0_SSID_CAP_LIST 0x00c0 +#define cfgBIFPLR6_0_SSID_CAP 0x00c4 +#define cfgBIFPLR6_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgBIFPLR6_0_MSI_MAP_CAP 0x00ca +#define cfgBIFPLR6_0_MSI_MAP_ADDR_LO 0x00cc +#define cfgBIFPLR6_0_MSI_MAP_ADDR_HI 0x00d0 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIFPLR6_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIFPLR6_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIFPLR6_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIFPLR6_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIFPLR6_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIFPLR6_0_PCIE_HDR_LOG0 0x016c +#define cfgBIFPLR6_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIFPLR6_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIFPLR6_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIFPLR6_0_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIFPLR6_0_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIFPLR6_0_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIFPLR6_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIFPLR6_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIFPLR6_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIFPLR6_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIFPLR6_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIFPLR6_0_PCIE_MC_CAP 0x02f4 +#define cfgBIFPLR6_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIFPLR6_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIFPLR6_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIFPLR6_0_PCIE_MC_RCV0 0x0300 +#define cfgBIFPLR6_0_PCIE_MC_RCV1 0x0304 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST 0x0380 +#define cfgBIFPLR6_0_PCIE_DPC_CAP_LIST 0x0384 +#define cfgBIFPLR6_0_PCIE_DPC_CNTL 0x0386 +#define cfgBIFPLR6_0_PCIE_DPC_STATUS 0x0388 +#define cfgBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a +#define cfgBIFPLR6_0_PCIE_RP_PIO_STATUS 0x038c +#define cfgBIFPLR6_0_PCIE_RP_PIO_MASK 0x0390 +#define cfgBIFPLR6_0_PCIE_RP_PIO_SEVERITY 0x0394 +#define cfgBIFPLR6_0_PCIE_RP_PIO_SYSERROR 0x0398 +#define cfgBIFPLR6_0_PCIE_RP_PIO_EXCEPTION 0x039c +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 +#define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 0x03ac +#define cfgBIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc +#define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgBIFPLR6_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgBIFPLR6_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgBIFPLR6_0_PCIE_ESM_STATUS 0x03ce +#define cfgBIFPLR6_0_PCIE_ESM_CTRL 0x03d0 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_3 0x03dc +#define cfgBIFPLR6_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgBIFPLR6_0_PCIE_ESM_CAP_7 0x03ec + + +// addressBlock: nbio_dbgu0_dbgudec +// base address: 0x700 +#define mmport_a_addr 0x01ac +#define mmport_a_addr_BASE_IDX 1 +#define mmport_a_data_lo 0x01ad +#define mmport_a_data_lo_BASE_IDX 1 +#define mmport_a_data_hi 0x01ae +#define mmport_a_data_hi_BASE_IDX 1 +#define mmport_b_addr 0x01af +#define mmport_b_addr_BASE_IDX 1 +#define mmport_b_data_lo 0x01b0 +#define mmport_b_data_lo_BASE_IDX 1 +#define mmport_b_data_hi 0x01b1 +#define mmport_b_data_hi_BASE_IDX 1 +#define mmport_c_addr 0x01b2 +#define mmport_c_addr_BASE_IDX 1 +#define mmport_c_data_lo 0x01b3 +#define mmport_c_data_lo_BASE_IDX 1 +#define mmport_c_data_hi 0x01b4 +#define mmport_c_data_hi_BASE_IDX 1 +#define mmport_d_addr 0x01b5 +#define mmport_d_addr_BASE_IDX 1 +#define mmport_d_data_lo 0x01b6 +#define mmport_d_data_lo_BASE_IDX 1 +#define mmport_d_data_hi 0x01b7 +#define mmport_d_data_hi_BASE_IDX 1 + + +// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg +// base address: 0x0 +#define mmIOMMU_MMIO_DEVTBL_BASE_0 0x0000 +#define mmIOMMU_MMIO_DEVTBL_BASE_0_BASE_IDX 0 +#define mmIOMMU_MMIO_DEVTBL_BASE_1 0x0001 +#define mmIOMMU_MMIO_DEVTBL_BASE_1_BASE_IDX 0 +#define mmIOMMU_MMIO_CMD_BASE_0 0x0002 +#define mmIOMMU_MMIO_CMD_BASE_0_BASE_IDX 0 +#define mmIOMMU_MMIO_CMD_BASE_1 0x0003 +#define mmIOMMU_MMIO_CMD_BASE_1_BASE_IDX 0 +#define mmIOMMU_MMIO_EVENT_BASE_0 0x0004 +#define mmIOMMU_MMIO_EVENT_BASE_0_BASE_IDX 0 +#define mmIOMMU_MMIO_EVENT_BASE_1 0x0005 +#define mmIOMMU_MMIO_EVENT_BASE_1_BASE_IDX 0 +#define mmIOMMU_MMIO_CNTRL_0 0x0006 +#define mmIOMMU_MMIO_CNTRL_0_BASE_IDX 0 +#define mmIOMMU_MMIO_CNTRL_1 0x0007 +#define mmIOMMU_MMIO_CNTRL_1_BASE_IDX 0 +#define mmIOMMU_MMIO_EXCL_BASE_0 0x0008 +#define mmIOMMU_MMIO_EXCL_BASE_0_BASE_IDX 0 +#define mmIOMMU_MMIO_EXCL_BASE_1 0x0009 +#define mmIOMMU_MMIO_EXCL_BASE_1_BASE_IDX 0 +#define mmIOMMU_MMIO_EXCL_LIM_0 0x000a +#define mmIOMMU_MMIO_EXCL_LIM_0_BASE_IDX 0 +#define mmIOMMU_MMIO_EXCL_LIM_1 0x000b +#define mmIOMMU_MMIO_EXCL_LIM_1_BASE_IDX 0 +#define mmIOMMU_MMIO_EFR_0 0x000c +#define mmIOMMU_MMIO_EFR_0_BASE_IDX 0 +#define mmIOMMU_MMIO_EFR_1 0x000d +#define mmIOMMU_MMIO_EFR_1_BASE_IDX 0 +#define mmIOMMU_MMIO_PPR_BASE_0 0x000e +#define mmIOMMU_MMIO_PPR_BASE_0_BASE_IDX 0 +#define mmIOMMU_MMIO_PPR_BASE_1 0x000f +#define mmIOMMU_MMIO_PPR_BASE_1_BASE_IDX 0 +#define mmIOMMU_MMIO_HW_ERR_UPPER_0 0x0010 +#define mmIOMMU_MMIO_HW_ERR_UPPER_0_BASE_IDX 0 +#define mmIOMMU_MMIO_HW_ERR_UPPER_1 0x0011 +#define mmIOMMU_MMIO_HW_ERR_UPPER_1_BASE_IDX 0 +#define mmIOMMU_MMIO_HW_ERR_LOWER_0 0x0012 +#define mmIOMMU_MMIO_HW_ERR_LOWER_0_BASE_IDX 0 +#define mmIOMMU_MMIO_HW_ERR_LOWER_1 0x0013 +#define mmIOMMU_MMIO_HW_ERR_LOWER_1_BASE_IDX 0 +#define mmIOMMU_MMIO_HW_ERR_STATUS_0 0x0000 +#define mmIOMMU_MMIO_HW_ERR_STATUS_0_BASE_IDX 1 +#define mmIOMMU_MMIO_HW_ERR_STATUS_1 0x0001 +#define mmIOMMU_MMIO_HW_ERR_STATUS_1_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_0_0 0x0004 +#define mmSMI_FILTER_REGISTER_0_0_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_0_1 0x0005 +#define mmSMI_FILTER_REGISTER_0_1_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_1_0 0x0006 +#define mmSMI_FILTER_REGISTER_1_0_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_1_1 0x0007 +#define mmSMI_FILTER_REGISTER_1_1_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_2_0 0x0008 +#define mmSMI_FILTER_REGISTER_2_0_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_2_1 0x0009 +#define mmSMI_FILTER_REGISTER_2_1_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_3_0 0x000a +#define mmSMI_FILTER_REGISTER_3_0_BASE_IDX 1 +#define mmSMI_FILTER_REGISTER_3_1 0x000b +#define mmSMI_FILTER_REGISTER_3_1_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_LOG_BASE_0 0x0024 +#define mmIOMMU_MMIO_GA_LOG_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_LOG_BASE_1 0x0025 +#define mmIOMMU_MMIO_GA_LOG_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 0x0026 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 0x0027 +#define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BASE_0 0x0028 +#define mmIOMMU_MMIO_PPR_B_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BASE_1 0x0029 +#define mmIOMMU_MMIO_PPR_B_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BASE_0 0x002a +#define mmIOMMU_MMIO_EVENT_B_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BASE_1 0x002b +#define mmIOMMU_MMIO_EVENT_B_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_1_BASE_0 0x002c +#define mmIOMMU_MMIO_DEVTBL_1_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_1_BASE_1 0x002d +#define mmIOMMU_MMIO_DEVTBL_1_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_2_BASE_0 0x002e +#define mmIOMMU_MMIO_DEVTBL_2_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_2_BASE_1 0x002f +#define mmIOMMU_MMIO_DEVTBL_2_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_0 0x0030 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_1 0x0031 +#define mmIOMMU_MMIO_DEVTBL_3_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_0 0x0032 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_1 0x0033 +#define mmIOMMU_MMIO_DEVTBL_4_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_0 0x0034 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_1 0x0035 +#define mmIOMMU_MMIO_DEVTBL_5_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_0 0x0036 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_1 0x0037 +#define mmIOMMU_MMIO_DEVTBL_6_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_0 0x0038 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_0_BASE_IDX 1 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_1 0x0039 +#define mmIOMMU_MMIO_DEVTBL_7_BASE_1_BASE_IDX 1 +#define mmIOMMU_MMIO_DSFX 0x003a +#define mmIOMMU_MMIO_DSFX_BASE_IDX 1 +#define mmIOMMU_MMIO_DSCX 0x003c +#define mmIOMMU_MMIO_DSCX_BASE_IDX 1 +#define mmIOMMU_MMIO_DSSX 0x003e +#define mmIOMMU_MMIO_DSSX_BASE_IDX 1 +#define mmIOMMU_MMIO_CAP_MISC 0x0040 +#define mmIOMMU_MMIO_CAP_MISC_BASE_IDX 1 +#define mmIOMMU_MMIO_CAP_MISC_1 0x0041 +#define mmIOMMU_MMIO_CAP_MISC_1_BASE_IDX 1 +#define mmIOMMU_MMIO_MSI_CAP 0x0042 +#define mmIOMMU_MMIO_MSI_CAP_BASE_IDX 1 +#define mmIOMMU_MMIO_MSI_ADDR_LO 0x0043 +#define mmIOMMU_MMIO_MSI_ADDR_LO_BASE_IDX 1 +#define mmIOMMU_MMIO_MSI_ADDR_HI 0x0044 +#define mmIOMMU_MMIO_MSI_ADDR_HI_BASE_IDX 1 +#define mmIOMMU_MMIO_MSI_DATA 0x0045 +#define mmIOMMU_MMIO_MSI_DATA_BASE_IDX 1 +#define mmIOMMU_MMIO_MSI_MAPPING_CAP 0x0046 +#define mmIOMMU_MMIO_MSI_MAPPING_CAP_BASE_IDX 1 +#define mmIOMMU_MMIO_CONTROL_W 0x0047 +#define mmIOMMU_MMIO_CONTROL_W_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_LO_0 0x006c +#define mmIOMMU_MARC_BASE_LO_0_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_HI_0 0x006d +#define mmIOMMU_MARC_BASE_HI_0_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_LO_0 0x006e +#define mmIOMMU_MARC_RELOC_LO_0_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_HI_0 0x006f +#define mmIOMMU_MARC_RELOC_HI_0_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_LO_0 0x0070 +#define mmIOMMU_MARC_LEN_LO_0_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_HI_0 0x0071 +#define mmIOMMU_MARC_LEN_HI_0_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_LO_1 0x0072 +#define mmIOMMU_MARC_BASE_LO_1_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_HI_1 0x0073 +#define mmIOMMU_MARC_BASE_HI_1_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_LO_1 0x0074 +#define mmIOMMU_MARC_RELOC_LO_1_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_HI_1 0x0075 +#define mmIOMMU_MARC_RELOC_HI_1_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_LO_1 0x0076 +#define mmIOMMU_MARC_LEN_LO_1_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_HI_1 0x0077 +#define mmIOMMU_MARC_LEN_HI_1_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_LO_2 0x0078 +#define mmIOMMU_MARC_BASE_LO_2_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_HI_2 0x0079 +#define mmIOMMU_MARC_BASE_HI_2_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_LO_2 0x007a +#define mmIOMMU_MARC_RELOC_LO_2_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_HI_2 0x007b +#define mmIOMMU_MARC_RELOC_HI_2_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_LO_2 0x007c +#define mmIOMMU_MARC_LEN_LO_2_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_HI_2 0x007d +#define mmIOMMU_MARC_LEN_HI_2_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_LO_3 0x007e +#define mmIOMMU_MARC_BASE_LO_3_BASE_IDX 1 +#define mmIOMMU_MARC_BASE_HI_3 0x007f +#define mmIOMMU_MARC_BASE_HI_3_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_LO_3 0x0080 +#define mmIOMMU_MARC_RELOC_LO_3_BASE_IDX 1 +#define mmIOMMU_MARC_RELOC_HI_3 0x0081 +#define mmIOMMU_MARC_RELOC_HI_3_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_LO_3 0x0082 +#define mmIOMMU_MARC_LEN_LO_3_BASE_IDX 1 +#define mmIOMMU_MARC_LEN_HI_3 0x0083 +#define mmIOMMU_MARC_LEN_HI_3_BASE_IDX 1 +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_0 0x07ec +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_1 0x07ed +#define mmIOMMU_MMIO_CMD_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0 0x07ee +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1 0x07ef +#define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0 0x07f0 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1 0x07f1 +#define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0 0x07f2 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1 0x07f3 +#define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_STATUS_0 0x07f4 +#define mmIOMMU_MMIO_STATUS_0_BASE_IDX 1 +#define mmIOMMU_MMIO_STATUS_1 0x07f5 +#define mmIOMMU_MMIO_STATUS_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_0 0x07f8 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_1 0x07f9 +#define mmIOMMU_MMIO_PPR_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0 0x07fa +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1 0x07fb +#define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_BUF_HDPTR_0 0x07fc +#define mmIOMMU_MMIO_GA_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_BUF_HDPTR_1 0x07fd +#define mmIOMMU_MMIO_GA_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_0 0x07fe +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_1 0x07ff +#define mmIOMMU_MMIO_GA_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0 0x0800 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1 0x0801 +#define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0 0x0802 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1 0x0803 +#define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0 0x0808 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1 0x0809 +#define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 0x080a +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_BASE_IDX 1 +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 0x080b +#define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_AUTORESP_0 0x080c +#define mmIOMMU_MMIO_PPR_AUTORESP_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0 0x080e +#define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0_BASE_IDX 1 +#define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 0x0810 +#define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_BASE_IDX 1 +#define mmIOMMU_MMIO_COUNTER_CONFIG_0 0x02e0 +#define mmIOMMU_MMIO_COUNTER_CONFIG_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_CONFIG_1 0x02e1 +#define mmIOMMU_MMIO_COUNTER_CONFIG_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 0x02e2 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 0x02e3 +#define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 0x02e4 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 0x02e5 +#define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 0x02e6 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 0x02e7 +#define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 0xf2e0 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 0xf2e1 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 0xf2e2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 0xf2e3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 0xf2e4 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 0xf2e5 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 0xf2e6 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 0xf2e7 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 0xf2e8 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 0xf2e9 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 0xf2ea +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 0xf2eb +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 0xf320 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 0xf321 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 0xf322 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 0xf323 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 0xf324 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 0xf325 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 0xf326 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 0xf327 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 0xf328 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 0xf329 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 0xf32a +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 0xf32b +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 0xf360 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 0xf361 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 0xf362 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 0xf363 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 0xf364 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 0xf365 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 0xf366 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 0xf367 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 0xf368 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 0xf369 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 0xf36a +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 0xf36b +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 0xf3a0 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 0xf3a1 +#define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 0xf3a2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 0xf3a3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 0xf3a4 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 0xf3a5 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 0xf3a6 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 0xf3a7 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 0xf3a8 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 0xf3a9 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 0xf3aa +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 0xf3ab +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_BASE_IDX 2 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 0x0000 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 0x0001 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 0x0002 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 0x0003 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 0x0004 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 0x0005 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 0x0006 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 0x0007 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 0x0008 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 0x0009 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 0x000a +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 0x000b +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 0x0040 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 0x0041 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 0x0042 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 0x0043 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 0x0044 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 0x0045 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 0x0046 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 0x0047 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 0x0048 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 0x0049 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 0x004a +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 0x004b +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 0x0080 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 0x0081 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 0x0082 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 0x0083 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 0x0084 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 0x0085 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 0x0086 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 0x0087 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 0x0088 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 0x0089 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 0x008a +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 0x008b +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 0x00c0 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 0x00c1 +#define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 0x00c2 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 0x00c3 +#define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 0x00c4 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 0x00c5 +#define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 0x00c6 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 0x00c7 +#define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 0x00c8 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 0x00c9 +#define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 0x00ca +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_BASE_IDX 3 +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 0x00cb +#define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define mmMM_INDEX 0x0000 +#define mmMM_INDEX_BASE_IDX 0 +#define mmMM_DATA 0x0001 +#define mmMM_DATA_BASE_IDX 0 +#define mmMM_INDEX_HI 0x0006 +#define mmMM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +// base address: 0x0 +#define mmSYSHUB_INDEX_OVLP 0x0008 +#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 +#define mmSYSHUB_DATA_OVLP 0x0009 +#define mmSYSHUB_DATA_OVLP_BASE_IDX 0 +#define mmPCIE_INDEX 0x000c +#define mmPCIE_INDEX_BASE_IDX 0 +#define mmPCIE_DATA 0x000d +#define mmPCIE_DATA_BASE_IDX 0 +#define mmPCIE_INDEX2 0x000e +#define mmPCIE_INDEX2_BASE_IDX 0 +#define mmPCIE_DATA2 0x000f +#define mmPCIE_DATA2_BASE_IDX 0 +#define mmSBIOS_SCRATCH_0 0x0034 +#define mmSBIOS_SCRATCH_0_BASE_IDX 1 +#define mmSBIOS_SCRATCH_1 0x0035 +#define mmSBIOS_SCRATCH_1_BASE_IDX 1 +#define mmSBIOS_SCRATCH_2 0x0036 +#define mmSBIOS_SCRATCH_2_BASE_IDX 1 +#define mmSBIOS_SCRATCH_3 0x0037 +#define mmSBIOS_SCRATCH_3_BASE_IDX 1 +#define mmBIOS_SCRATCH_0 0x0038 +#define mmBIOS_SCRATCH_0_BASE_IDX 1 +#define mmBIOS_SCRATCH_1 0x0039 +#define mmBIOS_SCRATCH_1_BASE_IDX 1 +#define mmBIOS_SCRATCH_2 0x003a +#define mmBIOS_SCRATCH_2_BASE_IDX 1 +#define mmBIOS_SCRATCH_3 0x003b +#define mmBIOS_SCRATCH_3_BASE_IDX 1 +#define mmBIOS_SCRATCH_4 0x003c +#define mmBIOS_SCRATCH_4_BASE_IDX 1 +#define mmBIOS_SCRATCH_5 0x003d +#define mmBIOS_SCRATCH_5_BASE_IDX 1 +#define mmBIOS_SCRATCH_6 0x003e +#define mmBIOS_SCRATCH_6_BASE_IDX 1 +#define mmBIOS_SCRATCH_7 0x003f +#define mmBIOS_SCRATCH_7_BASE_IDX 1 +#define mmBIOS_SCRATCH_8 0x0040 +#define mmBIOS_SCRATCH_8_BASE_IDX 1 +#define mmBIOS_SCRATCH_9 0x0041 +#define mmBIOS_SCRATCH_9_BASE_IDX 1 +#define mmBIOS_SCRATCH_10 0x0042 +#define mmBIOS_SCRATCH_10_BASE_IDX 1 +#define mmBIOS_SCRATCH_11 0x0043 +#define mmBIOS_SCRATCH_11_BASE_IDX 1 +#define mmBIOS_SCRATCH_12 0x0044 +#define mmBIOS_SCRATCH_12_BASE_IDX 1 +#define mmBIOS_SCRATCH_13 0x0045 +#define mmBIOS_SCRATCH_13_BASE_IDX 1 +#define mmBIOS_SCRATCH_14 0x0046 +#define mmBIOS_SCRATCH_14_BASE_IDX 1 +#define mmBIOS_SCRATCH_15 0x0047 +#define mmBIOS_SCRATCH_15_BASE_IDX 1 +#define mmBIF_RLC_INTR_CNTL 0x004c +#define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 +#define mmBIF_VCE_INTR_CNTL 0x004d +#define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 +#define mmBIF_UVD_INTR_CNTL 0x004e +#define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR0 0x006c +#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR1 0x006e +#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR2 0x0070 +#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR3 0x0072 +#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR4 0x0074 +#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR5 0x0076 +#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR6 0x0078 +#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR7 0x007a +#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_CNTL 0x007c +#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e +#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 + + +// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec +// base address: 0x0 +#define mmSYSHUB_INDEX 0x0008 +#define mmSYSHUB_INDEX_BASE_IDX 0 +#define mmSYSHUB_DATA 0x0009 +#define mmSYSHUB_DATA_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_STRAP0 0x000f +#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define mmEP_PCIE_SCRATCH 0x0023 +#define mmEP_PCIE_SCRATCH_BASE_IDX 2 +#define mmEP_PCIE_CNTL 0x0025 +#define mmEP_PCIE_CNTL_BASE_IDX 2 +#define mmEP_PCIE_INT_CNTL 0x0026 +#define mmEP_PCIE_INT_CNTL_BASE_IDX 2 +#define mmEP_PCIE_INT_STATUS 0x0027 +#define mmEP_PCIE_INT_STATUS_BASE_IDX 2 +#define mmEP_PCIE_RX_CNTL2 0x0028 +#define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 +#define mmEP_PCIE_BUS_CNTL 0x0029 +#define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 +#define mmEP_PCIE_CFG_CNTL 0x002a +#define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 +#define mmEP_PCIE_TX_LTR_CNTL 0x002c +#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_CAP 0x0032 +#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_CNTL 0x0033 +#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define mmEP_PCIE_PME_CONTROL 0x0035 +#define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 +#define mmEP_PCIEP_RESERVED 0x0036 +#define mmEP_PCIEP_RESERVED_BASE_IDX 2 +#define mmEP_PCIE_TX_CNTL 0x0038 +#define mmEP_PCIE_TX_CNTL_BASE_IDX 2 +#define mmEP_PCIE_TX_REQUESTER_ID 0x0039 +#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define mmEP_PCIE_ERR_CNTL 0x003a +#define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 +#define mmEP_PCIE_RX_CNTL 0x003b +#define mmEP_PCIE_RX_CNTL_BASE_IDX 2 +#define mmEP_PCIE_LC_SPEED_CNTL 0x003c +#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define mmDN_PCIE_RESERVED 0x0040 +#define mmDN_PCIE_RESERVED_BASE_IDX 2 +#define mmDN_PCIE_SCRATCH 0x0041 +#define mmDN_PCIE_SCRATCH_BASE_IDX 2 +#define mmDN_PCIE_CNTL 0x0043 +#define mmDN_PCIE_CNTL_BASE_IDX 2 +#define mmDN_PCIE_CONFIG_CNTL 0x0044 +#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define mmDN_PCIE_RX_CNTL2 0x0045 +#define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 +#define mmDN_PCIE_BUS_CNTL 0x0046 +#define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 +#define mmDN_PCIE_CFG_CNTL 0x0047 +#define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define mmPCIE_ERR_CNTL 0x004f +#define mmPCIE_ERR_CNTL_BASE_IDX 2 +#define mmPCIE_RX_CNTL 0x0050 +#define mmPCIE_RX_CNTL_BASE_IDX 2 +#define mmPCIE_LC_SPEED_CNTL 0x0051 +#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define mmPCIE_LC_CNTL2 0x0052 +#define mmPCIE_LC_CNTL2_BASE_IDX 2 +#define mmPCIEP_STRAP_MISC 0x0053 +#define mmPCIEP_STRAP_MISC_BASE_IDX 2 +#define mmLTR_MSG_INFO_FROM_EP 0x0054 +#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_ERR_LOG 0x0085 +#define mmRCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define mmRCC_ERR_INT_CNTL 0x0086 +#define mmRCC_ERR_INT_CNTL_BASE_IDX 2 +#define mmRCC_BACO_CNTL_MISC 0x0087 +#define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 +#define mmRCC_RESET_EN 0x0088 +#define mmRCC_RESET_EN_BASE_IDX 2 +#define mmRCC_VDM_SUPPORT 0x0089 +#define mmRCC_VDM_SUPPORT_BASE_IDX 2 +#define mmRCC_PEER_REG_RANGE0 0x00be +#define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 +#define mmRCC_PEER_REG_RANGE1 0x00bf +#define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 +#define mmRCC_BUS_CNTL 0x00c1 +#define mmRCC_BUS_CNTL_BASE_IDX 2 +#define mmRCC_CONFIG_CNTL 0x00c2 +#define mmRCC_CONFIG_CNTL_BASE_IDX 2 +#define mmRCC_CONFIG_F0_BASE 0x00c6 +#define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 +#define mmRCC_CONFIG_APER_SIZE 0x00c7 +#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 +#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define mmRCC_XDMA_LO 0x00c9 +#define mmRCC_XDMA_LO_BASE_IDX 2 +#define mmRCC_XDMA_HI 0x00ca +#define mmRCC_XDMA_HI_BASE_IDX 2 +#define mmRCC_FEATURES_CONTROL_MISC 0x00cb +#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define mmRCC_BUSNUM_CNTL1 0x00cc +#define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 +#define mmRCC_BUSNUM_LIST0 0x00cd +#define mmRCC_BUSNUM_LIST0_BASE_IDX 2 +#define mmRCC_BUSNUM_LIST1 0x00ce +#define mmRCC_BUSNUM_LIST1_BASE_IDX 2 +#define mmRCC_BUSNUM_CNTL2 0x00cf +#define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 +#define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define mmRCC_HOST_BUSNUM 0x00d1 +#define mmRCC_HOST_BUSNUM_BASE_IDX 2 +#define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 +#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 +#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 +#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 +#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 +#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 +#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 +#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 +#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_CMN_LINK_CNTL 0x00de +#define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 +#define mmRCC_EP_REQUESTERID_RESTORE 0x00df +#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define mmRCC_LTR_LSWITCH_CNTL 0x00e0 +#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define mmRCC_MH_ARB_CNTL 0x00e1 +#define mmRCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +// base address: 0x0 +#define mmBIF_MM_INDACCESS_CNTL 0x00e6 +#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define mmBUS_CNTL 0x00e7 +#define mmBUS_CNTL_BASE_IDX 2 +#define mmBIF_SCRATCH0 0x00e8 +#define mmBIF_SCRATCH0_BASE_IDX 2 +#define mmBIF_SCRATCH1 0x00e9 +#define mmBIF_SCRATCH1_BASE_IDX 2 +#define mmBX_RESET_EN 0x00ed +#define mmBX_RESET_EN_BASE_IDX 2 +#define mmMM_CFGREGS_CNTL 0x00ee +#define mmMM_CFGREGS_CNTL_BASE_IDX 2 +#define mmBX_RESET_CNTL 0x00f0 +#define mmBX_RESET_CNTL_BASE_IDX 2 +#define mmINTERRUPT_CNTL 0x00f1 +#define mmINTERRUPT_CNTL_BASE_IDX 2 +#define mmINTERRUPT_CNTL2 0x00f2 +#define mmINTERRUPT_CNTL2_BASE_IDX 2 +#define mmCLKREQB_PAD_CNTL 0x00f8 +#define mmCLKREQB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_FEATURES_CONTROL_MISC 0x00fb +#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define mmBIF_DOORBELL_CNTL 0x00fc +#define mmBIF_DOORBELL_CNTL_BASE_IDX 2 +#define mmBIF_DOORBELL_INT_CNTL 0x00fd +#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define mmBIF_FB_EN 0x00ff +#define mmBIF_FB_EN_BASE_IDX 2 +#define mmBIF_BUSY_DELAY_CNTR 0x0100 +#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 +#define mmBIF_MST_TRANS_PENDING_VF 0x0109 +#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define mmBIF_SLV_TRANS_PENDING_VF 0x010a +#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define mmBACO_CNTL 0x010b +#define mmBACO_CNTL_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIME0 0x010c +#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER1 0x010d +#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER2 0x010e +#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER3 0x010f +#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER4 0x0110 +#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define mmMEM_TYPE_CNTL 0x0111 +#define mmMEM_TYPE_CNTL_BASE_IDX 2 +#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113 +#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX0_LOWER 0x0114 +#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX0_UPPER 0x0115 +#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX1_LOWER 0x0116 +#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX1_UPPER 0x0117 +#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX2_LOWER 0x0118 +#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX2_UPPER 0x0119 +#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX3_LOWER 0x011a +#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX3_UPPER 0x011b +#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX4_LOWER 0x011c +#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX4_UPPER 0x011d +#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX5_LOWER 0x011e +#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_GFX5_UPPER 0x011f +#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV1_LOWER 0x0120 +#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV1_UPPER 0x0121 +#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV2_LOWER 0x0122 +#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV2_UPPER 0x0123 +#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV3_LOWER 0x0124 +#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV3_UPPER 0x0125 +#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV4_LOWER 0x0126 +#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2 +#define mmBIF_VDDGFX_RSV4_UPPER 0x0127 +#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2 +#define mmBIF_VDDGFX_FB_CMP 0x0128 +#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2 +#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129 +#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2 +#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a +#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2 +#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b +#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2 +#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c +#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2 +#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e +#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_RB_CNTL 0x012f +#define mmBIF_RB_CNTL_BASE_IDX 2 +#define mmBIF_RB_BASE 0x0130 +#define mmBIF_RB_BASE_BASE_IDX 2 +#define mmBIF_RB_RPTR 0x0131 +#define mmBIF_RB_RPTR_BASE_IDX 2 +#define mmBIF_RB_WPTR 0x0132 +#define mmBIF_RB_WPTR_BASE_IDX 2 +#define mmBIF_RB_WPTR_ADDR_HI 0x0133 +#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define mmBIF_RB_WPTR_ADDR_LO 0x0134 +#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define mmMAILBOX_INDEX 0x0135 +#define mmMAILBOX_INDEX_BASE_IDX 2 +#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 +#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 +#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_PERSTB_PAD_CNTL 0x0148 +#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_PX_EN_PAD_CNTL 0x0149 +#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define mmBIF_REFPADKIN_PAD_CNTL 0x014a +#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define mmBIF_CLKREQB_PAD_CNTL 0x014b +#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BME_STATUS 0x00eb +#define mmBIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmGPU_HDP_FLUSH_REQ 0x0106 +#define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmGPU_HDP_FLUSH_DONE 0x0107 +#define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_TRANS_PENDING 0x0108 +#define mmBIF_TRANS_PENDING_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmMAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmMAILBOX_CONTROL 0x013e +#define mmMAILBOX_CONTROL_BASE_IDX 2 +#define mmMAILBOX_INT_CNTL 0x013f +#define mmMAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_VMHV_MAILBOX 0x0140 +#define mmBIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define mmNGDC_SDP_PORT_CTRL 0x01c2 +#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 +#define mmSHUB_REGS_IF_CTL 0x01c3 +#define mmSHUB_REGS_IF_CTL_BASE_IDX 2 +#define mmNGDC_RESERVED_0 0x01cb +#define mmNGDC_RESERVED_0_BASE_IDX 2 +#define mmNGDC_RESERVED_1 0x01cc +#define mmNGDC_RESERVED_1_BASE_IDX 2 +#define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd +#define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 +#define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 +#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 +#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_IH_DOORBELL_RANGE 0x01d2 +#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 +#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 +#define mmATDMA_MISC_CNTL 0x01dd +#define mmATDMA_MISC_CNTL_BASE_IDX 2 +#define mmBIF_DOORBELL_FENCE_CNTL 0x01de +#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 +#define mmS2A_MISC_CNTL 0x01df +#define mmS2A_MISC_CNTL_BASE_IDX 2 +#define mmGDC_PG_MISC_CNTL 0x01f0 +#define mmGDC_PG_MISC_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 +// base address: 0x0 +#define mmGFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmGFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmGFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmGFXMSIX_VECT0_CONTROL 0x0403 +#define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmGFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmGFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmGFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmGFXMSIX_VECT1_CONTROL 0x0407 +#define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmGFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmGFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmGFXMSIX_VECT2_MSG_DATA 0x040a +#define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmGFXMSIX_VECT2_CONTROL 0x040b +#define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmGFXMSIX_PBA 0x0800 +#define mmGFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: syshub_mmreg_ind_syshubind +// base address: 0x0 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL 0x10018 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x1001c +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x10020 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10024 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10028 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x1002c +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x10030 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10034 +#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10038 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118 +#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c +#define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300 +#define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308 +#define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c +#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310 +#define ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET 0x10314 +#define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00 +#define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 +#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 +#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038 +#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c +#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040 +#define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108 +#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008 +#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008 +#define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008 +#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD 0x63108 +#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD 0x64108 +#define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD 0xc0108 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD 0xc1108 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD 0xc2108 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD 0xc3108 +#define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD 0xc4108 +#define ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD 0xd0008 +#define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD 0xe0108 +#define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD 0xe1108 +#define ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD 0xf0008 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h new file mode 100644 index 000000000000..88602479a1aa --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h @@ -0,0 +1,118945 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _nbio_7_0_SH_MASK_HEADER +#define _nbio_7_0_SH_MASK_HEADER + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +//NB_NBCFG0_NB_VENDOR_ID +#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//NB_NBCFG0_NB_DEVICE_ID +#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//NB_NBCFG0_NB_COMMAND +#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_NBCFG0_NB_STATUS +#define NB_NBCFG0_NB_STATUS__CAP_LIST__SHIFT 0x4 +#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define NB_NBCFG0_NB_STATUS__CAP_LIST_MASK 0x0010L +#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +//NB_NBCFG0_NB_REVISION_ID +#define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//NB_NBCFG0_NB_REGPROG_INF +#define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//NB_NBCFG0_NB_SUB_CLASS +#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//NB_NBCFG0_NB_BASE_CODE +#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//NB_NBCFG0_NB_CACHE_LINE +#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//NB_NBCFG0_NB_LATENCY +#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL +//NB_NBCFG0_NB_HEADER +#define NB_NBCFG0_NB_HEADER__HEADER_TYPE__SHIFT 0x0 +#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG0_NB_HEADER__HEADER_TYPE_MASK 0x7FL +#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE_MASK 0x80L +//NB_NBCFG0_NB_ADAPTER_ID +#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG0_NB_CAPABILITIES_PTR +#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//NB_NBCFG0_NB_HEADER_W +#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L +//NB_NBCFG0_NB_PCI_CTRL +#define NB_NBCFG0_NB_PCI_CTRL__PMEDis__SHIFT 0x4 +#define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT 0x5 +#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 +#define NB_NBCFG0_NB_PCI_CTRL__HPDis__SHIFT 0x1a +#define NB_NBCFG0_NB_PCI_CTRL__PMEDis_MASK 0x00000010L +#define NB_NBCFG0_NB_PCI_CTRL__SErrDis_MASK 0x00000020L +#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L +#define NB_NBCFG0_NB_PCI_CTRL__HPDis_MASK 0x04000000L +//NB_NBCFG0_NB_ADAPTER_ID_W +#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_0 +#define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_0 +#define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL +//NB_NBCFG0_NBCFG_SCRATCH_0 +#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL +//NB_NBCFG0_NBCFG_SCRATCH_1 +#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL +//NB_NBCFG0_NBCFG_SCRATCH_2 +#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL +//NB_NBCFG0_NBCFG_SCRATCH_3 +#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL +//NB_NBCFG0_NBCFG_SCRATCH_4 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_PCI_ARB +#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define NB_NBCFG0_NB_PCI_ARB__PMEMode__SHIFT 0x8 +#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 +#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa +#define NB_NBCFG0_NB_PCI_ARB__PMETarget__SHIFT 0x10 +#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +#define NB_NBCFG0_NB_PCI_ARB__PMEMode_MASK 0x00000100L +#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L +#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L +#define NB_NBCFG0_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L +//NB_NBCFG0_NB_DRAM_SLOT1_BASE +#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 +#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L +//NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 +#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 +#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L +#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_1 +#define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_1 +#define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_INDEX_DATA_MUTEX0 +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L +//NB_NBCFG0_NB_INDEX_DATA_MUTEX1 +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL +#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_2 +#define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_2 +#define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_3 +#define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_3 +#define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_4 +#define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_4 +#define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL +//NB_NBCFG0_NB_SMN_INDEX_5 +#define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_5 +#define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_PERF_CNT_CTRL +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L +#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L +//NB_NBCFG0_NB_SMN_INDEX_6 +#define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL +//NB_NBCFG0_NB_SMN_DATA_6 +#define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 +#define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +//IOMMU_L2_0_IOMMU_VENDOR_ID +#define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//IOMMU_L2_0_IOMMU_DEVICE_ID +#define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//IOMMU_L2_0_IOMMU_COMMAND +#define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved1__SHIFT 0x3 +#define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved0__SHIFT 0x7 +#define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved2__SHIFT 0x9 +#define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved__SHIFT 0xb +#define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved1_MASK 0x0038L +#define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved0_MASK 0x0080L +#define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN_MASK 0x0100L +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved2_MASK 0x0200L +#define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L +#define IOMMU_L2_0_IOMMU_COMMAND__Reserved_MASK 0xF800L +//IOMMU_L2_0_IOMMU_STATUS +#define IOMMU_L2_0_IOMMU_STATUS__Reserved__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_STATUS__INT_Status__SHIFT 0x3 +#define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 +#define IOMMU_L2_0_IOMMU_STATUS__Reserved1__SHIFT 0x5 +#define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_STATUS__Reserved2__SHIFT 0x9 +#define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define IOMMU_L2_0_IOMMU_STATUS__Reserved_MASK 0x0007L +#define IOMMU_L2_0_IOMMU_STATUS__INT_Status_MASK 0x0008L +#define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST_MASK 0x0010L +#define IOMMU_L2_0_IOMMU_STATUS__Reserved1_MASK 0x00E0L +#define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L +#define IOMMU_L2_0_IOMMU_STATUS__Reserved2_MASK 0x0600L +#define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//IOMMU_L2_0_IOMMU_REVISION_ID +#define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//IOMMU_L2_0_IOMMU_REGPROG_INF +#define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//IOMMU_L2_0_IOMMU_SUB_CLASS +#define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//IOMMU_L2_0_IOMMU_BASE_CODE +#define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//IOMMU_L2_0_IOMMU_CACHE_LINE +#define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//IOMMU_L2_0_IOMMU_LATENCY +#define IOMMU_L2_0_IOMMU_LATENCY__LATENCY__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_LATENCY__LATENCY_MASK 0xFFL +//IOMMU_L2_0_IOMMU_HEADER +#define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL +//IOMMU_L2_0_IOMMU_BIST +#define IOMMU_L2_0_IOMMU_BIST__BIST_COMP__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_BIST__BIST_STRT__SHIFT 0x6 +#define IOMMU_L2_0_IOMMU_BIST__BIST_CAP__SHIFT 0x7 +#define IOMMU_L2_0_IOMMU_BIST__BIST_COMP_MASK 0x0FL +#define IOMMU_L2_0_IOMMU_BIST__BIST_STRT_MASK 0x40L +#define IOMMU_L2_0_IOMMU_BIST__BIST_CAP_MASK 0x80L +//IOMMU_L2_0_IOMMU_ADAPTER_ID +#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//IOMMU_L2_0_IOMMU_CAPABILITIES_PTR +#define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//IOMMU_L2_0_IOMMU_INTERRUPT_LINE +#define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//IOMMU_L2_0_IOMMU_INTERRUPT_PIN +#define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IOMMU_L2_0_IOMMU_CAP_HEADER +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c +#define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L +#define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L +//IOMMU_L2_0_IOMMU_CAP_BASE_LO +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL +#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L +//IOMMU_L2_0_IOMMU_CAP_BASE_HI +#define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_0_IOMMU_CAP_RANGE +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL +#define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L +#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L +//IOMMU_L2_0_IOMMU_CAP_MISC +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +#define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L +#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L +//IOMMU_L2_0_IOMMU_CAP_MISC_1 +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L +#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L +//IOMMU_L2_0_IOMMU_MSI_CAP +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 +#define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L +#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L +#define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L +//IOMMU_L2_0_IOMMU_MSI_ADDR_LO +#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 +#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L +#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL +//IOMMU_L2_0_IOMMU_MSI_ADDR_HI +#define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_0_IOMMU_MSI_DATA +#define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL +#define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L +//IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L +#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L +//IOMMU_L2_0_IOMMU_ADAPTER_ID_W +#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL +#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L +//IOMMU_L2_0_IOMMU_CONTROL_W +#define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 +#define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 +#define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa +#define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd +#define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L +#define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L +#define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L +#define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L +#define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L +#define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L +//IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L +//IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L +#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L +//IOMMU_L2_0_IOMMU_RANGE_W +#define IOMMU_L2_0_IOMMU_RANGE_W__Reserved__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 +#define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 +#define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 +#define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL +#define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L +#define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L +#define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L +#define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L +//IOMMU_L2_0_IOMMU_DSFX_CONTROL +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2_0_IOMMU_DSSX_DUMMY_0 +#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL +#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_0_IOMMU_DSCX_DUMMY_0 +#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 +#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL +#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_0_L2B_POISON_DVM_CNTRL +#define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 +#define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L +//IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L +#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L +//IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control +#define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 +#define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L +//IOMMU_L2_0_SMMU_MMIO_IDR0_W +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L +//IOMMU_L2_0_SMMU_MMIO_IDR1_W +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L +#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L +//IOMMU_L2_0_SMMU_MMIO_IDR2_W +#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa +#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL +#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L +//IOMMU_L2_0_SMMU_MMIO_IDR3_W +#define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 +#define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L +//IOMMU_L2_0_SMMU_MMIO_IDR5_W +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L +#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L +//IOMMU_L2_0_SMMU_MMIO_IIDR_W +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L +#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L +//IOMMU_L2_0_SMMU_AIDR_W +#define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 +#define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 +#define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL +#define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_ROOT_CNTL +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC0_ROOT_CAP +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC0_ROOT_STATUS +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MAP_CAP +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +//BIF_CFG_DEV1_RC0_VENDOR_ID +#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC0_DEVICE_ID +#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC0_COMMAND +#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_RC0_STATUS +#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_REVISION_ID +#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_RC0_PROG_INTERFACE +#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_RC0_SUB_CLASS +#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC0_BASE_CLASS +#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC0_CACHE_LINE +#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_RC0_LATENCY +#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_RC0_HEADER +#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_RC0_BIST +#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV1_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC0_CAP_PTR +#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV1_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_PMI_CAP +#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_PCIE_CAP +#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_RC0_DEVICE_CAP +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_RC0_DEVICE_CNTL +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV1_RC0_DEVICE_STATUS +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_RC0_LINK_CAP +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_LINK_CNTL +#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_RC0_LINK_STATUS +#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_RC0_SLOT_CAP +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV1_RC0_SLOT_CNTL +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV1_RC0_SLOT_STATUS +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV1_RC0_ROOT_CNTL +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV1_RC0_ROOT_CAP +#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV1_RC0_ROOT_STATUS +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV1_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC0_LINK_CAP2 +#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_RC0_LINK_CNTL2 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_RC0_LINK_STATUS2 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_RC0_SLOT_CAP2 +#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_SSID_CAP +#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_MSI_MAP_CAP +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +//NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_0_STATUS_COMMAND +#define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_0_CLASS_CODE_REVID +#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY0_0_HEADER_TYPE +#define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY0_0_HEADER_TYPE_W +#define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +//NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_0_STATUS_COMMAND +#define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_0_CLASS_CODE_REVID +#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY1_0_HEADER_TYPE +#define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY1_0_HEADER_TYPE_W +#define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//VENDOR_ID +#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//DEVICE_ID +#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//COMMAND +#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define COMMAND__AD_STEPPING__SHIFT 0x7 +#define COMMAND__SERR_EN__SHIFT 0x8 +#define COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define COMMAND__INT_DIS__SHIFT 0xa +#define COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define COMMAND__AD_STEPPING_MASK 0x0080L +#define COMMAND__SERR_EN_MASK 0x0100L +#define COMMAND__FAST_B2B_EN_MASK 0x0200L +#define COMMAND__INT_DIS_MASK 0x0400L +//STATUS +#define STATUS__INT_STATUS__SHIFT 0x3 +#define STATUS__CAP_LIST__SHIFT 0x4 +#define STATUS__PCI_66_EN__SHIFT 0x5 +#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define STATUS__INT_STATUS_MASK 0x0008L +#define STATUS__CAP_LIST_MASK 0x0010L +#define STATUS__PCI_66_EN_MASK 0x0020L +#define STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define STATUS__DEVSEL_TIMING_MASK 0x0600L +#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//REVISION_ID +#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//PROG_INTERFACE +#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//SUB_CLASS +#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BASE_CLASS +#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BASE_CLASS__BASE_CLASS_MASK 0xFFL +//CACHE_LINE +#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//LATENCY +#define LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define LATENCY__LATENCY_TIMER_MASK 0xFFL +//HEADER +#define HEADER__HEADER_TYPE__SHIFT 0x0 +#define HEADER__DEVICE_TYPE__SHIFT 0x7 +#define HEADER__HEADER_TYPE_MASK 0x7FL +#define HEADER__DEVICE_TYPE_MASK 0x80L +//BIST +#define BIST__BIST_COMP__SHIFT 0x0 +#define BIST__BIST_STRT__SHIFT 0x6 +#define BIST__BIST_CAP__SHIFT 0x7 +#define BIST__BIST_COMP_MASK 0x0FL +#define BIST__BIST_STRT_MASK 0x40L +#define BIST__BIST_CAP_MASK 0x80L +//BASE_ADDR_1 +#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BASE_ADDR_2 +#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BASE_ADDR_3 +#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BASE_ADDR_4 +#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BASE_ADDR_5 +#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BASE_ADDR_6 +#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//ADAPTER_ID +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//ROM_BASE_ADDR +#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CAP_PTR +#define CAP_PTR__CAP_PTR__SHIFT 0x0 +#define CAP_PTR__CAP_PTR_MASK 0x000000FFL +//INTERRUPT_LINE +#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//INTERRUPT_PIN +#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//MIN_GRANT +#define MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define MIN_GRANT__MIN_GNT_MASK 0xFFL +//MAX_LATENCY +#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define MAX_LATENCY__MAX_LAT_MASK 0xFFL +//VENDOR_CAP_LIST +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//ADAPTER_ID_W +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//PMI_CAP_LIST +#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PMI_CAP +#define PMI_CAP__VERSION__SHIFT 0x0 +#define PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PMI_CAP__VERSION_MASK 0x0007L +#define PMI_CAP__PME_CLOCK_MASK 0x0008L +#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define PMI_CAP__PME_SUPPORT_MASK 0xF800L +//PMI_STATUS_CNTL +#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//PCIE_CAP_LIST +#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//PCIE_CAP +#define PCIE_CAP__VERSION__SHIFT 0x0 +#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define PCIE_CAP__VERSION_MASK 0x000FL +#define PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//DEVICE_CAP +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//DEVICE_CNTL +#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//DEVICE_STATUS +#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//LINK_CAP +#define LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//LINK_CNTL +#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define LINK_CNTL__LINK_DIS_MASK 0x0010L +#define LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//LINK_STATUS +#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//DEVICE_CAP2 +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//DEVICE_CNTL2 +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//DEVICE_STATUS2 +#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//LINK_CAP2 +#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define LINK_CAP2__RESERVED__SHIFT 0x9 +#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//LINK_CNTL2 +#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//LINK_STATUS2 +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//SLOT_CAP2 +#define SLOT_CAP2__RESERVED__SHIFT 0x0 +#define SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//SLOT_CNTL2 +#define SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//SLOT_STATUS2 +#define SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//MSI_CAP_LIST +#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//MSI_MSG_CNTL +#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//MSI_MSG_ADDR_LO +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//MSI_MSG_ADDR_HI +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//MSI_MSG_DATA +#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//MSI_MASK +#define MSI_MASK__MSI_MASK__SHIFT 0x0 +#define MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//MSI_MSG_DATA_64 +#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//MSI_MASK_64 +#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//MSI_PENDING +#define MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//MSI_PENDING_64 +#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//MSIX_CAP_LIST +#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//MSIX_MSG_CNTL +#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//MSIX_TABLE +#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//MSIX_PBA +#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC1 +#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC2 +#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//PCIE_VC_ENH_CAP_LIST +#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PORT_VC_CAP_REG1 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//PCIE_PORT_VC_CAP_REG2 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PCIE_PORT_VC_CNTL +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//PCIE_PORT_VC_STATUS +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//PCIE_VC0_RESOURCE_CAP +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PCIE_VC0_RESOURCE_CNTL +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PCIE_VC0_RESOURCE_STATUS +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PCIE_VC1_RESOURCE_CAP +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//PCIE_VC1_RESOURCE_CNTL +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//PCIE_VC1_RESOURCE_STATUS +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DEV_SERIAL_NUM_DW1 +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//PCIE_DEV_SERIAL_NUM_DW2 +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_UNCORR_ERR_STATUS +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//PCIE_UNCORR_ERR_MASK +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//PCIE_UNCORR_ERR_SEVERITY +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//PCIE_CORR_ERR_STATUS +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//PCIE_CORR_ERR_MASK +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//PCIE_ADV_ERR_CAP_CNTL +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//PCIE_HDR_LOG0 +#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_HDR_LOG1 +#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_HDR_LOG2 +#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_HDR_LOG3 +#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_TLP_PREFIX_LOG0 +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//PCIE_TLP_PREFIX_LOG1 +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//PCIE_TLP_PREFIX_LOG2 +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//PCIE_TLP_PREFIX_LOG3 +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//PCIE_BAR_ENH_CAP_LIST +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_BAR1_CAP +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR1_CNTL +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_BAR2_CAP +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR2_CNTL +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_BAR3_CAP +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR3_CNTL +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_BAR4_CAP +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR4_CNTL +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_BAR5_CAP +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR5_CNTL +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_BAR6_CAP +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//PCIE_BAR6_CNTL +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//PCIE_PWR_BUDGET_ENH_CAP_LIST +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PWR_BUDGET_DATA_SELECT +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//PCIE_PWR_BUDGET_DATA +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//PCIE_PWR_BUDGET_CAP +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//PCIE_DPA_ENH_CAP_LIST +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DPA_CAP +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//PCIE_DPA_LATENCY_INDICATOR +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//PCIE_DPA_STATUS +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//PCIE_DPA_CNTL +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_SECONDARY_ENH_CAP_LIST +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_LINK_CNTL3 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//PCIE_LANE_ERROR_STATUS +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//PCIE_LANE_0_EQUALIZATION_CNTL +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_1_EQUALIZATION_CNTL +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_2_EQUALIZATION_CNTL +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_3_EQUALIZATION_CNTL +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_4_EQUALIZATION_CNTL +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_5_EQUALIZATION_CNTL +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_6_EQUALIZATION_CNTL +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_7_EQUALIZATION_CNTL +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_8_EQUALIZATION_CNTL +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_9_EQUALIZATION_CNTL +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_10_EQUALIZATION_CNTL +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_11_EQUALIZATION_CNTL +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_12_EQUALIZATION_CNTL +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_13_EQUALIZATION_CNTL +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_14_EQUALIZATION_CNTL +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_LANE_15_EQUALIZATION_CNTL +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//PCIE_ACS_ENH_CAP_LIST +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_ACS_CAP +#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//PCIE_ACS_CNTL +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//PCIE_ATS_ENH_CAP_LIST +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_ATS_CAP +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//PCIE_ATS_CNTL +#define PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define PCIE_ATS_CNTL__STU_MASK 0x001FL +#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//PCIE_PAGE_REQ_ENH_CAP_LIST +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PAGE_REQ_CNTL +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//PCIE_PAGE_REQ_STATUS +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//PCIE_PASID_ENH_CAP_LIST +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PASID_CAP +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//PCIE_PASID_CNTL +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//PCIE_TPH_REQR_ENH_CAP_LIST +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_TPH_REQR_CAP +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//PCIE_TPH_REQR_CNTL +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//PCIE_MC_ENH_CAP_LIST +#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_MC_CAP +#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//PCIE_MC_CNTL +#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//PCIE_MC_ADDR0 +#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//PCIE_MC_ADDR1 +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//PCIE_MC_RCV0 +#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//PCIE_MC_RCV1 +#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//PCIE_MC_BLOCK_ALL0 +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//PCIE_MC_BLOCK_ALL1 +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//PCIE_MC_BLOCK_UNTRANSLATED_0 +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//PCIE_MC_BLOCK_UNTRANSLATED_1 +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//PCIE_LTR_ENH_CAP_LIST +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_LTR_CAP +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//PCIE_ARI_ENH_CAP_LIST +#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_ARI_CAP +#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//PCIE_ARI_CNTL +#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PCIE_SRIOV_ENH_CAP_LIST +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_SRIOV_CAP +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//PCIE_SRIOV_CONTROL +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//PCIE_SRIOV_STATUS +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//PCIE_SRIOV_INITIAL_VFS +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_TOTAL_VFS +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_NUM_VFS +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//PCIE_SRIOV_FUNC_DEP_LINK +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//PCIE_SRIOV_FIRST_VF_OFFSET +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//PCIE_SRIOV_VF_STRIDE +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//PCIE_SRIOV_VF_DEVICE_ID +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_1 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_2 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_3 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_4 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_5 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_COMMAND +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_STATUS +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_LATENCY +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_HEADER +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BIST +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_COMMAND +#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_0_STATUS +#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_REVISION_ID +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_LATENCY +#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_HEADER +#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_0_BIST +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_CAP_PTR +#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PMI_CAP +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_SBRN +#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_FLADJ +#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_0_LINK_CAP +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF2_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MASK +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_COMMAND +#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_0_STATUS +#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_REVISION_ID +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_LATENCY +#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_HEADER +#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_0_BIST +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_CAP_PTR +#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PMI_CAP +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_SBRN +#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_FLADJ +#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_0_LINK_CAP +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF3_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MASK +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +//BIF_CFG_DEV0_EPF4_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_0_COMMAND +#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF4_0_STATUS +#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_0_REVISION_ID +#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_LATENCY +#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_HEADER +#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF4_0_BIST +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_CAP_PTR +#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_PMI_CAP +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_0_SBRN +#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_FLADJ +#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_0_LINK_CAP +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF4_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF4_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF4_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_MASK +#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +//BIF_CFG_DEV0_EPF5_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_0_COMMAND +#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF5_0_STATUS +#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_0_REVISION_ID +#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_LATENCY +#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_HEADER +#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF5_0_BIST +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_CAP_PTR +#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_PMI_CAP +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_0_SBRN +#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_FLADJ +#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_0_LINK_CAP +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF5_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF5_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF5_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_MASK +#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +//BIF_CFG_DEV0_EPF6_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_0_COMMAND +#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF6_0_STATUS +#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_0_REVISION_ID +#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_LATENCY +#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_HEADER +#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF6_0_BIST +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_CAP_PTR +#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_PMI_CAP +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_0_SBRN +#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_FLADJ +#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_0_LINK_CAP +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF6_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF6_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF6_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_MASK +#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +//BIF_CFG_DEV0_EPF7_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_0_COMMAND +#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF7_0_STATUS +#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_0_REVISION_ID +#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_LATENCY +#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_HEADER +#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF7_0_BIST +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_CAP_PTR +#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_PMI_CAP +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_0_SBRN +#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_FLADJ +#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_0_LINK_CAP +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF7_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF7_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF7_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_0_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_MASK +#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_0_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_0_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +//BIF_CFG_DEV1_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_0_COMMAND +#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF0_0_STATUS +#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_REVISION_ID +#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_LATENCY +#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_HEADER +#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF0_0_BIST +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_CAP_PTR +#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_PMI_CAP +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_0_LINK_CAP +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_0_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_MASK +#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_0_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +//BIF_CFG_DEV1_EPF1_0_VENDOR_ID +#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_0_DEVICE_ID +#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_0_COMMAND +#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF1_0_STATUS +#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_0_REVISION_ID +#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_SUB_CLASS +#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_BASE_CLASS +#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_CACHE_LINE +#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_LATENCY +#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_HEADER +#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF1_0_BIST +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_CAP_PTR +#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_MIN_GRANT +#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_MAX_LATENCY +#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_PMI_CAP +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_0_SBRN +#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_FLADJ +#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_PCIE_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_0_LINK_CAP +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_0_LINK_CNTL +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF1_0_LINK_STATUS +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_0_LINK_CAP2 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF1_0_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF1_0_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_0_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_MASK +#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_PENDING +#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_0_MSIX_TABLE +#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_0_MSIX_PBA +#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_0_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_0_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +//BIF_CFG_DEV1_EPF2_0_VENDOR_ID +#define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_0_DEVICE_ID +#define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_0_COMMAND +#define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF2_0_STATUS +#define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_0_REVISION_ID +#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_SUB_CLASS +#define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_BASE_CLASS +#define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_CACHE_LINE +#define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_LATENCY +#define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_HEADER +#define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF2_0_BIST +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_ADAPTER_ID +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_CAP_PTR +#define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_MIN_GRANT +#define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_MAX_LATENCY +#define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_PMI_CAP +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_0_SBRN +#define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_FLADJ +#define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_PCIE_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF2_0_DEVICE_CAP +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_0_LINK_CAP +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_0_LINK_CNTL +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF2_0_LINK_STATUS +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_0_LINK_CAP2 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF2_0_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF2_0_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_0_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_MASK +#define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_PENDING +#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_0_MSIX_TABLE +#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_0_MSIX_PBA +#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_0_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_0_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +//BIFPLR0_0_VENDOR_ID +#define BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR0_0_DEVICE_ID +#define BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR0_0_COMMAND +#define BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR0_0_STATUS +#define BIFPLR0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_0_REVISION_ID +#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR0_0_PROG_INTERFACE +#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR0_0_SUB_CLASS +#define BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR0_0_BASE_CLASS +#define BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR0_0_CACHE_LINE +#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR0_0_LATENCY +#define BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR0_0_HEADER +#define BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR0_0_BIST +#define BIFPLR0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR0_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR0_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR0_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR0_0_IO_BASE_LIMIT +#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR0_0_SECONDARY_STATUS +#define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_0_MEM_BASE_LIMIT +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_0_PREF_BASE_LIMIT +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_0_PREF_BASE_UPPER +#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_0_PREF_LIMIT_UPPER +#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_0_IO_BASE_LIMIT_HI +#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR0_0_CAP_PTR +#define BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR0_0_INTERRUPT_LINE +#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR0_0_INTERRUPT_PIN +#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR0_0_IRQ_BRIDGE_CNTL +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR0_0_EXT_BRIDGE_CNTL +#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR0_0_PMI_CAP_LIST +#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_0_PMI_CAP +#define BIFPLR0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR0_0_PMI_STATUS_CNTL +#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR0_0_PCIE_CAP_LIST +#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_0_PCIE_CAP +#define BIFPLR0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR0_0_DEVICE_CAP +#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR0_0_DEVICE_CNTL +#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR0_0_DEVICE_STATUS +#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR0_0_LINK_CAP +#define BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR0_0_LINK_CNTL +#define BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR0_0_LINK_STATUS +#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR0_0_SLOT_CAP +#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR0_0_SLOT_CNTL +#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR0_0_SLOT_STATUS +#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR0_0_ROOT_CNTL +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR0_0_ROOT_CAP +#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR0_0_ROOT_STATUS +#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR0_0_DEVICE_CAP2 +#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR0_0_DEVICE_CNTL2 +#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR0_0_DEVICE_STATUS2 +#define BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_0_LINK_CAP2 +#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR0_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR0_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR0_0_LINK_CNTL2 +#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR0_0_LINK_STATUS2 +#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR0_0_SLOT_CAP2 +#define BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR0_0_SLOT_CNTL2 +#define BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR0_0_SLOT_STATUS2 +#define BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_0_MSI_CAP_LIST +#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_0_MSI_MSG_CNTL +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR0_0_MSI_MSG_ADDR_LO +#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR0_0_MSI_MSG_ADDR_HI +#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_0_MSI_MSG_DATA +#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR0_0_MSI_MSG_DATA_64 +#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR0_0_SSID_CAP_LIST +#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_0_SSID_CAP +#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR0_0_MSI_MAP_CAP_LIST +#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_0_MSI_MAP_CAP +#define BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR0_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR0_0_MSI_MAP_ADDR_LO +#define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR0_0_MSI_MAP_ADDR_HI +#define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR0_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_0_PCIE_PORT_VC_CNTL +#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR0_0_PCIE_PORT_VC_STATUS +#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR0_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR0_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR0_0_PCIE_CORR_ERR_STATUS +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR0_0_PCIE_CORR_ERR_MASK +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR0_0_PCIE_HDR_LOG0 +#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_HDR_LOG1 +#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_HDR_LOG2 +#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_HDR_LOG3 +#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_ROOT_ERR_CMD +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR0_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR0_0_PCIE_ERR_SRC_ID +#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR0_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_LINK_CNTL3 +#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_ACS_CAP +#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR0_0_PCIE_ACS_CNTL +#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR0_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_MC_CAP +#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR0_0_PCIE_MC_CNTL +#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR0_0_PCIE_MC_ADDR0 +#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR0_0_PCIE_MC_ADDR1 +#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_RCV0 +#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_RCV1 +#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR0_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_DPC_CAP_LIST +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR0_0_PCIE_DPC_CNTL +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR0_0_PCIE_DPC_STATUS +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR0_0_PCIE_RP_PIO_STATUS +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR0_0_PCIE_RP_PIO_MASK +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR0_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR0_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR0_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_0_PCIE_ESM_CAP_LIST +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_ESM_HEADER_1 +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR0_0_PCIE_ESM_HEADER_2 +#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR0_0_PCIE_ESM_STATUS +#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR0_0_PCIE_ESM_CTRL +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR0_0_PCIE_ESM_CAP_1 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR0_0_PCIE_ESM_CAP_2 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR0_0_PCIE_ESM_CAP_3 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR0_0_PCIE_ESM_CAP_4 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR0_0_PCIE_ESM_CAP_5 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR0_0_PCIE_ESM_CAP_6 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR0_0_PCIE_ESM_CAP_7 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +//BIFPLR1_0_VENDOR_ID +#define BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR1_0_DEVICE_ID +#define BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR1_0_COMMAND +#define BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR1_0_STATUS +#define BIFPLR1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_0_REVISION_ID +#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR1_0_PROG_INTERFACE +#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR1_0_SUB_CLASS +#define BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR1_0_BASE_CLASS +#define BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR1_0_CACHE_LINE +#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR1_0_LATENCY +#define BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR1_0_HEADER +#define BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR1_0_BIST +#define BIFPLR1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR1_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR1_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR1_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR1_0_IO_BASE_LIMIT +#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR1_0_SECONDARY_STATUS +#define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_0_MEM_BASE_LIMIT +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_0_PREF_BASE_LIMIT +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_0_PREF_BASE_UPPER +#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_0_PREF_LIMIT_UPPER +#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_0_IO_BASE_LIMIT_HI +#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR1_0_CAP_PTR +#define BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR1_0_INTERRUPT_LINE +#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR1_0_INTERRUPT_PIN +#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR1_0_IRQ_BRIDGE_CNTL +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR1_0_EXT_BRIDGE_CNTL +#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR1_0_PMI_CAP_LIST +#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_0_PMI_CAP +#define BIFPLR1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR1_0_PMI_STATUS_CNTL +#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR1_0_PCIE_CAP_LIST +#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_0_PCIE_CAP +#define BIFPLR1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR1_0_DEVICE_CAP +#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR1_0_DEVICE_CNTL +#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR1_0_DEVICE_STATUS +#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR1_0_LINK_CAP +#define BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR1_0_LINK_CNTL +#define BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR1_0_LINK_STATUS +#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR1_0_SLOT_CAP +#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR1_0_SLOT_CNTL +#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR1_0_SLOT_STATUS +#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR1_0_ROOT_CNTL +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR1_0_ROOT_CAP +#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR1_0_ROOT_STATUS +#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR1_0_DEVICE_CAP2 +#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR1_0_DEVICE_CNTL2 +#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR1_0_DEVICE_STATUS2 +#define BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_0_LINK_CAP2 +#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR1_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR1_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR1_0_LINK_CNTL2 +#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR1_0_LINK_STATUS2 +#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR1_0_SLOT_CAP2 +#define BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR1_0_SLOT_CNTL2 +#define BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR1_0_SLOT_STATUS2 +#define BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_0_MSI_CAP_LIST +#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_0_MSI_MSG_CNTL +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR1_0_MSI_MSG_ADDR_LO +#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR1_0_MSI_MSG_ADDR_HI +#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_0_MSI_MSG_DATA +#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR1_0_MSI_MSG_DATA_64 +#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR1_0_SSID_CAP_LIST +#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_0_SSID_CAP +#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR1_0_MSI_MAP_CAP_LIST +#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_0_MSI_MAP_CAP +#define BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR1_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR1_0_MSI_MAP_ADDR_LO +#define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR1_0_MSI_MAP_ADDR_HI +#define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR1_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_0_PCIE_PORT_VC_CNTL +#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR1_0_PCIE_PORT_VC_STATUS +#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR1_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR1_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR1_0_PCIE_CORR_ERR_STATUS +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR1_0_PCIE_CORR_ERR_MASK +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR1_0_PCIE_HDR_LOG0 +#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_HDR_LOG1 +#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_HDR_LOG2 +#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_HDR_LOG3 +#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_ROOT_ERR_CMD +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR1_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR1_0_PCIE_ERR_SRC_ID +#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR1_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_LINK_CNTL3 +#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_ACS_CAP +#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR1_0_PCIE_ACS_CNTL +#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR1_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_MC_CAP +#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR1_0_PCIE_MC_CNTL +#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR1_0_PCIE_MC_ADDR0 +#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR1_0_PCIE_MC_ADDR1 +#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_RCV0 +#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_RCV1 +#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR1_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_DPC_CAP_LIST +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR1_0_PCIE_DPC_CNTL +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR1_0_PCIE_DPC_STATUS +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR1_0_PCIE_RP_PIO_STATUS +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR1_0_PCIE_RP_PIO_MASK +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR1_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR1_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR1_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_0_PCIE_ESM_CAP_LIST +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_ESM_HEADER_1 +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR1_0_PCIE_ESM_HEADER_2 +#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR1_0_PCIE_ESM_STATUS +#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR1_0_PCIE_ESM_CTRL +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR1_0_PCIE_ESM_CAP_1 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR1_0_PCIE_ESM_CAP_2 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR1_0_PCIE_ESM_CAP_3 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR1_0_PCIE_ESM_CAP_4 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR1_0_PCIE_ESM_CAP_5 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR1_0_PCIE_ESM_CAP_6 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR1_0_PCIE_ESM_CAP_7 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +//BIFPLR2_0_VENDOR_ID +#define BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR2_0_DEVICE_ID +#define BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR2_0_COMMAND +#define BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR2_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR2_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR2_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR2_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR2_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR2_0_STATUS +#define BIFPLR2_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR2_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR2_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_0_REVISION_ID +#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR2_0_PROG_INTERFACE +#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR2_0_SUB_CLASS +#define BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR2_0_BASE_CLASS +#define BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR2_0_CACHE_LINE +#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR2_0_LATENCY +#define BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR2_0_HEADER +#define BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR2_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR2_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR2_0_BIST +#define BIFPLR2_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR2_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR2_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR2_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR2_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR2_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR2_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR2_0_IO_BASE_LIMIT +#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR2_0_SECONDARY_STATUS +#define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_0_MEM_BASE_LIMIT +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_0_PREF_BASE_LIMIT +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_0_PREF_BASE_UPPER +#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_0_PREF_LIMIT_UPPER +#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_0_IO_BASE_LIMIT_HI +#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR2_0_CAP_PTR +#define BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR2_0_INTERRUPT_LINE +#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR2_0_INTERRUPT_PIN +#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR2_0_IRQ_BRIDGE_CNTL +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR2_0_EXT_BRIDGE_CNTL +#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR2_0_PMI_CAP_LIST +#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_0_PMI_CAP +#define BIFPLR2_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR2_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR2_0_PMI_STATUS_CNTL +#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR2_0_PCIE_CAP_LIST +#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_0_PCIE_CAP +#define BIFPLR2_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR2_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR2_0_DEVICE_CAP +#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR2_0_DEVICE_CNTL +#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR2_0_DEVICE_STATUS +#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR2_0_LINK_CAP +#define BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR2_0_LINK_CNTL +#define BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR2_0_LINK_STATUS +#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR2_0_SLOT_CAP +#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR2_0_SLOT_CNTL +#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR2_0_SLOT_STATUS +#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR2_0_ROOT_CNTL +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR2_0_ROOT_CAP +#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR2_0_ROOT_STATUS +#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR2_0_DEVICE_CAP2 +#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR2_0_DEVICE_CNTL2 +#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR2_0_DEVICE_STATUS2 +#define BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_0_LINK_CAP2 +#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR2_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR2_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR2_0_LINK_CNTL2 +#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR2_0_LINK_STATUS2 +#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR2_0_SLOT_CAP2 +#define BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR2_0_SLOT_CNTL2 +#define BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR2_0_SLOT_STATUS2 +#define BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_0_MSI_CAP_LIST +#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_0_MSI_MSG_CNTL +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR2_0_MSI_MSG_ADDR_LO +#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR2_0_MSI_MSG_ADDR_HI +#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_0_MSI_MSG_DATA +#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR2_0_MSI_MSG_DATA_64 +#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR2_0_SSID_CAP_LIST +#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_0_SSID_CAP +#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR2_0_MSI_MAP_CAP_LIST +#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_0_MSI_MAP_CAP +#define BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR2_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR2_0_MSI_MAP_ADDR_LO +#define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR2_0_MSI_MAP_ADDR_HI +#define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR2_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_0_PCIE_PORT_VC_CNTL +#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR2_0_PCIE_PORT_VC_STATUS +#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR2_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR2_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR2_0_PCIE_CORR_ERR_STATUS +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR2_0_PCIE_CORR_ERR_MASK +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR2_0_PCIE_HDR_LOG0 +#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_HDR_LOG1 +#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_HDR_LOG2 +#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_HDR_LOG3 +#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_ROOT_ERR_CMD +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR2_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR2_0_PCIE_ERR_SRC_ID +#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR2_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_LINK_CNTL3 +#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_ACS_CAP +#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR2_0_PCIE_ACS_CNTL +#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR2_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_MC_CAP +#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR2_0_PCIE_MC_CNTL +#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR2_0_PCIE_MC_ADDR0 +#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR2_0_PCIE_MC_ADDR1 +#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_RCV0 +#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_RCV1 +#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR2_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_DPC_CAP_LIST +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR2_0_PCIE_DPC_CNTL +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR2_0_PCIE_DPC_STATUS +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR2_0_PCIE_RP_PIO_STATUS +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR2_0_PCIE_RP_PIO_MASK +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR2_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR2_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR2_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_0_PCIE_ESM_CAP_LIST +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_ESM_HEADER_1 +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR2_0_PCIE_ESM_HEADER_2 +#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR2_0_PCIE_ESM_STATUS +#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR2_0_PCIE_ESM_CTRL +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR2_0_PCIE_ESM_CAP_1 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR2_0_PCIE_ESM_CAP_2 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR2_0_PCIE_ESM_CAP_3 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR2_0_PCIE_ESM_CAP_4 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR2_0_PCIE_ESM_CAP_5 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR2_0_PCIE_ESM_CAP_6 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR2_0_PCIE_ESM_CAP_7 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +//BIFPLR3_0_VENDOR_ID +#define BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR3_0_DEVICE_ID +#define BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR3_0_COMMAND +#define BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR3_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR3_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR3_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR3_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR3_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR3_0_STATUS +#define BIFPLR3_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR3_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR3_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_0_REVISION_ID +#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR3_0_PROG_INTERFACE +#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR3_0_SUB_CLASS +#define BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR3_0_BASE_CLASS +#define BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR3_0_CACHE_LINE +#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR3_0_LATENCY +#define BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR3_0_HEADER +#define BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR3_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR3_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR3_0_BIST +#define BIFPLR3_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR3_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR3_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR3_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR3_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR3_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR3_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR3_0_IO_BASE_LIMIT +#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR3_0_SECONDARY_STATUS +#define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_0_MEM_BASE_LIMIT +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_0_PREF_BASE_LIMIT +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_0_PREF_BASE_UPPER +#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_0_PREF_LIMIT_UPPER +#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_0_IO_BASE_LIMIT_HI +#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR3_0_CAP_PTR +#define BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR3_0_INTERRUPT_LINE +#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR3_0_INTERRUPT_PIN +#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR3_0_IRQ_BRIDGE_CNTL +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR3_0_EXT_BRIDGE_CNTL +#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR3_0_PMI_CAP_LIST +#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_0_PMI_CAP +#define BIFPLR3_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR3_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR3_0_PMI_STATUS_CNTL +#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR3_0_PCIE_CAP_LIST +#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_0_PCIE_CAP +#define BIFPLR3_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR3_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR3_0_DEVICE_CAP +#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR3_0_DEVICE_CNTL +#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR3_0_DEVICE_STATUS +#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR3_0_LINK_CAP +#define BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR3_0_LINK_CNTL +#define BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR3_0_LINK_STATUS +#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR3_0_SLOT_CAP +#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR3_0_SLOT_CNTL +#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR3_0_SLOT_STATUS +#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR3_0_ROOT_CNTL +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR3_0_ROOT_CAP +#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR3_0_ROOT_STATUS +#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR3_0_DEVICE_CAP2 +#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR3_0_DEVICE_CNTL2 +#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR3_0_DEVICE_STATUS2 +#define BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_0_LINK_CAP2 +#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR3_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR3_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR3_0_LINK_CNTL2 +#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR3_0_LINK_STATUS2 +#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR3_0_SLOT_CAP2 +#define BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR3_0_SLOT_CNTL2 +#define BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR3_0_SLOT_STATUS2 +#define BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_0_MSI_CAP_LIST +#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_0_MSI_MSG_CNTL +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR3_0_MSI_MSG_ADDR_LO +#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR3_0_MSI_MSG_ADDR_HI +#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_0_MSI_MSG_DATA +#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR3_0_MSI_MSG_DATA_64 +#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR3_0_SSID_CAP_LIST +#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_0_SSID_CAP +#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR3_0_MSI_MAP_CAP_LIST +#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_0_MSI_MAP_CAP +#define BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR3_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR3_0_MSI_MAP_ADDR_LO +#define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR3_0_MSI_MAP_ADDR_HI +#define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR3_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_0_PCIE_PORT_VC_CNTL +#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR3_0_PCIE_PORT_VC_STATUS +#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR3_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR3_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR3_0_PCIE_CORR_ERR_STATUS +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR3_0_PCIE_CORR_ERR_MASK +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR3_0_PCIE_HDR_LOG0 +#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_HDR_LOG1 +#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_HDR_LOG2 +#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_HDR_LOG3 +#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_ROOT_ERR_CMD +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR3_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR3_0_PCIE_ERR_SRC_ID +#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR3_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_LINK_CNTL3 +#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_ACS_CAP +#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR3_0_PCIE_ACS_CNTL +#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR3_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_MC_CAP +#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR3_0_PCIE_MC_CNTL +#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR3_0_PCIE_MC_ADDR0 +#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR3_0_PCIE_MC_ADDR1 +#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_RCV0 +#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_RCV1 +#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR3_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_DPC_CAP_LIST +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR3_0_PCIE_DPC_CNTL +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR3_0_PCIE_DPC_STATUS +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR3_0_PCIE_RP_PIO_STATUS +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR3_0_PCIE_RP_PIO_MASK +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR3_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR3_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR3_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_0_PCIE_ESM_CAP_LIST +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_ESM_HEADER_1 +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR3_0_PCIE_ESM_HEADER_2 +#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR3_0_PCIE_ESM_STATUS +#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR3_0_PCIE_ESM_CTRL +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR3_0_PCIE_ESM_CAP_1 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR3_0_PCIE_ESM_CAP_2 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR3_0_PCIE_ESM_CAP_3 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR3_0_PCIE_ESM_CAP_4 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR3_0_PCIE_ESM_CAP_5 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR3_0_PCIE_ESM_CAP_6 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR3_0_PCIE_ESM_CAP_7 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +//BIFPLR4_0_VENDOR_ID +#define BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR4_0_DEVICE_ID +#define BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR4_0_COMMAND +#define BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR4_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR4_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR4_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR4_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR4_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR4_0_STATUS +#define BIFPLR4_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR4_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR4_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_0_REVISION_ID +#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR4_0_PROG_INTERFACE +#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR4_0_SUB_CLASS +#define BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR4_0_BASE_CLASS +#define BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR4_0_CACHE_LINE +#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR4_0_LATENCY +#define BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR4_0_HEADER +#define BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR4_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR4_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR4_0_BIST +#define BIFPLR4_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR4_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR4_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR4_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR4_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR4_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR4_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR4_0_IO_BASE_LIMIT +#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR4_0_SECONDARY_STATUS +#define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_0_MEM_BASE_LIMIT +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_0_PREF_BASE_LIMIT +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_0_PREF_BASE_UPPER +#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_0_PREF_LIMIT_UPPER +#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_0_IO_BASE_LIMIT_HI +#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR4_0_CAP_PTR +#define BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR4_0_INTERRUPT_LINE +#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR4_0_INTERRUPT_PIN +#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR4_0_IRQ_BRIDGE_CNTL +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR4_0_EXT_BRIDGE_CNTL +#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR4_0_PMI_CAP_LIST +#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_0_PMI_CAP +#define BIFPLR4_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR4_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR4_0_PMI_STATUS_CNTL +#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR4_0_PCIE_CAP_LIST +#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_0_PCIE_CAP +#define BIFPLR4_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR4_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR4_0_DEVICE_CAP +#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR4_0_DEVICE_CNTL +#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR4_0_DEVICE_STATUS +#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR4_0_LINK_CAP +#define BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR4_0_LINK_CNTL +#define BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR4_0_LINK_STATUS +#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR4_0_SLOT_CAP +#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR4_0_SLOT_CNTL +#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR4_0_SLOT_STATUS +#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR4_0_ROOT_CNTL +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR4_0_ROOT_CAP +#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR4_0_ROOT_STATUS +#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR4_0_DEVICE_CAP2 +#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR4_0_DEVICE_CNTL2 +#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR4_0_DEVICE_STATUS2 +#define BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_0_LINK_CAP2 +#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR4_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR4_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR4_0_LINK_CNTL2 +#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR4_0_LINK_STATUS2 +#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR4_0_SLOT_CAP2 +#define BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR4_0_SLOT_CNTL2 +#define BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR4_0_SLOT_STATUS2 +#define BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_0_MSI_CAP_LIST +#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_0_MSI_MSG_CNTL +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR4_0_MSI_MSG_ADDR_LO +#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR4_0_MSI_MSG_ADDR_HI +#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_0_MSI_MSG_DATA +#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR4_0_MSI_MSG_DATA_64 +#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR4_0_SSID_CAP_LIST +#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_0_SSID_CAP +#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR4_0_MSI_MAP_CAP_LIST +#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_0_MSI_MAP_CAP +#define BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR4_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR4_0_MSI_MAP_ADDR_LO +#define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR4_0_MSI_MAP_ADDR_HI +#define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR4_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_0_PCIE_PORT_VC_CNTL +#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR4_0_PCIE_PORT_VC_STATUS +#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR4_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR4_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR4_0_PCIE_CORR_ERR_STATUS +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR4_0_PCIE_CORR_ERR_MASK +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR4_0_PCIE_HDR_LOG0 +#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_HDR_LOG1 +#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_HDR_LOG2 +#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_HDR_LOG3 +#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_ROOT_ERR_CMD +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR4_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR4_0_PCIE_ERR_SRC_ID +#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR4_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_LINK_CNTL3 +#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_ACS_CAP +#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR4_0_PCIE_ACS_CNTL +#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR4_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_MC_CAP +#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR4_0_PCIE_MC_CNTL +#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR4_0_PCIE_MC_ADDR0 +#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR4_0_PCIE_MC_ADDR1 +#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_RCV0 +#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_RCV1 +#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR4_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_DPC_CAP_LIST +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR4_0_PCIE_DPC_CNTL +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR4_0_PCIE_DPC_STATUS +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR4_0_PCIE_RP_PIO_STATUS +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR4_0_PCIE_RP_PIO_MASK +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR4_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR4_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR4_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_0_PCIE_ESM_CAP_LIST +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_ESM_HEADER_1 +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR4_0_PCIE_ESM_HEADER_2 +#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR4_0_PCIE_ESM_STATUS +#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR4_0_PCIE_ESM_CTRL +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR4_0_PCIE_ESM_CAP_1 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR4_0_PCIE_ESM_CAP_2 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR4_0_PCIE_ESM_CAP_3 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR4_0_PCIE_ESM_CAP_4 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR4_0_PCIE_ESM_CAP_5 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR4_0_PCIE_ESM_CAP_6 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR4_0_PCIE_ESM_CAP_7 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +//BIFPLR5_0_VENDOR_ID +#define BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR5_0_DEVICE_ID +#define BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR5_0_COMMAND +#define BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR5_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR5_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR5_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR5_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR5_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR5_0_STATUS +#define BIFPLR5_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR5_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR5_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_0_REVISION_ID +#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR5_0_PROG_INTERFACE +#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR5_0_SUB_CLASS +#define BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR5_0_BASE_CLASS +#define BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR5_0_CACHE_LINE +#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR5_0_LATENCY +#define BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR5_0_HEADER +#define BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR5_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR5_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR5_0_BIST +#define BIFPLR5_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR5_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR5_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR5_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR5_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR5_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR5_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR5_0_IO_BASE_LIMIT +#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR5_0_SECONDARY_STATUS +#define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_0_MEM_BASE_LIMIT +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_0_PREF_BASE_LIMIT +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_0_PREF_BASE_UPPER +#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_0_PREF_LIMIT_UPPER +#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_0_IO_BASE_LIMIT_HI +#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR5_0_CAP_PTR +#define BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR5_0_INTERRUPT_LINE +#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR5_0_INTERRUPT_PIN +#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR5_0_IRQ_BRIDGE_CNTL +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR5_0_EXT_BRIDGE_CNTL +#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR5_0_PMI_CAP_LIST +#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_0_PMI_CAP +#define BIFPLR5_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR5_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR5_0_PMI_STATUS_CNTL +#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR5_0_PCIE_CAP_LIST +#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_0_PCIE_CAP +#define BIFPLR5_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR5_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR5_0_DEVICE_CAP +#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR5_0_DEVICE_CNTL +#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR5_0_DEVICE_STATUS +#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR5_0_LINK_CAP +#define BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR5_0_LINK_CNTL +#define BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR5_0_LINK_STATUS +#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR5_0_SLOT_CAP +#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR5_0_SLOT_CNTL +#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR5_0_SLOT_STATUS +#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR5_0_ROOT_CNTL +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR5_0_ROOT_CAP +#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR5_0_ROOT_STATUS +#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR5_0_DEVICE_CAP2 +#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR5_0_DEVICE_CNTL2 +#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR5_0_DEVICE_STATUS2 +#define BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_0_LINK_CAP2 +#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR5_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR5_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR5_0_LINK_CNTL2 +#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR5_0_LINK_STATUS2 +#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR5_0_SLOT_CAP2 +#define BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR5_0_SLOT_CNTL2 +#define BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR5_0_SLOT_STATUS2 +#define BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_0_MSI_CAP_LIST +#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_0_MSI_MSG_CNTL +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR5_0_MSI_MSG_ADDR_LO +#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR5_0_MSI_MSG_ADDR_HI +#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_0_MSI_MSG_DATA +#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR5_0_MSI_MSG_DATA_64 +#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR5_0_SSID_CAP_LIST +#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_0_SSID_CAP +#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR5_0_MSI_MAP_CAP_LIST +#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_0_MSI_MAP_CAP +#define BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR5_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR5_0_MSI_MAP_ADDR_LO +#define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR5_0_MSI_MAP_ADDR_HI +#define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR5_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_0_PCIE_PORT_VC_CNTL +#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR5_0_PCIE_PORT_VC_STATUS +#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR5_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR5_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR5_0_PCIE_CORR_ERR_STATUS +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR5_0_PCIE_CORR_ERR_MASK +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR5_0_PCIE_HDR_LOG0 +#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_HDR_LOG1 +#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_HDR_LOG2 +#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_HDR_LOG3 +#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_ROOT_ERR_CMD +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR5_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR5_0_PCIE_ERR_SRC_ID +#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR5_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_LINK_CNTL3 +#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_ACS_CAP +#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR5_0_PCIE_ACS_CNTL +#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR5_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_MC_CAP +#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR5_0_PCIE_MC_CNTL +#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR5_0_PCIE_MC_ADDR0 +#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR5_0_PCIE_MC_ADDR1 +#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_RCV0 +#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_RCV1 +#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR5_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_DPC_CAP_LIST +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR5_0_PCIE_DPC_CNTL +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR5_0_PCIE_DPC_STATUS +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR5_0_PCIE_RP_PIO_STATUS +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR5_0_PCIE_RP_PIO_MASK +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR5_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR5_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR5_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_0_PCIE_ESM_CAP_LIST +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_ESM_HEADER_1 +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR5_0_PCIE_ESM_HEADER_2 +#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR5_0_PCIE_ESM_STATUS +#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR5_0_PCIE_ESM_CTRL +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR5_0_PCIE_ESM_CAP_1 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR5_0_PCIE_ESM_CAP_2 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR5_0_PCIE_ESM_CAP_3 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR5_0_PCIE_ESM_CAP_4 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR5_0_PCIE_ESM_CAP_5 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR5_0_PCIE_ESM_CAP_6 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR5_0_PCIE_ESM_CAP_7 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +//BIFPLR6_0_VENDOR_ID +#define BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR6_0_DEVICE_ID +#define BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR6_0_COMMAND +#define BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR6_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR6_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR6_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR6_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR6_0_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR6_0_STATUS +#define BIFPLR6_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR6_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_0_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR6_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_0_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_0_REVISION_ID +#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR6_0_PROG_INTERFACE +#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR6_0_SUB_CLASS +#define BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR6_0_BASE_CLASS +#define BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR6_0_CACHE_LINE +#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR6_0_LATENCY +#define BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR6_0_HEADER +#define BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR6_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR6_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR6_0_BIST +#define BIFPLR6_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR6_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR6_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR6_0_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR6_0_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR6_0_BIST__BIST_CAP_MASK 0x80L +//BIFPLR6_0_SUB_BUS_NUMBER_LATENCY +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR6_0_IO_BASE_LIMIT +#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR6_0_SECONDARY_STATUS +#define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_0_MEM_BASE_LIMIT +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_0_PREF_BASE_LIMIT +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_0_PREF_BASE_UPPER +#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_0_PREF_LIMIT_UPPER +#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_0_IO_BASE_LIMIT_HI +#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR6_0_CAP_PTR +#define BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR6_0_INTERRUPT_LINE +#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR6_0_INTERRUPT_PIN +#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR6_0_IRQ_BRIDGE_CNTL +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR6_0_EXT_BRIDGE_CNTL +#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR6_0_PMI_CAP_LIST +#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_0_PMI_CAP +#define BIFPLR6_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR6_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR6_0_PMI_STATUS_CNTL +#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR6_0_PCIE_CAP_LIST +#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_0_PCIE_CAP +#define BIFPLR6_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR6_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR6_0_DEVICE_CAP +#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR6_0_DEVICE_CNTL +#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR6_0_DEVICE_STATUS +#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR6_0_LINK_CAP +#define BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR6_0_LINK_CNTL +#define BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR6_0_LINK_STATUS +#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR6_0_SLOT_CAP +#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR6_0_SLOT_CNTL +#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR6_0_SLOT_STATUS +#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR6_0_ROOT_CNTL +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR6_0_ROOT_CAP +#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR6_0_ROOT_STATUS +#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR6_0_DEVICE_CAP2 +#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR6_0_DEVICE_CNTL2 +#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR6_0_DEVICE_STATUS2 +#define BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_0_LINK_CAP2 +#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR6_0_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR6_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR6_0_LINK_CNTL2 +#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR6_0_LINK_STATUS2 +#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR6_0_SLOT_CAP2 +#define BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR6_0_SLOT_CNTL2 +#define BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR6_0_SLOT_STATUS2 +#define BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_0_MSI_CAP_LIST +#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_0_MSI_MSG_CNTL +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR6_0_MSI_MSG_ADDR_LO +#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR6_0_MSI_MSG_ADDR_HI +#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_0_MSI_MSG_DATA +#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR6_0_MSI_MSG_DATA_64 +#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR6_0_SSID_CAP_LIST +#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_0_SSID_CAP +#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR6_0_MSI_MAP_CAP_LIST +#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_0_MSI_MAP_CAP +#define BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR6_0_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR6_0_MSI_MAP_ADDR_LO +#define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR6_0_MSI_MAP_ADDR_HI +#define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_VC_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR6_0_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_0_PCIE_PORT_VC_CNTL +#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR6_0_PCIE_PORT_VC_STATUS +#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR6_0_PCIE_VC0_RESOURCE_CAP +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_0_PCIE_VC1_RESOURCE_CAP +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_UNCORR_ERR_STATUS +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR6_0_PCIE_UNCORR_ERR_MASK +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR6_0_PCIE_CORR_ERR_STATUS +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR6_0_PCIE_CORR_ERR_MASK +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR6_0_PCIE_HDR_LOG0 +#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_HDR_LOG1 +#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_HDR_LOG2 +#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_HDR_LOG3 +#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_ROOT_ERR_CMD +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR6_0_PCIE_ROOT_ERR_STATUS +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR6_0_PCIE_ERR_SRC_ID +#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR6_0_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_LINK_CNTL3 +#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_0_PCIE_LANE_ERROR_STATUS +#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_ACS_CAP +#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR6_0_PCIE_ACS_CNTL +#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR6_0_PCIE_MC_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_MC_CAP +#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR6_0_PCIE_MC_CNTL +#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR6_0_PCIE_MC_ADDR0 +#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR6_0_PCIE_MC_ADDR1 +#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_RCV0 +#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_RCV1 +#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_BLOCK_ALL0 +#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_BLOCK_ALL1 +#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR6_0_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_L1_PM_SUB_CAP +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_DPC_CAP_LIST +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR6_0_PCIE_DPC_CNTL +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR6_0_PCIE_DPC_STATUS +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR6_0_PCIE_RP_PIO_STATUS +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR6_0_PCIE_RP_PIO_MASK +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR6_0_PCIE_RP_PIO_SEVERITY +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR6_0_PCIE_RP_PIO_SYSERROR +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR6_0_PCIE_RP_PIO_EXCEPTION +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_0_PCIE_ESM_CAP_LIST +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_ESM_HEADER_1 +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR6_0_PCIE_ESM_HEADER_2 +#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR6_0_PCIE_ESM_STATUS +#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR6_0_PCIE_ESM_CTRL +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR6_0_PCIE_ESM_CAP_1 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR6_0_PCIE_ESM_CAP_2 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR6_0_PCIE_ESM_CAP_3 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR6_0_PCIE_ESM_CAP_4 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR6_0_PCIE_ESM_CAP_5 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR6_0_PCIE_ESM_CAP_6 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR6_0_PCIE_ESM_CAP_7 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_dbgu0_dbgudec +//port_a_addr +#define port_a_addr__Index__SHIFT 0x0 +#define port_a_addr__Reserved__SHIFT 0x8 +#define port_a_addr__ReadEnable__SHIFT 0x1f +#define port_a_addr__Index_MASK 0x000000FFL +#define port_a_addr__Reserved_MASK 0x7FFFFF00L +#define port_a_addr__ReadEnable_MASK 0x80000000L +//port_a_data_lo +#define port_a_data_lo__Data__SHIFT 0x0 +#define port_a_data_lo__Data_MASK 0xFFFFFFFFL +//port_a_data_hi +#define port_a_data_hi__Data__SHIFT 0x0 +#define port_a_data_hi__Data_MASK 0xFFFFFFFFL +//port_b_addr +#define port_b_addr__Index__SHIFT 0x0 +#define port_b_addr__Reserved__SHIFT 0x8 +#define port_b_addr__ReadEnable__SHIFT 0x1f +#define port_b_addr__Index_MASK 0x000000FFL +#define port_b_addr__Reserved_MASK 0x7FFFFF00L +#define port_b_addr__ReadEnable_MASK 0x80000000L +//port_b_data_lo +#define port_b_data_lo__Data__SHIFT 0x0 +#define port_b_data_lo__Data_MASK 0xFFFFFFFFL +//port_b_data_hi +#define port_b_data_hi__Data__SHIFT 0x0 +#define port_b_data_hi__Data_MASK 0xFFFFFFFFL +//port_c_addr +#define port_c_addr__Index__SHIFT 0x0 +#define port_c_addr__Reserved__SHIFT 0x8 +#define port_c_addr__ReadEnable__SHIFT 0x1f +#define port_c_addr__Index_MASK 0x000000FFL +#define port_c_addr__Reserved_MASK 0x7FFFFF00L +#define port_c_addr__ReadEnable_MASK 0x80000000L +//port_c_data_lo +#define port_c_data_lo__Data__SHIFT 0x0 +#define port_c_data_lo__Data_MASK 0xFFFFFFFFL +//port_c_data_hi +#define port_c_data_hi__Data__SHIFT 0x0 +#define port_c_data_hi__Data_MASK 0xFFFFFFFFL +//port_d_addr +#define port_d_addr__Index__SHIFT 0x0 +#define port_d_addr__Reserved__SHIFT 0x8 +#define port_d_addr__ReadEnable__SHIFT 0x1f +#define port_d_addr__Index_MASK 0x000000FFL +#define port_d_addr__Reserved_MASK 0x7FFFFF00L +#define port_d_addr__ReadEnable_MASK 0x80000000L +//port_d_data_lo +#define port_d_data_lo__Data__SHIFT 0x0 +#define port_d_data_lo__Data_MASK 0xFFFFFFFFL +//port_d_data_hi +#define port_d_data_hi__Data__SHIFT 0x0 +#define port_d_data_hi__Data_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//GDC0_NGDC_SDP_PORT_CTRL +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//GDC0_NGDC_RESERVED_0 +#define GDC0_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NGDC_RESERVED_1 +#define GDC0_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NGDC_SDP_PORT_CTRL_SOCCLK +#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 +#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL +//GDC0_BIF_SDMA0_DOORBELL_RANGE +#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC0_BIF_SDMA1_DOORBELL_RANGE +#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC0_BIF_IH_DOORBELL_RANGE +#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC0_BIF_MMSCH0_DOORBELL_RANGE +#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC0_ATDMA_MISC_CNTL +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC0_BIF_DOORBELL_FENCE_CNTL +#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 +#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L +#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +//GDC0_GDC_PG_MISC_CNTL +#define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 +#define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_syshub_mmreg_direct_syshubdirect +//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L +//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L +//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L +#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L +//SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L +//SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER +#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL +//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L +//SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET +#define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L +//SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH +#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK +#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L +//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L +//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L +//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L +#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2 +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L +#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L +//SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS +#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD +#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_nbif_sion_SIONDEC +//SION_CL0_RdRsp_BurstTarget_REG0 +#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL0_RdRsp_BurstTarget_REG1 +#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL0_RdRsp_TimeSlot_REG0 +#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL0_RdRsp_TimeSlot_REG1 +#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL0_WrRsp_BurstTarget_REG0 +#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL0_WrRsp_BurstTarget_REG1 +#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL0_WrRsp_TimeSlot_REG0 +#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL0_WrRsp_TimeSlot_REG1 +#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL0_Req_BurstTarget_REG0 +#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL0_Req_BurstTarget_REG1 +#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL0_Req_TimeSlot_REG0 +#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL0_Req_TimeSlot_REG1 +#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL0_ReqPoolCredit_Alloc_REG0 +#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL0_ReqPoolCredit_Alloc_REG1 +#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL0_DataPoolCredit_Alloc_REG0 +#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL0_DataPoolCredit_Alloc_REG1 +#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL1_RdRsp_BurstTarget_REG0 +#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL1_RdRsp_BurstTarget_REG1 +#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL1_RdRsp_TimeSlot_REG0 +#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL1_RdRsp_TimeSlot_REG1 +#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL1_WrRsp_BurstTarget_REG0 +#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL1_WrRsp_BurstTarget_REG1 +#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL1_WrRsp_TimeSlot_REG0 +#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL1_WrRsp_TimeSlot_REG1 +#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL1_Req_BurstTarget_REG0 +#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL1_Req_BurstTarget_REG1 +#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL1_Req_TimeSlot_REG0 +#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL1_Req_TimeSlot_REG1 +#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL1_ReqPoolCredit_Alloc_REG0 +#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL1_ReqPoolCredit_Alloc_REG1 +#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL1_DataPoolCredit_Alloc_REG0 +#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL1_DataPoolCredit_Alloc_REG1 +#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL2_RdRsp_BurstTarget_REG0 +#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL2_RdRsp_BurstTarget_REG1 +#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL2_RdRsp_TimeSlot_REG0 +#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL2_RdRsp_TimeSlot_REG1 +#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL2_WrRsp_BurstTarget_REG0 +#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL2_WrRsp_BurstTarget_REG1 +#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL2_WrRsp_TimeSlot_REG0 +#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL2_WrRsp_TimeSlot_REG1 +#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL2_Req_BurstTarget_REG0 +#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL2_Req_BurstTarget_REG1 +#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL2_Req_TimeSlot_REG0 +#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL2_Req_TimeSlot_REG1 +#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL2_ReqPoolCredit_Alloc_REG0 +#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL2_ReqPoolCredit_Alloc_REG1 +#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL2_DataPoolCredit_Alloc_REG0 +#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL2_DataPoolCredit_Alloc_REG1 +#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL2_RdRspPoolCredit_Alloc_REG0 +#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL2_RdRspPoolCredit_Alloc_REG1 +#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL2_WrRspPoolCredit_Alloc_REG0 +#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL2_WrRspPoolCredit_Alloc_REG1 +#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL3_RdRsp_BurstTarget_REG0 +#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL3_RdRsp_BurstTarget_REG1 +#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL3_RdRsp_TimeSlot_REG0 +#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL3_RdRsp_TimeSlot_REG1 +#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL3_WrRsp_BurstTarget_REG0 +#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL3_WrRsp_BurstTarget_REG1 +#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL3_WrRsp_TimeSlot_REG0 +#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL3_WrRsp_TimeSlot_REG1 +#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL3_Req_BurstTarget_REG0 +#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//SION_CL3_Req_BurstTarget_REG1 +#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//SION_CL3_Req_TimeSlot_REG0 +#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//SION_CL3_Req_TimeSlot_REG1 +#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//SION_CL3_ReqPoolCredit_Alloc_REG0 +#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL3_ReqPoolCredit_Alloc_REG1 +#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL3_DataPoolCredit_Alloc_REG0 +#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL3_DataPoolCredit_Alloc_REG1 +#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL3_RdRspPoolCredit_Alloc_REG0 +#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL3_RdRspPoolCredit_Alloc_REG1 +#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CL3_WrRspPoolCredit_Alloc_REG0 +#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//SION_CL3_WrRspPoolCredit_Alloc_REG1 +#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//SION_CNTL_REG0 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//SION_CNTL_REG1 +#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 +#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L + + +// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 +#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 +#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 +#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 +#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 +#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 +#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8 +#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9 +#define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa +#define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb +#define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc +#define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd +#define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe +#define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L +#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L +#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L +#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L +#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L +#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L +#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L +#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L +#define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L +#define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L +#define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L +#define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L +#define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L +#define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +//SHUB_PF0_VF_FLR_RST +#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 +#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 +#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 +#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 +#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 +#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 +#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 +#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 +#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa +#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb +#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc +#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd +#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe +#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf +#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f +#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L +#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L +#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L +#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L +#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L +#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L +#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L +#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L +#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L +#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L +#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L +#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L +#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L +#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L +#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L +#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 +#define SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK 0x00000001L +//SHUB_RST_MISC_TRL +#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT 0x0 +#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT 0x10 +#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK 0x00000001L +#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L + + +// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk +//GDC_RAS_LEAF0_CTRL +#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L +//GDC_RAS_LEAF1_CTRL +#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L +//GDC_RAS_LEAF2_CTRL +#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L +//GDC_RAS_LEAF3_CTRL +#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK 0x00200000L +//GDC_RAS_LEAF4_CTRL +#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK 0x00200000L +//GDC_RAS_LEAF5_CTRL +#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 +#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK 0x00000001L +#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK 0x00200000L + + +// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL +//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L +//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DSFX +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DSCX +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DSSX +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L +//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL +//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L +//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L +//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL +//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14 +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L + + +// addressBlock: nbio_iohub_nb_ioapicmio_ioapic_miodec +//IOAPICMIO_INDEX +#define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data__SHIFT 0x0 +#define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data_MASK 0xFFFFFFFFL +//IOAPICMIO_DATA +#define IOAPICMIO_DATA__IOAPICMIO_DATA__SHIFT 0x0 +#define IOAPICMIO_DATA__IOAPICMIO_DATA_MASK 0xFFFFFFFFL +//IRQ_PIN_ASSERTION_REGISTER +#define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ__SHIFT 0x0 +#define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ_MASK 0x000000FFL +//EOI_REGISTER +#define EOI_REGISTER__Vector__SHIFT 0x0 +#define EOI_REGISTER__Vector_MASK 0x000000FFL + + +// addressBlock: nbio_iohub_nb_ioapicmioindex_ioapic_mioindexdec +//IOAPIC_ID_REGISTER +#define IOAPIC_ID_REGISTER__DEV_ID__SHIFT 0x18 +#define IOAPIC_ID_REGISTER__EXTEND_ID__SHIFT 0x1c +#define IOAPIC_ID_REGISTER__DEV_ID_MASK 0x0F000000L +#define IOAPIC_ID_REGISTER__EXTEND_ID_MASK 0xF0000000L +//IOAPIC_VERSION_REGISTER +#define IOAPIC_VERSION_REGISTER__Version__SHIFT 0x0 +#define IOAPIC_VERSION_REGISTER__PRQ__SHIFT 0xf +#define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries__SHIFT 0x10 +#define IOAPIC_VERSION_REGISTER__Version_MASK 0x000000FFL +#define IOAPIC_VERSION_REGISTER__PRQ_MASK 0x00008000L +#define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries_MASK 0x00FF0000L +//IOAPIC_ARBITRATION_REGISTER +#define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID__SHIFT 0x18 +#define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID_MASK 0x0F000000L +//REDIRECTION_TABLE_ENTRY_LOW_0 +#define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_0 +#define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_1 +#define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_1 +#define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_2 +#define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_2 +#define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_3 +#define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_3 +#define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_4 +#define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_4 +#define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_5 +#define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_5 +#define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_6 +#define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_6 +#define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_7 +#define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_7 +#define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_8 +#define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_8 +#define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_9 +#define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_9 +#define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_10 +#define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_10 +#define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_11 +#define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_11 +#define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_12 +#define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_12 +#define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_13 +#define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_13 +#define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_14 +#define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_14 +#define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_15 +#define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_15 +#define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_16 +#define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_16 +#define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_17 +#define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_17 +#define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_18 +#define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_18 +#define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_19 +#define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_19 +#define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_20 +#define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_20 +#define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_21 +#define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_21 +#define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_22 +#define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_22 +#define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_23 +#define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_23 +#define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_24 +#define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_24 +#define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_25 +#define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_25 +#define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_26 +#define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_26 +#define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_27 +#define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_27 +#define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_28 +#define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_28 +#define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_29 +#define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_29 +#define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_30 +#define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_30 +#define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30_MASK 0xFF000000L +//REDIRECTION_TABLE_ENTRY_LOW_31 +#define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31__SHIFT 0x0 +#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31__SHIFT 0x8 +#define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31__SHIFT 0xb +#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31__SHIFT 0xc +#define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31__SHIFT 0xd +#define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31__SHIFT 0xe +#define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31__SHIFT 0xf +#define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31__SHIFT 0x10 +#define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31_MASK 0x000000FFL +#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31_MASK 0x00000700L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31_MASK 0x00000800L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31_MASK 0x00001000L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31_MASK 0x00002000L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31_MASK 0x00004000L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31_MASK 0x00008000L +#define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31_MASK 0x00010000L +//REDIRECTION_TABLE_ENTRY_HIGH_31 +#define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31__SHIFT 0x18 +#define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31_MASK 0xFF000000L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC1_VENDOR_ID +#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_DEVICE_ID +#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_COMMAND +#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC1_STATUS +#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_REVISION_ID +#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC1_PROG_INTERFACE +#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_SUB_CLASS +#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC1_BASE_CLASS +#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC1_CACHE_LINE +#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_LATENCY +#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC1_HEADER +#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC1_BIST +#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC1_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC1_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_CAP_PTR +#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_RC1_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC1_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC1_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PMI_CAP +#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PCIE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC1_DEVICE_CAP +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC1_DEVICE_CNTL +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC1_DEVICE_STATUS +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_RC1_LINK_CAP +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_LINK_CNTL +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_RC1_LINK_STATUS +#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC1_SLOT_CAP +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC1_SLOT_CNTL +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV0_RC1_SLOT_STATUS +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC1_ROOT_CNTL +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC1_ROOT_CAP +#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC1_ROOT_STATUS +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC1_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_RC1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_LINK_CAP2 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_RC1_LINK_CNTL2 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC1_LINK_STATUS2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_RC1_SLOT_CAP2 +#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC1_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC1_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_SSID_CAP +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_MSI_MAP_CAP +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +//BIF_CFG_DEV1_RC1_VENDOR_ID +#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC1_DEVICE_ID +#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC1_COMMAND +#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_RC1_STATUS +#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_REVISION_ID +#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_RC1_PROG_INTERFACE +#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_RC1_SUB_CLASS +#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC1_BASE_CLASS +#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC1_CACHE_LINE +#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_RC1_LATENCY +#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_RC1_HEADER +#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_RC1_BIST +#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_RC1_BASE_ADDR_1 +#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV1_RC1_SECONDARY_STATUS +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PREF_BASE_UPPER +#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER +#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC1_CAP_PTR +#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_RC1_INTERRUPT_LINE +#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_RC1_INTERRUPT_PIN +#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV1_RC1_PMI_CAP_LIST +#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_PMI_CAP +#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_PCIE_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_PCIE_CAP +#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_RC1_DEVICE_CAP +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_RC1_DEVICE_CNTL +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV1_RC1_DEVICE_STATUS +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_RC1_LINK_CAP +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_LINK_CNTL +#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_RC1_LINK_STATUS +#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_RC1_SLOT_CAP +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV1_RC1_SLOT_CNTL +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV1_RC1_SLOT_STATUS +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV1_RC1_ROOT_CNTL +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV1_RC1_ROOT_CAP +#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV1_RC1_ROOT_STATUS +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV1_RC1_DEVICE_CAP2 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_RC1_DEVICE_CNTL2 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_RC1_DEVICE_STATUS2 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC1_LINK_CAP2 +#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_RC1_LINK_CNTL2 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_RC1_LINK_STATUS2 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_RC1_SLOT_CAP2 +#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_SLOT_CNTL2 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC1_SLOT_STATUS2 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC1_MSI_CAP_LIST +#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_MSI_MSG_CNTL +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_MSI_MSG_DATA +#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC1_SSID_CAP_LIST +#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_SSID_CAP +#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_MSI_MAP_CAP +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC1_PCIE_ACS_CAP +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +//BIF_BX_PF0_SYSHUB_INDEX_OVLP +#define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX_PF0_SYSHUB_DATA_OVLP +#define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_PCIE_INDEX +#define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF0_PCIE_DATA +#define BIF_BX_PF0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX_PF0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_PCIE_INDEX2 +#define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX_PF0_PCIE_DATA2 +#define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX_PF0_SBIOS_SCRATCH_0 +#define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_SBIOS_SCRATCH_1 +#define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_SBIOS_SCRATCH_2 +#define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_SBIOS_SCRATCH_3 +#define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_0 +#define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_1 +#define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_2 +#define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_3 +#define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_4 +#define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_5 +#define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_6 +#define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_7 +#define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_8 +#define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_9 +#define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_10 +#define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_11 +#define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_12 +#define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_13 +#define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_14 +#define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIOS_SCRATCH_15 +#define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIF_RLC_INTR_CNTL +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF0_BIF_VCE_INTR_CNTL +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF0_BIF_UVD_INTR_CNTL +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +//BIF_BX_PF0_BIF_MM_INDACCESS_CNTL +#define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX_PF0_BUS_CNTL +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 +#define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX_PF0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 +#define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 +#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b +#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c +#define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L +#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L +#define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX_PF0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L +#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L +#define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L +#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L +#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L +#define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_SCRATCH0 +#define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIF_SCRATCH1 +#define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BX_RESET_EN +#define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 +#define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L +#define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L +#define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L +#define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L +#define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX_PF0_MM_CFGREGS_CNTL +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX_PF0_BX_RESET_CNTL +#define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX_PF0_INTERRUPT_CNTL +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +//BIF_BX_PF0_INTERRUPT_CNTL2 +#define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX_PF0_CLKREQB_PAD_CNTL +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L +#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L +//BIF_BX_PF0_BIF_DOORBELL_CNTL +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX_PF0_BIF_DOORBELL_INT_CNTL +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L +//BIF_BX_PF0_BIF_FB_EN +#define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_BUSY_DELAY_CNTR +#define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL +//BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL +//BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL +//BIF_BX_PF0_BACO_CNTL +#define BIF_BX_PF0_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 +#define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX_PF0_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX_PF0_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L +#define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX_PF0_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX_PF0_BIF_BACO_EXIT_TIME0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF0_BIF_BACO_EXIT_TIMER1 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX_PF0_BIF_BACO_EXIT_TIMER2 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF0_BIF_BACO_EXIT_TIMER3 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF0_BIF_BACO_EXIT_TIMER4 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF0_MEM_TYPE_CNTL +#define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS +#define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L +//BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_VDDGFX_FB_CMP +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L +#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L +//BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL +//BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L +//BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL +//BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX_PF0_BIF_RB_CNTL +#define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX_PF0_BIF_RB_BASE +#define BIF_BX_PF0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX_PF0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX_PF0_BIF_RB_RPTR +#define BIF_BX_PF0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX_PF0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_RB_WPTR +#define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX_PF0_MAILBOX_INDEX +#define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE +#define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE +#define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE +#define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF0_BIF_PERSTB_PAD_CNTL +#define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX_PF0_BIF_PX_EN_PAD_CNTL +#define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL +#define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_CONTROL +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF0_MAILBOX_INT_CNTL +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_VMHV_MAILBOX +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +//SHADOW_COMMAND +#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 +#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 +#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L +#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L +//SHADOW_BASE_ADDR_1 +#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL +//SHADOW_BASE_ADDR_2 +#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL +//SHADOW_SUB_BUS_NUMBER_LATENCY +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L +//SHADOW_IO_BASE_LIMIT +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L +//SHADOW_MEM_BASE_LIMIT +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_LIMIT +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_UPPER +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_PREF_LIMIT_UPPER +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_IO_BASE_LIMIT_HI +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L +//SHADOW_IRQ_BRIDGE_CNTL +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L +//SUC_INDEX +#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 +#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL +//SUC_DATA +#define SUC_DATA__SUC_DATA__SHIFT 0x0 +#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC +//RCC_EP_DEV1_EP_PCIE_SCRATCH +#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV1_EP_PCIE_CNTL +#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +//RCC_EP_DEV1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV1_EP_PCIEP_RESERVED +#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC +//RCC_DWN_DEV1_DN_PCIE_RESERVED +#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV1_DN_PCIE_CNTL +#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC +//RCC_DWNP_DEV1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +//RCC_DWNP_DEV1_PCIE_RX_CNTL +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +//RCC_DWNP_DEV1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_bif_bx_pf_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT 0x8 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK 0x0000FF00L +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT 0x8 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK 0x0000FF00L +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x1f +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x80000000L +//BIFC_BME_ERR_LOG +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x8 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x9 +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2__SHIFT 0xa +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3__SHIFT 0xb +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4__SHIFT 0xc +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5__SHIFT 0xd +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6__SHIFT 0xe +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7__SHIFT 0xf +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x18 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x19 +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2__SHIFT 0x1a +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3__SHIFT 0x1b +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4__SHIFT 0x1c +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5__SHIFT 0x1d +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6__SHIFT 0x1e +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7__SHIFT 0x1f +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK 0x00000100L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK 0x00000200L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2_MASK 0x00000400L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3_MASK 0x00000800L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4_MASK 0x00001000L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5_MASK 0x00002000L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6_MASK 0x00004000L +#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7_MASK 0x00008000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK 0x01000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK 0x02000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2_MASK 0x04000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3_MASK 0x08000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4_MASK 0x10000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5_MASK 0x20000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6_MASK 0x40000000L +#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7_MASK 0x80000000L +//BIFC_RCCBIH_BME_ERR_LOG +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x8 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x9 +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0xa +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0xb +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0xc +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0xd +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0xe +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0xf +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x18 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x19 +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0x1a +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0x1b +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0x1c +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0x1d +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0x1e +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0x1f +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x00000100L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x00000200L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x00000400L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x00000800L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x00001000L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x00002000L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x00004000L +#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x00008000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x01000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x02000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x04000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x08000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x10000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x20000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x40000000L +#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x80000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK 0x30000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK 0x30000000L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_SMN_VWR_VCHG_DIS_CTRL +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS__SHIFT 0xa +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS__SHIFT 0xb +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS__SHIFT 0xc +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS__SHIFT 0xd +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS__SHIFT 0xe +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS__SHIFT 0xf +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS__SHIFT 0x10 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS__SHIFT 0x11 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS_MASK 0x00000400L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS_MASK 0x00000800L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS_MASK 0x00001000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS_MASK 0x00002000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS_MASK 0x00004000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS_MASK 0x00008000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS_MASK 0x00010000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS_MASK 0x00020000L +//NBIF_SMN_VWR_VCHG_RST_CTRL0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV__SHIFT 0xa +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV__SHIFT 0xb +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV__SHIFT 0xc +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV__SHIFT 0xd +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV__SHIFT 0xe +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV__SHIFT 0xf +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV__SHIFT 0x10 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV__SHIFT 0x11 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV_MASK 0x00000400L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV_MASK 0x00000800L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV_MASK 0x00001000L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV_MASK 0x00002000L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV_MASK 0x00004000L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV_MASK 0x00008000L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV_MASK 0x00010000L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV_MASK 0x00020000L +//NBIF_SMN_VWR_VCHG_TRIG +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG__SHIFT 0xa +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG__SHIFT 0xb +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG__SHIFT 0xc +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG__SHIFT 0xd +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG__SHIFT 0xe +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG__SHIFT 0xf +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG__SHIFT 0x10 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG__SHIFT 0x11 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG_MASK 0x00000400L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG_MASK 0x00000800L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG_MASK 0x00001000L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG_MASK 0x00002000L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG_MASK 0x00004000L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG_MASK 0x00008000L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG_MASK 0x00010000L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG_MASK 0x00020000L +//NBIF_SMN_VWR_WTRIG_CNTL +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS__SHIFT 0xa +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS__SHIFT 0xb +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS__SHIFT 0xc +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS__SHIFT 0xd +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS__SHIFT 0xe +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS__SHIFT 0xf +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS__SHIFT 0x10 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS__SHIFT 0x11 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS_MASK 0x00000400L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS_MASK 0x00000800L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS_MASK 0x00001000L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS_MASK 0x00002000L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS_MASK 0x00004000L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS_MASK 0x00008000L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS_MASK 0x00010000L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS_MASK 0x00020000L +//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV__SHIFT 0xa +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV__SHIFT 0xb +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV__SHIFT 0xc +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV__SHIFT 0xd +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV__SHIFT 0xe +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV__SHIFT 0xf +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV__SHIFT 0x10 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV__SHIFT 0x11 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV_MASK 0x00000400L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV_MASK 0x00000800L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV_MASK 0x00001000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV_MASK 0x00002000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV_MASK 0x00004000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV_MASK 0x00008000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV_MASK 0x00010000L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV_MASK 0x00020000L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT 0x11 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT 0x15 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT 0x19 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT 0x1d +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK 0x00020000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK 0x00200000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK 0x02000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK 0x20000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT 0x8 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT 0x9 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT 0xa +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT 0xb +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT 0xc +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT 0xd +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT 0xe +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT 0xf +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK 0x00000100L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK 0x00000200L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK 0x00000400L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK 0x00000800L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK 0x00001000L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK 0x00002000L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK 0x00004000L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK 0x00008000L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT 0x8 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT 0x9 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT 0xa +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT 0xb +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT 0xc +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT 0xd +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT 0xe +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT 0xf +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK 0x00000100L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK 0x00000200L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK 0x00000400L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK 0x00000800L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK 0x00001000L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK 0x00002000L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK 0x00004000L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK 0x00008000L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT 0x10 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT 0x12 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT 0x14 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT 0x16 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT 0x18 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT 0x1a +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT 0x1c +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT 0x1e +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK 0x00030000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK 0x000C0000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK 0x00300000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK 0x00C00000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK 0x03000000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK 0x0C000000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK 0x30000000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK 0xC0000000L +//BIFC_THT_CNTL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x001F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x1F000000L +//BIFC_PERF_CNTL_1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L +//BIFC_PERF_CNT_MMIO_RD +#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR +#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_RD +#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_WR +#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb +#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc +#define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L +#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT 0x8 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT 0x9 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT 0xa +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT 0xb +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT 0xc +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT 0xd +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT 0xe +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT 0xf +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK 0x00000100L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK 0x00000200L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK 0x00000400L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK 0x00000800L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK 0x00001000L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK 0x00002000L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK 0x00004000L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK 0x00008000L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT 0x8 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT 0x9 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT 0xa +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT 0xb +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT 0xc +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT 0xd +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT 0xe +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT 0xf +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK 0x00000100L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK 0x00000200L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK 0x00000400L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK 0x00000800L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK 0x00001000L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK 0x00002000L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK 0x00004000L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK 0x00008000L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT 0x11 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK 0x00020000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT 0x8 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT 0x9 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT 0xa +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT 0xb +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT 0xc +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT 0xd +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT 0xe +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT 0xf +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK 0x00000100L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK 0x00000200L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK 0x00000400L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK 0x00000800L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK 0x00001000L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK 0x00002000L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK 0x00004000L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK 0x00008000L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK 0x0000FF00L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L +//BIF_GMI_CPLBUF_WR_CTRL +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV__SHIFT 0x0 +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV__SHIFT 0x4 +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV__SHIFT 0x8 +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV__SHIFT 0xc +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV_MASK 0x0000000FL +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV_MASK 0x000000F0L +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV_MASK 0x00000F00L +#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV_MASK 0x0000F000L +//BIF_GMI_CPLBUF_RD_CTRL +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV__SHIFT 0x0 +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV__SHIFT 0x4 +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV__SHIFT 0x8 +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV__SHIFT 0xc +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV_MASK 0x0000000FL +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV_MASK 0x000000F0L +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV_MASK 0x00000F00L +#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV_MASK 0x0000F000L + + +// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC +//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_psp_RCCPFCDEC +//RCC_PFC_PSP_RCC_PFC_LTR_CNTL +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_PSP_RCC_PFC_PME_RESTORE +#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_usb3_0_RCCPFCDEC +//RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE +#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_usb3_1_RCCPFCDEC +//RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE +#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_acp_RCCPFCDEC +//RCC_PFC_ACP_RCC_PFC_LTR_CNTL +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_ACP_RCC_PFC_PME_RESTORE +#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_az_RCCPFCDEC +//RCC_PFC_AZ_RCC_PFC_LTR_CNTL +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AZ_RCC_PFC_PME_RESTORE +#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_mp2_RCCPFCDEC +//RCC_PFC_MP2_RCC_PFC_LTR_CNTL +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_MP2_RCC_PFC_PME_RESTORE +#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_sata_RCCPFCDEC +//RCC_PFC_SATA_RCC_PFC_LTR_CNTL +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_SATA_RCC_PFC_PME_RESTORE +#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_gbe0_RCCPFCDEC +//RCC_PFC_GBE0_RCC_PFC_LTR_CNTL +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_GBE0_RCC_PFC_PME_RESTORE +#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_rcc_pfc_gbe1_RCCPFCDEC +//RCC_PFC_GBE1_RCC_PFC_LTR_CNTL +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_GBE1_RCC_PFC_PME_RESTORE +#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//RSMU_SOFT_RST_CTRL +#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L +#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT 0x8 +#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT 0x9 +#define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT 0xa +#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT 0xb +#define SELF_SOFT_RST__EP1_CFG_RST__SHIFT 0xc +#define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT 0xd +#define SELF_SOFT_RST__EP1_PRV_RST__SHIFT 0xe +#define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT 0xf +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__DSPT1_CFG_RST_MASK 0x00000100L +#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK 0x00000200L +#define SELF_SOFT_RST__DSPT1_PRV_RST_MASK 0x00000400L +#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK 0x00000800L +#define SELF_SOFT_RST__EP1_CFG_RST_MASK 0x00001000L +#define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK 0x00002000L +#define SELF_SOFT_RST__EP1_PRV_RST_MASK 0x00004000L +#define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK 0x00008000L +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT 0x13 +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK 0x00080000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF2_FLR_RST_CTRL +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF3_FLR_RST_CTRL +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF4_FLR_RST_CTRL +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF5_FLR_RST_CTRL +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF6_FLR_RST_CTRL +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV0_PF7_FLR_RST_CTRL +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT 0x8 +#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x9 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK 0x00000100L +#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000200L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 +#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 +#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 +#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 +#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 +#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 +#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT 0x8 +#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT 0x9 +#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT 0xa +#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT 0xb +#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT 0xc +#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT 0xd +#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT 0xe +#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT 0xf +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L +#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L +#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L +#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L +#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L +#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L +#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK 0x00000100L +#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK 0x00000200L +#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK 0x00000400L +#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK 0x00000800L +#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK 0x00001000L +#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK 0x00002000L +#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK 0x00004000L +#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK 0x00008000L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 +#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT 0x8 +#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT 0x9 +#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT 0xa +#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT 0xb +#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT 0xc +#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT 0xd +#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT 0xe +#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT 0xf +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK 0x00000100L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK 0x00000200L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK 0x00000400L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK 0x00000800L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK 0x00001000L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK 0x00002000L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK 0x00004000L +#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK 0x00008000L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT 0x1 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT 0x11 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK 0x00000002L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK 0x00020000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT 0x8 +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT 0x9 +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT 0xa +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT 0xb +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT 0xc +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT 0xd +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT 0xe +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT 0xf +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK 0x00000100L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK 0x00000200L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK 0x00000400L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK 0x00000800L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK 0x00001000L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK 0x00002000L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK 0x00004000L +#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK 0x00008000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT 0x8 +#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x9 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK 0x00000100L +#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000200L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 +#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT 0x8 +#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT 0x9 +#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT 0xa +#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT 0xb +#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT 0xc +#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT 0xd +#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT 0xe +#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT 0xf +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK 0x00000100L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK 0x00000200L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK 0x00000400L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK 0x00000800L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK 0x00001000L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK 0x00002000L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK 0x00004000L +#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK 0x00008000L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT 0x8 +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT 0x9 +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT 0xa +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT 0xb +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT 0xc +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT 0xd +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT 0xe +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT 0xf +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK 0x00000100L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK 0x00000200L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK 0x00000400L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK 0x00000800L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK 0x00001000L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK 0x00002000L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK 0x00004000L +#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK 0x00008000L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT 0x1 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT 0x11 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK 0x00000002L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK 0x00020000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT 0x8 +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT 0x9 +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT 0xa +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT 0xb +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT 0xc +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT 0xd +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT 0xe +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT 0xf +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK 0x00000100L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK 0x00000200L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK 0x00000400L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK 0x00000800L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK 0x00001000L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK 0x00002000L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK 0x00004000L +#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK 0x00008000L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 +#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 +#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 +#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 +#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 +#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 +#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8 +#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9 +#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa +#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb +#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc +#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd +#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe +#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L +#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L +#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L +#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L +#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L +#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L +#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L +#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L +#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L +#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L +#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L +#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L +#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L +#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF2_DSTATE_VALUE +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF3_DSTATE_VALUE +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF4_DSTATE_VALUE +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF5_DSTATE_VALUE +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF6_DSTATE_VALUE +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF7_DSTATE_VALUE +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF2_D3HOTD0_RST_CTRL +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF3_D3HOTD0_RST_CTRL +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF4_D3HOTD0_RST_CTRL +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF5_D3HOTD0_RST_CTRL +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF6_D3HOTD0_RST_CTRL +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF7_D3HOTD0_RST_CTRL +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF0_FLR_RST_CTRL +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF1_FLR_RST_CTRL +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF2_FLR_RST_CTRL +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF3_FLR_RST_CTRL +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF4_FLR_RST_CTRL +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF5_FLR_RST_CTRL +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF6_FLR_RST_CTRL +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//DEV1_PF7_FLR_RST_CTRL +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_DEV1_PF0_DSTATE_VALUE +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF1_DSTATE_VALUE +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF2_DSTATE_VALUE +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF3_DSTATE_VALUE +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF4_DSTATE_VALUE +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF5_DSTATE_VALUE +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF6_DSTATE_VALUE +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV1_PF7_DSTATE_VALUE +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L +//DEV1_PF0_D3HOTD0_RST_CTRL +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF1_D3HOTD0_RST_CTRL +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF2_D3HOTD0_RST_CTRL +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF3_D3HOTD0_RST_CTRL +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF4_D3HOTD0_RST_CTRL +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF5_D3HOTD0_RST_CTRL +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF6_D3HOTD0_RST_CTRL +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV1_PF7_D3HOTD0_RST_CTRL +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_PORT1_DSTATE_VALUE +#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK 0x00030000L + + +// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk +//BIF_RAS_LEAF0_CTRL +#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 +#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L +#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L +//BIF_RAS_LEAF1_CTRL +#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 +#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L +#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L +//BIF_RAS_LEAF2_CTRL +#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 +#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 +#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 +#define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7 +#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 +#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 +#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 +#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 +#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L +#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L +#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L +#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L +#define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L +#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L +#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L +#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L +#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L +#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L +#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L +//BIF_RAS_MISC_CTRL +#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 +#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK 0x00000001L +//BIF_IOHUB_RAS_IH_CNTL +#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 +#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK 0x00000001L +//BIF_RAS_VWR_FROM_IOHUB +#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 +#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_COMMAND +#define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_2_STATUS +#define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_LATENCY +#define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_HEADER +#define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_2_BIST +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_PMI_CAP +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF0_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF0_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_COMMAND +#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_1_STATUS +#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_LATENCY +#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_HEADER +#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_1_BIST +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF1_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_COMMAND +#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_1_STATUS +#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_REVISION_ID +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_LATENCY +#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_HEADER +#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_1_BIST +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_CAP_PTR +#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PMI_CAP +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_SBRN +#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_FLADJ +#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_1_LINK_CAP +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF2_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MASK +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_COMMAND +#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_1_STATUS +#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_REVISION_ID +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_LATENCY +#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_HEADER +#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_1_BIST +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_CAP_PTR +#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PMI_CAP +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_SBRN +#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_FLADJ +#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_1_LINK_CAP +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF3_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MASK +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +//BIF_CFG_DEV0_EPF4_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_1_COMMAND +#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF4_1_STATUS +#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_1_REVISION_ID +#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_LATENCY +#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_HEADER +#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF4_1_BIST +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_CAP_PTR +#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_PMI_CAP +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_1_SBRN +#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_FLADJ +#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_1_LINK_CAP +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF4_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF4_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF4_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_MASK +#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +//BIF_CFG_DEV0_EPF5_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_1_COMMAND +#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF5_1_STATUS +#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_1_REVISION_ID +#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_LATENCY +#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_HEADER +#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF5_1_BIST +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_CAP_PTR +#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_PMI_CAP +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_1_SBRN +#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_FLADJ +#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_1_LINK_CAP +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF5_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF5_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF5_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_MASK +#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +//BIF_CFG_DEV0_EPF6_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_1_COMMAND +#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF6_1_STATUS +#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_1_REVISION_ID +#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_LATENCY +#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_HEADER +#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF6_1_BIST +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_CAP_PTR +#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_PMI_CAP +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_1_SBRN +#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_FLADJ +#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_1_LINK_CAP +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF6_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF6_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF6_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_MASK +#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +//BIF_CFG_DEV0_EPF7_1_VENDOR_ID +#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_1_DEVICE_ID +#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_1_COMMAND +#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF7_1_STATUS +#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_1_REVISION_ID +#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_SUB_CLASS +#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_BASE_CLASS +#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_CACHE_LINE +#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_LATENCY +#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_HEADER +#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF7_1_BIST +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_CAP_PTR +#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_MIN_GRANT +#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_PMI_CAP +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_1_SBRN +#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_FLADJ +#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_PCIE_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_1_LINK_CAP +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_1_LINK_CNTL +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF7_1_LINK_STATUS +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF7_1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF7_1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_1_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_MASK +#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_PENDING +#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_1_MSIX_PBA +#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_1_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_1_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +//BIF_CFG_DEV1_EPF0_1_VENDOR_ID +#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_1_DEVICE_ID +#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_1_COMMAND +#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF0_1_STATUS +#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_REVISION_ID +#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_SUB_CLASS +#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_BASE_CLASS +#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_CACHE_LINE +#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_LATENCY +#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_HEADER +#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF0_1_BIST +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_CAP_PTR +#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_MIN_GRANT +#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_MAX_LATENCY +#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_PMI_CAP +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_PCIE_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_1_LINK_CAP +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_LINK_CNTL +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF0_1_LINK_STATUS +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_1_LINK_CAP2 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF0_1_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF0_1_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_1_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_MASK +#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_PENDING +#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_MSIX_TABLE +#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_1_MSIX_PBA +#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_1_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +//BIF_CFG_DEV1_EPF1_1_VENDOR_ID +#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_1_DEVICE_ID +#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_1_COMMAND +#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF1_1_STATUS +#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_1_REVISION_ID +#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_SUB_CLASS +#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_BASE_CLASS +#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_CACHE_LINE +#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_LATENCY +#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_HEADER +#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF1_1_BIST +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_CAP_PTR +#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_MIN_GRANT +#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_MAX_LATENCY +#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_PMI_CAP +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_1_SBRN +#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_FLADJ +#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_PCIE_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_1_LINK_CAP +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_1_LINK_CNTL +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF1_1_LINK_STATUS +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_1_LINK_CAP2 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF1_1_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF1_1_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_1_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_MASK +#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_PENDING +#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_1_MSIX_TABLE +#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_1_MSIX_PBA +#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_1_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_1_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +//BIF_CFG_DEV1_EPF2_1_VENDOR_ID +#define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_1_DEVICE_ID +#define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_1_COMMAND +#define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF2_1_STATUS +#define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_1_REVISION_ID +#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_SUB_CLASS +#define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_BASE_CLASS +#define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_CACHE_LINE +#define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_LATENCY +#define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_HEADER +#define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF2_1_BIST +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_ADAPTER_ID +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_CAP_PTR +#define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_MIN_GRANT +#define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_MAX_LATENCY +#define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_PMI_CAP +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_1_SBRN +#define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_FLADJ +#define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_PCIE_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF2_1_DEVICE_CAP +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_1_LINK_CAP +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_1_LINK_CNTL +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF2_1_LINK_STATUS +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_1_LINK_CAP2 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF2_1_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF2_1_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_1_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_MASK +#define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_PENDING +#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_1_MSIX_TABLE +#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_1_MSIX_PBA +#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_1_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_1_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXTDEC +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_psp_MSIXTDEC +//PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXTDEC +//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXTDEC +//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXTDEC +//PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXTDEC +//PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXTDEC +//PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXPDEC +//PCIEMSIX_AMDGFX_PCIEMSIX_PBA +#define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_psp_MSIXPDEC +//PCIEMSIX_PSP_PCIEMSIX_PBA +#define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXPDEC +//PCIEMSIX_USB3_0_PCIEMSIX_PBA +#define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXPDEC +//PCIEMSIX_USB3_1_PCIEMSIX_PBA +#define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXPDEC +//PCIEMSIX_MP2_PCIEMSIX_PBA +#define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXPDEC +//PCIEMSIX_GBE0_PCIEMSIX_PBA +#define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXPDEC +//PCIEMSIX_GBE1_PCIEMSIX_PBA +#define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +//BIFPLR0_1_VENDOR_ID +#define BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR0_1_DEVICE_ID +#define BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR0_1_COMMAND +#define BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR0_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR0_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR0_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR0_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR0_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR0_1_STATUS +#define BIFPLR0_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR0_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR0_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_1_REVISION_ID +#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR0_1_PROG_INTERFACE +#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR0_1_SUB_CLASS +#define BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR0_1_BASE_CLASS +#define BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR0_1_CACHE_LINE +#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR0_1_LATENCY +#define BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR0_1_HEADER +#define BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR0_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR0_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR0_1_BIST +#define BIFPLR0_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR0_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR0_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR0_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR0_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR0_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR0_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR0_1_IO_BASE_LIMIT +#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR0_1_SECONDARY_STATUS +#define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_1_MEM_BASE_LIMIT +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_1_PREF_BASE_LIMIT +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_1_PREF_BASE_UPPER +#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_1_PREF_LIMIT_UPPER +#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_1_IO_BASE_LIMIT_HI +#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR0_1_CAP_PTR +#define BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR0_1_INTERRUPT_LINE +#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR0_1_INTERRUPT_PIN +#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR0_1_IRQ_BRIDGE_CNTL +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR0_1_EXT_BRIDGE_CNTL +#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR0_1_PMI_CAP_LIST +#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_1_PMI_CAP +#define BIFPLR0_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR0_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR0_1_PMI_STATUS_CNTL +#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR0_1_PCIE_CAP_LIST +#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_1_PCIE_CAP +#define BIFPLR0_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR0_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR0_1_DEVICE_CAP +#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR0_1_DEVICE_CNTL +#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR0_1_DEVICE_STATUS +#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR0_1_LINK_CAP +#define BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR0_1_LINK_CNTL +#define BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR0_1_LINK_STATUS +#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR0_1_SLOT_CAP +#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR0_1_SLOT_CNTL +#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR0_1_SLOT_STATUS +#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR0_1_ROOT_CNTL +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR0_1_ROOT_CAP +#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR0_1_ROOT_STATUS +#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR0_1_DEVICE_CAP2 +#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR0_1_DEVICE_CNTL2 +#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR0_1_DEVICE_STATUS2 +#define BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_1_LINK_CAP2 +#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR0_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR0_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR0_1_LINK_CNTL2 +#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR0_1_LINK_STATUS2 +#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR0_1_SLOT_CAP2 +#define BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR0_1_SLOT_CNTL2 +#define BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR0_1_SLOT_STATUS2 +#define BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_1_MSI_CAP_LIST +#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_1_MSI_MSG_CNTL +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR0_1_MSI_MSG_ADDR_LO +#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR0_1_MSI_MSG_ADDR_HI +#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_1_MSI_MSG_DATA +#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR0_1_MSI_MSG_DATA_64 +#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR0_1_SSID_CAP_LIST +#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_1_SSID_CAP +#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR0_1_MSI_MAP_CAP_LIST +#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_1_MSI_MAP_CAP +#define BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR0_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR0_1_MSI_MAP_ADDR_LO +#define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR0_1_MSI_MAP_ADDR_HI +#define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR0_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_1_PCIE_PORT_VC_CNTL +#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR0_1_PCIE_PORT_VC_STATUS +#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR0_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR0_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR0_1_PCIE_CORR_ERR_STATUS +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR0_1_PCIE_CORR_ERR_MASK +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR0_1_PCIE_HDR_LOG0 +#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_HDR_LOG1 +#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_HDR_LOG2 +#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_HDR_LOG3 +#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_ROOT_ERR_CMD +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR0_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR0_1_PCIE_ERR_SRC_ID +#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR0_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_LINK_CNTL3 +#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_ACS_CAP +#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR0_1_PCIE_ACS_CNTL +#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR0_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_MC_CAP +#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR0_1_PCIE_MC_CNTL +#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR0_1_PCIE_MC_ADDR0 +#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR0_1_PCIE_MC_ADDR1 +#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_RCV0 +#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_RCV1 +#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR0_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_DPC_CAP_LIST +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR0_1_PCIE_DPC_CNTL +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR0_1_PCIE_DPC_STATUS +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR0_1_PCIE_RP_PIO_STATUS +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR0_1_PCIE_RP_PIO_MASK +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR0_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR0_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR0_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_1_PCIE_ESM_CAP_LIST +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_ESM_HEADER_1 +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR0_1_PCIE_ESM_HEADER_2 +#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR0_1_PCIE_ESM_STATUS +#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR0_1_PCIE_ESM_CTRL +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR0_1_PCIE_ESM_CAP_1 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR0_1_PCIE_ESM_CAP_2 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR0_1_PCIE_ESM_CAP_3 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR0_1_PCIE_ESM_CAP_4 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR0_1_PCIE_ESM_CAP_5 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR0_1_PCIE_ESM_CAP_6 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR0_1_PCIE_ESM_CAP_7 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +//BIFPLR1_1_VENDOR_ID +#define BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR1_1_DEVICE_ID +#define BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR1_1_COMMAND +#define BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR1_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR1_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR1_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR1_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR1_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR1_1_STATUS +#define BIFPLR1_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR1_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR1_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_1_REVISION_ID +#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR1_1_PROG_INTERFACE +#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR1_1_SUB_CLASS +#define BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR1_1_BASE_CLASS +#define BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR1_1_CACHE_LINE +#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR1_1_LATENCY +#define BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR1_1_HEADER +#define BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR1_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR1_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR1_1_BIST +#define BIFPLR1_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR1_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR1_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR1_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR1_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR1_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR1_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR1_1_IO_BASE_LIMIT +#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR1_1_SECONDARY_STATUS +#define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_1_MEM_BASE_LIMIT +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_1_PREF_BASE_LIMIT +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_1_PREF_BASE_UPPER +#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_1_PREF_LIMIT_UPPER +#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_1_IO_BASE_LIMIT_HI +#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR1_1_CAP_PTR +#define BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR1_1_INTERRUPT_LINE +#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR1_1_INTERRUPT_PIN +#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR1_1_IRQ_BRIDGE_CNTL +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR1_1_EXT_BRIDGE_CNTL +#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR1_1_PMI_CAP_LIST +#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_1_PMI_CAP +#define BIFPLR1_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR1_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR1_1_PMI_STATUS_CNTL +#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR1_1_PCIE_CAP_LIST +#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_1_PCIE_CAP +#define BIFPLR1_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR1_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR1_1_DEVICE_CAP +#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR1_1_DEVICE_CNTL +#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR1_1_DEVICE_STATUS +#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR1_1_LINK_CAP +#define BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR1_1_LINK_CNTL +#define BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR1_1_LINK_STATUS +#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR1_1_SLOT_CAP +#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR1_1_SLOT_CNTL +#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR1_1_SLOT_STATUS +#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR1_1_ROOT_CNTL +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR1_1_ROOT_CAP +#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR1_1_ROOT_STATUS +#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR1_1_DEVICE_CAP2 +#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR1_1_DEVICE_CNTL2 +#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR1_1_DEVICE_STATUS2 +#define BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_1_LINK_CAP2 +#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR1_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR1_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR1_1_LINK_CNTL2 +#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR1_1_LINK_STATUS2 +#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR1_1_SLOT_CAP2 +#define BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR1_1_SLOT_CNTL2 +#define BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR1_1_SLOT_STATUS2 +#define BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_1_MSI_CAP_LIST +#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_1_MSI_MSG_CNTL +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR1_1_MSI_MSG_ADDR_LO +#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR1_1_MSI_MSG_ADDR_HI +#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_1_MSI_MSG_DATA +#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR1_1_MSI_MSG_DATA_64 +#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR1_1_SSID_CAP_LIST +#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_1_SSID_CAP +#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR1_1_MSI_MAP_CAP_LIST +#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_1_MSI_MAP_CAP +#define BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR1_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR1_1_MSI_MAP_ADDR_LO +#define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR1_1_MSI_MAP_ADDR_HI +#define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR1_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_1_PCIE_PORT_VC_CNTL +#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR1_1_PCIE_PORT_VC_STATUS +#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR1_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR1_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR1_1_PCIE_CORR_ERR_STATUS +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR1_1_PCIE_CORR_ERR_MASK +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR1_1_PCIE_HDR_LOG0 +#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_HDR_LOG1 +#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_HDR_LOG2 +#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_HDR_LOG3 +#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_ROOT_ERR_CMD +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR1_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR1_1_PCIE_ERR_SRC_ID +#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR1_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_LINK_CNTL3 +#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_ACS_CAP +#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR1_1_PCIE_ACS_CNTL +#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR1_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_MC_CAP +#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR1_1_PCIE_MC_CNTL +#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR1_1_PCIE_MC_ADDR0 +#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR1_1_PCIE_MC_ADDR1 +#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_RCV0 +#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_RCV1 +#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR1_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_DPC_CAP_LIST +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR1_1_PCIE_DPC_CNTL +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR1_1_PCIE_DPC_STATUS +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR1_1_PCIE_RP_PIO_STATUS +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR1_1_PCIE_RP_PIO_MASK +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR1_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR1_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR1_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_1_PCIE_ESM_CAP_LIST +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_ESM_HEADER_1 +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR1_1_PCIE_ESM_HEADER_2 +#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR1_1_PCIE_ESM_STATUS +#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR1_1_PCIE_ESM_CTRL +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR1_1_PCIE_ESM_CAP_1 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR1_1_PCIE_ESM_CAP_2 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR1_1_PCIE_ESM_CAP_3 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR1_1_PCIE_ESM_CAP_4 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR1_1_PCIE_ESM_CAP_5 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR1_1_PCIE_ESM_CAP_6 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR1_1_PCIE_ESM_CAP_7 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +//BIFPLR2_1_VENDOR_ID +#define BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR2_1_DEVICE_ID +#define BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR2_1_COMMAND +#define BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR2_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR2_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR2_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR2_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR2_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR2_1_STATUS +#define BIFPLR2_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR2_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR2_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_1_REVISION_ID +#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR2_1_PROG_INTERFACE +#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR2_1_SUB_CLASS +#define BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR2_1_BASE_CLASS +#define BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR2_1_CACHE_LINE +#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR2_1_LATENCY +#define BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR2_1_HEADER +#define BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR2_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR2_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR2_1_BIST +#define BIFPLR2_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR2_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR2_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR2_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR2_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR2_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR2_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR2_1_IO_BASE_LIMIT +#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR2_1_SECONDARY_STATUS +#define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_1_MEM_BASE_LIMIT +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_1_PREF_BASE_LIMIT +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_1_PREF_BASE_UPPER +#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_1_PREF_LIMIT_UPPER +#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_1_IO_BASE_LIMIT_HI +#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR2_1_CAP_PTR +#define BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR2_1_INTERRUPT_LINE +#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR2_1_INTERRUPT_PIN +#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR2_1_IRQ_BRIDGE_CNTL +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR2_1_EXT_BRIDGE_CNTL +#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR2_1_PMI_CAP_LIST +#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_1_PMI_CAP +#define BIFPLR2_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR2_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR2_1_PMI_STATUS_CNTL +#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR2_1_PCIE_CAP_LIST +#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_1_PCIE_CAP +#define BIFPLR2_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR2_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR2_1_DEVICE_CAP +#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR2_1_DEVICE_CNTL +#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR2_1_DEVICE_STATUS +#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR2_1_LINK_CAP +#define BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR2_1_LINK_CNTL +#define BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR2_1_LINK_STATUS +#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR2_1_SLOT_CAP +#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR2_1_SLOT_CNTL +#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR2_1_SLOT_STATUS +#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR2_1_ROOT_CNTL +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR2_1_ROOT_CAP +#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR2_1_ROOT_STATUS +#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR2_1_DEVICE_CAP2 +#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR2_1_DEVICE_CNTL2 +#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR2_1_DEVICE_STATUS2 +#define BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_1_LINK_CAP2 +#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR2_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR2_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR2_1_LINK_CNTL2 +#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR2_1_LINK_STATUS2 +#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR2_1_SLOT_CAP2 +#define BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR2_1_SLOT_CNTL2 +#define BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR2_1_SLOT_STATUS2 +#define BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_1_MSI_CAP_LIST +#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_1_MSI_MSG_CNTL +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR2_1_MSI_MSG_ADDR_LO +#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR2_1_MSI_MSG_ADDR_HI +#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_1_MSI_MSG_DATA +#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR2_1_MSI_MSG_DATA_64 +#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR2_1_SSID_CAP_LIST +#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_1_SSID_CAP +#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR2_1_MSI_MAP_CAP_LIST +#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_1_MSI_MAP_CAP +#define BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR2_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR2_1_MSI_MAP_ADDR_LO +#define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR2_1_MSI_MAP_ADDR_HI +#define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR2_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_1_PCIE_PORT_VC_CNTL +#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR2_1_PCIE_PORT_VC_STATUS +#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR2_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR2_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR2_1_PCIE_CORR_ERR_STATUS +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR2_1_PCIE_CORR_ERR_MASK +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR2_1_PCIE_HDR_LOG0 +#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_HDR_LOG1 +#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_HDR_LOG2 +#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_HDR_LOG3 +#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_ROOT_ERR_CMD +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR2_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR2_1_PCIE_ERR_SRC_ID +#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR2_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_LINK_CNTL3 +#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_ACS_CAP +#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR2_1_PCIE_ACS_CNTL +#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR2_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_MC_CAP +#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR2_1_PCIE_MC_CNTL +#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR2_1_PCIE_MC_ADDR0 +#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR2_1_PCIE_MC_ADDR1 +#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_RCV0 +#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_RCV1 +#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR2_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_DPC_CAP_LIST +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR2_1_PCIE_DPC_CNTL +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR2_1_PCIE_DPC_STATUS +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR2_1_PCIE_RP_PIO_STATUS +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR2_1_PCIE_RP_PIO_MASK +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR2_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR2_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR2_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_1_PCIE_ESM_CAP_LIST +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_ESM_HEADER_1 +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR2_1_PCIE_ESM_HEADER_2 +#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR2_1_PCIE_ESM_STATUS +#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR2_1_PCIE_ESM_CTRL +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR2_1_PCIE_ESM_CAP_1 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR2_1_PCIE_ESM_CAP_2 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR2_1_PCIE_ESM_CAP_3 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR2_1_PCIE_ESM_CAP_4 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR2_1_PCIE_ESM_CAP_5 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR2_1_PCIE_ESM_CAP_6 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR2_1_PCIE_ESM_CAP_7 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +//BIFPLR3_1_VENDOR_ID +#define BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR3_1_DEVICE_ID +#define BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR3_1_COMMAND +#define BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR3_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR3_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR3_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR3_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR3_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR3_1_STATUS +#define BIFPLR3_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR3_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR3_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_1_REVISION_ID +#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR3_1_PROG_INTERFACE +#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR3_1_SUB_CLASS +#define BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR3_1_BASE_CLASS +#define BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR3_1_CACHE_LINE +#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR3_1_LATENCY +#define BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR3_1_HEADER +#define BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR3_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR3_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR3_1_BIST +#define BIFPLR3_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR3_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR3_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR3_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR3_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR3_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR3_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR3_1_IO_BASE_LIMIT +#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR3_1_SECONDARY_STATUS +#define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_1_MEM_BASE_LIMIT +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_1_PREF_BASE_LIMIT +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_1_PREF_BASE_UPPER +#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_1_PREF_LIMIT_UPPER +#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_1_IO_BASE_LIMIT_HI +#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR3_1_CAP_PTR +#define BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR3_1_INTERRUPT_LINE +#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR3_1_INTERRUPT_PIN +#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR3_1_IRQ_BRIDGE_CNTL +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR3_1_EXT_BRIDGE_CNTL +#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR3_1_PMI_CAP_LIST +#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_1_PMI_CAP +#define BIFPLR3_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR3_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR3_1_PMI_STATUS_CNTL +#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR3_1_PCIE_CAP_LIST +#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_1_PCIE_CAP +#define BIFPLR3_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR3_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR3_1_DEVICE_CAP +#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR3_1_DEVICE_CNTL +#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR3_1_DEVICE_STATUS +#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR3_1_LINK_CAP +#define BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR3_1_LINK_CNTL +#define BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR3_1_LINK_STATUS +#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR3_1_SLOT_CAP +#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR3_1_SLOT_CNTL +#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR3_1_SLOT_STATUS +#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR3_1_ROOT_CNTL +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR3_1_ROOT_CAP +#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR3_1_ROOT_STATUS +#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR3_1_DEVICE_CAP2 +#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR3_1_DEVICE_CNTL2 +#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR3_1_DEVICE_STATUS2 +#define BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_1_LINK_CAP2 +#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR3_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR3_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR3_1_LINK_CNTL2 +#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR3_1_LINK_STATUS2 +#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR3_1_SLOT_CAP2 +#define BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR3_1_SLOT_CNTL2 +#define BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR3_1_SLOT_STATUS2 +#define BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_1_MSI_CAP_LIST +#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_1_MSI_MSG_CNTL +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR3_1_MSI_MSG_ADDR_LO +#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR3_1_MSI_MSG_ADDR_HI +#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_1_MSI_MSG_DATA +#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR3_1_MSI_MSG_DATA_64 +#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR3_1_SSID_CAP_LIST +#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_1_SSID_CAP +#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR3_1_MSI_MAP_CAP_LIST +#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_1_MSI_MAP_CAP +#define BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR3_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR3_1_MSI_MAP_ADDR_LO +#define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR3_1_MSI_MAP_ADDR_HI +#define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR3_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_1_PCIE_PORT_VC_CNTL +#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR3_1_PCIE_PORT_VC_STATUS +#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR3_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR3_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR3_1_PCIE_CORR_ERR_STATUS +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR3_1_PCIE_CORR_ERR_MASK +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR3_1_PCIE_HDR_LOG0 +#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_HDR_LOG1 +#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_HDR_LOG2 +#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_HDR_LOG3 +#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_ROOT_ERR_CMD +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR3_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR3_1_PCIE_ERR_SRC_ID +#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR3_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_LINK_CNTL3 +#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_ACS_CAP +#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR3_1_PCIE_ACS_CNTL +#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR3_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_MC_CAP +#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR3_1_PCIE_MC_CNTL +#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR3_1_PCIE_MC_ADDR0 +#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR3_1_PCIE_MC_ADDR1 +#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_RCV0 +#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_RCV1 +#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR3_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_DPC_CAP_LIST +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR3_1_PCIE_DPC_CNTL +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR3_1_PCIE_DPC_STATUS +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR3_1_PCIE_RP_PIO_STATUS +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR3_1_PCIE_RP_PIO_MASK +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR3_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR3_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR3_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_1_PCIE_ESM_CAP_LIST +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_ESM_HEADER_1 +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR3_1_PCIE_ESM_HEADER_2 +#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR3_1_PCIE_ESM_STATUS +#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR3_1_PCIE_ESM_CTRL +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR3_1_PCIE_ESM_CAP_1 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR3_1_PCIE_ESM_CAP_2 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR3_1_PCIE_ESM_CAP_3 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR3_1_PCIE_ESM_CAP_4 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR3_1_PCIE_ESM_CAP_5 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR3_1_PCIE_ESM_CAP_6 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR3_1_PCIE_ESM_CAP_7 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +//BIFPLR4_1_VENDOR_ID +#define BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR4_1_DEVICE_ID +#define BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR4_1_COMMAND +#define BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR4_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR4_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR4_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR4_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR4_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR4_1_STATUS +#define BIFPLR4_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR4_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR4_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_1_REVISION_ID +#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR4_1_PROG_INTERFACE +#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR4_1_SUB_CLASS +#define BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR4_1_BASE_CLASS +#define BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR4_1_CACHE_LINE +#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR4_1_LATENCY +#define BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR4_1_HEADER +#define BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR4_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR4_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR4_1_BIST +#define BIFPLR4_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR4_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR4_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR4_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR4_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR4_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR4_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR4_1_IO_BASE_LIMIT +#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR4_1_SECONDARY_STATUS +#define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_1_MEM_BASE_LIMIT +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_1_PREF_BASE_LIMIT +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_1_PREF_BASE_UPPER +#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_1_PREF_LIMIT_UPPER +#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_1_IO_BASE_LIMIT_HI +#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR4_1_CAP_PTR +#define BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR4_1_INTERRUPT_LINE +#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR4_1_INTERRUPT_PIN +#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR4_1_IRQ_BRIDGE_CNTL +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR4_1_EXT_BRIDGE_CNTL +#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR4_1_PMI_CAP_LIST +#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_1_PMI_CAP +#define BIFPLR4_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR4_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR4_1_PMI_STATUS_CNTL +#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR4_1_PCIE_CAP_LIST +#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_1_PCIE_CAP +#define BIFPLR4_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR4_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR4_1_DEVICE_CAP +#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR4_1_DEVICE_CNTL +#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR4_1_DEVICE_STATUS +#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR4_1_LINK_CAP +#define BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR4_1_LINK_CNTL +#define BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR4_1_LINK_STATUS +#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR4_1_SLOT_CAP +#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR4_1_SLOT_CNTL +#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR4_1_SLOT_STATUS +#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR4_1_ROOT_CNTL +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR4_1_ROOT_CAP +#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR4_1_ROOT_STATUS +#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR4_1_DEVICE_CAP2 +#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR4_1_DEVICE_CNTL2 +#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR4_1_DEVICE_STATUS2 +#define BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_1_LINK_CAP2 +#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR4_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR4_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR4_1_LINK_CNTL2 +#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR4_1_LINK_STATUS2 +#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR4_1_SLOT_CAP2 +#define BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR4_1_SLOT_CNTL2 +#define BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR4_1_SLOT_STATUS2 +#define BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_1_MSI_CAP_LIST +#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_1_MSI_MSG_CNTL +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR4_1_MSI_MSG_ADDR_LO +#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR4_1_MSI_MSG_ADDR_HI +#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_1_MSI_MSG_DATA +#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR4_1_MSI_MSG_DATA_64 +#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR4_1_SSID_CAP_LIST +#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_1_SSID_CAP +#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR4_1_MSI_MAP_CAP_LIST +#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_1_MSI_MAP_CAP +#define BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR4_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR4_1_MSI_MAP_ADDR_LO +#define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR4_1_MSI_MAP_ADDR_HI +#define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR4_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_1_PCIE_PORT_VC_CNTL +#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR4_1_PCIE_PORT_VC_STATUS +#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR4_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR4_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR4_1_PCIE_CORR_ERR_STATUS +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR4_1_PCIE_CORR_ERR_MASK +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR4_1_PCIE_HDR_LOG0 +#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_HDR_LOG1 +#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_HDR_LOG2 +#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_HDR_LOG3 +#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_ROOT_ERR_CMD +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR4_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR4_1_PCIE_ERR_SRC_ID +#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR4_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_LINK_CNTL3 +#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_ACS_CAP +#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR4_1_PCIE_ACS_CNTL +#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR4_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_MC_CAP +#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR4_1_PCIE_MC_CNTL +#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR4_1_PCIE_MC_ADDR0 +#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR4_1_PCIE_MC_ADDR1 +#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_RCV0 +#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_RCV1 +#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR4_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_DPC_CAP_LIST +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR4_1_PCIE_DPC_CNTL +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR4_1_PCIE_DPC_STATUS +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR4_1_PCIE_RP_PIO_STATUS +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR4_1_PCIE_RP_PIO_MASK +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR4_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR4_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR4_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_1_PCIE_ESM_CAP_LIST +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_ESM_HEADER_1 +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR4_1_PCIE_ESM_HEADER_2 +#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR4_1_PCIE_ESM_STATUS +#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR4_1_PCIE_ESM_CTRL +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR4_1_PCIE_ESM_CAP_1 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR4_1_PCIE_ESM_CAP_2 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR4_1_PCIE_ESM_CAP_3 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR4_1_PCIE_ESM_CAP_4 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR4_1_PCIE_ESM_CAP_5 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR4_1_PCIE_ESM_CAP_6 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR4_1_PCIE_ESM_CAP_7 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +//BIFPLR5_1_VENDOR_ID +#define BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR5_1_DEVICE_ID +#define BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR5_1_COMMAND +#define BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR5_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR5_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR5_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR5_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR5_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR5_1_STATUS +#define BIFPLR5_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR5_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR5_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_1_REVISION_ID +#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR5_1_PROG_INTERFACE +#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR5_1_SUB_CLASS +#define BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR5_1_BASE_CLASS +#define BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR5_1_CACHE_LINE +#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR5_1_LATENCY +#define BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR5_1_HEADER +#define BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR5_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR5_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR5_1_BIST +#define BIFPLR5_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR5_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR5_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR5_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR5_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR5_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR5_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR5_1_IO_BASE_LIMIT +#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR5_1_SECONDARY_STATUS +#define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_1_MEM_BASE_LIMIT +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_1_PREF_BASE_LIMIT +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_1_PREF_BASE_UPPER +#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_1_PREF_LIMIT_UPPER +#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_1_IO_BASE_LIMIT_HI +#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR5_1_CAP_PTR +#define BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR5_1_INTERRUPT_LINE +#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR5_1_INTERRUPT_PIN +#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR5_1_IRQ_BRIDGE_CNTL +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR5_1_EXT_BRIDGE_CNTL +#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR5_1_PMI_CAP_LIST +#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_1_PMI_CAP +#define BIFPLR5_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR5_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR5_1_PMI_STATUS_CNTL +#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR5_1_PCIE_CAP_LIST +#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_1_PCIE_CAP +#define BIFPLR5_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR5_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR5_1_DEVICE_CAP +#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR5_1_DEVICE_CNTL +#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR5_1_DEVICE_STATUS +#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR5_1_LINK_CAP +#define BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR5_1_LINK_CNTL +#define BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR5_1_LINK_STATUS +#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR5_1_SLOT_CAP +#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR5_1_SLOT_CNTL +#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR5_1_SLOT_STATUS +#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR5_1_ROOT_CNTL +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR5_1_ROOT_CAP +#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR5_1_ROOT_STATUS +#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR5_1_DEVICE_CAP2 +#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR5_1_DEVICE_CNTL2 +#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR5_1_DEVICE_STATUS2 +#define BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_1_LINK_CAP2 +#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR5_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR5_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR5_1_LINK_CNTL2 +#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR5_1_LINK_STATUS2 +#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR5_1_SLOT_CAP2 +#define BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR5_1_SLOT_CNTL2 +#define BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR5_1_SLOT_STATUS2 +#define BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_1_MSI_CAP_LIST +#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_1_MSI_MSG_CNTL +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR5_1_MSI_MSG_ADDR_LO +#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR5_1_MSI_MSG_ADDR_HI +#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_1_MSI_MSG_DATA +#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR5_1_MSI_MSG_DATA_64 +#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR5_1_SSID_CAP_LIST +#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_1_SSID_CAP +#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR5_1_MSI_MAP_CAP_LIST +#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_1_MSI_MAP_CAP +#define BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR5_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR5_1_MSI_MAP_ADDR_LO +#define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR5_1_MSI_MAP_ADDR_HI +#define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR5_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_1_PCIE_PORT_VC_CNTL +#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR5_1_PCIE_PORT_VC_STATUS +#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR5_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR5_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR5_1_PCIE_CORR_ERR_STATUS +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR5_1_PCIE_CORR_ERR_MASK +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR5_1_PCIE_HDR_LOG0 +#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_HDR_LOG1 +#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_HDR_LOG2 +#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_HDR_LOG3 +#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_ROOT_ERR_CMD +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR5_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR5_1_PCIE_ERR_SRC_ID +#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR5_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_LINK_CNTL3 +#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_ACS_CAP +#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR5_1_PCIE_ACS_CNTL +#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR5_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_MC_CAP +#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR5_1_PCIE_MC_CNTL +#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR5_1_PCIE_MC_ADDR0 +#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR5_1_PCIE_MC_ADDR1 +#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_RCV0 +#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_RCV1 +#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR5_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_DPC_CAP_LIST +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR5_1_PCIE_DPC_CNTL +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR5_1_PCIE_DPC_STATUS +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR5_1_PCIE_RP_PIO_STATUS +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR5_1_PCIE_RP_PIO_MASK +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR5_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR5_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR5_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_1_PCIE_ESM_CAP_LIST +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_ESM_HEADER_1 +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR5_1_PCIE_ESM_HEADER_2 +#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR5_1_PCIE_ESM_STATUS +#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR5_1_PCIE_ESM_CTRL +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR5_1_PCIE_ESM_CAP_1 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR5_1_PCIE_ESM_CAP_2 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR5_1_PCIE_ESM_CAP_3 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR5_1_PCIE_ESM_CAP_4 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR5_1_PCIE_ESM_CAP_5 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR5_1_PCIE_ESM_CAP_6 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR5_1_PCIE_ESM_CAP_7 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +//BIFPLR6_1_VENDOR_ID +#define BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR6_1_DEVICE_ID +#define BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR6_1_COMMAND +#define BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR6_1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR6_1_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR6_1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR6_1_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR6_1_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR6_1_STATUS +#define BIFPLR6_1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR6_1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_1_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_1_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR6_1_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_1_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_1_REVISION_ID +#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR6_1_PROG_INTERFACE +#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR6_1_SUB_CLASS +#define BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR6_1_BASE_CLASS +#define BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR6_1_CACHE_LINE +#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR6_1_LATENCY +#define BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR6_1_HEADER +#define BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR6_1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR6_1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR6_1_BIST +#define BIFPLR6_1_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR6_1_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR6_1_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR6_1_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR6_1_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR6_1_BIST__BIST_CAP_MASK 0x80L +//BIFPLR6_1_SUB_BUS_NUMBER_LATENCY +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR6_1_IO_BASE_LIMIT +#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR6_1_SECONDARY_STATUS +#define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_1_MEM_BASE_LIMIT +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_1_PREF_BASE_LIMIT +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_1_PREF_BASE_UPPER +#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_1_PREF_LIMIT_UPPER +#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_1_IO_BASE_LIMIT_HI +#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR6_1_CAP_PTR +#define BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR6_1_INTERRUPT_LINE +#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR6_1_INTERRUPT_PIN +#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR6_1_IRQ_BRIDGE_CNTL +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR6_1_EXT_BRIDGE_CNTL +#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR6_1_PMI_CAP_LIST +#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_1_PMI_CAP +#define BIFPLR6_1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR6_1_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR6_1_PMI_STATUS_CNTL +#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR6_1_PCIE_CAP_LIST +#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_1_PCIE_CAP +#define BIFPLR6_1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR6_1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR6_1_DEVICE_CAP +#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR6_1_DEVICE_CNTL +#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR6_1_DEVICE_STATUS +#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR6_1_LINK_CAP +#define BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR6_1_LINK_CNTL +#define BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR6_1_LINK_STATUS +#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR6_1_SLOT_CAP +#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR6_1_SLOT_CNTL +#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR6_1_SLOT_STATUS +#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR6_1_ROOT_CNTL +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR6_1_ROOT_CAP +#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR6_1_ROOT_STATUS +#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR6_1_DEVICE_CAP2 +#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR6_1_DEVICE_CNTL2 +#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR6_1_DEVICE_STATUS2 +#define BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_1_LINK_CAP2 +#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR6_1_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR6_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR6_1_LINK_CNTL2 +#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR6_1_LINK_STATUS2 +#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR6_1_SLOT_CAP2 +#define BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR6_1_SLOT_CNTL2 +#define BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR6_1_SLOT_STATUS2 +#define BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_1_MSI_CAP_LIST +#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_1_MSI_MSG_CNTL +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR6_1_MSI_MSG_ADDR_LO +#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR6_1_MSI_MSG_ADDR_HI +#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_1_MSI_MSG_DATA +#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR6_1_MSI_MSG_DATA_64 +#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR6_1_SSID_CAP_LIST +#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_1_SSID_CAP +#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR6_1_MSI_MAP_CAP_LIST +#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_1_MSI_MAP_CAP +#define BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR6_1_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR6_1_MSI_MAP_ADDR_LO +#define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR6_1_MSI_MAP_ADDR_HI +#define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_VC_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR6_1_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_1_PCIE_PORT_VC_CNTL +#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR6_1_PCIE_PORT_VC_STATUS +#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR6_1_PCIE_VC0_RESOURCE_CAP +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_1_PCIE_VC1_RESOURCE_CAP +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_UNCORR_ERR_STATUS +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR6_1_PCIE_UNCORR_ERR_MASK +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR6_1_PCIE_CORR_ERR_STATUS +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR6_1_PCIE_CORR_ERR_MASK +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR6_1_PCIE_HDR_LOG0 +#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_HDR_LOG1 +#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_HDR_LOG2 +#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_HDR_LOG3 +#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_ROOT_ERR_CMD +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR6_1_PCIE_ROOT_ERR_STATUS +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR6_1_PCIE_ERR_SRC_ID +#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR6_1_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_LINK_CNTL3 +#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_1_PCIE_LANE_ERROR_STATUS +#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_ACS_CAP +#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR6_1_PCIE_ACS_CNTL +#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR6_1_PCIE_MC_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_MC_CAP +#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR6_1_PCIE_MC_CNTL +#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR6_1_PCIE_MC_ADDR0 +#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR6_1_PCIE_MC_ADDR1 +#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_RCV0 +#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_RCV1 +#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_BLOCK_ALL0 +#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_BLOCK_ALL1 +#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR6_1_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_L1_PM_SUB_CAP +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_DPC_CAP_LIST +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR6_1_PCIE_DPC_CNTL +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR6_1_PCIE_DPC_STATUS +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR6_1_PCIE_RP_PIO_STATUS +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR6_1_PCIE_RP_PIO_MASK +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR6_1_PCIE_RP_PIO_SEVERITY +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR6_1_PCIE_RP_PIO_SYSERROR +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR6_1_PCIE_RP_PIO_EXCEPTION +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_1_PCIE_ESM_CAP_LIST +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_ESM_HEADER_1 +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR6_1_PCIE_ESM_HEADER_2 +#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR6_1_PCIE_ESM_STATUS +#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR6_1_PCIE_ESM_CTRL +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR6_1_PCIE_ESM_CAP_1 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR6_1_PCIE_ESM_CAP_2 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR6_1_PCIE_ESM_CAP_3 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR6_1_PCIE_ESM_CAP_4 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR6_1_PCIE_ESM_CAP_5 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR6_1_PCIE_ESM_CAP_6 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR6_1_PCIE_ESM_CAP_7 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifp0_pciedir_p +//BIFP0_PCIEP_RESERVED +#define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP0_PCIEP_SCRATCH +#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP0_PCIEP_PORT_CNTL +#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP0_PCIE_TX_CNTL +#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP0_PCIE_TX_REQUESTER_ID +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP0_PCIE_TX_VENDOR_SPECIFIC +#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP0_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP0_PCIE_TX_SEQ +#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP0_PCIE_TX_REPLAY +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP0_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP0_PCIE_TX_CREDITS_ADVT_P +#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_ADVT_NP +#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_INIT_P +#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_INIT_NP +#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_INIT_CPL +#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP0_PCIE_TX_CREDITS_STATUS +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP0_PCIE_P_PORT_LANE_STATUS +#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP0_PCIE_FC_P +#define BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP0_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP0_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP0_PCIE_FC_NP +#define BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP0_PCIE_FC_CPL +#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP0_PCIE_ERR_CNTL +#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP0_PCIE_RX_CNTL +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP0_PCIE_RX_EXPECTED_SEQNUM +#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP0_PCIE_RX_VENDOR_SPECIFIC +#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP0_PCIE_RX_CNTL3 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP0_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP0_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP0_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP0_PCIEP_NAK_COUNTER +#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP0_PCIE_LC_CNTL +#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP0_PCIE_LC_TRAINING_CNTL +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP0_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP0_PCIE_LC_N_FTS_CNTL +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP0_PCIE_LC_SPEED_CNTL +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP0_PCIE_LC_STATE0 +#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP0_PCIE_LC_STATE1 +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP0_PCIE_LC_STATE2 +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP0_PCIE_LC_STATE3 +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP0_PCIE_LC_STATE4 +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP0_PCIE_LC_STATE5 +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP0_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP0_PCIE_LC_CNTL2 +#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP0_PCIE_LC_BW_CHANGE_CNTL +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP0_PCIE_LC_CDR_CNTL +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP0_PCIE_LC_LANE_CNTL +#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP0_PCIE_LC_CNTL3 +#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP0_PCIE_LC_CNTL4 +#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP0_PCIE_LC_CNTL5 +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP0_PCIE_LC_FORCE_COEFF +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP0_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP0_PCIE_LC_CNTL6 +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP0_PCIE_LC_CNTL7 +#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP0_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP0_PCIE_LINK_MANAGEMENT_MASK +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP0_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP0_PCIEP_STRAP_LC +#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP0_PCIEP_STRAP_MISC +#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP0_PCIE_LC_L1_PM_SUBSTATE +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP0_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP0_PCIE_LC_PORT_ORDER +#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP0_PCIEP_BCH_ECC_CNTL +#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP0_PCIEP_HPGI_PRIVATE +#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP0_PCIEP_HPGI +#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP0_PCIEP_HCNT_DESCRIPTOR +#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp1_pciedir_p +//BIFP1_PCIEP_RESERVED +#define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP1_PCIEP_SCRATCH +#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP1_PCIEP_PORT_CNTL +#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP1_PCIE_TX_CNTL +#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP1_PCIE_TX_REQUESTER_ID +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP1_PCIE_TX_VENDOR_SPECIFIC +#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP1_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP1_PCIE_TX_SEQ +#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP1_PCIE_TX_REPLAY +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP1_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP1_PCIE_TX_CREDITS_ADVT_P +#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_ADVT_NP +#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_INIT_P +#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_INIT_NP +#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_INIT_CPL +#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP1_PCIE_TX_CREDITS_STATUS +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP1_PCIE_P_PORT_LANE_STATUS +#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP1_PCIE_FC_P +#define BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP1_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP1_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP1_PCIE_FC_NP +#define BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP1_PCIE_FC_CPL +#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP1_PCIE_ERR_CNTL +#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP1_PCIE_RX_CNTL +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP1_PCIE_RX_EXPECTED_SEQNUM +#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP1_PCIE_RX_VENDOR_SPECIFIC +#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP1_PCIE_RX_CNTL3 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP1_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP1_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP1_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP1_PCIEP_NAK_COUNTER +#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP1_PCIE_LC_CNTL +#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP1_PCIE_LC_TRAINING_CNTL +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP1_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP1_PCIE_LC_N_FTS_CNTL +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP1_PCIE_LC_SPEED_CNTL +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP1_PCIE_LC_STATE0 +#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP1_PCIE_LC_STATE1 +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP1_PCIE_LC_STATE2 +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP1_PCIE_LC_STATE3 +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP1_PCIE_LC_STATE4 +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP1_PCIE_LC_STATE5 +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP1_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP1_PCIE_LC_CNTL2 +#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP1_PCIE_LC_BW_CHANGE_CNTL +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP1_PCIE_LC_CDR_CNTL +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP1_PCIE_LC_LANE_CNTL +#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP1_PCIE_LC_CNTL3 +#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP1_PCIE_LC_CNTL4 +#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP1_PCIE_LC_CNTL5 +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP1_PCIE_LC_FORCE_COEFF +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP1_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP1_PCIE_LC_CNTL6 +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP1_PCIE_LC_CNTL7 +#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP1_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP1_PCIE_LINK_MANAGEMENT_MASK +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP1_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP1_PCIEP_STRAP_LC +#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP1_PCIEP_STRAP_MISC +#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP1_PCIE_LC_L1_PM_SUBSTATE +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP1_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP1_PCIE_LC_PORT_ORDER +#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP1_PCIEP_BCH_ECC_CNTL +#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP1_PCIEP_HPGI_PRIVATE +#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP1_PCIEP_HPGI +#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP1_PCIEP_HCNT_DESCRIPTOR +#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp2_pciedir_p +//BIFP2_PCIEP_RESERVED +#define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP2_PCIEP_SCRATCH +#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP2_PCIEP_PORT_CNTL +#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP2_PCIE_TX_CNTL +#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP2_PCIE_TX_REQUESTER_ID +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP2_PCIE_TX_VENDOR_SPECIFIC +#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP2_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP2_PCIE_TX_SEQ +#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP2_PCIE_TX_REPLAY +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP2_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP2_PCIE_TX_CREDITS_ADVT_P +#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_ADVT_NP +#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_INIT_P +#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_INIT_NP +#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_INIT_CPL +#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP2_PCIE_TX_CREDITS_STATUS +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP2_PCIE_P_PORT_LANE_STATUS +#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP2_PCIE_FC_P +#define BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP2_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP2_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP2_PCIE_FC_NP +#define BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP2_PCIE_FC_CPL +#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP2_PCIE_ERR_CNTL +#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP2_PCIE_RX_CNTL +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP2_PCIE_RX_EXPECTED_SEQNUM +#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP2_PCIE_RX_VENDOR_SPECIFIC +#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP2_PCIE_RX_CNTL3 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP2_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP2_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP2_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP2_PCIEP_NAK_COUNTER +#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP2_PCIE_LC_CNTL +#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP2_PCIE_LC_TRAINING_CNTL +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP2_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP2_PCIE_LC_N_FTS_CNTL +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP2_PCIE_LC_SPEED_CNTL +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP2_PCIE_LC_STATE0 +#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP2_PCIE_LC_STATE1 +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP2_PCIE_LC_STATE2 +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP2_PCIE_LC_STATE3 +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP2_PCIE_LC_STATE4 +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP2_PCIE_LC_STATE5 +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP2_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP2_PCIE_LC_CNTL2 +#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP2_PCIE_LC_BW_CHANGE_CNTL +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP2_PCIE_LC_CDR_CNTL +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP2_PCIE_LC_LANE_CNTL +#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP2_PCIE_LC_CNTL3 +#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP2_PCIE_LC_CNTL4 +#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP2_PCIE_LC_CNTL5 +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP2_PCIE_LC_FORCE_COEFF +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP2_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP2_PCIE_LC_CNTL6 +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP2_PCIE_LC_CNTL7 +#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP2_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP2_PCIE_LINK_MANAGEMENT_MASK +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP2_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP2_PCIEP_STRAP_LC +#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP2_PCIEP_STRAP_MISC +#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP2_PCIE_LC_L1_PM_SUBSTATE +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP2_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP2_PCIE_LC_PORT_ORDER +#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP2_PCIEP_BCH_ECC_CNTL +#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP2_PCIEP_HPGI_PRIVATE +#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP2_PCIEP_HPGI +#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP2_PCIEP_HCNT_DESCRIPTOR +#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp3_pciedir_p +//BIFP3_PCIEP_RESERVED +#define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP3_PCIEP_SCRATCH +#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP3_PCIEP_PORT_CNTL +#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP3_PCIE_TX_CNTL +#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP3_PCIE_TX_REQUESTER_ID +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP3_PCIE_TX_VENDOR_SPECIFIC +#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP3_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP3_PCIE_TX_SEQ +#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP3_PCIE_TX_REPLAY +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP3_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP3_PCIE_TX_CREDITS_ADVT_P +#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_ADVT_NP +#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_INIT_P +#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_INIT_NP +#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_INIT_CPL +#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP3_PCIE_TX_CREDITS_STATUS +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP3_PCIE_P_PORT_LANE_STATUS +#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP3_PCIE_FC_P +#define BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP3_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP3_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP3_PCIE_FC_NP +#define BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP3_PCIE_FC_CPL +#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP3_PCIE_ERR_CNTL +#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP3_PCIE_RX_CNTL +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP3_PCIE_RX_EXPECTED_SEQNUM +#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP3_PCIE_RX_VENDOR_SPECIFIC +#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP3_PCIE_RX_CNTL3 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP3_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP3_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP3_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP3_PCIEP_NAK_COUNTER +#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP3_PCIE_LC_CNTL +#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP3_PCIE_LC_TRAINING_CNTL +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP3_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP3_PCIE_LC_N_FTS_CNTL +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP3_PCIE_LC_SPEED_CNTL +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP3_PCIE_LC_STATE0 +#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP3_PCIE_LC_STATE1 +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP3_PCIE_LC_STATE2 +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP3_PCIE_LC_STATE3 +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP3_PCIE_LC_STATE4 +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP3_PCIE_LC_STATE5 +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP3_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP3_PCIE_LC_CNTL2 +#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP3_PCIE_LC_BW_CHANGE_CNTL +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP3_PCIE_LC_CDR_CNTL +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP3_PCIE_LC_LANE_CNTL +#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP3_PCIE_LC_CNTL3 +#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP3_PCIE_LC_CNTL4 +#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP3_PCIE_LC_CNTL5 +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP3_PCIE_LC_FORCE_COEFF +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP3_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP3_PCIE_LC_CNTL6 +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP3_PCIE_LC_CNTL7 +#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP3_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP3_PCIE_LINK_MANAGEMENT_MASK +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP3_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP3_PCIEP_STRAP_LC +#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP3_PCIEP_STRAP_MISC +#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP3_PCIE_LC_L1_PM_SUBSTATE +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP3_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP3_PCIE_LC_PORT_ORDER +#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP3_PCIEP_BCH_ECC_CNTL +#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP3_PCIEP_HPGI_PRIVATE +#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP3_PCIEP_HPGI +#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP3_PCIEP_HCNT_DESCRIPTOR +#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp4_pciedir_p +//BIFP4_PCIEP_RESERVED +#define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP4_PCIEP_SCRATCH +#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP4_PCIEP_PORT_CNTL +#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP4_PCIE_TX_CNTL +#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP4_PCIE_TX_REQUESTER_ID +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP4_PCIE_TX_VENDOR_SPECIFIC +#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP4_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP4_PCIE_TX_SEQ +#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP4_PCIE_TX_REPLAY +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP4_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP4_PCIE_TX_CREDITS_ADVT_P +#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_ADVT_NP +#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_INIT_P +#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_INIT_NP +#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_INIT_CPL +#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP4_PCIE_TX_CREDITS_STATUS +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP4_PCIE_P_PORT_LANE_STATUS +#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP4_PCIE_FC_P +#define BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP4_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP4_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP4_PCIE_FC_NP +#define BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP4_PCIE_FC_CPL +#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP4_PCIE_ERR_CNTL +#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP4_PCIE_RX_CNTL +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP4_PCIE_RX_EXPECTED_SEQNUM +#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP4_PCIE_RX_VENDOR_SPECIFIC +#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP4_PCIE_RX_CNTL3 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP4_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP4_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP4_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP4_PCIEP_NAK_COUNTER +#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP4_PCIE_LC_CNTL +#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP4_PCIE_LC_TRAINING_CNTL +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP4_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP4_PCIE_LC_N_FTS_CNTL +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP4_PCIE_LC_SPEED_CNTL +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP4_PCIE_LC_STATE0 +#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP4_PCIE_LC_STATE1 +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP4_PCIE_LC_STATE2 +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP4_PCIE_LC_STATE3 +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP4_PCIE_LC_STATE4 +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP4_PCIE_LC_STATE5 +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP4_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP4_PCIE_LC_CNTL2 +#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP4_PCIE_LC_BW_CHANGE_CNTL +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP4_PCIE_LC_CDR_CNTL +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP4_PCIE_LC_LANE_CNTL +#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP4_PCIE_LC_CNTL3 +#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP4_PCIE_LC_CNTL4 +#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP4_PCIE_LC_CNTL5 +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP4_PCIE_LC_FORCE_COEFF +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP4_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP4_PCIE_LC_CNTL6 +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP4_PCIE_LC_CNTL7 +#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP4_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP4_PCIE_LINK_MANAGEMENT_MASK +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP4_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP4_PCIEP_STRAP_LC +#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP4_PCIEP_STRAP_MISC +#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP4_PCIE_LC_L1_PM_SUBSTATE +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP4_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP4_PCIE_LC_PORT_ORDER +#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP4_PCIEP_BCH_ECC_CNTL +#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP4_PCIEP_HPGI_PRIVATE +#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP4_PCIEP_HPGI +#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP4_PCIEP_HCNT_DESCRIPTOR +#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp5_pciedir_p +//BIFP5_PCIEP_RESERVED +#define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP5_PCIEP_SCRATCH +#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP5_PCIEP_PORT_CNTL +#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP5_PCIE_TX_CNTL +#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP5_PCIE_TX_REQUESTER_ID +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP5_PCIE_TX_VENDOR_SPECIFIC +#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP5_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP5_PCIE_TX_SEQ +#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP5_PCIE_TX_REPLAY +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP5_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP5_PCIE_TX_CREDITS_ADVT_P +#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_ADVT_NP +#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_INIT_P +#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_INIT_NP +#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_INIT_CPL +#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP5_PCIE_TX_CREDITS_STATUS +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP5_PCIE_P_PORT_LANE_STATUS +#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP5_PCIE_FC_P +#define BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP5_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP5_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP5_PCIE_FC_NP +#define BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP5_PCIE_FC_CPL +#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP5_PCIE_ERR_CNTL +#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP5_PCIE_RX_CNTL +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP5_PCIE_RX_EXPECTED_SEQNUM +#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP5_PCIE_RX_VENDOR_SPECIFIC +#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP5_PCIE_RX_CNTL3 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP5_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP5_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP5_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP5_PCIEP_NAK_COUNTER +#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP5_PCIE_LC_CNTL +#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP5_PCIE_LC_TRAINING_CNTL +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP5_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP5_PCIE_LC_N_FTS_CNTL +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP5_PCIE_LC_SPEED_CNTL +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP5_PCIE_LC_STATE0 +#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP5_PCIE_LC_STATE1 +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP5_PCIE_LC_STATE2 +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP5_PCIE_LC_STATE3 +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP5_PCIE_LC_STATE4 +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP5_PCIE_LC_STATE5 +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP5_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP5_PCIE_LC_CNTL2 +#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP5_PCIE_LC_BW_CHANGE_CNTL +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP5_PCIE_LC_CDR_CNTL +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP5_PCIE_LC_LANE_CNTL +#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP5_PCIE_LC_CNTL3 +#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP5_PCIE_LC_CNTL4 +#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP5_PCIE_LC_CNTL5 +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP5_PCIE_LC_FORCE_COEFF +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP5_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP5_PCIE_LC_CNTL6 +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP5_PCIE_LC_CNTL7 +#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP5_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP5_PCIE_LINK_MANAGEMENT_MASK +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP5_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP5_PCIEP_STRAP_LC +#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP5_PCIEP_STRAP_MISC +#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP5_PCIE_LC_L1_PM_SUBSTATE +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP5_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP5_PCIE_LC_PORT_ORDER +#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP5_PCIEP_BCH_ECC_CNTL +#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP5_PCIEP_HPGI_PRIVATE +#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP5_PCIEP_HPGI +#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP5_PCIEP_HCNT_DESCRIPTOR +#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_bifp6_pciedir_p +//BIFP6_PCIEP_RESERVED +#define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//BIFP6_PCIEP_SCRATCH +#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL +//BIFP6_PCIEP_PORT_CNTL +#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 +#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L +#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L +#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L +#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L +//BIFP6_PCIE_TX_CNTL +#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +//BIFP6_PCIE_TX_REQUESTER_ID +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//BIFP6_PCIE_TX_VENDOR_SPECIFIC +#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL +//BIFP6_PCIE_TX_REQUEST_NUM_CNTL +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +//BIFP6_PCIE_TX_SEQ +#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L +//BIFP6_PCIE_TX_REPLAY +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L +//BIFP6_PCIE_TX_ACK_LATENCY_LIMIT +#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +//BIFP6_PCIE_TX_CREDITS_ADVT_P +#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_ADVT_NP +#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_ADVT_CPL +#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_INIT_P +#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_INIT_NP +#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_INIT_CPL +#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL +#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L +//BIFP6_PCIE_TX_CREDITS_STATUS +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +//BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +//BIFP6_PCIE_P_PORT_LANE_STATUS +#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL +//BIFP6_PCIE_FC_P +#define BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define BIFP6_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL +#define BIFP6_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L +//BIFP6_PCIE_FC_NP +#define BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL +#define BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L +//BIFP6_PCIE_FC_CPL +#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL +#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L +//BIFP6_PCIE_ERR_CNTL +#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L +#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +//BIFP6_PCIE_RX_CNTL +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//BIFP6_PCIE_RX_EXPECTED_SEQNUM +#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL +//BIFP6_PCIE_RX_VENDOR_SPECIFIC +#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL +#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +//BIFP6_PCIE_RX_CNTL3 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +//BIFP6_PCIE_RX_CREDITS_ALLOCATED_P +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L +//BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L +//BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL +#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L +//BIFP6_PCIEP_ERROR_INJECT_PHYSICAL +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L +#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L +//BIFP6_PCIEP_ERROR_INJECT_TRANSACTION +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L +#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L +//BIFP6_PCIEP_NAK_COUNTER +#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 +#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 +#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL +#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L +//BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0 +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8 +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9 +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L +//BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0 +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L +#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L +//BIFP6_PCIE_LC_CNTL +#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L +#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L +#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L +#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L +#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +//BIFP6_PCIE_LC_TRAINING_CNTL +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L +//BIFP6_PCIE_LC_LINK_WIDTH_CNTL +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L +#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L +//BIFP6_PCIE_LC_N_FTS_CNTL +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L +#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L +//BIFP6_PCIE_LC_SPEED_CNTL +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +//BIFP6_PCIE_LC_STATE0 +#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L +//BIFP6_PCIE_LC_STATE1 +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L +//BIFP6_PCIE_LC_STATE2 +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L +//BIFP6_PCIE_LC_STATE3 +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L +//BIFP6_PCIE_LC_STATE4 +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L +//BIFP6_PCIE_LC_STATE5 +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L +#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L +//BIFP6_PCIE_LINK_MANAGEMENT_CNTL2 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L +//BIFP6_PCIE_LC_CNTL2 +#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL +#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L +#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +//BIFP6_PCIE_LC_BW_CHANGE_CNTL +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L +//BIFP6_PCIE_LC_CDR_CNTL +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L +#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +//BIFP6_PCIE_LC_LANE_CNTL +#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL +#define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L +//BIFP6_PCIE_LC_CNTL3 +#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L +#define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L +#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +//BIFP6_PCIE_LC_CNTL4 +#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L +#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L +#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L +#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L +#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L +//BIFP6_PCIE_LC_CNTL5 +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 +#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a +#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b +#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c +#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L +#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L +#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L +#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L +#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L +#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L +#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L +#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L +//BIFP6_PCIE_LC_FORCE_COEFF +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L +//BIFP6_PCIE_LC_BEST_EQ_SETTINGS +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L +#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L +//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L +#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L +//BIFP6_PCIE_LC_CNTL6 +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5 +#define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 +#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 +#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 +#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 +#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L +#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L +#define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L +#define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L +#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L +#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L +#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L +#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L +#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L +#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L +#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L +#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L +//BIFP6_PCIE_LC_CNTL7 +#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 +#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 +#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 +#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 +#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 +#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 +#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 +#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 +#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 +#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 +#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa +#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 +#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 +#define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18 +#define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d +#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e +#define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f +#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L +#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L +#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L +#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L +#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L +#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L +#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L +#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L +#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L +#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L +#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L +#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L +#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L +#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L +#define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L +#define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L +#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L +#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L +#define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L +//BIFP6_PCIE_LINK_MANAGEMENT_STATUS +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L +#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L +//BIFP6_PCIE_LINK_MANAGEMENT_MASK +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L +#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L +//BIFP6_PCIE_LINK_MANAGEMENT_CNTL +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L +#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L +//BIFP6_PCIEP_STRAP_LC +#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL +#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L +#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +//BIFP6_PCIEP_STRAP_MISC +#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L +//BIFP6_PCIE_LC_L1_PM_SUBSTATE +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L +//BIFP6_PCIE_LC_L1_PM_SUBSTATE2 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L +#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L +//BIFP6_PCIE_LC_PORT_ORDER +#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 +#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL +//BIFP6_PCIEP_BCH_ECC_CNTL +#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L +#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L +#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L +//BIFP6_PCIEP_HPGI_PRIVATE +#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L +#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L +//BIFP6_PCIEP_HPGI +#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L +#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L +#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L +#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L +#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L +#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L +#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L +#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L +#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L +#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L +#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L +//BIFP6_PCIEP_HCNT_DESCRIPTOR +#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0 +#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f +#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL +#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L +//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK +#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0 +#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10 +#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL +#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L + + +// addressBlock: nbio_pcie0_pciedir +//PCIE_RESERVED +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//PCIE_SCRATCH +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//PCIE_RX_NUM_NAK +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL +//PCIE_RX_NUM_NAK_GENERATED +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL +//PCIE_CNTL +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L +//PCIE_CONFIG_CNTL +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8 +#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c +#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L +#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L +#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L +#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L +//PCIE_TX_TRACKING_ADDR_LO +#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2 +#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL +//PCIE_TX_TRACKING_ADDR_HI +#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0 +#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL +//PCIE_TX_TRACKING_CTRL_STATUS +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8 +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L +#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L +//PCIE_BW_BY_UNITID +#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0 +#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8 +#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L +#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L +//PCIE_CNTL2 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc +#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd +#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d +#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e +#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L +#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L +#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L +#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L +#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L +#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L +#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L +//PCIE_RX_CNTL2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//PCIE_TX_F0_ATTR_CNTL +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L +//PCIE_TX_SWUS_ATTR_CNTL +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L +#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L +//PCIE_CI_CNTL +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10 +#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11 +#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12 +#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13 +#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14 +#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15 +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16 +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17 +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L +#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L +#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L +#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L +#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L +#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L +#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L +#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L +#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L +//PCIE_BUS_CNTL +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L +//PCIE_LC_STATE6 +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L +//PCIE_LC_STATE7 +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L +//PCIE_LC_STATE8 +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L +//PCIE_LC_STATE9 +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L +//PCIE_LC_STATE10 +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L +//PCIE_LC_STATE11 +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L +//PCIE_LC_STATUS1 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L +//PCIE_LC_STATUS2 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L +//PCIE_WPR_CNTL +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L +//PCIE_RX_LAST_TLP0 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP1 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP2 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL +//PCIE_RX_LAST_TLP3 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP1 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP2 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL +//PCIE_TX_LAST_TLP3 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL +//PCIE_I2C_REG_ADDR_EXPAND +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL +//PCIE_I2C_REG_DATA +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL +//PCIE_CFG_CNTL +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//PCIE_LC_PM_CNTL +#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0 +#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4 +#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8 +#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc +#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10 +#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14 +#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18 +#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c +#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL +#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L +#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L +#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L +#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L +#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L +#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L +#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L +//PCIE_LC_PORT_ORDER_CNTL +#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0 +#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L +//PCIE_P_CNTL +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L +#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L +//PCIE_P_BUF_STATUS +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L +//PCIE_P_DECODER_STATUS +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL +//PCIE_P_MISC_STATUS +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L +//PCIE_P_RCV_L0S_FTS_DET +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L +//PCIE_RX_AD +#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0 +#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1 +#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2 +#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3 +#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4 +#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5 +#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8 +#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9 +#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa +#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb +#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc +#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd +#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe +#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf +#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L +#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L +#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L +#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L +#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L +#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L +#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L +#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L +#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L +#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L +#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L +#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L +#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L +#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L +//PCIE_SDP_CTRL +#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0 +#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4 +#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5 +#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6 +#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7 +#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8 +#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9 +#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa +#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb +#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc +#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd +#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe +#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf +#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL +#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L +#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L +#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L +#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L +#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L +#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L +#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L +#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L +#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L +#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L +#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L +#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L +//NBIO_CLKREQb_MAP_CNTL +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP__SHIFT 0x0 +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP__SHIFT 0x4 +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP__SHIFT 0x8 +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP__SHIFT 0xc +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP__SHIFT 0x10 +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK__SHIFT 0x1c +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP_MASK 0x0000000FL +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP_MASK 0x000000F0L +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP_MASK 0x00000F00L +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP_MASK 0x0000F000L +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP_MASK 0x000F0000L +#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK_MASK 0x10000000L +//PCIE_SDP_SWUS_SLV_ATTR_CTRL +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L +#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L +//PCIE_SDP_RC_SLV_ATTR_CTRL +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L +#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L +//PCIE_PERF_COUNT_CNTL +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L +//PCIE_PERF_CNTL_TXCLK +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_TXCLK +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_MST_R_CLK +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_MST_R_CLK +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_MST_R_CLK +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_MST_C_CLK +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_MST_C_CLK +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_MST_C_CLK +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_SLV_R_CLK +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_SLV_R_CLK +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_SLV_R_CLK +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_SLV_S_C_CLK +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_SLV_S_C_CLK +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_SLV_S_C_CLK +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_SLV_NS_C_CLK +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_SLV_NS_C_CLK +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_SLV_NS_C_CLK +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_EVENT0_PORT_SEL +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000FL +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000F0L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000F00L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0F000000L +//PCIE_PERF_CNTL_EVENT1_PORT_SEL +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000FL +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000F0L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000F00L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0F000000L +//PCIE_PERF_CNTL_TXCLK2 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_TXCLK2 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK2 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PRBS_CLR +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L +//PCIE_PRBS_STATUS1 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L +//PCIE_PRBS_STATUS2 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL +//PCIE_PRBS_FREERUN +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL +//PCIE_PRBS_MISC +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L +//PCIE_PRBS_USER_PATTERN +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL +//PCIE_PRBS_LO_BITCNT +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL +//PCIE_PRBS_HI_BITCNT +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL +//PCIE_PRBS_ERRCNT_0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_1 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_2 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_3 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_4 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_5 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_6 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_7 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_8 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_9 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_10 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_11 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_12 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_13 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_14 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL +//PCIE_PRBS_ERRCNT_15 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL +//SWRST_COMMAND_STATUS +#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 +#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 +#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 +#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19 +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f +#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L +#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L +#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L +#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L +#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L +#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L +#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L +//SWRST_GENERAL_CONTROL +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 +#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc +#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11 +#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18 +#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19 +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L +#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L +#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L +#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L +#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L +//SWRST_COMMAND_0 +#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0 +#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8 +#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9 +#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa +#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb +#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc +#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd +#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe +#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18 +#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19 +#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b +#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c +#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e +#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L +#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L +#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L +#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L +#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L +#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L +#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L +#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L +#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L +#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L +#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L +#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L +#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L +//SWRST_COMMAND_1 +#define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0 +#define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1 +#define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2 +#define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3 +#define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4 +#define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5 +#define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6 +#define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7 +#define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8 +#define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9 +#define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa +#define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb +#define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc +#define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd +#define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe +#define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf +#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15 +#define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16 +#define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17 +#define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18 +#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19 +#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a +#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b +#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c +#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d +#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e +#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f +#define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L +#define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L +#define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L +#define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L +#define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L +#define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L +#define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L +#define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L +#define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L +#define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L +#define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L +#define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L +#define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L +#define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L +#define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L +#define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L +#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L +#define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L +#define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L +#define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L +#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L +#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L +#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L +#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L +#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L +#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L +#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L +//SWRST_CONTROL_0 +#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0 +#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8 +#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9 +#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa +#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb +#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc +#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd +#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe +#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18 +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19 +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e +#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L +#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L +#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L +#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L +#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L +#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L +#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L +#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L +#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L +//SWRST_CONTROL_1 +#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0 +#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1 +#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2 +#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3 +#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4 +#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5 +#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6 +#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7 +#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8 +#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9 +#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa +#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb +#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc +#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd +#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe +#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf +#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15 +#define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16 +#define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17 +#define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18 +#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19 +#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a +#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b +#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c +#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d +#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e +#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f +#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L +#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L +#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L +#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L +#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L +#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L +#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L +#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L +#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L +#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L +#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L +#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L +#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L +#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L +#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L +#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L +#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L +#define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L +#define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L +#define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L +#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L +#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L +#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L +#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L +#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L +#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L +#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L +//SWRST_CONTROL_2 +#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0 +#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8 +#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9 +#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa +#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb +#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc +#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd +#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe +#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18 +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19 +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e +#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L +#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L +#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L +#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L +#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L +#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L +#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L +#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L +#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L +//SWRST_CONTROL_3 +#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0 +#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1 +#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2 +#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3 +#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4 +#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5 +#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6 +#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7 +#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8 +#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9 +#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa +#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb +#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc +#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd +#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe +#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf +#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15 +#define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16 +#define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17 +#define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18 +#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19 +#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a +#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b +#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c +#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d +#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e +#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f +#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L +#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L +#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L +#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L +#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L +#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L +#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L +#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L +#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L +#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L +#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L +#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L +#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L +#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L +#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L +#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L +#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L +#define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L +#define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L +#define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L +#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L +#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L +#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L +#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L +#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L +#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L +#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L +//SWRST_CONTROL_4 +#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0 +#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8 +#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9 +#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa +#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb +#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc +#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd +#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe +#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18 +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19 +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e +#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L +#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L +#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L +#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L +#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L +#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L +#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L +#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L +#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L +//SWRST_CONTROL_5 +#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0 +#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1 +#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2 +#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3 +#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4 +#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5 +#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6 +#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7 +#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8 +#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9 +#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa +#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb +#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc +#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd +#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe +#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf +#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15 +#define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16 +#define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17 +#define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18 +#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19 +#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a +#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b +#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c +#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d +#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e +#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f +#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L +#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L +#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L +#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L +#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L +#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L +#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L +#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L +#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L +#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L +#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L +#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L +#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L +#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L +#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L +#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L +#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L +#define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L +#define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L +#define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L +#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L +#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L +#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L +#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L +#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L +#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L +#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L +//SWRST_CONTROL_6 +#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0 +#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1 +#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2 +#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3 +#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4 +#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5 +#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6 +#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7 +#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8 +#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9 +#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa +#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L +#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L +#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L +#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L +#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L +#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L +#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L +#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L +#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L +#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L +#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L +//SWRST_EP_COMMAND_0 +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 +#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L +#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L +//SWRST_EP_CONTROL_0 +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L +//CPM_CONTROL +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 +#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb +#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xc +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10 +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11 +#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12 +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 +#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18 +#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19 +#define CPM_CONTROL__SPARE_REGS__SHIFT 0x1a +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L +#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x00000004L +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00000800L +#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x00003000L +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L +#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L +#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L +#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L +#define CPM_CONTROL__SPARE_REGS_MASK 0xFC000000L +//SMN_APERTURE_ID_A +#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0 +#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc +#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL +#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L +//SMN_APERTURE_ID_B +#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0 +#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc +#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL +#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L +//RSMU_MASTER_CONTROL +#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT 0x0 +#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK 0x00000001L +//RSMU_SLAVE_CONTROL +#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT 0x0 +#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT 0x2 +#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK 0x00000001L +#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK 0x00000004L +//RSMU_POWER_GATING_CONTROL +#define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY__SHIFT 0x0 +#define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY__SHIFT 0x1 +#define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY_MASK 0x00000001L +#define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY_MASK 0x00000002L +//RSMU_BIOS_TIMER_CMD +#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT 0x0 +#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK 0xFFFFFFFFL +//RSMU_BIOS_TIMER_CNTL +#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT 0x0 +#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK 0x000000FFL +//LNCNT_CONTROL +#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0 +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1 +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2 +#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3 +#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4 +#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L +#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L +#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L +//CFG_LNC_WINDOW_REGISTER +#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW__SHIFT 0x0 +#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW_MASK 0x00FFFFFFL +//LNCNT_QUAN_THRD +#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0 +#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4 +#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L +#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L +//LNCNT_WEIGHT +#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0 +#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10 +#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL +#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L +//LNC_TOTAL_WACC_REGISTER +#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC__SHIFT 0x0 +#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC_MASK 0xFFFFFFFFL +//LNC_BW_WACC_REGISTER +#define LNC_BW_WACC_REGISTER__LNC_BW_WACC__SHIFT 0x0 +#define LNC_BW_WACC_REGISTER__LNC_BW_WACC_MASK 0xFFFFFFFFL +//LNC_CMN_WACC_REGISTER +#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC__SHIFT 0x0 +#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC_MASK 0xFFFFFFFFL +//SMU_HP_STATUS_UPDATE +#define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS__SHIFT 0x0 +#define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS_MASK 0xFFFFFFFFL +//HP_SMU_COMMAND_UPDATE +#define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND__SHIFT 0x0 +#define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND_MASK 0xFFFFFFFFL +//SMU_HP_END_OF_INTERRUPT +#define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI__SHIFT 0x0 +#define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI_MASK 0x00000001L +//SMU_INT_PIN_SHARING_PORT_INDICATOR +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10 +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L +#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L +//PCIE_PGMST_CNTL +#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 +#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 +#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe +#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L +#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L +//PCIE_PGSLV_CNTL +#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//SMU_PCIE_FENCED1_REG +#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x0 +#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x00000001L +//SMU_PCIE_FENCED2_REG + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +//NB_NBCFG1_NB_VENDOR_ID +#define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//NB_NBCFG1_NB_DEVICE_ID +#define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//NB_NBCFG1_NB_COMMAND +#define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_NBCFG1_NB_STATUS +#define NB_NBCFG1_NB_STATUS__CAP_LIST__SHIFT 0x4 +#define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define NB_NBCFG1_NB_STATUS__CAP_LIST_MASK 0x0010L +#define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +//NB_NBCFG1_NB_REVISION_ID +#define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//NB_NBCFG1_NB_REGPROG_INF +#define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//NB_NBCFG1_NB_SUB_CLASS +#define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//NB_NBCFG1_NB_BASE_CODE +#define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//NB_NBCFG1_NB_CACHE_LINE +#define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//NB_NBCFG1_NB_LATENCY +#define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL +//NB_NBCFG1_NB_HEADER +#define NB_NBCFG1_NB_HEADER__HEADER_TYPE__SHIFT 0x0 +#define NB_NBCFG1_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG1_NB_HEADER__HEADER_TYPE_MASK 0x7FL +#define NB_NBCFG1_NB_HEADER__DEVICE_TYPE_MASK 0x80L +//NB_NBCFG1_NB_ADAPTER_ID +#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG1_NB_CAPABILITIES_PTR +#define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//NB_NBCFG1_NB_HEADER_W +#define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L +//NB_NBCFG1_NB_PCI_CTRL +#define NB_NBCFG1_NB_PCI_CTRL__PMEDis__SHIFT 0x4 +#define NB_NBCFG1_NB_PCI_CTRL__SErrDis__SHIFT 0x5 +#define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 +#define NB_NBCFG1_NB_PCI_CTRL__HPDis__SHIFT 0x1a +#define NB_NBCFG1_NB_PCI_CTRL__PMEDis_MASK 0x00000010L +#define NB_NBCFG1_NB_PCI_CTRL__SErrDis_MASK 0x00000020L +#define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L +#define NB_NBCFG1_NB_PCI_CTRL__HPDis_MASK 0x04000000L +//NB_NBCFG1_NB_ADAPTER_ID_W +#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_0 +#define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_0 +#define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL +//NB_NBCFG1_NBCFG_SCRATCH_0 +#define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 +#define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL +//NB_NBCFG1_NBCFG_SCRATCH_1 +#define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 +#define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL +//NB_NBCFG1_NBCFG_SCRATCH_2 +#define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 +#define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL +//NB_NBCFG1_NBCFG_SCRATCH_3 +#define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 +#define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL +//NB_NBCFG1_NBCFG_SCRATCH_4 +#define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 +#define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_PCI_ARB +#define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define NB_NBCFG1_NB_PCI_ARB__PMEMode__SHIFT 0x8 +#define NB_NBCFG1_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 +#define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa +#define NB_NBCFG1_NB_PCI_ARB__PMETarget__SHIFT 0x10 +#define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +#define NB_NBCFG1_NB_PCI_ARB__PMEMode_MASK 0x00000100L +#define NB_NBCFG1_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L +#define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L +#define NB_NBCFG1_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L +//NB_NBCFG1_NB_DRAM_SLOT1_BASE +#define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 +#define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L +//NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1 +#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 +#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L +#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_1 +#define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_1 +#define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_INDEX_DATA_MUTEX0 +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L +//NB_NBCFG1_NB_INDEX_DATA_MUTEX1 +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL +#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_2 +#define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_2 +#define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_3 +#define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_3 +#define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_4 +#define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_4 +#define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL +//NB_NBCFG1_NB_SMN_INDEX_5 +#define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_5 +#define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_PERF_CNT_CTRL +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L +#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L +//NB_NBCFG1_NB_SMN_INDEX_6 +#define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL +//NB_NBCFG1_NB_SMN_DATA_6 +#define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 +#define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_iommushadow_iommushadow_cfgdecp +//SHADOW_IOMMU_MMIO_CNTRL_0 +#define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +//SHADOW_IOMMU_CAP_BASE_LO +#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 +#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L +//SHADOW_IOMMU_CAP_BASE_HI +#define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 +#define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp +//NB_PCIE0SHADOW0_COMMAND +#define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW0_IO_BASE_LIMIT +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW0_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW0_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW0_PREF_BASE_UPPER +#define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW0_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW0_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW0_SLOT_CAP +#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW0_ROOT_CNTL +#define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW0_DEVICE_CNTL2 +#define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp +//NB_PCIE0SHADOW1_COMMAND +#define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW1_IO_BASE_LIMIT +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW1_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW1_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW1_PREF_BASE_UPPER +#define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW1_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW1_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW1_SLOT_CAP +#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW1_ROOT_CNTL +#define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW1_DEVICE_CNTL2 +#define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp +//NB_PCIE0SHADOW2_COMMAND +#define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW2_IO_BASE_LIMIT +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW2_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW2_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW2_PREF_BASE_UPPER +#define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW2_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW2_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW2_SLOT_CAP +#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW2_ROOT_CNTL +#define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW2_DEVICE_CNTL2 +#define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp +//NB_PCIE0SHADOW3_COMMAND +#define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW3_IO_BASE_LIMIT +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW3_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW3_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW3_PREF_BASE_UPPER +#define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW3_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW3_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW3_SLOT_CAP +#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW3_ROOT_CNTL +#define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW3_DEVICE_CNTL2 +#define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp +//NB_PCIE0SHADOW4_COMMAND +#define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW4_IO_BASE_LIMIT +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW4_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW4_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW4_PREF_BASE_UPPER +#define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW4_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW4_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW4_SLOT_CAP +#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW4_ROOT_CNTL +#define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW4_DEVICE_CNTL2 +#define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp +//NB_PCIE0SHADOW5_COMMAND +#define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW5_IO_BASE_LIMIT +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW5_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW5_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW5_PREF_BASE_UPPER +#define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW5_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW5_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW5_SLOT_CAP +#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW5_ROOT_CNTL +#define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW5_DEVICE_CNTL2 +#define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp +//NB_PCIE0SHADOW6_COMMAND +#define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY +#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_PCIE0SHADOW6_IO_BASE_LIMIT +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_PCIE0SHADOW6_MEM_BASE_LIMIT +#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW6_PREF_BASE_LIMIT +#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_PCIE0SHADOW6_PREF_BASE_UPPER +#define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW6_PREF_LIMIT_UPPER +#define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL +#define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_PCIE0SHADOW6_PMI_STATUS_CNTL +#define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_PCIE0SHADOW6_SLOT_CAP +#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_PCIE0SHADOW6_ROOT_CNTL +#define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_PCIE0SHADOW6_DEVICE_CNTL2 +#define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp +//NB_NBIF1SHADOW0_COMMAND +#define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY +#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_NBIF1SHADOW0_IO_BASE_LIMIT +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_NBIF1SHADOW0_MEM_BASE_LIMIT +#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_NBIF1SHADOW0_PREF_BASE_LIMIT +#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_NBIF1SHADOW0_PREF_BASE_UPPER +#define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_NBIF1SHADOW0_PREF_LIMIT_UPPER +#define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL +#define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_NBIF1SHADOW0_PMI_STATUS_CNTL +#define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_NBIF1SHADOW0_SLOT_CAP +#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_NBIF1SHADOW0_ROOT_CNTL +#define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_NBIF1SHADOW0_DEVICE_CNTL2 +#define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp +//NB_NBIF1SHADOW1_COMMAND +#define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY +#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//NB_NBIF1SHADOW1_IO_BASE_LIMIT +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//NB_NBIF1SHADOW1_MEM_BASE_LIMIT +#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_NBIF1SHADOW1_PREF_BASE_LIMIT +#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//NB_NBIF1SHADOW1_PREF_BASE_UPPER +#define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//NB_NBIF1SHADOW1_PREF_LIMIT_UPPER +#define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL +#define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//NB_NBIF1SHADOW1_PMI_STATUS_CNTL +#define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//NB_NBIF1SHADOW1_SLOT_CAP +#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//NB_NBIF1SHADOW1_ROOT_CNTL +#define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//NB_NBIF1SHADOW1_DEVICE_CNTL2 +#define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L + + +// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec +//FASTREG_APERTURE +#define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT 0x0 +#define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT 0x10 +#define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT 0x1f +#define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK 0x00000FFFL +#define FASTREG_APERTURE__FASTREG_NODE_ID_MASK 0x000F0000L +#define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK 0x80000000L + + +// addressBlock: nbio_iohub_nb_misc_misc_cfgdec +//NB_CNTL +#define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7 +#define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L +//NB_SPARE1 +#define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0 +#define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL +//NB_SPARE2 +#define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0 +#define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1 +#define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2 +#define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3 +#define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4 +#define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5 +#define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6 +#define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7 +#define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8 +#define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9 +#define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa +#define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb +#define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc +#define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd +#define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe +#define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf +#define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10 +#define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11 +#define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12 +#define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13 +#define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14 +#define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15 +#define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16 +#define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17 +#define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18 +#define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19 +#define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a +#define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b +#define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c +#define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d +#define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e +#define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f +#define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L +#define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L +#define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L +#define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L +#define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L +#define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L +#define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L +#define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L +#define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L +#define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L +#define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L +#define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L +#define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L +#define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L +#define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L +#define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L +#define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L +#define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L +#define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L +#define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L +#define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L +#define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L +#define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L +#define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L +#define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L +#define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L +#define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L +#define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L +#define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L +#define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L +#define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L +#define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L +//NB_REVID +#define NB_REVID__REVISION_ID__SHIFT 0x0 +#define NB_REVID__REVISION_ID_MASK 0x000003FFL +//IOHC_REFCLK_MODE +#define IOHC_REFCLK_MODE__MODE_100MHZ__SHIFT 0x0 +#define IOHC_REFCLK_MODE__MODE_25MHZ__SHIFT 0x1 +#define IOHC_REFCLK_MODE__MODE_27MHZ__SHIFT 0x2 +#define IOHC_REFCLK_MODE__MODE_100MHZ_MASK 0x00000001L +#define IOHC_REFCLK_MODE__MODE_25MHZ_MASK 0x00000002L +#define IOHC_REFCLK_MODE__MODE_27MHZ_MASK 0x00000004L +//IOHC_PCIE_CRS_Count +#define IOHC_PCIE_CRS_Count__CrsDelayCount__SHIFT 0x0 +#define IOHC_PCIE_CRS_Count__CrsLimitCount__SHIFT 0x10 +#define IOHC_PCIE_CRS_Count__CrsDelayCount_MASK 0x0000FFFFL +#define IOHC_PCIE_CRS_Count__CrsLimitCount_MASK 0x0FFF0000L +//IOHC_P2P_CNTL +#define IOHC_P2P_CNTL__DLDownResetEn__SHIFT 0xb +#define IOHC_P2P_CNTL__DLDownResetEn_MASK 0x00000800L +//CFG_IOHC_PCI +#define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn__SHIFT 0x0 +#define CFG_IOHC_PCI__IOMMU_DIS__SHIFT 0x1f +#define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn_MASK 0x00000001L +#define CFG_IOHC_PCI__IOMMU_DIS_MASK 0x80000000L +//NB_BUS_NUM_CNTL +#define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0 +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8 +#define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L +//IOHC_AER_CNTL +#define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN__SHIFT 0x1 +#define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN_MASK 0x00000002L +//NB_MMIOBASE +#define NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//NB_MMIOLIMIT +#define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//NB_LOWER_TOP_OF_DRAM2 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//NB_UPPER_TOP_OF_DRAM2 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL +//NB_LOWER_DRAM2_BASE +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17 +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L +//NB_UPPER_DRAM2_BASE +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0 +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL +//SB_LOCATION +#define SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//IOHC_GLUE_CG_LCLK_CTRL_0 +#define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOHC_GLUE_CG_LCLK_CTRL_1 +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOHC_GLUE_CG_LCLK_CTRL_2 +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOHC_PERF_CNTL +#define IOHC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 +#define IOHC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 +#define IOHC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 +#define IOHC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 +#define IOHC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL +#define IOHC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L +#define IOHC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L +#define IOHC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L +//IOHC_PERF_COUNT0 +#define IOHC_PERF_COUNT0__COUNTER0__SHIFT 0x0 +#define IOHC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL +//IOHC_PERF_COUNT0_UPPER +#define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 +#define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL +//IOHC_PERF_COUNT1 +#define IOHC_PERF_COUNT1__COUNTER1__SHIFT 0x0 +#define IOHC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL +//IOHC_PERF_COUNT1_UPPER +#define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 +#define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL +//IOHC_PERF_COUNT2 +#define IOHC_PERF_COUNT2__COUNTER2__SHIFT 0x0 +#define IOHC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL +//IOHC_PERF_COUNT2_UPPER +#define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 +#define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL +//IOHC_PERF_COUNT3 +#define IOHC_PERF_COUNT3__COUNTER3__SHIFT 0x0 +#define IOHC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL +//IOHC_PERF_COUNT3_UPPER +#define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 +#define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL +//NB_PROG_DEVICE_REMAP_PBr0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr1 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr2 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr3 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr4 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr5 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr6 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr7 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr8 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL +//SW_NMI_CNTL +#define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0 +#define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL +//SW_SMI_CNTL +#define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0 +#define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL +//SW_SCI_CNTL +#define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0 +#define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL +//APML_SW_STATUS +#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0 +#define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L +//IOHC_FEATURE_CNTL +#define IOHC_FEATURE_CNTL__HpPmpme_DevID_En__SHIFT 0x0 +#define IOHC_FEATURE_CNTL__P2P_mode__SHIFT 0x1 +#define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE__SHIFT 0x3 +#define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED__SHIFT 0x16 +#define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE__SHIFT 0x1c +#define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL__SHIFT 0x1d +#define IOHC_FEATURE_CNTL__HpPmpme_DevID_En_MASK 0x00000001L +#define IOHC_FEATURE_CNTL__P2P_mode_MASK 0x00000006L +#define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE_MASK 0x00000008L +#define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED_MASK 0x00400000L +#define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE_MASK 0x10000000L +#define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL_MASK 0xE0000000L +//SW_GIC_SPI_CNTL +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0 +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8 +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10 +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L +//IOHC_INTERRUPT_EOI +#define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT 0x0 +#define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT 0x1 +#define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT 0x2 +#define IOHC_INTERRUPT_EOI__SMI_EOI_MASK 0x00000001L +#define IOHC_INTERRUPT_EOI__SCI_EOI_MASK 0x00000002L +#define IOHC_INTERRUPT_EOI__NMI_EOI_MASK 0x00000004L +//SW_SYNCFLOOD_CNTL +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L +//IOHC_PIN_CNTL +#define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE__SHIFT 0x0 +#define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE_MASK 0x00000001L +//IOHC_INTR_CNTL +#define IOHC_INTR_CNTL__NMI_DEST_ctrl__SHIFT 0x8 +#define IOHC_INTR_CNTL__NMI_DEST_ctrl_MASK 0x0000FF00L +//IOHC_FEATURE_CNTL2 +#define IOHC_FEATURE_CNTL2__NMI_status__SHIFT 0x0 +#define IOHC_FEATURE_CNTL2__SErr_status__SHIFT 0x1 +#define IOHC_FEATURE_CNTL2__CrsStatus__SHIFT 0x10 +#define IOHC_FEATURE_CNTL2__P_DMA_DROPPED__SHIFT 0x11 +#define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED__SHIFT 0x12 +#define IOHC_FEATURE_CNTL2__NMI_status_MASK 0x00000001L +#define IOHC_FEATURE_CNTL2__SErr_status_MASK 0x00000002L +#define IOHC_FEATURE_CNTL2__CrsStatus_MASK 0x00010000L +#define IOHC_FEATURE_CNTL2__P_DMA_DROPPED_MASK 0x00020000L +#define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED_MASK 0x00040000L +//NB_TOP_OF_DRAM3 +#define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 +#define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f +#define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL +#define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L +//CAM_CONTROL +#define CAM_CONTROL__CAM_En__SHIFT 0x0 +#define CAM_CONTROL__Op__SHIFT 0x1 +#define CAM_CONTROL__AccessType__SHIFT 0x2 +#define CAM_CONTROL__DataMatchEn__SHIFT 0x3 +#define CAM_CONTROL__VC__SHIFT 0x4 +#define CAM_CONTROL__CrossTrigger__SHIFT 0x8 +#define CAM_CONTROL__CAM_En_MASK 0x00000001L +#define CAM_CONTROL__Op_MASK 0x00000002L +#define CAM_CONTROL__AccessType_MASK 0x00000004L +#define CAM_CONTROL__DataMatchEn_MASK 0x00000008L +#define CAM_CONTROL__VC_MASK 0x00000070L +#define CAM_CONTROL__CrossTrigger_MASK 0x0000FF00L +//CAM_TARGET_INDEX_ADDR_BOTTOM +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_ADDR_TOP +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA +#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA_MASK +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_BOTTOM +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_TOP +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA +#define CAM_TARGET_DATA__Data__SHIFT 0x0 +#define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_MASK +#define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0 +#define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL +//P_DMA_DROPPED_LOG_LOWER +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//P_DMA_DROPPED_LOG_UPPER +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_LOWER +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_UPPER +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//PCIE_VDM_NODE0_CTRL4 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8 +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L +//PCIE_VDM_CNTL2 +#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0 +#define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4 +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5 +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6 +#define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT 0xf +#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L +#define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L +#define PCIE_VDM_CNTL2__MCTPMasterValid_MASK 0x00008000L +#define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L +//PCIE_VDM_CNTL3 +#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf +#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L +#define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L +//STALL_CONTROL_XBARPORT0_0 +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT0_1 +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_0 +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_1 +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_0 +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_1 +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_0 +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_1 +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_0 +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_1 +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L +//NB_DRAM3_BASE +#define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0 +#define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL +//PSP_BASE_ADDR_LO +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0 +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8 +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14 +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L +//PSP_BASE_ADDR_HI +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0 +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL +//SMU_BASE_ADDR_LO +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0 +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1 +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14 +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L +//SMU_BASE_ADDR_HI +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0 +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL +//IOAPIC_BASE_ADDR_LO +#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN__SHIFT 0x0 +#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK__SHIFT 0x1 +#define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO__SHIFT 0x8 +#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN_MASK 0x00000001L +#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK_MASK 0x00000002L +#define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO_MASK 0xFFFFFF00L +//IOAPIC_BASE_ADDR_HI +#define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI__SHIFT 0x0 +#define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI_MASK 0x0000FFFFL +//FASTREG_BASE_ADDR_LO +#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT 0x0 +#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT 0x1 +#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT 0x14 +#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK 0x00000001L +#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK 0x00000002L +#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK 0xFFF00000L +//FASTREG_BASE_ADDR_HI +#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT 0x0 +#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK 0x0000FFFFL +//FASTREGCNTL_BASE_ADDR_LO +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT 0x0 +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT 0x1 +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT 0xc +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK 0x00000001L +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK 0x00000002L +#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK 0xFFFFF000L +//FASTREGCNTL_BASE_ADDR_HI +#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT 0x0 +#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK 0x0000FFFFL +//SMMU_BASE_ADDR_LO +#define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN__SHIFT 0x0 +#define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK__SHIFT 0x1 +#define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO__SHIFT 0x13 +#define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN_MASK 0x00000001L +#define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK_MASK 0x00000002L +#define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO_MASK 0xFFF80000L +//SMMU_BASE_ADDR_HI +#define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI__SHIFT 0x0 +#define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI_MASK 0x0000FFFFL +//IOHC_PGMST_CNTL +#define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 +#define IOHC_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 +#define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define IOHC_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L +#define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//IOHC_SDP_PORT_CONTROL +#define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 +#define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis__SHIFT 0x6 +#define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf +#define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10 +#define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL +#define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis_MASK 0x00000FC0L +#define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L +#define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L +//IOHC_SDP_PARITY_CONTROL +#define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis__SHIFT 0x0 +#define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis_MASK 0x00000001L +//IOHC_PGSLV_CNTL +#define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//SCRATCH_4 +#define SCRATCH_4__SCRATCH_4__SHIFT 0x0 +#define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL +//SCRATCH_5 +#define SCRATCH_5__SCRATCH_5__SHIFT 0x0 +#define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL +//SMU_BLOCK_CPU +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0 +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L +//SMU_BLOCK_CPU_STATUS +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0 +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L +//TRAP_STATUS +#define TRAP_STATUS__TrapReqValid__SHIFT 0x0 +#define TRAP_STATUS__TrapNumber__SHIFT 0x8 +#define TRAP_STATUS__TrapReqValid_MASK 0x00000001L +#define TRAP_STATUS__TrapNumber_MASK 0x00000F00L +//TRAP_REQUEST0 +#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2 +#define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL +//TRAP_REQUEST1 +#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0 +#define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL +//TRAP_REQUEST2 +#define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0 +#define TRAP_REQUEST2__TrapAttr__SHIFT 0x8 +#define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10 +#define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL +#define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L +#define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L +//TRAP_REQUEST3 +#define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0 +#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4 +#define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6 +#define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7 +#define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8 +#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9 +#define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10 +#define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L +#define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L +#define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L +#define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L +#define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L +#define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L +#define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L +//TRAP_REQUEST4 +#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0 +#define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x00000007L +//TRAP_REQUEST5 +#define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0 +#define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4 +#define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8 +#define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L +#define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L +#define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L +//TRAP_REQUEST_DATASTRB0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATASTRB1 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA0 +#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0 +#define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA1 +#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0 +#define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA2 +#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0 +#define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA3 +#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0 +#define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA4 +#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0 +#define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA5 +#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0 +#define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA6 +#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0 +#define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA7 +#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0 +#define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA8 +#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0 +#define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA9 +#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0 +#define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA10 +#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0 +#define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA11 +#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0 +#define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA12 +#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0 +#define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA13 +#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0 +#define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA14 +#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0 +#define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA15 +#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0 +#define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_CONTROL +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0 +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L +//TRAP_RESPONSE0 +#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0 +#define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4 +#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10 +#define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L +#define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L +#define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x000F0000L +//TRAP_RESPONSE_DATA0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA1 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA2 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA3 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA4 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA5 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA6 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA7 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA8 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA9 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA10 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA11 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA12 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA13 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA14 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA15 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL +//TRAP0_CONTROL0 +#define TRAP0_CONTROL0__Trap0En__SHIFT 0x0 +#define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3 +#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18 +#define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L +#define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L +#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0xFF000000L +//TRAP0_ADDRESS_LO +#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2 +#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI +#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0 +#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0x0000FFFFL +//TRAP0_COMMAND +#define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0 +#define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8 +#define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL +#define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L +//TRAP0_ADDRESS_LO_MASK +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2 +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI_MASK +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0 +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0x0000FFFFL +//TRAP0_COMMAND_MASK +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0 +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8 +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L +//TRAP1_CONTROL0 +#define TRAP1_CONTROL0__Trap1En__SHIFT 0x0 +#define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3 +#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18 +#define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L +#define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L +#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0xFF000000L +//TRAP1_ADDRESS_LO +#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2 +#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI +#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0 +#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0x0000FFFFL +//TRAP1_COMMAND +#define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0 +#define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8 +#define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL +#define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L +//TRAP1_ADDRESS_LO_MASK +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2 +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI_MASK +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0 +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0x0000FFFFL +//TRAP1_COMMAND_MASK +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0 +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8 +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L +//TRAP2_CONTROL0 +#define TRAP2_CONTROL0__Trap2En__SHIFT 0x0 +#define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3 +#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18 +#define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L +#define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L +#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0xFF000000L +//TRAP2_ADDRESS_LO +#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2 +#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI +#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0 +#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0x0000FFFFL +//TRAP2_COMMAND +#define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0 +#define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8 +#define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL +#define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L +//TRAP2_ADDRESS_LO_MASK +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2 +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI_MASK +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0 +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0x0000FFFFL +//TRAP2_COMMAND_MASK +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0 +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8 +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L +//TRAP3_CONTROL0 +#define TRAP3_CONTROL0__Trap3En__SHIFT 0x0 +#define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3 +#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18 +#define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L +#define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L +#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0xFF000000L +//TRAP3_ADDRESS_LO +#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2 +#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI +#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0 +#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0x0000FFFFL +//TRAP3_COMMAND +#define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0 +#define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8 +#define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL +#define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L +//TRAP3_ADDRESS_LO_MASK +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2 +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI_MASK +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0 +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0x0000FFFFL +//TRAP3_COMMAND_MASK +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0 +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8 +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L +//TRAP4_CONTROL0 +#define TRAP4_CONTROL0__Trap4En__SHIFT 0x0 +#define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3 +#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18 +#define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L +#define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L +#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0xFF000000L +//TRAP4_ADDRESS_LO +#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2 +#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI +#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0 +#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0x0000FFFFL +//TRAP4_COMMAND +#define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0 +#define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8 +#define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL +#define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L +//TRAP4_ADDRESS_LO_MASK +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2 +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI_MASK +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0 +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0x0000FFFFL +//TRAP4_COMMAND_MASK +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0 +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8 +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L +//TRAP5_CONTROL0 +#define TRAP5_CONTROL0__Trap5En__SHIFT 0x0 +#define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3 +#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18 +#define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L +#define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L +#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0xFF000000L +//TRAP5_ADDRESS_LO +#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2 +#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI +#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0 +#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0x0000FFFFL +//TRAP5_COMMAND +#define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0 +#define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8 +#define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL +#define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L +//TRAP5_ADDRESS_LO_MASK +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2 +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI_MASK +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0 +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0x0000FFFFL +//TRAP5_COMMAND_MASK +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0 +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8 +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L +//TRAP6_CONTROL0 +#define TRAP6_CONTROL0__Trap6En__SHIFT 0x0 +#define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3 +#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18 +#define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L +#define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L +#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0xFF000000L +//TRAP6_ADDRESS_LO +#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2 +#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI +#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0 +#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0x0000FFFFL +//TRAP6_COMMAND +#define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0 +#define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8 +#define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL +#define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L +//TRAP6_ADDRESS_LO_MASK +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2 +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI_MASK +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0 +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0x0000FFFFL +//TRAP6_COMMAND_MASK +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0 +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8 +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L +//TRAP7_CONTROL0 +#define TRAP7_CONTROL0__Trap7En__SHIFT 0x0 +#define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3 +#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18 +#define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L +#define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L +#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0xFF000000L +//TRAP7_ADDRESS_LO +#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2 +#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI +#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0 +#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0x0000FFFFL +//TRAP7_COMMAND +#define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0 +#define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8 +#define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL +#define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L +//TRAP7_ADDRESS_LO_MASK +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2 +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI_MASK +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0 +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0x0000FFFFL +//TRAP7_COMMAND_MASK +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0 +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8 +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L +//TRAP8_CONTROL0 +#define TRAP8_CONTROL0__Trap8En__SHIFT 0x0 +#define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3 +#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18 +#define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L +#define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L +#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0xFF000000L +//TRAP8_ADDRESS_LO +#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2 +#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI +#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0 +#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0x0000FFFFL +//TRAP8_COMMAND +#define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0 +#define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8 +#define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL +#define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L +//TRAP8_ADDRESS_LO_MASK +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2 +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI_MASK +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0 +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0x0000FFFFL +//TRAP8_COMMAND_MASK +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0 +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8 +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L +//TRAP9_CONTROL0 +#define TRAP9_CONTROL0__Trap9En__SHIFT 0x0 +#define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3 +#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18 +#define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L +#define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L +#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0xFF000000L +//TRAP9_ADDRESS_LO +#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2 +#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI +#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0 +#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0x0000FFFFL +//TRAP9_COMMAND +#define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0 +#define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8 +#define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL +#define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L +//TRAP9_ADDRESS_LO_MASK +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2 +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI_MASK +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0 +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0x0000FFFFL +//TRAP9_COMMAND_MASK +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0 +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8 +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L +//TRAP10_CONTROL0 +#define TRAP10_CONTROL0__Trap10En__SHIFT 0x0 +#define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3 +#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18 +#define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L +#define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L +#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0xFF000000L +//TRAP10_ADDRESS_LO +#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2 +#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI +#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0 +#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0x0000FFFFL +//TRAP10_COMMAND +#define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0 +#define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8 +#define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL +#define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L +//TRAP10_ADDRESS_LO_MASK +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2 +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI_MASK +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0 +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0x0000FFFFL +//TRAP10_COMMAND_MASK +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0 +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8 +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L +//TRAP11_CONTROL0 +#define TRAP11_CONTROL0__Trap11En__SHIFT 0x0 +#define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3 +#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18 +#define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L +#define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L +#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0xFF000000L +//TRAP11_ADDRESS_LO +#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2 +#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI +#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0 +#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0x0000FFFFL +//TRAP11_COMMAND +#define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0 +#define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8 +#define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL +#define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L +//TRAP11_ADDRESS_LO_MASK +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2 +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI_MASK +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0 +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0x0000FFFFL +//TRAP11_COMMAND_MASK +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0 +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8 +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L +//TRAP12_CONTROL0 +#define TRAP12_CONTROL0__Trap12En__SHIFT 0x0 +#define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3 +#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18 +#define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L +#define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L +#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0xFF000000L +//TRAP12_ADDRESS_LO +#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2 +#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI +#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0 +#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0x0000FFFFL +//TRAP12_COMMAND +#define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0 +#define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8 +#define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL +#define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L +//TRAP12_ADDRESS_LO_MASK +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2 +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI_MASK +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0 +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0x0000FFFFL +//TRAP12_COMMAND_MASK +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0 +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8 +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L +//TRAP13_CONTROL0 +#define TRAP13_CONTROL0__Trap13En__SHIFT 0x0 +#define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3 +#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18 +#define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L +#define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L +#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0xFF000000L +//TRAP13_ADDRESS_LO +#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2 +#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI +#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0 +#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0x0000FFFFL +//TRAP13_COMMAND +#define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0 +#define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8 +#define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL +#define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L +//TRAP13_ADDRESS_LO_MASK +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2 +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI_MASK +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0 +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0x0000FFFFL +//TRAP13_COMMAND_MASK +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0 +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8 +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L +//TRAP14_CONTROL0 +#define TRAP14_CONTROL0__Trap14En__SHIFT 0x0 +#define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3 +#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18 +#define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L +#define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L +#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0xFF000000L +//TRAP14_ADDRESS_LO +#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2 +#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI +#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0 +#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0x0000FFFFL +//TRAP14_COMMAND +#define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0 +#define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8 +#define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL +#define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L +//TRAP14_ADDRESS_LO_MASK +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2 +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI_MASK +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0 +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0x0000FFFFL +//TRAP14_COMMAND_MASK +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0 +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8 +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L +//TRAP15_CONTROL0 +#define TRAP15_CONTROL0__Trap15En__SHIFT 0x0 +#define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3 +#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18 +#define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L +#define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L +#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0xFF000000L +//TRAP15_ADDRESS_LO +#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2 +#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI +#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0 +#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0x0000FFFFL +//TRAP15_COMMAND +#define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0 +#define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8 +#define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL +#define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L +//TRAP15_ADDRESS_LO_MASK +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2 +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI_MASK +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0 +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0x0000FFFFL +//TRAP15_COMMAND_MASK +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0 +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8 +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L +//IOHC_REQDECODE_OVERRIDE +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18 +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L +#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L +//IOHC_RSPDECODE_OVERRIDE +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18 +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L +#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L +//IOHC_RSPPASSPW_OVERRIDE +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0__SHIFT 0x0 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1__SHIFT 0x4 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2__SHIFT 0x8 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3__SHIFT 0xc +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4__SHIFT 0x10 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5__SHIFT 0x14 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6__SHIFT 0x18 +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7__SHIFT 0x1c +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0_MASK 0x0000000FL +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1_MASK 0x000000F0L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2_MASK 0x00000F00L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3_MASK 0x0000F000L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4_MASK 0x000F0000L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5_MASK 0x00F00000L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6_MASK 0x0F000000L +#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7_MASK 0xF0000000L +//IOHC_USERBIT_BYPASS +#define IOHC_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0 +#define IOHC_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L +//IOHC_SMN_MASTER_CNTL +#define IOHC_SMN_MASTER_CNTL__SmnErrRspMap__SHIFT 0x0 +#define IOHC_SMN_MASTER_CNTL__SmnErrRspMap_MASK 0x00000001L +//IOHC_SMN_MASTER_STATUS +#define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus__SHIFT 0x0 +#define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus_MASK 0x00000001L +//SB_COMMAND +#define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//SB_SUB_BUS_NUMBER_LATENCY +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//SB_IO_BASE_LIMIT +#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//SB_MEM_BASE_LIMIT +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_LIMIT +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_UPPER +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//SB_PREF_LIMIT_UPPER +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//SB_IO_BASE_LIMIT_HI +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//SB_IRQ_BRIDGE_CNTL +#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//SB_EXT_BRIDGE_CNTL +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//SB_PMI_STATUS_CNTL +#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//SB_SLOT_CAP +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//SB_ROOT_CNTL +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//SB_DEVICE_CNTL2 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +//IOHC_QOS_CONTROL +#define IOHC_QOS_CONTROL__VC0QoSPriority__SHIFT 0x0 +#define IOHC_QOS_CONTROL__VC1QoSPriority__SHIFT 0x4 +#define IOHC_QOS_CONTROL__VC2QoSPriority__SHIFT 0x8 +#define IOHC_QOS_CONTROL__VC3QoSPriority__SHIFT 0xc +#define IOHC_QOS_CONTROL__VC4QoSPriority__SHIFT 0x10 +#define IOHC_QOS_CONTROL__VC5QoSPriority__SHIFT 0x14 +#define IOHC_QOS_CONTROL__VC6QoSPriority__SHIFT 0x18 +#define IOHC_QOS_CONTROL__VC7QoSPriority__SHIFT 0x1c +#define IOHC_QOS_CONTROL__VC0QoSPriority_MASK 0x0000000FL +#define IOHC_QOS_CONTROL__VC1QoSPriority_MASK 0x000000F0L +#define IOHC_QOS_CONTROL__VC2QoSPriority_MASK 0x00000F00L +#define IOHC_QOS_CONTROL__VC3QoSPriority_MASK 0x0000F000L +#define IOHC_QOS_CONTROL__VC4QoSPriority_MASK 0x000F0000L +#define IOHC_QOS_CONTROL__VC5QoSPriority_MASK 0x00F00000L +#define IOHC_QOS_CONTROL__VC6QoSPriority_MASK 0x0F000000L +#define IOHC_QOS_CONTROL__VC7QoSPriority_MASK 0xF0000000L +//USB_QoS_CNTL +#define USB_QoS_CNTL__UnitID0__SHIFT 0x0 +#define USB_QoS_CNTL__UnitID0QoSPriority__SHIFT 0x8 +#define USB_QoS_CNTL__UnitID0Enable__SHIFT 0xc +#define USB_QoS_CNTL__UnitID1__SHIFT 0x10 +#define USB_QoS_CNTL__UnitID1QoSPriority__SHIFT 0x18 +#define USB_QoS_CNTL__UnitID1Enable__SHIFT 0x1c +#define USB_QoS_CNTL__UnitID0_MASK 0x0000007FL +#define USB_QoS_CNTL__UnitID0QoSPriority_MASK 0x00000F00L +#define USB_QoS_CNTL__UnitID0Enable_MASK 0x00001000L +#define USB_QoS_CNTL__UnitID1_MASK 0x007F0000L +#define USB_QoS_CNTL__UnitID1QoSPriority_MASK 0x0F000000L +#define USB_QoS_CNTL__UnitID1Enable_MASK 0x10000000L +//IOHC_SION_S0_Client0_Req_BurstTarget_Lower +#define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_Req_BurstTarget_Upper +#define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_Req_TimeSlot_Lower +#define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_Req_TimeSlot_Upper +#define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_Req_BurstTarget_Lower +#define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_Req_BurstTarget_Upper +#define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_Req_TimeSlot_Lower +#define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_Req_TimeSlot_Upper +#define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower +#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper +#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_DataPoolCredit_Alloc_Lower +#define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_DataPoolCredit_Alloc_Upper +#define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_Req_BurstTarget_Lower +#define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_Req_BurstTarget_Upper +#define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_Req_TimeSlot_Lower +#define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_Req_TimeSlot_Upper +#define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_Req_BurstTarget_Lower +#define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_Req_BurstTarget_Upper +#define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_Req_TimeSlot_Lower +#define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_Req_TimeSlot_Upper +#define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower +#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper +#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_DataPoolCredit_Alloc_Lower +#define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_DataPoolCredit_Alloc_Upper +#define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_Req_BurstTarget_Lower +#define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_Req_BurstTarget_Upper +#define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_Req_TimeSlot_Lower +#define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_Req_TimeSlot_Upper +#define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_Req_BurstTarget_Lower +#define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_Req_BurstTarget_Upper +#define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_Req_TimeSlot_Lower +#define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_Req_TimeSlot_Upper +#define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower +#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper +#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_DataPoolCredit_Alloc_Lower +#define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_DataPoolCredit_Alloc_Upper +#define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_Req_BurstTarget_Lower +#define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_Req_BurstTarget_Upper +#define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_Req_TimeSlot_Lower +#define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_Req_TimeSlot_Upper +#define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_Req_BurstTarget_Lower +#define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_Req_BurstTarget_Upper +#define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_Req_TimeSlot_Lower +#define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_Req_TimeSlot_Upper +#define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower +#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper +#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_DataPoolCredit_Alloc_Lower +#define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_DataPoolCredit_Alloc_Upper +#define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_Req_BurstTarget_Lower +#define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_Req_BurstTarget_Upper +#define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_Req_TimeSlot_Lower +#define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_Req_TimeSlot_Upper +#define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower +#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper +#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower +#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper +#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_Req_BurstTarget_Lower +#define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_Req_BurstTarget_Upper +#define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_Req_TimeSlot_Lower +#define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_Req_TimeSlot_Upper +#define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower +#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper +#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower +#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper +#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower +#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper +#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_DataPoolCredit_Alloc_Lower +#define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_DataPoolCredit_Alloc_Upper +#define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower +#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper +#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOHC_SION_LiveLock_WatchDog_Threshold +#define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0 +#define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL + + +// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec +//PARITY_CONTROL_0 +#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0 +#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10 +#define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL +#define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L +//PARITY_CONTROL_1 +#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0 +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8 +#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb +#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10 +#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e +#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f +#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L +#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L +#define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L +#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L +#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L +//PARITY_SEVERITY_CONTROL_UNCORR_0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L +//PARITY_SEVERITY_CONTROL_CORR_0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L +//PARITY_SEVERITY_CONTROL_UCP_0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L +//RAS_GLOBAL_STATUS_LO +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9 +#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa +#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb +#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L +#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L +#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L +#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L +#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L +//RAS_GLOBAL_STATUS_HI +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK 0x00000100L +//PARITY_ERROR_STATUS_UNCORR_GRP0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP0 +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP1 +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP2 +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP3 +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP4 +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP0 +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP1 +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP2 +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP3 +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP4 +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L +//MISC_SEVERITY_CONTROL +#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4 +#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6 +#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L +#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L +//MISC_RAS_CONTROL +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2 +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3 +#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9 +#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa +#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb +#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc +#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd +#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe +#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf +#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10 +#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11 +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L +#define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L +#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L +#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L +#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L +#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L +#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L +#define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L +#define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L +#define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L +//RAS_SCRATCH_0 +#define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//RAS_SCRATCH_1 +#define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL +//ErrEvent_ACTION_CONTROL +#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParitySerr_ACTION_CONTROL +#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityFatal_ACTION_CONTROL +#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityNonFatal_ACTION_CONTROL +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityCorr_ACTION_CONTROL +#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortASerr_ACTION_CONTROL +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntFatal_ACTION_CONTROL +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntNonFatal_ACTION_CONTROL +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntCorr_ACTION_CONTROL +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtFatal_ACTION_CONTROL +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtNonFatal_ACTION_CONTROL +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtCorr_ACTION_CONTROL +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAParityErr_ACTION_CONTROL +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBSerr_ACTION_CONTROL +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntFatal_ACTION_CONTROL +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntNonFatal_ACTION_CONTROL +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntCorr_ACTION_CONTROL +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtFatal_ACTION_CONTROL +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtNonFatal_ACTION_CONTROL +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtCorr_ACTION_CONTROL +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBParityErr_ACTION_CONTROL +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCSerr_ACTION_CONTROL +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntFatal_ACTION_CONTROL +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntNonFatal_ACTION_CONTROL +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntCorr_ACTION_CONTROL +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtFatal_ACTION_CONTROL +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtNonFatal_ACTION_CONTROL +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtCorr_ACTION_CONTROL +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCParityErr_ACTION_CONTROL +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDSerr_ACTION_CONTROL +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntFatal_ACTION_CONTROL +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntNonFatal_ACTION_CONTROL +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntCorr_ACTION_CONTROL +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtFatal_ACTION_CONTROL +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtNonFatal_ACTION_CONTROL +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtCorr_ACTION_CONTROL +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDParityErr_ACTION_CONTROL +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortESerr_ACTION_CONTROL +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntFatal_ACTION_CONTROL +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntNonFatal_ACTION_CONTROL +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntCorr_ACTION_CONTROL +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtFatal_ACTION_CONTROL +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtNonFatal_ACTION_CONTROL +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtCorr_ACTION_CONTROL +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEParityErr_ACTION_CONTROL +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFSerr_ACTION_CONTROL +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntFatal_ACTION_CONTROL +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntNonFatal_ACTION_CONTROL +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntCorr_ACTION_CONTROL +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtFatal_ACTION_CONTROL +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtNonFatal_ACTION_CONTROL +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtCorr_ACTION_CONTROL +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFParityErr_ACTION_CONTROL +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGSerr_ACTION_CONTROL +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntFatal_ACTION_CONTROL +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntNonFatal_ACTION_CONTROL +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntCorr_ACTION_CONTROL +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtFatal_ACTION_CONTROL +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtNonFatal_ACTION_CONTROL +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtCorr_ACTION_CONTROL +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGParityErr_ACTION_CONTROL +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortASerr_ACTION_CONTROL +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntFatal_ACTION_CONTROL +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntNonFatal_ACTION_CONTROL +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntCorr_ACTION_CONTROL +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtFatal_ACTION_CONTROL +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtNonFatal_ACTION_CONTROL +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtCorr_ACTION_CONTROL +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAParityErr_ACTION_CONTROL +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBSerr_ACTION_CONTROL +#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBIntFatal_ACTION_CONTROL +#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBIntNonFatal_ACTION_CONTROL +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBIntCorr_ACTION_CONTROL +#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBExtFatal_ACTION_CONTROL +#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBExtNonFatal_ACTION_CONTROL +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBExtCorr_ACTION_CONTROL +#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortBParityErr_ACTION_CONTROL +#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//SYNCFLOOD_STATUS +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0 +#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1 +#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2 +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT 0x8 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT 0x9 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT 0xa +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT 0xb +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT 0xc +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT 0xd +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT 0xe +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT 0xf +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT 0x10 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT 0x11 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT 0x12 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT 0x13 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT 0x14 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT 0x15 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT 0x16 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT 0x17 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT 0x18 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT 0x19 +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT 0x1a +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT 0x1b +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT 0x1c +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT 0x1d +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT 0x1e +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT 0x1f +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L +#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L +#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK 0x00000100L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK 0x00000200L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK 0x00000400L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK 0x00000800L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK 0x00001000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK 0x00002000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK 0x00004000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK 0x00008000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK 0x00010000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK 0x00020000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK 0x00040000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK 0x00080000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK 0x00100000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK 0x00200000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK 0x00400000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK 0x00800000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK 0x01000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK 0x02000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK 0x04000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK 0x08000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK 0x10000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK 0x20000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK 0x40000000L +#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK 0x80000000L +//NMI_STATUS +#define NMI_STATUS__NMIFromPin__SHIFT 0x0 +#define NMI_STATUS__NMIFromPin_MASK 0x00000001L +//POISON_ACTION_CONTROL +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0 +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1 +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3 +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4 +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8 +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9 +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10 +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11 +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13 +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14 +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L +//INTERNAL_POISON_STATUS +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L +//INTERNAL_POISON_MASK +#define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0 +#define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL +//EGRESS_POISON_STATUS_LO +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L +//EGRESS_POISON_STATUS_HI +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L +//EGRESS_POISON_MASK_LO +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0 +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL +//EGRESS_POISON_MASK_HI +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0 +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_DOWN +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_UPPER +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL +//APML_STATUS +#define APML_STATUS__APML_Corr__SHIFT 0x0 +#define APML_STATUS__APML_NonFatal__SHIFT 0x1 +#define APML_STATUS__APML_Fatal__SHIFT 0x2 +#define APML_STATUS__APML_Serr__SHIFT 0x3 +#define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4 +#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5 +#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6 +#define APML_STATUS__APML_Corr_MASK 0x00000001L +#define APML_STATUS__APML_NonFatal_MASK 0x00000002L +#define APML_STATUS__APML_Fatal_MASK 0x00000004L +#define APML_STATUS__APML_Serr_MASK 0x00000008L +#define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L +#define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L +#define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L +//APML_CONTROL +#define APML_CONTROL__APML_NMI_En__SHIFT 0x0 +#define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1 +#define APML_CONTROL__APML_OutputDis__SHIFT 0x8 +#define APML_CONTROL__APML_NMI_En_MASK 0x00000001L +#define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L +#define APML_CONTROL__APML_OutputDis_MASK 0x00000100L +//APML_TRIGGER +#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0 +#define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L + + +// addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec +//PSP_SYNCFLOOD_STATUS +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl__SHIFT 0x0 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML__SHIFT 0x1 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin__SHIFT 0x2 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate__SHIFT 0x4 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8__SHIFT 0x8 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9__SHIFT 0x9 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10__SHIFT 0xa +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11__SHIFT 0xb +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12__SHIFT 0xc +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13__SHIFT 0xd +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14__SHIFT 0xe +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15__SHIFT 0xf +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16__SHIFT 0x10 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17__SHIFT 0x11 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18__SHIFT 0x12 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19__SHIFT 0x13 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20__SHIFT 0x14 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21__SHIFT 0x15 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22__SHIFT 0x16 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23__SHIFT 0x17 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24__SHIFT 0x18 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25__SHIFT 0x19 +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26__SHIFT 0x1a +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27__SHIFT 0x1b +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28__SHIFT 0x1c +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29__SHIFT 0x1d +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30__SHIFT 0x1e +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31__SHIFT 0x1f +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl_MASK 0x00000001L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML_MASK 0x00000002L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin_MASK 0x00000004L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate_MASK 0x00000010L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8_MASK 0x00000100L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9_MASK 0x00000200L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10_MASK 0x00000400L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11_MASK 0x00000800L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12_MASK 0x00001000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13_MASK 0x00002000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14_MASK 0x00004000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15_MASK 0x00008000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16_MASK 0x00010000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17_MASK 0x00020000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18_MASK 0x00040000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19_MASK 0x00080000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20_MASK 0x00100000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21_MASK 0x00200000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22_MASK 0x00400000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23_MASK 0x00800000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24_MASK 0x01000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25_MASK 0x02000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26_MASK 0x04000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27_MASK 0x08000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28_MASK 0x10000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29_MASK 0x20000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30_MASK 0x40000000L +#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31_MASK 0x80000000L +//PSP_INTERNAL_POISON_STATUS +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT 0x0 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT 0x1 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT 0x2 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT 0x3 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT 0x4 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT 0x5 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT 0x6 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT 0x7 +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK 0x00000001L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK 0x00000002L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK 0x00000004L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK 0x00000008L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK 0x00000010L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK 0x00000020L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK 0x00000040L +#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK 0x00000080L +//PSP_EGRESS_POISON_STATUS_LO +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT 0x0 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT 0x1 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT 0x2 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT 0x3 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT 0x4 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT 0x5 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT 0x6 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT 0x7 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT 0x8 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT 0x9 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT 0xa +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT 0xb +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT 0xc +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT 0xd +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT 0xe +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT 0xf +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT 0x10 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT 0x11 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT 0x12 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT 0x13 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT 0x14 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT 0x15 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT 0x16 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT 0x17 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT 0x18 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT 0x19 +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT 0x1a +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT 0x1b +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT 0x1c +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT 0x1d +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT 0x1e +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT 0x1f +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK 0x00000001L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK 0x00000002L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK 0x00000004L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK 0x00000008L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK 0x00000010L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK 0x00000020L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK 0x00000040L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK 0x00000080L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK 0x00000100L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK 0x00000200L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK 0x00000400L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK 0x00000800L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK 0x00001000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK 0x00002000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK 0x00004000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK 0x00008000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK 0x00010000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK 0x00020000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK 0x00040000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK 0x00080000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK 0x00100000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK 0x00200000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK 0x00400000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK 0x00800000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK 0x01000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK 0x02000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK 0x04000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK 0x08000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK 0x10000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK 0x20000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK 0x40000000L +#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK 0x80000000L +//PSP_EGRESS_POISON_STATUS_HI +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT 0x0 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT 0x1 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT 0x2 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT 0x3 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT 0x4 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT 0x5 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT 0x6 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT 0x7 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT 0x8 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT 0x9 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT 0xa +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT 0xb +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT 0xc +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT 0xd +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT 0xe +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT 0xf +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT 0x10 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT 0x11 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT 0x12 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT 0x13 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT 0x14 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT 0x15 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT 0x16 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT 0x17 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT 0x18 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT 0x19 +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT 0x1a +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT 0x1b +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT 0x1c +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT 0x1d +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT 0x1e +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT 0x1f +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK 0x00000001L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK 0x00000002L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK 0x00000004L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK 0x00000008L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK 0x00000010L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK 0x00000020L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK 0x00000040L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK 0x00000080L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK 0x00000100L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK 0x00000200L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK 0x00000400L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK 0x00000800L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK 0x00001000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK 0x00002000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK 0x00004000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK 0x00008000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK 0x00010000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK 0x00020000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK 0x00040000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK 0x00080000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK 0x00100000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK 0x00200000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK 0x00400000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK 0x00800000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK 0x01000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK 0x02000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK 0x04000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK 0x08000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK 0x10000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK 0x20000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK 0x40000000L +#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK 0x80000000L +//PSP_PARITY_CONTROL_0 +#define PSP_PARITY_CONTROL_0__PspParityCorrThreshold__SHIFT 0x0 +#define PSP_PARITY_CONTROL_0__PspParityUCPThreshold__SHIFT 0x10 +#define PSP_PARITY_CONTROL_0__PspParityCorrThreshold_MASK 0x0000FFFFL +#define PSP_PARITY_CONTROL_0__PspParityUCPThreshold_MASK 0xFFFF0000L +//PSP_PARITY_STATUS +#define PSP_PARITY_STATUS__ParityErrCorr__SHIFT 0x0 +#define PSP_PARITY_STATUS__ParityErrNonFatal__SHIFT 0x1 +#define PSP_PARITY_STATUS__ParityErrFatal__SHIFT 0x2 +#define PSP_PARITY_STATUS__ParityErrSerr__SHIFT 0x3 +#define PSP_PARITY_STATUS__ParityErrCorr_MASK 0x00000001L +#define PSP_PARITY_STATUS__ParityErrNonFatal_MASK 0x00000002L +#define PSP_PARITY_STATUS__ParityErrFatal_MASK 0x00000004L +#define PSP_PARITY_STATUS__ParityErrSerr_MASK 0x00000008L +//PSP_PARITY_ERROR_STATUS_UNCORR_GRP0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UNCORR_GRP1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UNCORR_GRP2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UNCORR_GRP3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UNCORR_GRP4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UCP_GRP0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UCP_GRP1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UCP_GRP2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UCP_GRP3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_UCP_GRP4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_COUNTER_UCP_GRP0 +#define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_UCP_GRP1 +#define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_UCP_GRP2 +#define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_UCP_GRP3 +#define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_UCP_GRP4 +#define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_CORR_GRP0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_CORR_GRP1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_CORR_GRP2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_CORR_GRP3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_ERROR_STATUS_CORR_GRP4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PSP_PARITY_COUNTER_CORR_GRP0 +#define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_CORR_GRP1 +#define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_CORR_GRP2 +#define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_CORR_GRP3 +#define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L +//PSP_PARITY_COUNTER_CORR_GRP4 +#define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 +#define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f +#define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L +//PSP_ParitySerr_ACTION_CONTROL +#define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +//PSP_ParityFatal_ACTION_CONTROL +#define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +//PSP_ParityNonFatal_ACTION_CONTROL +#define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +//PSP_ParityCorr_ACTION_CONTROL +#define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +//NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG0_STEERING_CNTL +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +//NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG1_STEERING_CNTL +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +//NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG2_STEERING_CNTL +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +//NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG3_STEERING_CNTL +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +//NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG4_STEERING_CNTL +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +//NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG5_STEERING_CNTL +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +//NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_PCIE0DEVINDCFG6_STEERING_CNTL +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +//NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_NBIF1DEVINDCFG0_STEERING_CNTL +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_NBIF1devindcfg1_devind_cfgdecp +//NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_NBIF1DEVINDCFG1_STEERING_CNTL +#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +//NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L +//NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L +//NB_INTSBDEVINDCFG0_STEERING_CNTL +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L +//NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +//NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_1_STATUS_COMMAND +#define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_1_CLASS_CODE_REVID +#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY0_1_HEADER_TYPE +#define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY0_1_HEADER_TYPE_W +#define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +//NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_1_STATUS_COMMAND +#define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_1_CLASS_CODE_REVID +#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY1_1_HEADER_TYPE +#define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY1_1_HEADER_TYPE_W +#define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_iohub_iommu_indcfg_iommuind_cfgdec +//IOMMU_SMN_INDEX_0 +#define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0__SHIFT 0x0 +#define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0_MASK 0xFFFFFFFFL +//IOMMU_SMN_DATA_0 +#define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0__SHIFT 0x0 +#define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0_MASK 0xFFFFFFFFL +//IOMMU_SMN_INDEX_1 +#define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1__SHIFT 0x0 +#define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1_MASK 0xFFFFFFFFL +//IOMMU_SMN_DATA_1 +#define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1__SHIFT 0x0 +#define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_ioapic_indcfg_ioapicind_cfgdec +//IOAPIC_MIO_INDEX +#define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data__SHIFT 0x0 +#define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data_MASK 0xFFFFFFFFL +//IOAPIC_MIO_DATA +#define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA__SHIFT 0x0 +#define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg1_pciercbdgind_cfgdec +//NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX +#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA +#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +//IOMMU_L2_1_IOMMU_VENDOR_ID +#define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//IOMMU_L2_1_IOMMU_DEVICE_ID +#define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//IOMMU_L2_1_IOMMU_COMMAND +#define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved1__SHIFT 0x3 +#define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved0__SHIFT 0x7 +#define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved2__SHIFT 0x9 +#define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved__SHIFT 0xb +#define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved1_MASK 0x0038L +#define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved0_MASK 0x0080L +#define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN_MASK 0x0100L +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved2_MASK 0x0200L +#define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L +#define IOMMU_L2_1_IOMMU_COMMAND__Reserved_MASK 0xF800L +//IOMMU_L2_1_IOMMU_STATUS +#define IOMMU_L2_1_IOMMU_STATUS__Reserved__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_STATUS__INT_Status__SHIFT 0x3 +#define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 +#define IOMMU_L2_1_IOMMU_STATUS__Reserved1__SHIFT 0x5 +#define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_STATUS__Reserved2__SHIFT 0x9 +#define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define IOMMU_L2_1_IOMMU_STATUS__Reserved_MASK 0x0007L +#define IOMMU_L2_1_IOMMU_STATUS__INT_Status_MASK 0x0008L +#define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST_MASK 0x0010L +#define IOMMU_L2_1_IOMMU_STATUS__Reserved1_MASK 0x00E0L +#define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L +#define IOMMU_L2_1_IOMMU_STATUS__Reserved2_MASK 0x0600L +#define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//IOMMU_L2_1_IOMMU_REVISION_ID +#define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//IOMMU_L2_1_IOMMU_REGPROG_INF +#define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//IOMMU_L2_1_IOMMU_SUB_CLASS +#define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//IOMMU_L2_1_IOMMU_BASE_CODE +#define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//IOMMU_L2_1_IOMMU_CACHE_LINE +#define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//IOMMU_L2_1_IOMMU_LATENCY +#define IOMMU_L2_1_IOMMU_LATENCY__LATENCY__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_LATENCY__LATENCY_MASK 0xFFL +//IOMMU_L2_1_IOMMU_HEADER +#define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL +//IOMMU_L2_1_IOMMU_BIST +#define IOMMU_L2_1_IOMMU_BIST__BIST_COMP__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_BIST__BIST_STRT__SHIFT 0x6 +#define IOMMU_L2_1_IOMMU_BIST__BIST_CAP__SHIFT 0x7 +#define IOMMU_L2_1_IOMMU_BIST__BIST_COMP_MASK 0x0FL +#define IOMMU_L2_1_IOMMU_BIST__BIST_STRT_MASK 0x40L +#define IOMMU_L2_1_IOMMU_BIST__BIST_CAP_MASK 0x80L +//IOMMU_L2_1_IOMMU_ADAPTER_ID +#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//IOMMU_L2_1_IOMMU_CAPABILITIES_PTR +#define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//IOMMU_L2_1_IOMMU_INTERRUPT_LINE +#define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//IOMMU_L2_1_IOMMU_INTERRUPT_PIN +#define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IOMMU_L2_1_IOMMU_CAP_HEADER +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c +#define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L +#define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L +//IOMMU_L2_1_IOMMU_CAP_BASE_LO +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL +#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L +//IOMMU_L2_1_IOMMU_CAP_BASE_HI +#define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_1_IOMMU_CAP_RANGE +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL +#define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L +#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L +//IOMMU_L2_1_IOMMU_CAP_MISC +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +#define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L +#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L +//IOMMU_L2_1_IOMMU_CAP_MISC_1 +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L +#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L +//IOMMU_L2_1_IOMMU_MSI_CAP +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 +#define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L +#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L +#define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L +//IOMMU_L2_1_IOMMU_MSI_ADDR_LO +#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 +#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L +#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL +//IOMMU_L2_1_IOMMU_MSI_ADDR_HI +#define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_1_IOMMU_MSI_DATA +#define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL +#define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L +//IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L +#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L +//IOMMU_L2_1_IOMMU_ADAPTER_ID_W +#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL +#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L +//IOMMU_L2_1_IOMMU_CONTROL_W +#define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 +#define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 +#define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa +#define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd +#define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L +#define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L +#define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L +#define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L +#define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L +#define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L +//IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L +//IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L +#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L +//IOMMU_L2_1_IOMMU_RANGE_W +#define IOMMU_L2_1_IOMMU_RANGE_W__Reserved__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 +#define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 +#define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 +#define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL +#define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L +#define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L +#define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L +#define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L +//IOMMU_L2_1_IOMMU_DSFX_CONTROL +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2_1_IOMMU_DSSX_DUMMY_0 +#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL +#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_1_IOMMU_DSCX_DUMMY_0 +#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 +#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL +#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_1_L2B_POISON_DVM_CNTRL +#define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 +#define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L +//IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L +#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L +//IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control +#define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 +#define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L +//IOMMU_L2_1_SMMU_MMIO_IDR0_W +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L +//IOMMU_L2_1_SMMU_MMIO_IDR1_W +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L +#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L +//IOMMU_L2_1_SMMU_MMIO_IDR2_W +#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa +#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL +#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L +//IOMMU_L2_1_SMMU_MMIO_IDR3_W +#define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 +#define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L +//IOMMU_L2_1_SMMU_MMIO_IDR5_W +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L +#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L +//IOMMU_L2_1_SMMU_MMIO_IIDR_W +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L +#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L +//IOMMU_L2_1_SMMU_AIDR_W +#define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 +#define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 +#define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL +#define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L + + +// addressBlock: nbio_iohub_iommu_l2indx_l2indxcfg +//L2_STATUS_1 +#define L2_STATUS_1__L2STATUS1__SHIFT 0x0 +#define L2_STATUS_1__L2STATUS1_MASK 0xFFFFFFFFL +//L2_SB_LOCATION +#define L2_SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define L2_SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define L2_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define L2_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//L2_CONTROL_5 +#define L2_CONTROL_5__QueueArbFBPri__SHIFT 0x0 +#define L2_CONTROL_5__FC1Dis__SHIFT 0x2 +#define L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT 0x3 +#define L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT 0x4 +#define L2_CONTROL_5__FC3Dis__SHIFT 0x6 +#define L2_CONTROL_5__RESERVED__SHIFT 0x7 +#define L2_CONTROL_5__ForceTWonVC7__SHIFT 0xb +#define L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT 0xc +#define L2_CONTROL_5__PCTRL_hysteresis__SHIFT 0x13 +#define L2_CONTROL_5__DTCUpdatePri__SHIFT 0x19 +#define L2_CONTROL_5__QueueArbFBPri_MASK 0x00000001L +#define L2_CONTROL_5__FC1Dis_MASK 0x00000004L +#define L2_CONTROL_5__DTCUpdateVOneIVZero_MASK 0x00000008L +#define L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK 0x00000010L +#define L2_CONTROL_5__FC3Dis_MASK 0x00000040L +#define L2_CONTROL_5__RESERVED_MASK 0x00000780L +#define L2_CONTROL_5__ForceTWonVC7_MASK 0x00000800L +#define L2_CONTROL_5__GST_partial_ptc_cntrl_MASK 0x0007F000L +#define L2_CONTROL_5__PCTRL_hysteresis_MASK 0x01F80000L +#define L2_CONTROL_5__DTCUpdatePri_MASK 0x02000000L +//L2_CONTROL_6 +#define L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT 0x8 +#define L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_6__Perf2Threshold__SHIFT 0x18 +#define L2_CONTROL_6__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK 0x0000FF00L +#define L2_CONTROL_6__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_6__Perf2Threshold_MASK 0xFF000000L +//L2_PDC_CONTROL +#define L2_PDC_CONTROL__RESERVED__SHIFT 0x0 +#define L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT 0x3 +#define L2_PDC_CONTROL__PDCParityEn__SHIFT 0x4 +#define L2_PDC_CONTROL__PDCInvalidationSel__SHIFT 0x8 +#define L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT 0xa +#define L2_PDC_CONTROL__PDCSearchDirection__SHIFT 0xc +#define L2_PDC_CONTROL__PDCBypass__SHIFT 0xd +#define L2_PDC_CONTROL__PDCParitySupport__SHIFT 0xf +#define L2_PDC_CONTROL__PDCWays__SHIFT 0x10 +#define L2_PDC_CONTROL__PDCEntries__SHIFT 0x1c +#define L2_PDC_CONTROL__RESERVED_MASK 0x00000003L +#define L2_PDC_CONTROL__PDCLRUUpdatePri_MASK 0x00000008L +#define L2_PDC_CONTROL__PDCParityEn_MASK 0x00000010L +#define L2_PDC_CONTROL__PDCInvalidationSel_MASK 0x00000300L +#define L2_PDC_CONTROL__PDCSoftInvalidate_MASK 0x00000400L +#define L2_PDC_CONTROL__PDCSearchDirection_MASK 0x00001000L +#define L2_PDC_CONTROL__PDCBypass_MASK 0x00002000L +#define L2_PDC_CONTROL__PDCParitySupport_MASK 0x00008000L +#define L2_PDC_CONTROL__PDCWays_MASK 0x00FF0000L +#define L2_PDC_CONTROL__PDCEntries_MASK 0xF0000000L +//L2_PDC_HASH_CONTROL +#define L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT 0x10 +#define L2_PDC_HASH_CONTROL__PDCAddressMask_MASK 0xFFFF0000L +//L2_PDC_WAY_CONTROL +#define L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT 0x0 +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT 0x10 +#define L2_PDC_WAY_CONTROL__PDCWayDisable_MASK 0x0000FFFFL +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK 0xFFFF0000L +//L2B_UPDATE_FILTER_CNTL +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT 0x0 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT 0x1 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK 0x00000001L +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_TW_CONTROL +#define L2_TW_CONTROL__RESERVED__SHIFT 0x0 +#define L2_TW_CONTROL__TWForceCoherent__SHIFT 0x6 +#define L2_TW_CONTROL__TWPrefetchEn__SHIFT 0x8 +#define L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT 0x9 +#define L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT 0xa +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT 0xb +#define L2_TW_CONTROL__TWPrefetchRange__SHIFT 0xc +#define L2_TW_CONTROL__TWFilter_Dis__SHIFT 0x10 +#define L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT 0x11 +#define L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT 0x12 +#define L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT 0x13 +#define L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT 0x14 +#define L2_TW_CONTROL__TWGuestPrefetchEn__SHIFT 0x15 +#define L2_TW_CONTROL__TWGuestPrefetchRange__SHIFT 0x16 +#define L2_TW_CONTROL__RESERVED_MASK 0x0000003FL +#define L2_TW_CONTROL__TWForceCoherent_MASK 0x00000040L +#define L2_TW_CONTROL__TWPrefetchEn_MASK 0x00000100L +#define L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK 0x00000200L +#define L2_TW_CONTROL__TWPTEOnUntransExcl_MASK 0x00000400L +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_TW_CONTROL__TWPrefetchRange_MASK 0x00007000L +#define L2_TW_CONTROL__TWFilter_Dis_MASK 0x00010000L +#define L2_TW_CONTROL__TWFilter_64B_Dis_MASK 0x00020000L +#define L2_TW_CONTROL__TWContWalkOnPErrDis_MASK 0x00040000L +#define L2_TW_CONTROL__TWSetAccessBit_Dis_MASK 0x00080000L +#define L2_TW_CONTROL__TWClearAPBit_Dis_MASK 0x00100000L +#define L2_TW_CONTROL__TWGuestPrefetchEn_MASK 0x00200000L +#define L2_TW_CONTROL__TWGuestPrefetchRange_MASK 0x01C00000L +//L2_CP_CONTROL +#define L2_CP_CONTROL__CPPrefetchDis__SHIFT 0x0 +#define L2_CP_CONTROL__CPFlushOnWait__SHIFT 0x1 +#define L2_CP_CONTROL__CPFlushOnInv__SHIFT 0x2 +#define L2_CP_CONTROL__CPRdDelay__SHIFT 0x10 +#define L2_CP_CONTROL__CPPrefetchDis_MASK 0x00000001L +#define L2_CP_CONTROL__CPFlushOnWait_MASK 0x00000002L +#define L2_CP_CONTROL__CPFlushOnInv_MASK 0x00000004L +#define L2_CP_CONTROL__CPRdDelay_MASK 0xFFFF0000L +//L2_CP_CONTROL_1 +#define L2_CP_CONTROL_1__CPL1Off__SHIFT 0x0 +#define L2_CP_CONTROL_1__Reserved__SHIFT 0x10 +#define L2_CP_CONTROL_1__CPL1Off_MASK 0x0000FFFFL +#define L2_CP_CONTROL_1__Reserved_MASK 0xFFFF0000L +//IOMMU_L2_GUEST_ADDR_CNTRL +#define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK__SHIFT 0x0 +#define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved__SHIFT 0x18 +#define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK_MASK 0x00FFFFFFL +#define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved_MASK 0xFF000000L +//L2_TW_CONTROL_1 +#define L2_TW_CONTROL_1__TWDebugEn__SHIFT 0x0 +#define L2_TW_CONTROL_1__TWDebugNoWrap__SHIFT 0x1 +#define L2_TW_CONTROL_1__TWDebugForceDisable__SHIFT 0x2 +#define L2_TW_CONTROL_1__TWDebugMask__SHIFT 0xf +#define L2_TW_CONTROL_1__TWDebugEn_MASK 0x00000001L +#define L2_TW_CONTROL_1__TWDebugNoWrap_MASK 0x00000002L +#define L2_TW_CONTROL_1__TWDebugForceDisable_MASK 0x00000004L +#define L2_TW_CONTROL_1__TWDebugMask_MASK 0xFFFF8000L +//L2_TW_CONTROL_2 +#define L2_TW_CONTROL_2__TWDebugAddrLo__SHIFT 0xc +#define L2_TW_CONTROL_2__TWDebugAddrLo_MASK 0xFFFFF000L +//L2_TW_CONTROL_3 +#define L2_TW_CONTROL_3__TWDebugAddrHi__SHIFT 0x0 +#define L2_TW_CONTROL_3__TWDebugAddrHi_MASK 0xFFFFFFFFL +//L2_CREDIT_CONTROL_0 +#define L2_CREDIT_CONTROL_0__FC1Credits__SHIFT 0x0 +#define L2_CREDIT_CONTROL_0__FC1Override__SHIFT 0x7 +#define L2_CREDIT_CONTROL_0__FC2Credits__SHIFT 0x8 +#define L2_CREDIT_CONTROL_0__FC2Override__SHIFT 0xe +#define L2_CREDIT_CONTROL_0__FC3Credits__SHIFT 0xf +#define L2_CREDIT_CONTROL_0__FC3Override__SHIFT 0x15 +#define L2_CREDIT_CONTROL_0__MultATSCredits__SHIFT 0x16 +#define L2_CREDIT_CONTROL_0__FC1Credits_MASK 0x0000007FL +#define L2_CREDIT_CONTROL_0__FC1Override_MASK 0x00000080L +#define L2_CREDIT_CONTROL_0__FC2Credits_MASK 0x00003F00L +#define L2_CREDIT_CONTROL_0__FC2Override_MASK 0x00004000L +#define L2_CREDIT_CONTROL_0__FC3Credits_MASK 0x001F8000L +#define L2_CREDIT_CONTROL_0__FC3Override_MASK 0x00200000L +#define L2_CREDIT_CONTROL_0__MultATSCredits_MASK 0xFFC00000L +//L2_CREDIT_CONTROL_1 +#define L2_CREDIT_CONTROL_1__PDTIECredits__SHIFT 0x0 +#define L2_CREDIT_CONTROL_1__RESERVED__SHIFT 0x7 +#define L2_CREDIT_CONTROL_1__TWELCredits__SHIFT 0x8 +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT 0x10 +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT 0x14 +#define L2_CREDIT_CONTROL_1__PDTIECredits_MASK 0x0000003FL +#define L2_CREDIT_CONTROL_1__RESERVED_MASK 0x00000080L +#define L2_CREDIT_CONTROL_1__TWELCredits_MASK 0x00003F00L +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK 0x000F0000L +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK 0x00F00000L +//L2_ERR_RULE_CONTROL_0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT 0x4 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK 0xFFFFFFF0L +//L2_ERR_RULE_CONTROL_1 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_2 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK 0xFFFFFFFFL +//L2_L2B_CK_GATE_CONTROL +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT 0x0 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT 0x1 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT 0x2 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT 0x3 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT 0x4 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT 0x6 +#define L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT 0x8 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK 0x00000001L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK 0x00000002L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK 0x00000004L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK 0x00000008L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK 0x00000030L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK 0x000000C0L +#define L2_L2B_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L +//PPR_CONTROL +#define PPR_CONTROL__PPR_IntTimeDelay__SHIFT 0x0 +#define PPR_CONTROL__PPR_IntReqDelay__SHIFT 0x8 +#define PPR_CONTROL__PPR_IntCoallesce_En__SHIFT 0x10 +#define PPR_CONTROL__Reserved__SHIFT 0x11 +#define PPR_CONTROL__PPR_IntTimeDelay_MASK 0x000000FFL +#define PPR_CONTROL__PPR_IntReqDelay_MASK 0x0000FF00L +#define PPR_CONTROL__PPR_IntCoallesce_En_MASK 0x00010000L +#define PPR_CONTROL__Reserved_MASK 0xFFFE0000L +//L2_L2B_PGSIZE_CONTROL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK 0x00007F00L +//L2_L2B_MEMPWR_GATE_1 +#define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN__SHIFT 0x1 +#define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN__SHIFT 0x2 +#define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL__SHIFT 0x3 +#define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL__SHIFT 0x4 +#define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN_MASK 0x00000001L +#define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN_MASK 0x00000002L +#define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN_MASK 0x00000004L +#define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL_MASK 0x00000008L +#define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL_MASK 0x00000010L +//L2_L2B_MEMPWR_GATE_2 +#define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_3 +#define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_4 +#define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_2 +#define L2_PERF_CNTL_2__L2PerfEvent4__SHIFT 0x0 +#define L2_PERF_CNTL_2__L2PerfEvent5__SHIFT 0x8 +#define L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT 0x10 +#define L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT 0x18 +#define L2_PERF_CNTL_2__L2PerfEvent4_MASK 0x000000FFL +#define L2_PERF_CNTL_2__L2PerfEvent5_MASK 0x0000FF00L +#define L2_PERF_CNTL_2__L2PerfCountUpper4_MASK 0x00FF0000L +#define L2_PERF_CNTL_2__L2PerfCountUpper5_MASK 0xFF000000L +//L2_PERF_COUNT_4 +#define L2_PERF_COUNT_4__L2PerfCount4__SHIFT 0x0 +#define L2_PERF_COUNT_4__L2PerfCount4_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_5 +#define L2_PERF_COUNT_5__L2PerfCount5__SHIFT 0x0 +#define L2_PERF_COUNT_5__L2PerfCount5_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_3 +#define L2_PERF_CNTL_3__L2PerfEvent6__SHIFT 0x0 +#define L2_PERF_CNTL_3__L2PerfEvent7__SHIFT 0x8 +#define L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT 0x10 +#define L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT 0x18 +#define L2_PERF_CNTL_3__L2PerfEvent6_MASK 0x000000FFL +#define L2_PERF_CNTL_3__L2PerfEvent7_MASK 0x0000FF00L +#define L2_PERF_CNTL_3__L2PerfCountUpper6_MASK 0x00FF0000L +#define L2_PERF_CNTL_3__L2PerfCountUpper7_MASK 0xFF000000L +//L2_PERF_COUNT_6 +#define L2_PERF_COUNT_6__L2PerfCount6__SHIFT 0x0 +#define L2_PERF_COUNT_6__L2PerfCount6_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_7 +#define L2_PERF_COUNT_7__L2PerfCount7__SHIFT 0x0 +#define L2_PERF_COUNT_7__L2PerfCount7_MASK 0xFFFFFFFFL +//L2_L2B_DVM_CTRL_0 +#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID__SHIFT 0x0 +#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID__SHIFT 0x10 +#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID_MASK 0x0000FFFFL +#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID_MASK 0xFFFF0000L +//L2_L2B_DVM_CTRL_1 +#define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND__SHIFT 0x0 +#define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE__SHIFT 0x8 +#define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE__SHIFT 0xb +#define L2_L2B_DVM_CTRL_1__DVM_V1_Disable__SHIFT 0xe +#define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE__SHIFT 0xf +#define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND_MASK 0x000000FFL +#define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE_MASK 0x00000700L +#define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE_MASK 0x00003800L +#define L2_L2B_DVM_CTRL_1__DVM_V1_Disable_MASK 0x00004000L +#define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE_MASK 0x00FF8000L +//L2B_SDP_MAXCRED +#define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED__SHIFT 0x0 +#define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED__SHIFT 0xc +#define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED__SHIFT 0x14 +#define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED__SHIFT 0x18 +#define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED_MASK 0x00000FFFL +#define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED_MASK 0x000FF000L +#define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED_MASK 0x00F00000L +#define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED_MASK 0x0F000000L +//L2B_SDP_PARITY_ERROR_EN +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT 0x0 +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT 0x1 +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT 0x2 +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK 0x00000001L +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK 0x00000002L +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK 0x00000004L +//L2_ECO_CNTRL_1 +#define L2_ECO_CNTRL_1__L2_ECO_1__SHIFT 0x0 +#define L2_ECO_CNTRL_1__L2_ECO_1_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_5 +#define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_6 +#define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_7 +#define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_8 +#define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_9 +#define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2B_MEMPWR_GATE_10 +#define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2bshdw_l2bshdw +//SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM_MASK 0x00FF0000L +//SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY +#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS__SHIFT 0x8 +#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM__SHIFT 0x10 +#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS_MASK 0x0000FF00L +#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM_MASK 0x00FF0000L + + +// addressBlock: nbio_iohub_iommu_l2bpsp_l2bpsp +//L2BPSP_ERR_REP_ENABLE +#define L2BPSP_ERR_REP_ENABLE__HE_SUP__SHIFT 0x0 +#define L2BPSP_ERR_REP_ENABLE__Reserved__SHIFT 0x1 +#define L2BPSP_ERR_REP_ENABLE__HE_SUP_MASK 0x00000001L +#define L2BPSP_ERR_REP_ENABLE__Reserved_MASK 0xFFFFFFFEL +//L2BPSP_HW_ERR_STATUS_0 +#define L2BPSP_HW_ERR_STATUS_0__HEV__SHIFT 0x0 +#define L2BPSP_HW_ERR_STATUS_0__HEO__SHIFT 0x1 +#define L2BPSP_HW_ERR_STATUS_0__Reserved__SHIFT 0x3 +#define L2BPSP_HW_ERR_STATUS_0__HEV_MASK 0x00000001L +#define L2BPSP_HW_ERR_STATUS_0__HEO_MASK 0x00000002L +#define L2BPSP_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFF8L +//L2BPSP_HW_ERR_STATUS_1 +#define L2BPSP_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 +#define L2BPSP_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL +//L2BPSP_HW_ERR_LOWER_0 +#define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 +#define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL +//L2BPSP_HW_ERR_LOWER_1 +#define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 +#define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL +//L2BPSP_HW_ERR_UPPER_0 +#define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 +#define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL +//L2BPSP_HW_ERR_UPPER_1 +#define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 +#define L2BPSP_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c +#define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL +#define L2BPSP_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L + + +// addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +//FEATURES_ENABLE +#define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2 +#define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4 +#define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5 +#define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8 +#define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9 +#define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L +#define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L +#define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L +#define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L +#define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L +//IOAPIC_BR0_INTERRUPT_ROUTING +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR1_INTERRUPT_ROUTING +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR2_INTERRUPT_ROUTING +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR3_INTERRUPT_ROUTING +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR4_INTERRUPT_ROUTING +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR5_INTERRUPT_ROUTING +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR6_INTERRUPT_ROUTING +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR7_INTERRUPT_ROUTING +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map_MASK 0x001F0000L +//IOAPIC_BR8_INTERRUPT_ROUTING +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp__SHIFT 0x0 +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz__SHIFT 0x4 +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map__SHIFT 0x10 +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp_MASK 0x00000007L +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz_MASK 0x00000030L +#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map_MASK 0x001F0000L +//IOAPIC_SERIAL_IRQ_STATUS +#define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts__SHIFT 0x0 +#define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts_MASK 0xFFFFFFFFL +//IOAPIC_SCRATCH_0 +#define IOAPIC_SCRATCH_0__Scratch_0__SHIFT 0x0 +#define IOAPIC_SCRATCH_0__Scratch_0_MASK 0xFFFFFFFFL +//IOAPIC_SCRATCH_1 +#define IOAPIC_SCRATCH_1__Scratch_1__SHIFT 0x0 +#define IOAPIC_SCRATCH_1__Scratch_1_MASK 0xFFFFFFFFL +//IOAPIC_GLUE_CG_LCLK_CTRL_0 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOAPIC_SDP_PORT_CONTROL +#define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 +#define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL +//IOAPIC_PERF_CNTL +#define IOAPIC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 +#define IOAPIC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 +#define IOAPIC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 +#define IOAPIC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 +#define IOAPIC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL +#define IOAPIC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L +#define IOAPIC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L +#define IOAPIC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L +//IOAPIC_PERF_COUNT0 +#define IOAPIC_PERF_COUNT0__COUNTER0__SHIFT 0x0 +#define IOAPIC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL +//IOAPIC_PERF_COUNT0_UPPER +#define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 +#define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL +//IOAPIC_PERF_COUNT1 +#define IOAPIC_PERF_COUNT1__COUNTER1__SHIFT 0x0 +#define IOAPIC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL +//IOAPIC_PERF_COUNT1_UPPER +#define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 +#define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL +//IOAPIC_PERF_COUNT2 +#define IOAPIC_PERF_COUNT2__COUNTER2__SHIFT 0x0 +#define IOAPIC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL +//IOAPIC_PERF_COUNT2_UPPER +#define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 +#define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL +//IOAPIC_PERF_COUNT3 +#define IOAPIC_PERF_COUNT3__COUNTER3__SHIFT 0x0 +#define IOAPIC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL +//IOAPIC_PERF_COUNT3_UPPER +#define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 +#define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL +//IOAPIC_PGSLV_CONTROL +#define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis__SHIFT 0x0 +#define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis_MASK 0x0000001FL + + +// addressBlock: nbio_iohub_nb_ioapicshdw_ioapic_shdwdec +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL +//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 +#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL + + +// addressBlock: nbio_iohub_iommu_l1_PCIE0_iommul1cfg +//IOMMU_L1_PCIE0_L1_PERF_CNTL +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L +#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L +//IOMMU_L1_PCIE0_L1_PERF_COUNT_0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PERF_COUNT_1 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PERF_CNTL_B +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L +#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L +//IOMMU_L1_PCIE0_L1_PERF_COUNT_B0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PERF_COUNT_B1 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_SB_LOCATION +#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//IOMMU_L1_PCIE0_L1_CNTRL_0 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED__SHIFT 0x5 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1__SHIFT 0xe +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks__SHIFT 0x14 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0_MASK 0x00000010L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED_MASK 0x00000020L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits_MASK 0x00003F00L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1_MASK 0x000FC000L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks_MASK 0x00300000L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries_MASK 0x0F000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L +//IOMMU_L1_PCIE0_L1_CNTRL_1 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass__SHIFT 0x9 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn__SHIFT 0xb +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis__SHIFT 0xc +#define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en__SHIFT 0x15 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17 +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c +#define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f +#define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED_MASK 0x000001FFL +#define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass_MASK 0x00000200L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en_MASK 0x00200000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L +//IOMMU_L1_PCIE0_L1_CNTRL_2 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d +#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e +#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L +#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L +//IOMMU_L1_PCIE0_L1_CNTRL_3 +#define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_BANK_SEL_0 +#define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL +//IOMMU_L1_PCIE0_L1_BANK_DISABLE_0 +#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL +#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L +//IOMMU_L1_PCIE0_L1_WQ_STATUS_0 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L +//IOMMU_L1_PCIE0_L1_WQ_STATUS_1 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L +//IOMMU_L1_PCIE0_L1_WQ_STATUS_2 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L +//IOMMU_L1_PCIE0_L1_WQ_STATUS_3 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L +#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L +//IOMMU_L1_PCIE0_L1_FEATURE_CNTRL +#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL +#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_CNTRL_4 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18 +#define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L +#define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L +#define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L +#define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L +//IOMMU_L1_PCIE0_L1_CLKCNTRL_0 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved__SHIFT 0x16 +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L +#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L +//IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL +#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L +//IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL +#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L +//IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5 +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L +#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L +//IOMMU_L1_PCIE0_L1_CNTRL_5 +#define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL +#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5 +#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L +//IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0 +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8 +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L +#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L +//IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6 +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L +#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L +//IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2 +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6 +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L +#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L +//IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control +#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +//IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control +#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 +#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2 +#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L +#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL +//IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0 +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4 +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L +#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L +//IOMMU_L1_PCIE0_L1_ECO_CNTRL +#define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0 +#define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l1shdw_PCIE0_l1shdw +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L + + +// addressBlock: nbio_iohub_iommu_l1psp_PCIE0_l1psp +//IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL +#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1 +#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L +#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL +//IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L +//IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL +#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0 +#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1 +#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L +#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL + + +// addressBlock: nbio_iohub_iommu_l1_IOAGR_iommul1cfg +//IOMMU_L1_IOAGR_L1_PERF_CNTL +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L +#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L +//IOMMU_L1_IOAGR_L1_PERF_COUNT_0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PERF_COUNT_1 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PERF_CNTL_B +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L +#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L +//IOMMU_L1_IOAGR_L1_PERF_COUNT_B0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PERF_COUNT_B1 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_SB_LOCATION +#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//IOMMU_L1_IOAGR_L1_CNTRL_0 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED__SHIFT 0x5 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1__SHIFT 0xe +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks__SHIFT 0x14 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0_MASK 0x00000010L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED_MASK 0x00000020L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits_MASK 0x00003F00L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1_MASK 0x000FC000L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks_MASK 0x00300000L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries_MASK 0x0F000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L +//IOMMU_L1_IOAGR_L1_CNTRL_1 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass__SHIFT 0x9 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn__SHIFT 0xb +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis__SHIFT 0xc +#define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en__SHIFT 0x15 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17 +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c +#define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f +#define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED_MASK 0x000001FFL +#define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass_MASK 0x00000200L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en_MASK 0x00200000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L +//IOMMU_L1_IOAGR_L1_CNTRL_2 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d +#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e +#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L +#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L +//IOMMU_L1_IOAGR_L1_CNTRL_3 +#define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_BANK_SEL_0 +#define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL +//IOMMU_L1_IOAGR_L1_BANK_DISABLE_0 +#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL +#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L +//IOMMU_L1_IOAGR_L1_WQ_STATUS_0 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L +//IOMMU_L1_IOAGR_L1_WQ_STATUS_1 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L +//IOMMU_L1_IOAGR_L1_WQ_STATUS_2 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L +//IOMMU_L1_IOAGR_L1_WQ_STATUS_3 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L +#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L +//IOMMU_L1_IOAGR_L1_FEATURE_CNTRL +#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL +#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_CNTRL_4 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18 +#define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L +#define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L +#define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L +#define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L +//IOMMU_L1_IOAGR_L1_CLKCNTRL_0 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved__SHIFT 0x16 +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L +#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L +//IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL +#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L +//IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL +#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L +//IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5 +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L +#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L +//IOMMU_L1_IOAGR_L1_CNTRL_5 +#define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL +//IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL +#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5 +#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L +//IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0 +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8 +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L +#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L +//IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6 +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L +#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L +//IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2 +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6 +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L +#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L +//IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control +#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +//IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control +#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0 +#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2 +#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L +#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL +//IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0 +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4 +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L +#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L +//IOMMU_L1_IOAGR_L1_ECO_CNTRL +#define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0 +#define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l1shdw_IOAGR_l1shdw +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L + + +// addressBlock: nbio_iohub_iommu_l1psp_IOAGR_l1psp +//IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL +#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1 +#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L +#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL +//IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L +//IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL +#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0 +#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1 +#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L +#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL + + +// addressBlock: nbio_iohub_iommu_l2a_l2acfg +//L2_PERF_CNTL_0 +#define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0 +#define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8 +#define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10 +#define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18 +#define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL +#define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L +#define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L +#define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L +//L2_PERF_COUNT_0 +#define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0 +#define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_1 +#define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0 +#define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_1 +#define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0 +#define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8 +#define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10 +#define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18 +#define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL +#define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L +#define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L +#define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L +//L2_PERF_COUNT_2 +#define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0 +#define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_3 +#define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0 +#define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL +//L2_STATUS_0 +#define L2_STATUS_0__L2STATUS0__SHIFT 0x0 +#define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL +//L2_CONTROL_0 +#define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1 +#define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2 +#define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3 +#define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb +#define L2_CONTROL_0__RESERVED__SHIFT 0xc +#define L2_CONTROL_0__FLTCMBPriority__SHIFT 0x12 +#define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14 +#define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18 +#define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L +#define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L +#define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L +#define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_CONTROL_0__RESERVED_MASK 0x0003F000L +#define L2_CONTROL_0__FLTCMBPriority_MASK 0x00040000L +#define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L +#define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L +//L2_CONTROL_1 +#define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8 +#define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_1__PerfThreshold__SHIFT 0x18 +#define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L +#define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L +//L2_DTC_CONTROL +#define L2_DTC_CONTROL__RESERVED__SHIFT 0x0 +#define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3 +#define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4 +#define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8 +#define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa +#define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd +#define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf +#define L2_DTC_CONTROL__DTCWays__SHIFT 0x10 +#define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c +#define L2_DTC_CONTROL__RESERVED_MASK 0x00000003L +#define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L +#define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L +#define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L +#define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L +#define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L +#define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L +#define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L +#define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L +//L2_DTC_HASH_CONTROL +#define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10 +#define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L +//L2_DTC_WAY_CONTROL +#define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0 +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10 +#define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L +//L2_ITC_CONTROL +#define L2_ITC_CONTROL__RESERVED__SHIFT 0x0 +#define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3 +#define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4 +#define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8 +#define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa +#define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd +#define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf +#define L2_ITC_CONTROL__ITCWays__SHIFT 0x10 +#define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c +#define L2_ITC_CONTROL__RESERVED_MASK 0x00000003L +#define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L +#define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L +#define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L +#define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L +#define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L +#define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L +#define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L +#define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L +//L2_ITC_HASH_CONTROL +#define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10 +#define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L +//L2_ITC_WAY_CONTROL +#define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0 +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10 +#define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L +//L2_PTC_A_CONTROL +#define L2_PTC_A_CONTROL__RESERVED__SHIFT 0x0 +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3 +#define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4 +#define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8 +#define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa +#define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb +#define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd +#define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf +#define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10 +#define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c +#define L2_PTC_A_CONTROL__RESERVED_MASK 0x00000003L +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L +#define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L +#define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L +#define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L +#define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L +#define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L +#define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L +#define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L +#define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L +//L2_PTC_A_HASH_CONTROL +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10 +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L +//L2_PTC_A_WAY_CONTROL +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0 +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10 +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L +//L2_CREDIT_CONTROL_2 +#define L2_CREDIT_CONTROL_2__QUEUECredits__SHIFT 0x0 +#define L2_CREDIT_CONTROL_2__QUEUEOverride__SHIFT 0x7 +#define L2_CREDIT_CONTROL_2__FLTCMBCredits__SHIFT 0x8 +#define L2_CREDIT_CONTROL_2__FLTCMBOverride__SHIFT 0xf +#define L2_CREDIT_CONTROL_2__FCELCredits__SHIFT 0x10 +#define L2_CREDIT_CONTROL_2__FCELOverride__SHIFT 0x17 +#define L2_CREDIT_CONTROL_2__PPR_logger_credits__SHIFT 0x18 +#define L2_CREDIT_CONTROL_2__QUEUECredits_MASK 0x0000003FL +#define L2_CREDIT_CONTROL_2__QUEUEOverride_MASK 0x00000080L +#define L2_CREDIT_CONTROL_2__FLTCMBCredits_MASK 0x00003F00L +#define L2_CREDIT_CONTROL_2__FLTCMBOverride_MASK 0x00008000L +#define L2_CREDIT_CONTROL_2__FCELCredits_MASK 0x003F0000L +#define L2_CREDIT_CONTROL_2__FCELOverride_MASK 0x00800000L +#define L2_CREDIT_CONTROL_2__PPR_logger_credits_MASK 0x0F000000L +//L2A_UPDATE_FILTER_CNTL +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_ERR_RULE_CONTROL_3 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L +//L2_ERR_RULE_CONTROL_4 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_5 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL +//L2_L2A_CK_GATE_CONTROL +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT 0x0 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT 0x1 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT 0x2 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare__SHIFT 0x3 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT 0x4 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT 0x6 +#define L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT 0x8 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK 0x00000001L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK 0x00000002L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK 0x00000004L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare_MASK 0x00000008L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK 0x00000030L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK 0x000000C0L +#define L2_L2A_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L +//L2_L2A_PGSIZE_CONTROL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L +//L2_L2A_MEMPWR_GATE_1 +#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN__SHIFT 0x1 +#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN__SHIFT 0x2 +#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL__SHIFT 0x4 +#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN_MASK 0x00000001L +#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN_MASK 0x00000002L +#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN_MASK 0x00000004L +#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL_MASK 0x00000010L +//L2_L2A_MEMPWR_GATE_2 +#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_3 +#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_4 +#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_5 +#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_6 +#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_7 +#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_8 +#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_9 +#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_PWRGATE_CNTRL_REG_0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK 0xFFFFFFFFL +//L2_L2A_MEMPWR_GATE_10 +#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt__SHIFT 0x0 +#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL +//L2_PWRGATE_CNTRL_REG_3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT 0x1 +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT 0x2 +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT 0x3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK 0x00000001L +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK 0x00000002L +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK 0x00000004L +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK 0x00000018L +//L2_ECO_CNTRL_0 +#define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0 +#define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw +//SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_CNTRL_0 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L +#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L +//SHDWL2A_IOMMU_MMIO_CNTRL_1 +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L +#define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L +//SHDWL2A_IOMMU_MMIO_EXCL_BASE_0 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L +//SHDWL2A_IOMMU_MMIO_EXCL_BASE_1 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL +#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L +//SHDWL2A_IOMMU_MMIO_EXCL_LIM_0 +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L +//SHDWL2A_IOMMU_MMIO_EXCL_LIM_1 +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL +#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L +//SHDWL2A_SMI_FILTER_REGISTER_0_0 +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L +#define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L +//SHDWL2A_SMI_FILTER_REGISTER_1_0 +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L +#define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L +//SHDWL2A_SMI_FILTER_REGISTER_2_0 +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L +#define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L +//SHDWL2A_SMI_FILTER_REGISTER_3_0 +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L +#define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L +//SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL +//SHDWL2A_IOMMU_CAP_BASE_LO +#define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +//SHDWL2A_IOMMU_CAP_MISC +#define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +//SHDWL2A_IOMMU_CAP_MISC_1 +#define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L +//SHDWL2A_IOMMU_CONTROL_W +#define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 +#define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 +#define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L +#define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L +//SHDWL2A_IOMMU_MMIO_CONTROL0_W +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L +#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L +//SHDWL2A_IOMMU_MMIO_CONTROL1_W +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L +#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L + + +// addressBlock: nbio_iohub_smmu_mmio_smmummiocfg +//SMMU_IDR0 +#define SMMU_IDR0__S2P__SHIFT 0x0 +#define SMMU_IDR0__S1P__SHIFT 0x1 +#define SMMU_IDR0__TTF__SHIFT 0x2 +#define SMMU_IDR0__COHACC__SHIFT 0x4 +#define SMMU_IDR0__BTM__SHIFT 0x5 +#define SMMU_IDR0__HTTU__SHIFT 0x6 +#define SMMU_IDR0__DORMHINT__SHIFT 0x8 +#define SMMU_IDR0__Hyp__SHIFT 0x9 +#define SMMU_IDR0__ATS__SHIFT 0xa +#define SMMU_IDR0__PERFCTRS__SHIFT 0xb +#define SMMU_IDR0__ASID16__SHIFT 0xc +#define SMMU_IDR0__MSI__SHIFT 0xd +#define SMMU_IDR0__SEV__SHIFT 0xe +#define SMMU_IDR0__ATOS__SHIFT 0xf +#define SMMU_IDR0__PRI__SHIFT 0x10 +#define SMMU_IDR0__VMW__SHIFT 0x11 +#define SMMU_IDR0__VMID16__SHIFT 0x12 +#define SMMU_IDR0__CD2L__SHIFT 0x13 +#define SMMU_IDR0__VATOS__SHIFT 0x14 +#define SMMU_IDR0__TTENDIAN__SHIFT 0x15 +#define SMMU_IDR0__STALL_MODEL__SHIFT 0x18 +#define SMMU_IDR0__TERM_MODEL__SHIFT 0x1a +#define SMMU_IDR0__ST_LEVEL__SHIFT 0x1b +#define SMMU_IDR0__RAS__SHIFT 0x1d +#define SMMU_IDR0__S2P_MASK 0x00000001L +#define SMMU_IDR0__S1P_MASK 0x00000002L +#define SMMU_IDR0__TTF_MASK 0x0000000CL +#define SMMU_IDR0__COHACC_MASK 0x00000010L +#define SMMU_IDR0__BTM_MASK 0x00000020L +#define SMMU_IDR0__HTTU_MASK 0x000000C0L +#define SMMU_IDR0__DORMHINT_MASK 0x00000100L +#define SMMU_IDR0__Hyp_MASK 0x00000200L +#define SMMU_IDR0__ATS_MASK 0x00000400L +#define SMMU_IDR0__PERFCTRS_MASK 0x00000800L +#define SMMU_IDR0__ASID16_MASK 0x00001000L +#define SMMU_IDR0__MSI_MASK 0x00002000L +#define SMMU_IDR0__SEV_MASK 0x00004000L +#define SMMU_IDR0__ATOS_MASK 0x00008000L +#define SMMU_IDR0__PRI_MASK 0x00010000L +#define SMMU_IDR0__VMW_MASK 0x00020000L +#define SMMU_IDR0__VMID16_MASK 0x00040000L +#define SMMU_IDR0__CD2L_MASK 0x00080000L +#define SMMU_IDR0__VATOS_MASK 0x00100000L +#define SMMU_IDR0__TTENDIAN_MASK 0x00600000L +#define SMMU_IDR0__STALL_MODEL_MASK 0x03000000L +#define SMMU_IDR0__TERM_MODEL_MASK 0x04000000L +#define SMMU_IDR0__ST_LEVEL_MASK 0x18000000L +#define SMMU_IDR0__RAS_MASK 0x20000000L +//SMMU_IDR1 +#define SMMU_IDR1__SIDSIZE__SHIFT 0x0 +#define SMMU_IDR1__SSIDSIZE__SHIFT 0x6 +#define SMMU_IDR1__PRIQS__SHIFT 0xb +#define SMMU_IDR1__EVENTQS__SHIFT 0x10 +#define SMMU_IDR1__CMDQS__SHIFT 0x15 +#define SMMU_IDR1__ATTR_PERMS_OVR__SHIFT 0x1a +#define SMMU_IDR1__ATTR_TYPES_OVR__SHIFT 0x1b +#define SMMU_IDR1__REL__SHIFT 0x1c +#define SMMU_IDR1__QUEUES_PRESET__SHIFT 0x1d +#define SMMU_IDR1__TABLES_PRESET__SHIFT 0x1e +#define SMMU_IDR1__SIDSIZE_MASK 0x0000003FL +#define SMMU_IDR1__SSIDSIZE_MASK 0x000007C0L +#define SMMU_IDR1__PRIQS_MASK 0x0000F800L +#define SMMU_IDR1__EVENTQS_MASK 0x001F0000L +#define SMMU_IDR1__CMDQS_MASK 0x03E00000L +#define SMMU_IDR1__ATTR_PERMS_OVR_MASK 0x04000000L +#define SMMU_IDR1__ATTR_TYPES_OVR_MASK 0x08000000L +#define SMMU_IDR1__REL_MASK 0x10000000L +#define SMMU_IDR1__QUEUES_PRESET_MASK 0x20000000L +#define SMMU_IDR1__TABLES_PRESET_MASK 0x40000000L +//SMMU_IDR2 +#define SMMU_IDR2__BA_VATOS__SHIFT 0x0 +#define SMMU_IDR2__BA_RAS__SHIFT 0xa +#define SMMU_IDR2__BA_VATOS_MASK 0x000003FFL +#define SMMU_IDR2__BA_RAS_MASK 0x000FFC00L +//SMMU_IDR3 +#define SMMU_IDR3__RESERVED__SHIFT 0x0 +#define SMMU_IDR3__HAD__SHIFT 0x2 +#define SMMU_IDR3__RESERVED_MASK 0x00000003L +#define SMMU_IDR3__HAD_MASK 0x00000004L +//SMMU_IDR4 +#define SMMU_IDR4__IMPDEF__SHIFT 0x0 +#define SMMU_IDR4__IMPDEF_MASK 0xFFFFFFFFL +//SMMU_IDR5 +#define SMMU_IDR5__OAS__SHIFT 0x0 +#define SMMU_IDR5__GRAN4K__SHIFT 0x4 +#define SMMU_IDR5__GRAN16K__SHIFT 0x5 +#define SMMU_IDR5__GRAN64K__SHIFT 0x6 +#define SMMU_IDR5__STALL_MAX__SHIFT 0x10 +#define SMMU_IDR5__OAS_MASK 0x00000007L +#define SMMU_IDR5__GRAN4K_MASK 0x00000010L +#define SMMU_IDR5__GRAN16K_MASK 0x00000020L +#define SMMU_IDR5__GRAN64K_MASK 0x00000040L +#define SMMU_IDR5__STALL_MAX_MASK 0xFFFF0000L +//SMMU_IIDR +#define SMMU_IIDR__Implementer__SHIFT 0x0 +#define SMMU_IIDR__Revision__SHIFT 0xc +#define SMMU_IIDR__Variant__SHIFT 0x10 +#define SMMU_IIDR__ProductID__SHIFT 0x14 +#define SMMU_IIDR__Implementer_MASK 0x00000FFFL +#define SMMU_IIDR__Revision_MASK 0x0000F000L +#define SMMU_IIDR__Variant_MASK 0x000F0000L +#define SMMU_IIDR__ProductID_MASK 0xFFF00000L +//SMMU_AIDR +#define SMMU_AIDR__ArchMinorRev__SHIFT 0x0 +#define SMMU_AIDR__ArchMajorRev__SHIFT 0x4 +#define SMMU_AIDR__ArchMinorRev_MASK 0x0000000FL +#define SMMU_AIDR__ArchMajorRev_MASK 0x000000F0L +//SMMU_CR0 +#define SMMU_CR0__SMMUEN__SHIFT 0x0 +#define SMMU_CR0__PRIQEN__SHIFT 0x1 +#define SMMU_CR0__EVQEN__SHIFT 0x2 +#define SMMU_CR0__CMDEN__SHIFT 0x3 +#define SMMU_CR0__ATSCHK__SHIFT 0x4 +#define SMMU_CR0__VMW__SHIFT 0x6 +#define SMMU_CR0__SMMUEN_MASK 0x00000001L +#define SMMU_CR0__PRIQEN_MASK 0x00000002L +#define SMMU_CR0__EVQEN_MASK 0x00000004L +#define SMMU_CR0__CMDEN_MASK 0x00000008L +#define SMMU_CR0__ATSCHK_MASK 0x00000010L +#define SMMU_CR0__VMW_MASK 0x000001C0L +//SMMU_CR0ACK +#define SMMU_CR0ACK__SMMUEN__SHIFT 0x0 +#define SMMU_CR0ACK__PRIQEN__SHIFT 0x1 +#define SMMU_CR0ACK__EVQEN__SHIFT 0x2 +#define SMMU_CR0ACK__CMDEN__SHIFT 0x3 +#define SMMU_CR0ACK__ATSCHK__SHIFT 0x4 +#define SMMU_CR0ACK__VMW__SHIFT 0x6 +#define SMMU_CR0ACK__SMMUEN_MASK 0x00000001L +#define SMMU_CR0ACK__PRIQEN_MASK 0x00000002L +#define SMMU_CR0ACK__EVQEN_MASK 0x00000004L +#define SMMU_CR0ACK__CMDEN_MASK 0x00000008L +#define SMMU_CR0ACK__ATSCHK_MASK 0x00000010L +#define SMMU_CR0ACK__VMW_MASK 0x000001C0L +//SMMU_CR2 +#define SMMU_CR2__E2H__SHIFT 0x0 +#define SMMU_CR2__RECINVSID__SHIFT 0x1 +#define SMMU_CR2__PTM__SHIFT 0x2 +#define SMMU_CR2__E2H_MASK 0x00000001L +#define SMMU_CR2__RECINVSID_MASK 0x00000002L +#define SMMU_CR2__PTM_MASK 0x00000004L +//SMMU_GBPA +#define SMMU_GBPA__ABORT__SHIFT 0x14 +#define SMMU_GBPA__Update__SHIFT 0x1f +#define SMMU_GBPA__ABORT_MASK 0x00100000L +#define SMMU_GBPA__Update_MASK 0x80000000L +//SMMU_STRTAB_BASE_HI +#define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI__SHIFT 0x0 +#define SMMU_STRTAB_BASE_HI__STRTAB_RA__SHIFT 0x1e +#define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI_MASK 0x0000FFFFL +#define SMMU_STRTAB_BASE_HI__STRTAB_RA_MASK 0x40000000L +//SMMU_STRTAB_BASE_LO +#define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO__SHIFT 0x6 +#define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO_MASK 0xFFFFFFC0L +//SMMU_STRTAB_BASE_CFG +#define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE__SHIFT 0x0 +#define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT__SHIFT 0x6 +#define SMMU_STRTAB_BASE_CFG__STRTAB_FMT__SHIFT 0x10 +#define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE_MASK 0x0000003FL +#define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT_MASK 0x000007C0L +#define SMMU_STRTAB_BASE_CFG__STRTAB_FMT_MASK 0x00030000L + + +// addressBlock: nbio_iohub_nb_ioagrcfg_ioagr_cfgdec +//IOAGR_GLUE_CG_LCLK_CTRL_0 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOAGR_GLUE_CG_LCLK_CTRL_1 +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16 +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17 +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18 +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19 +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L +#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L +//IOAGR_REQDECODE_OVERRIDE +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18 +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L +#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L +//IOAGR_RSPDECODE_OVERRIDE +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18 +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L +#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L +//IOAGR_USERBIT_BYPASS +#define IOAGR_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0 +#define IOAGR_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L +//IOAGR_SDP_PORT_CONTROL +#define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0 +#define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf +#define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10 +#define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL +#define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L +#define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L +//IOAGR_PERF_CNTL +#define IOAGR_PERF_CNTL__EVENT0_SEL__SHIFT 0x0 +#define IOAGR_PERF_CNTL__EVENT1_SEL__SHIFT 0x8 +#define IOAGR_PERF_CNTL__EVENT2_SEL__SHIFT 0x10 +#define IOAGR_PERF_CNTL__EVENT3_SEL__SHIFT 0x18 +#define IOAGR_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL +#define IOAGR_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L +#define IOAGR_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L +#define IOAGR_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L +//IOAGR_PERF_COUNT0 +#define IOAGR_PERF_COUNT0__COUNTER0__SHIFT 0x0 +#define IOAGR_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL +//IOAGR_PERF_COUNT0_UPPER +#define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0 +#define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL +//IOAGR_PERF_COUNT1 +#define IOAGR_PERF_COUNT1__COUNTER1__SHIFT 0x0 +#define IOAGR_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL +//IOAGR_PERF_COUNT1_UPPER +#define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0 +#define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL +//IOAGR_PERF_COUNT2 +#define IOAGR_PERF_COUNT2__COUNTER2__SHIFT 0x0 +#define IOAGR_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL +//IOAGR_PERF_COUNT2_UPPER +#define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0 +#define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL +//IOAGR_PERF_COUNT3 +#define IOAGR_PERF_COUNT3__COUNTER3__SHIFT 0x0 +#define IOAGR_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL +//IOAGR_PERF_COUNT3_UPPER +#define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0 +#define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL +//IOAGR_PGMST_CNTL +#define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 +#define IOAGR_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 +#define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define IOAGR_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L +#define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//IOAGR_PGSLV_CNTL +#define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//IOAGR_SION_S0_Client0_Req_BurstTarget_Lower +#define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_Req_BurstTarget_Upper +#define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_Req_TimeSlot_Lower +#define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_Req_TimeSlot_Upper +#define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_Req_BurstTarget_Lower +#define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_Req_BurstTarget_Upper +#define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_Req_TimeSlot_Lower +#define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_Req_TimeSlot_Upper +#define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower +#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper +#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower +#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper +#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_Req_BurstTarget_Lower +#define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_Req_BurstTarget_Upper +#define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_Req_TimeSlot_Lower +#define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_Req_TimeSlot_Upper +#define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_Req_BurstTarget_Lower +#define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_Req_BurstTarget_Upper +#define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_Req_TimeSlot_Lower +#define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_Req_TimeSlot_Upper +#define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower +#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper +#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower +#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper +#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_Req_BurstTarget_Lower +#define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_Req_BurstTarget_Upper +#define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_Req_TimeSlot_Lower +#define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_Req_TimeSlot_Upper +#define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_Req_BurstTarget_Lower +#define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_Req_BurstTarget_Upper +#define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_Req_TimeSlot_Lower +#define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_Req_TimeSlot_Upper +#define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower +#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper +#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower +#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper +#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_Req_BurstTarget_Lower +#define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_Req_BurstTarget_Upper +#define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_Req_TimeSlot_Lower +#define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_Req_TimeSlot_Upper +#define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_Req_BurstTarget_Lower +#define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_Req_BurstTarget_Upper +#define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_Req_TimeSlot_Lower +#define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_Req_TimeSlot_Upper +#define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower +#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper +#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower +#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper +#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0 +#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower +#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper +#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower +#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper +#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower +#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0 +#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL +//IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper +#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0 +#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL +//IOAGR_SION_LiveLock_WatchDog_Threshold +#define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0 +#define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL + + +// addressBlock: nbio_sst0_sst_core_sstcorecfg +//SST_CORE0_SST_CLOCK_CTRL +#define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0 +#define SST_CORE0_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1 +#define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8 +#define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10 +#define SST_CORE0_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11 +#define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L +#define SST_CORE0_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL +#define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L +#define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L +#define SST_CORE0_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L +//SST_CORE0_SST_ENABLE_CTRL +#define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0 +#define SST_CORE0_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1 +#define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8 +#define SST_CORE0_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9 +#define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L +#define SST_CORE0_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL +#define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L +#define SST_CORE0_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L +//SST_CORE0_SST_RSMU_HCID +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0 +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6 +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd +#define SST_CORE0_SST_RSMU_HCID__RESERVED__SHIFT 0x14 +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L +#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L +#define SST_CORE0_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L +//SST_CORE0_SST_RSMU_SIID +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0 +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6 +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd +#define SST_CORE0_SST_RSMU_SIID__RESERVED__SHIFT 0x14 +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L +#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L +#define SST_CORE0_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L +//SST_CORE0_SST_STATISTIC_0 +#define SST_CORE0_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0 +#define SST_CORE0_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10 +#define SST_CORE0_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL +#define SST_CORE0_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L +//SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO +#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI +#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO +#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI +#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO +#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI +#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO +#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI +#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO +#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI +#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO +#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI +#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS +#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0 +#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8 +#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL +#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L +//SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L +#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L +//SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO +#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI +#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO +#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI +#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO +#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI +#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO +#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI +#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE0_SST_BACKDOOR0 +#define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0 +#define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL +//SST_CORE0_SST_BACKDOOR1 +#define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0 +#define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL +//SST_CORE0_SST_BACKDOOR2 +#define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0 +#define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_sst1_sst_core_sstcorecfg +//SST_CORE1_SST_CLOCK_CTRL +#define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0 +#define SST_CORE1_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1 +#define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8 +#define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10 +#define SST_CORE1_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11 +#define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L +#define SST_CORE1_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL +#define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L +#define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L +#define SST_CORE1_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L +//SST_CORE1_SST_ENABLE_CTRL +#define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0 +#define SST_CORE1_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1 +#define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8 +#define SST_CORE1_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9 +#define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L +#define SST_CORE1_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL +#define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L +#define SST_CORE1_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L +//SST_CORE1_SST_RSMU_HCID +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0 +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6 +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd +#define SST_CORE1_SST_RSMU_HCID__RESERVED__SHIFT 0x14 +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L +#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L +#define SST_CORE1_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L +//SST_CORE1_SST_RSMU_SIID +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0 +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6 +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd +#define SST_CORE1_SST_RSMU_SIID__RESERVED__SHIFT 0x14 +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L +#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L +#define SST_CORE1_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L +//SST_CORE1_SST_STATISTIC_0 +#define SST_CORE1_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0 +#define SST_CORE1_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10 +#define SST_CORE1_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL +#define SST_CORE1_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L +//SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO +#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI +#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO +#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI +#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO +#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI +#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO +#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI +#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO +#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI +#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO +#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL +//SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI +#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0 +#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL +//SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS +#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0 +#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8 +#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL +#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L +//SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L +#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L +//SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO +#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI +#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO +#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI +#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO +#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI +#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO +#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0 +#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL +//SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI +#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0 +#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL +//SST_CORE1_SST_BACKDOOR0 +#define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0 +#define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL +//SST_CORE1_SST_BACKDOOR1 +#define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0 +#define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL +//SST_CORE1_SST_BACKDOOR2 +#define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0 +#define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg +//IOMMU_MMIO_DEVTBL_BASE_0 +#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_BASE_1 +#define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_CMD_BASE_0 +#define IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_CMD_BASE_1 +#define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18 +#define IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L +#define IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_MMIO_EVENT_BASE_0 +#define IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_EVENT_BASE_1 +#define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18 +#define IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L +#define IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_MMIO_CNTRL_0 +#define IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0 +#define IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1 +#define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2 +#define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3 +#define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4 +#define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5 +#define IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8 +#define IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9 +#define IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa +#define IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb +#define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc +#define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd +#define IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe +#define IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf +#define IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10 +#define IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11 +#define IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12 +#define IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16 +#define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18 +#define IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19 +#define IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c +#define IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d +#define IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e +#define IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L +#define IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L +#define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L +#define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L +#define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L +#define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L +#define IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L +#define IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L +#define IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L +#define IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L +#define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L +#define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L +#define IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L +#define IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L +#define IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L +#define IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L +#define IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L +#define IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L +#define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L +#define IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L +#define IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L +#define IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L +#define IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L +//IOMMU_MMIO_CNTRL_1 +#define IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0 +#define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2 +#define IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4 +#define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5 +#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7 +#define IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8 +#define IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9 +#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa +#define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb +#define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc +#define IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd +#define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe +#define IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10 +#define IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11 +#define IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L +#define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL +#define IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L +#define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L +#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L +#define IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L +#define IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L +#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L +#define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L +#define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L +#define IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L +#define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L +#define IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L +#define IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L +//IOMMU_MMIO_EXCL_BASE_0 +#define IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0 +#define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1 +#define IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2 +#define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L +#define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L +#define IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL +#define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_EXCL_BASE_1 +#define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_EXCL_LIM_0 +#define IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc +#define IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL +#define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_EXCL_LIM_1 +#define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0 +#define IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_EFR_0 +#define IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0 +#define IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1 +#define IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2 +#define IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3 +#define IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4 +#define IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5 +#define IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6 +#define IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7 +#define IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8 +#define IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9 +#define IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa +#define IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc +#define IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe +#define IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10 +#define IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12 +#define IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15 +#define IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18 +#define IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a +#define IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c +#define IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e +#define IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f +#define IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L +#define IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L +#define IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L +#define IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L +#define IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L +#define IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L +#define IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L +#define IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L +#define IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L +#define IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L +#define IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L +#define IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L +#define IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L +#define IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L +#define IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L +#define IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L +#define IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L +#define IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L +#define IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L +#define IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L +#define IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L +//IOMMU_MMIO_EFR_1 +#define IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0 +#define IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4 +#define IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5 +#define IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6 +#define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8 +#define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9 +#define IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa +#define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc +#define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd +#define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe +#define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf +#define IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10 +#define IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11 +#define IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12 +#define IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13 +#define IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14 +#define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15 +#define IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16 +#define IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17 +#define IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL +#define IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L +#define IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L +#define IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L +#define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L +#define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L +#define IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L +#define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L +#define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L +#define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L +#define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L +#define IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L +#define IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L +#define IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L +#define IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L +#define IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L +#define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L +#define IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L +#define IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L +//IOMMU_MMIO_PPR_BASE_0 +#define IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_PPR_BASE_1 +#define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18 +#define IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L +#define IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_MMIO_HW_ERR_UPPER_0 +#define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_HW_ERR_UPPER_1 +#define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c +#define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL +#define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L +//IOMMU_MMIO_HW_ERR_LOWER_0 +#define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_HW_ERR_LOWER_1 +#define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL +//IOMMU_MMIO_HW_ERR_STATUS_0 +#define IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1 +#define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2 +#define IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L +#define IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L +#define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL +//IOMMU_MMIO_HW_ERR_STATUS_1 +#define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0 +#define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL +//SMI_FILTER_REGISTER_0_0 +#define SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0 +#define SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10 +#define SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11 +#define SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12 +#define SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL +#define SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L +#define SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L +#define SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L +//SMI_FILTER_REGISTER_0_1 +#define SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0 +#define SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL +//SMI_FILTER_REGISTER_1_0 +#define SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0 +#define SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10 +#define SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11 +#define SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12 +#define SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL +#define SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L +#define SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L +#define SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L +//SMI_FILTER_REGISTER_1_1 +#define SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0 +#define SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL +//SMI_FILTER_REGISTER_2_0 +#define SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0 +#define SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10 +#define SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11 +#define SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12 +#define SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL +#define SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L +#define SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L +#define SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L +//SMI_FILTER_REGISTER_2_1 +#define SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0 +#define SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL +//SMI_FILTER_REGISTER_3_0 +#define SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0 +#define SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10 +#define SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11 +#define SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12 +#define SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL +#define SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L +#define SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L +#define SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L +//SMI_FILTER_REGISTER_3_1 +#define SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0 +#define SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL +//IOMMU_MMIO_GA_LOG_BASE_0 +#define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_GA_LOG_BASE_1 +#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18 +#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L +//IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 +#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3 +#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L +//IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 +#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0 +#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL +//IOMMU_MMIO_PPR_B_BASE_0 +#define IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_PPR_B_BASE_1 +#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18 +#define IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L +#define IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_MMIO_EVENT_B_BASE_0 +#define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL +#define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_EVENT_B_BASE_1 +#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14 +#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18 +#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c +#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L +#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L +#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L +//IOMMU_MMIO_DEVTBL_1_BASE_0 +#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_1_BASE_1 +#define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_2_BASE_0 +#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_2_BASE_1 +#define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_3_BASE_0 +#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_3_BASE_1 +#define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_4_BASE_0 +#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_4_BASE_1 +#define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_5_BASE_0 +#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_5_BASE_1 +#define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_6_BASE_0 +#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_6_BASE_1 +#define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DEVTBL_7_BASE_0 +#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9 +#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc +#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL +#define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L +#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L +//IOMMU_MMIO_DEVTBL_7_BASE_1 +#define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0 +#define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L +//IOMMU_MMIO_DSFX +#define IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0 +#define IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL +#define IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_MMIO_DSCX +#define IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0 +#define IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL +#define IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_MMIO_DSSX +#define IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0 +#define IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL +#define IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_MMIO_CAP_MISC +#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 +#define IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5 +#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b +#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL +#define IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L +#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L +//IOMMU_MMIO_CAP_MISC_1 +#define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 +#define IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5 +#define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL +#define IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L +//IOMMU_MMIO_MSI_CAP +#define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 +#define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 +#define IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10 +#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 +#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 +#define IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17 +#define IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18 +#define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL +#define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L +#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L +#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L +#define IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L +#define IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L +//IOMMU_MMIO_MSI_ADDR_LO +#define IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0 +#define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 +#define IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L +#define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL +//IOMMU_MMIO_MSI_ADDR_HI +#define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 +#define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_MMIO_MSI_DATA +#define IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0 +#define IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL +#define IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_MSI_MAPPING_CAP +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L +#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L +//IOMMU_MMIO_CONTROL_W +#define IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd +#define IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe +#define IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL +#define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L +#define IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L +//IOMMU_MARC_BASE_LO_0 +#define IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0 +#define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc +#define IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L +//IOMMU_MARC_BASE_HI_0 +#define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0 +#define IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL +#define IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_RELOC_LO_0 +#define IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0 +#define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1 +#define IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2 +#define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc +#define IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L +#define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L +#define IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL +#define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L +//IOMMU_MARC_RELOC_HI_0 +#define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0 +#define IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL +#define IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_LEN_LO_0 +#define IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0 +#define IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc +#define IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L +//IOMMU_MARC_LEN_HI_0 +#define IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0 +#define IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14 +#define IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL +#define IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_BASE_LO_1 +#define IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0 +#define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc +#define IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L +//IOMMU_MARC_BASE_HI_1 +#define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0 +#define IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL +#define IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_RELOC_LO_1 +#define IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0 +#define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1 +#define IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2 +#define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc +#define IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L +#define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L +#define IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL +#define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L +//IOMMU_MARC_RELOC_HI_1 +#define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0 +#define IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL +#define IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_LEN_LO_1 +#define IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0 +#define IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc +#define IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L +//IOMMU_MARC_LEN_HI_1 +#define IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0 +#define IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14 +#define IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL +#define IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_BASE_LO_2 +#define IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0 +#define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc +#define IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L +//IOMMU_MARC_BASE_HI_2 +#define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0 +#define IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL +#define IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_RELOC_LO_2 +#define IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0 +#define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1 +#define IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2 +#define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc +#define IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L +#define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L +#define IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL +#define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L +//IOMMU_MARC_RELOC_HI_2 +#define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0 +#define IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL +#define IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_LEN_LO_2 +#define IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0 +#define IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc +#define IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L +//IOMMU_MARC_LEN_HI_2 +#define IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0 +#define IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14 +#define IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL +#define IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_BASE_LO_3 +#define IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0 +#define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc +#define IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L +//IOMMU_MARC_BASE_HI_3 +#define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0 +#define IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL +#define IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_RELOC_LO_3 +#define IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0 +#define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1 +#define IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2 +#define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc +#define IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L +#define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L +#define IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL +#define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L +//IOMMU_MARC_RELOC_HI_3 +#define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0 +#define IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL +#define IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_MARC_LEN_LO_3 +#define IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0 +#define IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc +#define IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL +#define IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L +//IOMMU_MARC_LEN_HI_3 +#define IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0 +#define IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14 +#define IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL +#define IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L +//IOMMU_MMIO_CMD_BUF_HDPTR_0 +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4 +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_CMD_BUF_HDPTR_1 +#define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_CMD_BUF_TAILPTR_0 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_CMD_BUF_TAILPTR_1 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_EVENT_BUF_HDPTR_0 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_EVENT_BUF_HDPTR_1 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_EVENT_BUF_TAILPTR_0 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_EVENT_BUF_TAILPTR_1 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_STATUS_0 +#define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0 +#define IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1 +#define IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2 +#define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3 +#define IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4 +#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5 +#define IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6 +#define IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7 +#define IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8 +#define IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9 +#define IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa +#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb +#define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc +#define IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd +#define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf +#define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10 +#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11 +#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12 +#define IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L +#define IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L +#define IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L +#define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L +#define IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L +#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L +#define IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L +#define IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L +#define IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L +#define IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L +#define IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L +#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L +#define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L +#define IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L +#define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L +#define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L +#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L +#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L +#define IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_STATUS_1 +#define IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PPR_BUF_HDPTR_0 +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4 +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_PPR_BUF_HDPTR_1 +#define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PPR_BUF_TAILPTR_0 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_PPR_BUF_TAILPTR_1 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_GA_BUF_HDPTR_0 +#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3 +#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L +#define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L +#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L +//IOMMU_MMIO_GA_BUF_HDPTR_1 +#define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_GA_BUF_TAILPTR_0 +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3 +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L +#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L +//IOMMU_MMIO_GA_BUF_TAILPTR_1 +#define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PPR_B_BUF_HDPTR_0 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_PPR_B_BUF_HDPTR_1 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PPR_B_BUF_TAILPTR_0 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_PPR_B_BUF_TAILPTR_1 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_EVENT_B_BUF_HDPTR_0 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_EVENT_B_BUF_HDPTR_1 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L +//IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PPR_AUTORESP_0 +#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0 +#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4 +#define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5 +#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL +#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L +#define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L +//IOMMU_MMIO_PPR_OVERFLOW_EARLY_0 +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0 +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L +#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L +//IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0 +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L +#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_CONFIG_0 +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7 +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb +#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12 +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL +#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L +#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L +#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L +//IOMMU_MMIO_COUNTER_CONFIG_1 +#define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 +#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 +#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 +#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 +#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 +#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 +#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10 +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL +#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L +//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L +//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L +//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L +//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10 +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL +#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL +//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14 +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L +#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L + + +// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec +//NB_NBCFG2_NB_VENDOR_ID +#define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//NB_NBCFG2_NB_DEVICE_ID +#define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//NB_NBCFG2_NB_COMMAND +#define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//NB_NBCFG2_NB_STATUS +#define NB_NBCFG2_NB_STATUS__CAP_LIST__SHIFT 0x4 +#define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define NB_NBCFG2_NB_STATUS__CAP_LIST_MASK 0x0010L +#define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +//NB_NBCFG2_NB_REVISION_ID +#define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//NB_NBCFG2_NB_REGPROG_INF +#define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//NB_NBCFG2_NB_SUB_CLASS +#define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//NB_NBCFG2_NB_BASE_CODE +#define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//NB_NBCFG2_NB_CACHE_LINE +#define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//NB_NBCFG2_NB_LATENCY +#define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL +//NB_NBCFG2_NB_HEADER +#define NB_NBCFG2_NB_HEADER__HEADER_TYPE__SHIFT 0x0 +#define NB_NBCFG2_NB_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG2_NB_HEADER__HEADER_TYPE_MASK 0x7FL +#define NB_NBCFG2_NB_HEADER__DEVICE_TYPE_MASK 0x80L +//NB_NBCFG2_NB_ADAPTER_ID +#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG2_NB_CAPABILITIES_PTR +#define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//NB_NBCFG2_NB_HEADER_W +#define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L +//NB_NBCFG2_NB_PCI_CTRL +#define NB_NBCFG2_NB_PCI_CTRL__PMEDis__SHIFT 0x4 +#define NB_NBCFG2_NB_PCI_CTRL__SErrDis__SHIFT 0x5 +#define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17 +#define NB_NBCFG2_NB_PCI_CTRL__HPDis__SHIFT 0x1a +#define NB_NBCFG2_NB_PCI_CTRL__PMEDis_MASK 0x00000010L +#define NB_NBCFG2_NB_PCI_CTRL__SErrDis_MASK 0x00000020L +#define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L +#define NB_NBCFG2_NB_PCI_CTRL__HPDis_MASK 0x04000000L +//NB_NBCFG2_NB_ADAPTER_ID_W +#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_0 +#define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_0 +#define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL +//NB_NBCFG2_NBCFG_SCRATCH_0 +#define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0 +#define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL +//NB_NBCFG2_NBCFG_SCRATCH_1 +#define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0 +#define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL +//NB_NBCFG2_NBCFG_SCRATCH_2 +#define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0 +#define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL +//NB_NBCFG2_NBCFG_SCRATCH_3 +#define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0 +#define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL +//NB_NBCFG2_NBCFG_SCRATCH_4 +#define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 +#define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_PCI_ARB +#define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define NB_NBCFG2_NB_PCI_ARB__PMEMode__SHIFT 0x8 +#define NB_NBCFG2_NB_PCI_ARB__PMETurnOff__SHIFT 0x9 +#define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa +#define NB_NBCFG2_NB_PCI_ARB__PMETarget__SHIFT 0x10 +#define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +#define NB_NBCFG2_NB_PCI_ARB__PMEMode_MASK 0x00000100L +#define NB_NBCFG2_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L +#define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L +#define NB_NBCFG2_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L +//NB_NBCFG2_NB_DRAM_SLOT1_BASE +#define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17 +#define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L +//NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1 +#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0 +#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L +#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_1 +#define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_1 +#define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_INDEX_DATA_MUTEX0 +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0 +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L +//NB_NBCFG2_NB_INDEX_DATA_MUTEX1 +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0 +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL +#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_2 +#define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_2 +#define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_3 +#define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_3 +#define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_4 +#define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_4 +#define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL +//NB_NBCFG2_NB_SMN_INDEX_5 +#define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_5 +#define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_PERF_CNT_CTRL +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17 +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L +#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L +//NB_NBCFG2_NB_SMN_INDEX_6 +#define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL +//NB_NBCFG2_NB_SMN_DATA_6 +#define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0 +#define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_iohub_iommu_l2_iommul2cfg +//IOMMU_L2_2_IOMMU_VENDOR_ID +#define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//IOMMU_L2_2_IOMMU_DEVICE_ID +#define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//IOMMU_L2_2_IOMMU_COMMAND +#define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved1__SHIFT 0x3 +#define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6 +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved0__SHIFT 0x7 +#define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved2__SHIFT 0x9 +#define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved__SHIFT 0xb +#define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved1_MASK 0x0038L +#define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved0_MASK 0x0080L +#define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN_MASK 0x0100L +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved2_MASK 0x0200L +#define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L +#define IOMMU_L2_2_IOMMU_COMMAND__Reserved_MASK 0xF800L +//IOMMU_L2_2_IOMMU_STATUS +#define IOMMU_L2_2_IOMMU_STATUS__Reserved__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_STATUS__INT_Status__SHIFT 0x3 +#define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST__SHIFT 0x4 +#define IOMMU_L2_2_IOMMU_STATUS__Reserved1__SHIFT 0x5 +#define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_STATUS__Reserved2__SHIFT 0x9 +#define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define IOMMU_L2_2_IOMMU_STATUS__Reserved_MASK 0x0007L +#define IOMMU_L2_2_IOMMU_STATUS__INT_Status_MASK 0x0008L +#define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST_MASK 0x0010L +#define IOMMU_L2_2_IOMMU_STATUS__Reserved1_MASK 0x00E0L +#define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L +#define IOMMU_L2_2_IOMMU_STATUS__Reserved2_MASK 0x0600L +#define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//IOMMU_L2_2_IOMMU_REVISION_ID +#define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//IOMMU_L2_2_IOMMU_REGPROG_INF +#define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL +//IOMMU_L2_2_IOMMU_SUB_CLASS +#define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL +//IOMMU_L2_2_IOMMU_BASE_CODE +#define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL +//IOMMU_L2_2_IOMMU_CACHE_LINE +#define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//IOMMU_L2_2_IOMMU_LATENCY +#define IOMMU_L2_2_IOMMU_LATENCY__LATENCY__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_LATENCY__LATENCY_MASK 0xFFL +//IOMMU_L2_2_IOMMU_HEADER +#define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL +//IOMMU_L2_2_IOMMU_BIST +#define IOMMU_L2_2_IOMMU_BIST__BIST_COMP__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_BIST__BIST_STRT__SHIFT 0x6 +#define IOMMU_L2_2_IOMMU_BIST__BIST_CAP__SHIFT 0x7 +#define IOMMU_L2_2_IOMMU_BIST__BIST_COMP_MASK 0x0FL +#define IOMMU_L2_2_IOMMU_BIST__BIST_STRT_MASK 0x40L +#define IOMMU_L2_2_IOMMU_BIST__BIST_CAP_MASK 0x80L +//IOMMU_L2_2_IOMMU_ADAPTER_ID +#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//IOMMU_L2_2_IOMMU_CAPABILITIES_PTR +#define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL +//IOMMU_L2_2_IOMMU_INTERRUPT_LINE +#define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//IOMMU_L2_2_IOMMU_INTERRUPT_PIN +#define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IOMMU_L2_2_IOMMU_CAP_HEADER +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19 +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c +#define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L +#define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L +//IOMMU_L2_2_IOMMU_CAP_BASE_LO +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1 +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13 +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL +#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L +//IOMMU_L2_2_IOMMU_CAP_BASE_HI +#define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_2_IOMMU_CAP_RANGE +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL +#define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L +#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L +//IOMMU_L2_2_IOMMU_CAP_MISC +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5 +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16 +#define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17 +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L +#define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L +#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L +//IOMMU_L2_2_IOMMU_CAP_MISC_1 +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5 +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6 +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L +#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L +//IOMMU_L2_2_IOMMU_MSI_CAP +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17 +#define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L +#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L +#define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L +//IOMMU_L2_2_IOMMU_MSI_ADDR_LO +#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2 +#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L +#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL +//IOMMU_L2_2_IOMMU_MSI_ADDR_HI +#define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL +//IOMMU_L2_2_IOMMU_MSI_DATA +#define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL +#define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L +//IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11 +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12 +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L +#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L +//IOMMU_L2_2_IOMMU_ADAPTER_ID_W +#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL +#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L +//IOMMU_L2_2_IOMMU_CONTROL_W +#define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4 +#define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9 +#define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa +#define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd +#define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L +#define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L +#define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L +#define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L +#define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L +#define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L +//IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L +//IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15 +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L +#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L +//IOMMU_L2_2_IOMMU_RANGE_W +#define IOMMU_L2_2_IOMMU_RANGE_W__Reserved__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7 +#define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8 +#define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10 +#define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL +#define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L +#define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L +#define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L +#define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L +//IOMMU_L2_2_IOMMU_DSFX_CONTROL +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L +#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L +//IOMMU_L2_2_IOMMU_DSSX_DUMMY_0 +#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL +#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_2_IOMMU_DSCX_DUMMY_0 +#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0 +#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18 +#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL +#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L +//IOMMU_L2_2_L2B_POISON_DVM_CNTRL +#define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0 +#define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L +//IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0 +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2 +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8 +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L +#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L +//IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control +#define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4 +#define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L +//IOMMU_L2_2_SMMU_MMIO_IDR0_W +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18 +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L +//IOMMU_L2_2_SMMU_MMIO_IDR1_W +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6 +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10 +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15 +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L +#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L +//IOMMU_L2_2_SMMU_MMIO_IDR2_W +#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa +#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL +#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L +//IOMMU_L2_2_SMMU_MMIO_IDR3_W +#define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2 +#define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L +//IOMMU_L2_2_SMMU_MMIO_IDR5_W +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4 +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5 +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6 +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10 +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L +#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L +//IOMMU_L2_2_SMMU_MMIO_IIDR_W +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10 +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14 +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L +#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L +//IOMMU_L2_2_SMMU_AIDR_W +#define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0 +#define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4 +#define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL +#define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L + + +// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec +//NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_2_STATUS_COMMAND +#define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY0_2_CLASS_CODE_REVID +#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY0_2_HEADER_TYPE +#define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY0_2_HEADER_TYPE_W +#define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_pcie0_bifplr0_cfgdecp +//BIFPLR0_2_VENDOR_ID +#define BIFPLR0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR0_2_DEVICE_ID +#define BIFPLR0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR0_2_COMMAND +#define BIFPLR0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR0_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR0_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR0_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR0_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR0_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR0_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR0_2_STATUS +#define BIFPLR0_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR0_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR0_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_2_REVISION_ID +#define BIFPLR0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR0_2_PROG_INTERFACE +#define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR0_2_SUB_CLASS +#define BIFPLR0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR0_2_BASE_CLASS +#define BIFPLR0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR0_2_CACHE_LINE +#define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR0_2_LATENCY +#define BIFPLR0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR0_2_HEADER +#define BIFPLR0_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR0_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR0_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR0_2_BIST +#define BIFPLR0_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR0_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR0_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR0_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR0_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR0_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR0_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR0_2_IO_BASE_LIMIT +#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR0_2_SECONDARY_STATUS +#define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR0_2_MEM_BASE_LIMIT +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_2_PREF_BASE_LIMIT +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR0_2_PREF_BASE_UPPER +#define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_2_PREF_LIMIT_UPPER +#define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR0_2_IO_BASE_LIMIT_HI +#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR0_2_CAP_PTR +#define BIFPLR0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR0_2_INTERRUPT_LINE +#define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR0_2_INTERRUPT_PIN +#define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR0_2_IRQ_BRIDGE_CNTL +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR0_2_EXT_BRIDGE_CNTL +#define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR0_2_PMI_CAP_LIST +#define BIFPLR0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_2_PMI_CAP +#define BIFPLR0_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR0_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR0_2_PMI_STATUS_CNTL +#define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR0_2_PCIE_CAP_LIST +#define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_2_PCIE_CAP +#define BIFPLR0_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR0_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR0_2_DEVICE_CAP +#define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR0_2_DEVICE_CNTL +#define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR0_2_DEVICE_STATUS +#define BIFPLR0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR0_2_LINK_CAP +#define BIFPLR0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR0_2_LINK_CNTL +#define BIFPLR0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR0_2_LINK_STATUS +#define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR0_2_SLOT_CAP +#define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR0_2_SLOT_CNTL +#define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR0_2_SLOT_STATUS +#define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR0_2_ROOT_CNTL +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR0_2_ROOT_CAP +#define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR0_2_ROOT_STATUS +#define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR0_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR0_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR0_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR0_2_DEVICE_CAP2 +#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR0_2_DEVICE_CNTL2 +#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR0_2_DEVICE_STATUS2 +#define BIFPLR0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_2_LINK_CAP2 +#define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR0_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR0_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR0_2_LINK_CNTL2 +#define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR0_2_LINK_STATUS2 +#define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR0_2_SLOT_CAP2 +#define BIFPLR0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR0_2_SLOT_CNTL2 +#define BIFPLR0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR0_2_SLOT_STATUS2 +#define BIFPLR0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR0_2_MSI_CAP_LIST +#define BIFPLR0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_2_MSI_MSG_CNTL +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR0_2_MSI_MSG_ADDR_LO +#define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR0_2_MSI_MSG_ADDR_HI +#define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_2_MSI_MSG_DATA +#define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR0_2_MSI_MSG_DATA_64 +#define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR0_2_SSID_CAP_LIST +#define BIFPLR0_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_2_SSID_CAP +#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR0_2_MSI_MAP_CAP_LIST +#define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR0_2_MSI_MAP_CAP +#define BIFPLR0_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR0_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR0_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR0_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR0_2_MSI_MAP_ADDR_LO +#define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR0_2_MSI_MAP_ADDR_HI +#define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR0_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_2_PCIE_PORT_VC_CNTL +#define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR0_2_PCIE_PORT_VC_STATUS +#define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR0_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR0_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR0_2_PCIE_CORR_ERR_STATUS +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR0_2_PCIE_CORR_ERR_MASK +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR0_2_PCIE_HDR_LOG0 +#define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_HDR_LOG1 +#define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_HDR_LOG2 +#define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_HDR_LOG3 +#define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_ROOT_ERR_CMD +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR0_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR0_2_PCIE_ERR_SRC_ID +#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR0_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_LINK_CNTL3 +#define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_ACS_CAP +#define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR0_2_PCIE_ACS_CNTL +#define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR0_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_MC_CAP +#define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR0_2_PCIE_MC_CNTL +#define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR0_2_PCIE_MC_ADDR0 +#define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR0_2_PCIE_MC_ADDR1 +#define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_RCV0 +#define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_RCV1 +#define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR0_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR0_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_DPC_CAP_LIST +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR0_2_PCIE_DPC_CNTL +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR0_2_PCIE_DPC_STATUS +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR0_2_PCIE_RP_PIO_STATUS +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR0_2_PCIE_RP_PIO_MASK +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR0_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR0_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR0_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR0_2_PCIE_ESM_CAP_LIST +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_ESM_HEADER_1 +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR0_2_PCIE_ESM_HEADER_2 +#define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR0_2_PCIE_ESM_STATUS +#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR0_2_PCIE_ESM_CTRL +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR0_2_PCIE_ESM_CAP_1 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR0_2_PCIE_ESM_CAP_2 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR0_2_PCIE_ESM_CAP_3 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR0_2_PCIE_ESM_CAP_4 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR0_2_PCIE_ESM_CAP_5 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR0_2_PCIE_ESM_CAP_6 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR0_2_PCIE_ESM_CAP_7 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr1_cfgdecp +//BIFPLR1_2_VENDOR_ID +#define BIFPLR1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR1_2_DEVICE_ID +#define BIFPLR1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR1_2_COMMAND +#define BIFPLR1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR1_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR1_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR1_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR1_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR1_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR1_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR1_2_STATUS +#define BIFPLR1_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR1_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR1_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_2_REVISION_ID +#define BIFPLR1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR1_2_PROG_INTERFACE +#define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR1_2_SUB_CLASS +#define BIFPLR1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR1_2_BASE_CLASS +#define BIFPLR1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR1_2_CACHE_LINE +#define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR1_2_LATENCY +#define BIFPLR1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR1_2_HEADER +#define BIFPLR1_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR1_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR1_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR1_2_BIST +#define BIFPLR1_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR1_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR1_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR1_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR1_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR1_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR1_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR1_2_IO_BASE_LIMIT +#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR1_2_SECONDARY_STATUS +#define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR1_2_MEM_BASE_LIMIT +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_2_PREF_BASE_LIMIT +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR1_2_PREF_BASE_UPPER +#define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_2_PREF_LIMIT_UPPER +#define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR1_2_IO_BASE_LIMIT_HI +#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR1_2_CAP_PTR +#define BIFPLR1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR1_2_INTERRUPT_LINE +#define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR1_2_INTERRUPT_PIN +#define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR1_2_IRQ_BRIDGE_CNTL +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR1_2_EXT_BRIDGE_CNTL +#define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR1_2_PMI_CAP_LIST +#define BIFPLR1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_2_PMI_CAP +#define BIFPLR1_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR1_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR1_2_PMI_STATUS_CNTL +#define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR1_2_PCIE_CAP_LIST +#define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_2_PCIE_CAP +#define BIFPLR1_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR1_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR1_2_DEVICE_CAP +#define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR1_2_DEVICE_CNTL +#define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR1_2_DEVICE_STATUS +#define BIFPLR1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR1_2_LINK_CAP +#define BIFPLR1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR1_2_LINK_CNTL +#define BIFPLR1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR1_2_LINK_STATUS +#define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR1_2_SLOT_CAP +#define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR1_2_SLOT_CNTL +#define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR1_2_SLOT_STATUS +#define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR1_2_ROOT_CNTL +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR1_2_ROOT_CAP +#define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR1_2_ROOT_STATUS +#define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR1_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR1_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR1_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR1_2_DEVICE_CAP2 +#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR1_2_DEVICE_CNTL2 +#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR1_2_DEVICE_STATUS2 +#define BIFPLR1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_2_LINK_CAP2 +#define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR1_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR1_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR1_2_LINK_CNTL2 +#define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR1_2_LINK_STATUS2 +#define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR1_2_SLOT_CAP2 +#define BIFPLR1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR1_2_SLOT_CNTL2 +#define BIFPLR1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR1_2_SLOT_STATUS2 +#define BIFPLR1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR1_2_MSI_CAP_LIST +#define BIFPLR1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_2_MSI_MSG_CNTL +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR1_2_MSI_MSG_ADDR_LO +#define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR1_2_MSI_MSG_ADDR_HI +#define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_2_MSI_MSG_DATA +#define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR1_2_MSI_MSG_DATA_64 +#define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR1_2_SSID_CAP_LIST +#define BIFPLR1_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_2_SSID_CAP +#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR1_2_MSI_MAP_CAP_LIST +#define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR1_2_MSI_MAP_CAP +#define BIFPLR1_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR1_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR1_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR1_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR1_2_MSI_MAP_ADDR_LO +#define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR1_2_MSI_MAP_ADDR_HI +#define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR1_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_2_PCIE_PORT_VC_CNTL +#define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR1_2_PCIE_PORT_VC_STATUS +#define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR1_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR1_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR1_2_PCIE_CORR_ERR_STATUS +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR1_2_PCIE_CORR_ERR_MASK +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR1_2_PCIE_HDR_LOG0 +#define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_HDR_LOG1 +#define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_HDR_LOG2 +#define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_HDR_LOG3 +#define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_ROOT_ERR_CMD +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR1_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR1_2_PCIE_ERR_SRC_ID +#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR1_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_LINK_CNTL3 +#define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_ACS_CAP +#define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR1_2_PCIE_ACS_CNTL +#define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR1_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_MC_CAP +#define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR1_2_PCIE_MC_CNTL +#define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR1_2_PCIE_MC_ADDR0 +#define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR1_2_PCIE_MC_ADDR1 +#define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_RCV0 +#define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_RCV1 +#define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR1_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR1_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_DPC_CAP_LIST +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR1_2_PCIE_DPC_CNTL +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR1_2_PCIE_DPC_STATUS +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR1_2_PCIE_RP_PIO_STATUS +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR1_2_PCIE_RP_PIO_MASK +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR1_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR1_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR1_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR1_2_PCIE_ESM_CAP_LIST +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_ESM_HEADER_1 +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR1_2_PCIE_ESM_HEADER_2 +#define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR1_2_PCIE_ESM_STATUS +#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR1_2_PCIE_ESM_CTRL +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR1_2_PCIE_ESM_CAP_1 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR1_2_PCIE_ESM_CAP_2 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR1_2_PCIE_ESM_CAP_3 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR1_2_PCIE_ESM_CAP_4 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR1_2_PCIE_ESM_CAP_5 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR1_2_PCIE_ESM_CAP_6 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR1_2_PCIE_ESM_CAP_7 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr2_cfgdecp +//BIFPLR2_2_VENDOR_ID +#define BIFPLR2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR2_2_DEVICE_ID +#define BIFPLR2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR2_2_COMMAND +#define BIFPLR2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR2_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR2_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR2_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR2_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR2_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR2_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR2_2_STATUS +#define BIFPLR2_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR2_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR2_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_2_REVISION_ID +#define BIFPLR2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR2_2_PROG_INTERFACE +#define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR2_2_SUB_CLASS +#define BIFPLR2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR2_2_BASE_CLASS +#define BIFPLR2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR2_2_CACHE_LINE +#define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR2_2_LATENCY +#define BIFPLR2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR2_2_HEADER +#define BIFPLR2_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR2_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR2_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR2_2_BIST +#define BIFPLR2_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR2_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR2_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR2_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR2_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR2_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR2_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR2_2_IO_BASE_LIMIT +#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR2_2_SECONDARY_STATUS +#define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR2_2_MEM_BASE_LIMIT +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_2_PREF_BASE_LIMIT +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR2_2_PREF_BASE_UPPER +#define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_2_PREF_LIMIT_UPPER +#define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR2_2_IO_BASE_LIMIT_HI +#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR2_2_CAP_PTR +#define BIFPLR2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR2_2_INTERRUPT_LINE +#define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR2_2_INTERRUPT_PIN +#define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR2_2_IRQ_BRIDGE_CNTL +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR2_2_EXT_BRIDGE_CNTL +#define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR2_2_PMI_CAP_LIST +#define BIFPLR2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_2_PMI_CAP +#define BIFPLR2_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR2_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR2_2_PMI_STATUS_CNTL +#define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR2_2_PCIE_CAP_LIST +#define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_2_PCIE_CAP +#define BIFPLR2_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR2_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR2_2_DEVICE_CAP +#define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR2_2_DEVICE_CNTL +#define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR2_2_DEVICE_STATUS +#define BIFPLR2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR2_2_LINK_CAP +#define BIFPLR2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR2_2_LINK_CNTL +#define BIFPLR2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR2_2_LINK_STATUS +#define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR2_2_SLOT_CAP +#define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR2_2_SLOT_CNTL +#define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR2_2_SLOT_STATUS +#define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR2_2_ROOT_CNTL +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR2_2_ROOT_CAP +#define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR2_2_ROOT_STATUS +#define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR2_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR2_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR2_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR2_2_DEVICE_CAP2 +#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR2_2_DEVICE_CNTL2 +#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR2_2_DEVICE_STATUS2 +#define BIFPLR2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_2_LINK_CAP2 +#define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR2_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR2_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR2_2_LINK_CNTL2 +#define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR2_2_LINK_STATUS2 +#define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR2_2_SLOT_CAP2 +#define BIFPLR2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR2_2_SLOT_CNTL2 +#define BIFPLR2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR2_2_SLOT_STATUS2 +#define BIFPLR2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR2_2_MSI_CAP_LIST +#define BIFPLR2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_2_MSI_MSG_CNTL +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR2_2_MSI_MSG_ADDR_LO +#define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR2_2_MSI_MSG_ADDR_HI +#define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_2_MSI_MSG_DATA +#define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR2_2_MSI_MSG_DATA_64 +#define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR2_2_SSID_CAP_LIST +#define BIFPLR2_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_2_SSID_CAP +#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR2_2_MSI_MAP_CAP_LIST +#define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR2_2_MSI_MAP_CAP +#define BIFPLR2_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR2_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR2_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR2_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR2_2_MSI_MAP_ADDR_LO +#define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR2_2_MSI_MAP_ADDR_HI +#define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR2_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_2_PCIE_PORT_VC_CNTL +#define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR2_2_PCIE_PORT_VC_STATUS +#define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR2_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR2_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR2_2_PCIE_CORR_ERR_STATUS +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR2_2_PCIE_CORR_ERR_MASK +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR2_2_PCIE_HDR_LOG0 +#define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_HDR_LOG1 +#define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_HDR_LOG2 +#define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_HDR_LOG3 +#define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_ROOT_ERR_CMD +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR2_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR2_2_PCIE_ERR_SRC_ID +#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR2_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_LINK_CNTL3 +#define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_ACS_CAP +#define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR2_2_PCIE_ACS_CNTL +#define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR2_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_MC_CAP +#define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR2_2_PCIE_MC_CNTL +#define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR2_2_PCIE_MC_ADDR0 +#define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR2_2_PCIE_MC_ADDR1 +#define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_RCV0 +#define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_RCV1 +#define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR2_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR2_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_DPC_CAP_LIST +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR2_2_PCIE_DPC_CNTL +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR2_2_PCIE_DPC_STATUS +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR2_2_PCIE_RP_PIO_STATUS +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR2_2_PCIE_RP_PIO_MASK +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR2_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR2_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR2_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR2_2_PCIE_ESM_CAP_LIST +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_ESM_HEADER_1 +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR2_2_PCIE_ESM_HEADER_2 +#define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR2_2_PCIE_ESM_STATUS +#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR2_2_PCIE_ESM_CTRL +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR2_2_PCIE_ESM_CAP_1 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR2_2_PCIE_ESM_CAP_2 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR2_2_PCIE_ESM_CAP_3 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR2_2_PCIE_ESM_CAP_4 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR2_2_PCIE_ESM_CAP_5 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR2_2_PCIE_ESM_CAP_6 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR2_2_PCIE_ESM_CAP_7 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr3_cfgdecp +//BIFPLR3_2_VENDOR_ID +#define BIFPLR3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR3_2_DEVICE_ID +#define BIFPLR3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR3_2_COMMAND +#define BIFPLR3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR3_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR3_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR3_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR3_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR3_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR3_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR3_2_STATUS +#define BIFPLR3_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR3_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR3_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_2_REVISION_ID +#define BIFPLR3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR3_2_PROG_INTERFACE +#define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR3_2_SUB_CLASS +#define BIFPLR3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR3_2_BASE_CLASS +#define BIFPLR3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR3_2_CACHE_LINE +#define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR3_2_LATENCY +#define BIFPLR3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR3_2_HEADER +#define BIFPLR3_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR3_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR3_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR3_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR3_2_BIST +#define BIFPLR3_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR3_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR3_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR3_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR3_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR3_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR3_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR3_2_IO_BASE_LIMIT +#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR3_2_SECONDARY_STATUS +#define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR3_2_MEM_BASE_LIMIT +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_2_PREF_BASE_LIMIT +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR3_2_PREF_BASE_UPPER +#define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_2_PREF_LIMIT_UPPER +#define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR3_2_IO_BASE_LIMIT_HI +#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR3_2_CAP_PTR +#define BIFPLR3_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR3_2_INTERRUPT_LINE +#define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR3_2_INTERRUPT_PIN +#define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR3_2_IRQ_BRIDGE_CNTL +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR3_2_EXT_BRIDGE_CNTL +#define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR3_2_PMI_CAP_LIST +#define BIFPLR3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_2_PMI_CAP +#define BIFPLR3_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR3_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR3_2_PMI_STATUS_CNTL +#define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR3_2_PCIE_CAP_LIST +#define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_2_PCIE_CAP +#define BIFPLR3_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR3_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR3_2_DEVICE_CAP +#define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR3_2_DEVICE_CNTL +#define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR3_2_DEVICE_STATUS +#define BIFPLR3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR3_2_LINK_CAP +#define BIFPLR3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR3_2_LINK_CNTL +#define BIFPLR3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR3_2_LINK_STATUS +#define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR3_2_SLOT_CAP +#define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR3_2_SLOT_CNTL +#define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR3_2_SLOT_STATUS +#define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR3_2_ROOT_CNTL +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR3_2_ROOT_CAP +#define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR3_2_ROOT_STATUS +#define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR3_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR3_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR3_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR3_2_DEVICE_CAP2 +#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR3_2_DEVICE_CNTL2 +#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR3_2_DEVICE_STATUS2 +#define BIFPLR3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_2_LINK_CAP2 +#define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR3_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR3_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR3_2_LINK_CNTL2 +#define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR3_2_LINK_STATUS2 +#define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR3_2_SLOT_CAP2 +#define BIFPLR3_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR3_2_SLOT_CNTL2 +#define BIFPLR3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR3_2_SLOT_STATUS2 +#define BIFPLR3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR3_2_MSI_CAP_LIST +#define BIFPLR3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_2_MSI_MSG_CNTL +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR3_2_MSI_MSG_ADDR_LO +#define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR3_2_MSI_MSG_ADDR_HI +#define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_2_MSI_MSG_DATA +#define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR3_2_MSI_MSG_DATA_64 +#define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR3_2_SSID_CAP_LIST +#define BIFPLR3_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_2_SSID_CAP +#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR3_2_MSI_MAP_CAP_LIST +#define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR3_2_MSI_MAP_CAP +#define BIFPLR3_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR3_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR3_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR3_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR3_2_MSI_MAP_ADDR_LO +#define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR3_2_MSI_MAP_ADDR_HI +#define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR3_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_2_PCIE_PORT_VC_CNTL +#define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR3_2_PCIE_PORT_VC_STATUS +#define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR3_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR3_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR3_2_PCIE_CORR_ERR_STATUS +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR3_2_PCIE_CORR_ERR_MASK +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR3_2_PCIE_HDR_LOG0 +#define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_HDR_LOG1 +#define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_HDR_LOG2 +#define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_HDR_LOG3 +#define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_ROOT_ERR_CMD +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR3_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR3_2_PCIE_ERR_SRC_ID +#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR3_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_LINK_CNTL3 +#define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_ACS_CAP +#define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR3_2_PCIE_ACS_CNTL +#define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR3_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_MC_CAP +#define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR3_2_PCIE_MC_CNTL +#define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR3_2_PCIE_MC_ADDR0 +#define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR3_2_PCIE_MC_ADDR1 +#define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_RCV0 +#define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_RCV1 +#define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR3_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR3_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_DPC_CAP_LIST +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR3_2_PCIE_DPC_CNTL +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR3_2_PCIE_DPC_STATUS +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR3_2_PCIE_RP_PIO_STATUS +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR3_2_PCIE_RP_PIO_MASK +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR3_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR3_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR3_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR3_2_PCIE_ESM_CAP_LIST +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_ESM_HEADER_1 +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR3_2_PCIE_ESM_HEADER_2 +#define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR3_2_PCIE_ESM_STATUS +#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR3_2_PCIE_ESM_CTRL +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR3_2_PCIE_ESM_CAP_1 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR3_2_PCIE_ESM_CAP_2 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR3_2_PCIE_ESM_CAP_3 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR3_2_PCIE_ESM_CAP_4 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR3_2_PCIE_ESM_CAP_5 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR3_2_PCIE_ESM_CAP_6 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR3_2_PCIE_ESM_CAP_7 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr4_cfgdecp +//BIFPLR4_2_VENDOR_ID +#define BIFPLR4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR4_2_DEVICE_ID +#define BIFPLR4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR4_2_COMMAND +#define BIFPLR4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR4_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR4_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR4_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR4_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR4_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR4_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR4_2_STATUS +#define BIFPLR4_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR4_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR4_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_2_REVISION_ID +#define BIFPLR4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR4_2_PROG_INTERFACE +#define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR4_2_SUB_CLASS +#define BIFPLR4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR4_2_BASE_CLASS +#define BIFPLR4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR4_2_CACHE_LINE +#define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR4_2_LATENCY +#define BIFPLR4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR4_2_HEADER +#define BIFPLR4_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR4_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR4_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR4_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR4_2_BIST +#define BIFPLR4_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR4_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR4_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR4_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR4_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR4_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR4_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR4_2_IO_BASE_LIMIT +#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR4_2_SECONDARY_STATUS +#define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR4_2_MEM_BASE_LIMIT +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_2_PREF_BASE_LIMIT +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR4_2_PREF_BASE_UPPER +#define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_2_PREF_LIMIT_UPPER +#define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR4_2_IO_BASE_LIMIT_HI +#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR4_2_CAP_PTR +#define BIFPLR4_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR4_2_INTERRUPT_LINE +#define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR4_2_INTERRUPT_PIN +#define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR4_2_IRQ_BRIDGE_CNTL +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR4_2_EXT_BRIDGE_CNTL +#define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR4_2_PMI_CAP_LIST +#define BIFPLR4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_2_PMI_CAP +#define BIFPLR4_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR4_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR4_2_PMI_STATUS_CNTL +#define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR4_2_PCIE_CAP_LIST +#define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_2_PCIE_CAP +#define BIFPLR4_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR4_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR4_2_DEVICE_CAP +#define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR4_2_DEVICE_CNTL +#define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR4_2_DEVICE_STATUS +#define BIFPLR4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR4_2_LINK_CAP +#define BIFPLR4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR4_2_LINK_CNTL +#define BIFPLR4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR4_2_LINK_STATUS +#define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR4_2_SLOT_CAP +#define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR4_2_SLOT_CNTL +#define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR4_2_SLOT_STATUS +#define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR4_2_ROOT_CNTL +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR4_2_ROOT_CAP +#define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR4_2_ROOT_STATUS +#define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR4_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR4_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR4_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR4_2_DEVICE_CAP2 +#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR4_2_DEVICE_CNTL2 +#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR4_2_DEVICE_STATUS2 +#define BIFPLR4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_2_LINK_CAP2 +#define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR4_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR4_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR4_2_LINK_CNTL2 +#define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR4_2_LINK_STATUS2 +#define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR4_2_SLOT_CAP2 +#define BIFPLR4_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR4_2_SLOT_CNTL2 +#define BIFPLR4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR4_2_SLOT_STATUS2 +#define BIFPLR4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR4_2_MSI_CAP_LIST +#define BIFPLR4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_2_MSI_MSG_CNTL +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR4_2_MSI_MSG_ADDR_LO +#define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR4_2_MSI_MSG_ADDR_HI +#define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_2_MSI_MSG_DATA +#define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR4_2_MSI_MSG_DATA_64 +#define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR4_2_SSID_CAP_LIST +#define BIFPLR4_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_2_SSID_CAP +#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR4_2_MSI_MAP_CAP_LIST +#define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR4_2_MSI_MAP_CAP +#define BIFPLR4_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR4_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR4_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR4_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR4_2_MSI_MAP_ADDR_LO +#define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR4_2_MSI_MAP_ADDR_HI +#define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR4_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_2_PCIE_PORT_VC_CNTL +#define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR4_2_PCIE_PORT_VC_STATUS +#define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR4_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR4_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR4_2_PCIE_CORR_ERR_STATUS +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR4_2_PCIE_CORR_ERR_MASK +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR4_2_PCIE_HDR_LOG0 +#define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_HDR_LOG1 +#define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_HDR_LOG2 +#define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_HDR_LOG3 +#define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_ROOT_ERR_CMD +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR4_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR4_2_PCIE_ERR_SRC_ID +#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR4_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_LINK_CNTL3 +#define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_ACS_CAP +#define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR4_2_PCIE_ACS_CNTL +#define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR4_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_MC_CAP +#define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR4_2_PCIE_MC_CNTL +#define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR4_2_PCIE_MC_ADDR0 +#define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR4_2_PCIE_MC_ADDR1 +#define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_RCV0 +#define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_RCV1 +#define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR4_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR4_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_DPC_CAP_LIST +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR4_2_PCIE_DPC_CNTL +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR4_2_PCIE_DPC_STATUS +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR4_2_PCIE_RP_PIO_STATUS +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR4_2_PCIE_RP_PIO_MASK +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR4_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR4_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR4_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR4_2_PCIE_ESM_CAP_LIST +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_ESM_HEADER_1 +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR4_2_PCIE_ESM_HEADER_2 +#define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR4_2_PCIE_ESM_STATUS +#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR4_2_PCIE_ESM_CTRL +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR4_2_PCIE_ESM_CAP_1 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR4_2_PCIE_ESM_CAP_2 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR4_2_PCIE_ESM_CAP_3 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR4_2_PCIE_ESM_CAP_4 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR4_2_PCIE_ESM_CAP_5 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR4_2_PCIE_ESM_CAP_6 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR4_2_PCIE_ESM_CAP_7 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr5_cfgdecp +//BIFPLR5_2_VENDOR_ID +#define BIFPLR5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR5_2_DEVICE_ID +#define BIFPLR5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR5_2_COMMAND +#define BIFPLR5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR5_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR5_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR5_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR5_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR5_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR5_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR5_2_STATUS +#define BIFPLR5_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR5_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR5_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_2_REVISION_ID +#define BIFPLR5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR5_2_PROG_INTERFACE +#define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR5_2_SUB_CLASS +#define BIFPLR5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR5_2_BASE_CLASS +#define BIFPLR5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR5_2_CACHE_LINE +#define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR5_2_LATENCY +#define BIFPLR5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR5_2_HEADER +#define BIFPLR5_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR5_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR5_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR5_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR5_2_BIST +#define BIFPLR5_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR5_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR5_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR5_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR5_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR5_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR5_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR5_2_IO_BASE_LIMIT +#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR5_2_SECONDARY_STATUS +#define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR5_2_MEM_BASE_LIMIT +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_2_PREF_BASE_LIMIT +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR5_2_PREF_BASE_UPPER +#define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_2_PREF_LIMIT_UPPER +#define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR5_2_IO_BASE_LIMIT_HI +#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR5_2_CAP_PTR +#define BIFPLR5_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR5_2_INTERRUPT_LINE +#define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR5_2_INTERRUPT_PIN +#define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR5_2_IRQ_BRIDGE_CNTL +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR5_2_EXT_BRIDGE_CNTL +#define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR5_2_PMI_CAP_LIST +#define BIFPLR5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_2_PMI_CAP +#define BIFPLR5_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR5_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR5_2_PMI_STATUS_CNTL +#define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR5_2_PCIE_CAP_LIST +#define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_2_PCIE_CAP +#define BIFPLR5_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR5_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR5_2_DEVICE_CAP +#define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR5_2_DEVICE_CNTL +#define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR5_2_DEVICE_STATUS +#define BIFPLR5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR5_2_LINK_CAP +#define BIFPLR5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR5_2_LINK_CNTL +#define BIFPLR5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR5_2_LINK_STATUS +#define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR5_2_SLOT_CAP +#define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR5_2_SLOT_CNTL +#define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR5_2_SLOT_STATUS +#define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR5_2_ROOT_CNTL +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR5_2_ROOT_CAP +#define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR5_2_ROOT_STATUS +#define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR5_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR5_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR5_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR5_2_DEVICE_CAP2 +#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR5_2_DEVICE_CNTL2 +#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR5_2_DEVICE_STATUS2 +#define BIFPLR5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_2_LINK_CAP2 +#define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR5_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR5_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR5_2_LINK_CNTL2 +#define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR5_2_LINK_STATUS2 +#define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR5_2_SLOT_CAP2 +#define BIFPLR5_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR5_2_SLOT_CNTL2 +#define BIFPLR5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR5_2_SLOT_STATUS2 +#define BIFPLR5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR5_2_MSI_CAP_LIST +#define BIFPLR5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_2_MSI_MSG_CNTL +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR5_2_MSI_MSG_ADDR_LO +#define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR5_2_MSI_MSG_ADDR_HI +#define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_2_MSI_MSG_DATA +#define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR5_2_MSI_MSG_DATA_64 +#define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR5_2_SSID_CAP_LIST +#define BIFPLR5_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_2_SSID_CAP +#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR5_2_MSI_MAP_CAP_LIST +#define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR5_2_MSI_MAP_CAP +#define BIFPLR5_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR5_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR5_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR5_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR5_2_MSI_MAP_ADDR_LO +#define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR5_2_MSI_MAP_ADDR_HI +#define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR5_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_2_PCIE_PORT_VC_CNTL +#define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR5_2_PCIE_PORT_VC_STATUS +#define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR5_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR5_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR5_2_PCIE_CORR_ERR_STATUS +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR5_2_PCIE_CORR_ERR_MASK +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR5_2_PCIE_HDR_LOG0 +#define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_HDR_LOG1 +#define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_HDR_LOG2 +#define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_HDR_LOG3 +#define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_ROOT_ERR_CMD +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR5_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR5_2_PCIE_ERR_SRC_ID +#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR5_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_LINK_CNTL3 +#define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_ACS_CAP +#define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR5_2_PCIE_ACS_CNTL +#define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR5_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_MC_CAP +#define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR5_2_PCIE_MC_CNTL +#define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR5_2_PCIE_MC_ADDR0 +#define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR5_2_PCIE_MC_ADDR1 +#define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_RCV0 +#define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_RCV1 +#define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR5_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR5_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_DPC_CAP_LIST +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR5_2_PCIE_DPC_CNTL +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR5_2_PCIE_DPC_STATUS +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR5_2_PCIE_RP_PIO_STATUS +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR5_2_PCIE_RP_PIO_MASK +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR5_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR5_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR5_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR5_2_PCIE_ESM_CAP_LIST +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_ESM_HEADER_1 +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR5_2_PCIE_ESM_HEADER_2 +#define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR5_2_PCIE_ESM_STATUS +#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR5_2_PCIE_ESM_CTRL +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR5_2_PCIE_ESM_CAP_1 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR5_2_PCIE_ESM_CAP_2 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR5_2_PCIE_ESM_CAP_3 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR5_2_PCIE_ESM_CAP_4 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR5_2_PCIE_ESM_CAP_5 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR5_2_PCIE_ESM_CAP_6 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR5_2_PCIE_ESM_CAP_7 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_pcie0_bifplr6_cfgdecp +//BIFPLR6_2_VENDOR_ID +#define BIFPLR6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIFPLR6_2_DEVICE_ID +#define BIFPLR6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIFPLR6_2_COMMAND +#define BIFPLR6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIFPLR6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIFPLR6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIFPLR6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIFPLR6_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIFPLR6_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIFPLR6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIFPLR6_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIFPLR6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIFPLR6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIFPLR6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIFPLR6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIFPLR6_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIFPLR6_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIFPLR6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIFPLR6_2_COMMAND__INT_DIS_MASK 0x0400L +//BIFPLR6_2_STATUS +#define BIFPLR6_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIFPLR6_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIFPLR6_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_2_REVISION_ID +#define BIFPLR6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIFPLR6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIFPLR6_2_PROG_INTERFACE +#define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIFPLR6_2_SUB_CLASS +#define BIFPLR6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIFPLR6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIFPLR6_2_BASE_CLASS +#define BIFPLR6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIFPLR6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIFPLR6_2_CACHE_LINE +#define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIFPLR6_2_LATENCY +#define BIFPLR6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIFPLR6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIFPLR6_2_HEADER +#define BIFPLR6_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIFPLR6_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIFPLR6_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIFPLR6_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIFPLR6_2_BIST +#define BIFPLR6_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIFPLR6_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIFPLR6_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIFPLR6_2_BIST__BIST_COMP_MASK 0x0FL +#define BIFPLR6_2_BIST__BIST_STRT_MASK 0x40L +#define BIFPLR6_2_BIST__BIST_CAP_MASK 0x80L +//BIFPLR6_2_SUB_BUS_NUMBER_LATENCY +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIFPLR6_2_IO_BASE_LIMIT +#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIFPLR6_2_SECONDARY_STATUS +#define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIFPLR6_2_MEM_BASE_LIMIT +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_2_PREF_BASE_LIMIT +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIFPLR6_2_PREF_BASE_UPPER +#define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_2_PREF_LIMIT_UPPER +#define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIFPLR6_2_IO_BASE_LIMIT_HI +#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIFPLR6_2_CAP_PTR +#define BIFPLR6_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIFPLR6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIFPLR6_2_INTERRUPT_LINE +#define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIFPLR6_2_INTERRUPT_PIN +#define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIFPLR6_2_IRQ_BRIDGE_CNTL +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIFPLR6_2_EXT_BRIDGE_CNTL +#define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIFPLR6_2_PMI_CAP_LIST +#define BIFPLR6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_2_PMI_CAP +#define BIFPLR6_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIFPLR6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIFPLR6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIFPLR6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIFPLR6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIFPLR6_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIFPLR6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIFPLR6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIFPLR6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIFPLR6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIFPLR6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIFPLR6_2_PMI_STATUS_CNTL +#define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIFPLR6_2_PCIE_CAP_LIST +#define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_2_PCIE_CAP +#define BIFPLR6_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIFPLR6_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIFPLR6_2_DEVICE_CAP +#define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIFPLR6_2_DEVICE_CNTL +#define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIFPLR6_2_DEVICE_STATUS +#define BIFPLR6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIFPLR6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIFPLR6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIFPLR6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIFPLR6_2_LINK_CAP +#define BIFPLR6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIFPLR6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIFPLR6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIFPLR6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIFPLR6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIFPLR6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIFPLR6_2_LINK_CNTL +#define BIFPLR6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIFPLR6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIFPLR6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIFPLR6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIFPLR6_2_LINK_STATUS +#define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIFPLR6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIFPLR6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIFPLR6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIFPLR6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIFPLR6_2_SLOT_CAP +#define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIFPLR6_2_SLOT_CNTL +#define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +//BIFPLR6_2_SLOT_STATUS +#define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIFPLR6_2_ROOT_CNTL +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIFPLR6_2_ROOT_CAP +#define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIFPLR6_2_ROOT_STATUS +#define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIFPLR6_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIFPLR6_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIFPLR6_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIFPLR6_2_DEVICE_CAP2 +#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIFPLR6_2_DEVICE_CNTL2 +#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIFPLR6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIFPLR6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIFPLR6_2_DEVICE_STATUS2 +#define BIFPLR6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_2_LINK_CAP2 +#define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIFPLR6_2_LINK_CAP2__RESERVED__SHIFT 0x13 +#define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L +#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L +#define BIFPLR6_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L +//BIFPLR6_2_LINK_CNTL2 +#define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIFPLR6_2_LINK_STATUS2 +#define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIFPLR6_2_SLOT_CAP2 +#define BIFPLR6_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIFPLR6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIFPLR6_2_SLOT_CNTL2 +#define BIFPLR6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIFPLR6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIFPLR6_2_SLOT_STATUS2 +#define BIFPLR6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIFPLR6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIFPLR6_2_MSI_CAP_LIST +#define BIFPLR6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_2_MSI_MSG_CNTL +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIFPLR6_2_MSI_MSG_ADDR_LO +#define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIFPLR6_2_MSI_MSG_ADDR_HI +#define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_2_MSI_MSG_DATA +#define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIFPLR6_2_MSI_MSG_DATA_64 +#define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIFPLR6_2_SSID_CAP_LIST +#define BIFPLR6_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_2_SSID_CAP +#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIFPLR6_2_MSI_MAP_CAP_LIST +#define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIFPLR6_2_MSI_MAP_CAP +#define BIFPLR6_2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIFPLR6_2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIFPLR6_2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIFPLR6_2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIFPLR6_2_MSI_MAP_ADDR_LO +#define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIFPLR6_2_MSI_MAP_ADDR_HI +#define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_VENDOR_SPECIFIC1 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_VENDOR_SPECIFIC2 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_VC_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_PORT_VC_CAP_REG1 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIFPLR6_2_PCIE_PORT_VC_CAP_REG2 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_2_PCIE_PORT_VC_CNTL +#define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIFPLR6_2_PCIE_PORT_VC_STATUS +#define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIFPLR6_2_PCIE_VC0_RESOURCE_CAP +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS +#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_2_PCIE_VC1_RESOURCE_CAP +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS +#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_UNCORR_ERR_STATUS +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIFPLR6_2_PCIE_UNCORR_ERR_MASK +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIFPLR6_2_PCIE_CORR_ERR_STATUS +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIFPLR6_2_PCIE_CORR_ERR_MASK +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIFPLR6_2_PCIE_HDR_LOG0 +#define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_HDR_LOG1 +#define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_HDR_LOG2 +#define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_HDR_LOG3 +#define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_ROOT_ERR_CMD +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIFPLR6_2_PCIE_ROOT_ERR_STATUS +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIFPLR6_2_PCIE_ERR_SRC_ID +#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIFPLR6_2_PCIE_TLP_PREFIX_LOG0 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_TLP_PREFIX_LOG1 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_TLP_PREFIX_LOG2 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_TLP_PREFIX_LOG3 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_LINK_CNTL3 +#define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 +#define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +#define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_2_PCIE_LANE_ERROR_STATUS +#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +//BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_ACS_CAP +#define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIFPLR6_2_PCIE_ACS_CNTL +#define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIFPLR6_2_PCIE_MC_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_MC_CAP +#define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIFPLR6_2_PCIE_MC_CNTL +#define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIFPLR6_2_PCIE_MC_ADDR0 +#define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIFPLR6_2_PCIE_MC_ADDR1 +#define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_RCV0 +#define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_RCV1 +#define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_BLOCK_ALL0 +#define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_BLOCK_ALL1 +#define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_MC_OVERLAY_BAR0 +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L +//BIFPLR6_2_PCIE_MC_OVERLAY_BAR1 +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_L1_PM_SUB_CAP +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L +//BIFPLR6_2_PCIE_L1_PM_SUB_CNTL +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L +//BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L +#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L +//BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_DPC_CAP_LIST +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5 +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6 +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7 +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8 +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L +#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L +//BIFPLR6_2_PCIE_DPC_CNTL +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2 +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3 +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4 +#define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5 +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6 +#define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7 +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L +#define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L +#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L +#define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L +//BIFPLR6_2_PCIE_DPC_STATUS +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1 +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3 +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4 +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5 +#define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8 +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L +#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L +#define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L +//BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID +#define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL +//BIFPLR6_2_PCIE_RP_PIO_STATUS +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L +//BIFPLR6_2_PCIE_RP_PIO_MASK +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L +//BIFPLR6_2_PCIE_RP_PIO_SEVERITY +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L +//BIFPLR6_2_PCIE_RP_PIO_SYSERROR +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L +//BIFPLR6_2_PCIE_RP_PIO_EXCEPTION +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12 +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L +#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L +//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG +#define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIFPLR6_2_PCIE_ESM_CAP_LIST +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_ESM_HEADER_1 +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L +#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L +//BIFPLR6_2_PCIE_ESM_HEADER_2 +#define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL +//BIFPLR6_2_PCIE_ESM_STATUS +#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL +#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L +//BIFPLR6_2_PCIE_ESM_CTRL +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L +#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L +//BIFPLR6_2_PCIE_ESM_CAP_1 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L +//BIFPLR6_2_PCIE_ESM_CAP_2 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L +//BIFPLR6_2_PCIE_ESM_CAP_3 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L +//BIFPLR6_2_PCIE_ESM_CAP_4 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L +//BIFPLR6_2_PCIE_ESM_CAP_5 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L +//BIFPLR6_2_PCIE_ESM_CAP_6 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L +//BIFPLR6_2_PCIE_ESM_CAP_7 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L +#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L + + +// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec +//NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID +#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10 +#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_2_STATUS_COMMAND +#define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND__SHIFT 0x0 +#define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS__SHIFT 0x10 +#define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL +#define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L +//NB_PCIEDUMMY1_2_CLASS_CODE_REVID +#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID__SHIFT 0x0 +#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8 +#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL +#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L +//NB_PCIEDUMMY1_2_HEADER_TYPE +#define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10 +#define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17 +#define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L +#define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L +//NB_PCIEDUMMY1_2_HEADER_TYPE_W +#define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7 +#define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC2_VENDOR_ID +#define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC2_DEVICE_ID +#define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC2_COMMAND +#define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC2_STATUS +#define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_REVISION_ID +#define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC2_PROG_INTERFACE +#define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC2_SUB_CLASS +#define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC2_BASE_CLASS +#define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC2_CACHE_LINE +#define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC2_LATENCY +#define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC2_HEADER +#define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC2_BIST +#define BIF_CFG_DEV0_RC2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC2_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC2_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC2_CAP_PTR +#define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_RC2_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC2_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC2_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_PMI_CAP +#define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_PCIE_CAP +#define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC2_DEVICE_CAP +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC2_DEVICE_CNTL +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC2_DEVICE_STATUS +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_RC2_LINK_CAP +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_LINK_CNTL +#define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_RC2_LINK_STATUS +#define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC2_SLOT_CAP +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC2_SLOT_CNTL +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV0_RC2_SLOT_STATUS +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC2_ROOT_CNTL +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC2_ROOT_CAP +#define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC2_ROOT_STATUS +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC2_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_RC2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC2_LINK_CAP2 +#define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_RC2_LINK_CNTL2 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC2_LINK_STATUS2 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_RC2_SLOT_CAP2 +#define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC2_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC2_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC2_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_SSID_CAP +#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_MSI_MAP_CAP +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp +//BIF_CFG_DEV1_RC2_VENDOR_ID +#define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC2_DEVICE_ID +#define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_RC2_COMMAND +#define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_RC2_STATUS +#define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_REVISION_ID +#define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_RC2_PROG_INTERFACE +#define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_RC2_SUB_CLASS +#define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC2_BASE_CLASS +#define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_RC2_CACHE_LINE +#define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_RC2_LATENCY +#define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_RC2_HEADER +#define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_RC2_BIST +#define BIF_CFG_DEV1_RC2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_RC2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_RC2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_RC2_BASE_ADDR_1 +#define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_IO_BASE_LIMIT +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV1_RC2_SECONDARY_STATUS +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PREF_BASE_UPPER +#define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER +#define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC2_CAP_PTR +#define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_RC2_INTERRUPT_LINE +#define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_RC2_INTERRUPT_PIN +#define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +//BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV1_RC2_PMI_CAP_LIST +#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_PMI_CAP +#define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_PCIE_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_PCIE_CAP +#define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_RC2_DEVICE_CAP +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_RC2_DEVICE_CNTL +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV1_RC2_DEVICE_STATUS +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_RC2_LINK_CAP +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_LINK_CNTL +#define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_RC2_LINK_STATUS +#define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_RC2_SLOT_CAP +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV1_RC2_SLOT_CNTL +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +//BIF_CFG_DEV1_RC2_SLOT_STATUS +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV1_RC2_ROOT_CNTL +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV1_RC2_ROOT_CAP +#define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV1_RC2_ROOT_STATUS +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV1_RC2_DEVICE_CAP2 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_RC2_DEVICE_CNTL2 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_RC2_DEVICE_STATUS2 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC2_LINK_CAP2 +#define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_RC2_LINK_CNTL2 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_RC2_LINK_STATUS2 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_RC2_SLOT_CAP2 +#define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_SLOT_CNTL2 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC2_SLOT_STATUS2 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_RC2_MSI_CAP_LIST +#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_MSI_MSG_CNTL +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_MSI_MSG_DATA +#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_RC2_SSID_CAP_LIST +#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_SSID_CAP +#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_MSI_MAP_CAP +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L +//BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO +#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI +#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_RC2_PCIE_ACS_CAP +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_COMMAND +#define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_3_STATUS +#define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_LATENCY +#define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_HEADER +#define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_3_BIST +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_PMI_CAP +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF0_3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF0_3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_3_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_COMMAND +#define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_2_STATUS +#define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_REVISION_ID +#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_LATENCY +#define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_HEADER +#define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_2_BIST +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_CAP_PTR +#define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_PMI_CAP +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_2_LINK_CAP +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF1_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF1_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF1_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_MASK +#define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +//BIF_CFG_DEV0_EPF2_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_2_COMMAND +#define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF2_2_STATUS +#define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_2_REVISION_ID +#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_LATENCY +#define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_HEADER +#define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF2_2_BIST +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_CAP_PTR +#define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_PMI_CAP +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_2_SBRN +#define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_FLADJ +#define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF2_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_2_LINK_CAP +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF2_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF2_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF2_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF2_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_MASK +#define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF2_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF2_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +//BIF_CFG_DEV0_EPF3_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_2_COMMAND +#define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF3_2_STATUS +#define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_2_REVISION_ID +#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_LATENCY +#define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_HEADER +#define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF3_2_BIST +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_CAP_PTR +#define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_PMI_CAP +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_2_SBRN +#define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_FLADJ +#define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF3_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_2_LINK_CAP +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF3_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF3_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF3_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF3_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_MASK +#define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF3_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF3_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp +//BIF_CFG_DEV0_EPF4_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_2_COMMAND +#define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF4_2_STATUS +#define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_2_REVISION_ID +#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_LATENCY +#define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_HEADER +#define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF4_2_BIST +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_CAP_PTR +#define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_PMI_CAP +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_2_SBRN +#define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_FLADJ +#define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF4_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_2_LINK_CAP +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF4_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF4_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF4_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF4_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_MASK +#define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF4_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF4_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp +//BIF_CFG_DEV0_EPF5_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_2_COMMAND +#define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF5_2_STATUS +#define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_2_REVISION_ID +#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_LATENCY +#define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_HEADER +#define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF5_2_BIST +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_CAP_PTR +#define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_PMI_CAP +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_2_SBRN +#define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_FLADJ +#define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF5_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_2_LINK_CAP +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF5_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF5_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF5_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF5_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_MASK +#define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF5_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF5_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp +//BIF_CFG_DEV0_EPF6_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_2_COMMAND +#define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF6_2_STATUS +#define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_2_REVISION_ID +#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_LATENCY +#define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_HEADER +#define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF6_2_BIST +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_CAP_PTR +#define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_PMI_CAP +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_2_SBRN +#define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_FLADJ +#define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF6_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_2_LINK_CAP +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF6_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF6_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF6_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF6_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_MASK +#define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF6_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF6_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp +//BIF_CFG_DEV0_EPF7_2_VENDOR_ID +#define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_2_DEVICE_ID +#define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_2_COMMAND +#define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF7_2_STATUS +#define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_2_REVISION_ID +#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_SUB_CLASS +#define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_BASE_CLASS +#define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_CACHE_LINE +#define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_LATENCY +#define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_HEADER +#define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF7_2_BIST +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_CAP_PTR +#define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_MIN_GRANT +#define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_PMI_CAP +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_2_SBRN +#define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_FLADJ +#define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD +#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_PCIE_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF7_2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_2_LINK_CAP +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_2_LINK_CNTL +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV0_EPF7_2_LINK_STATUS +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV0_EPF7_2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF7_2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV0_EPF7_2_SLOT_CAP2 +#define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2 +#define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2 +#define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_MASK +#define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_PENDING +#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF7_2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_2_MSIX_PBA +#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF7_2_SATA_CAP_0 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_2_SATA_CAP_1 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp +//BIF_CFG_DEV1_EPF0_2_VENDOR_ID +#define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_2_DEVICE_ID +#define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_2_COMMAND +#define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF0_2_STATUS +#define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_REVISION_ID +#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_SUB_CLASS +#define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_BASE_CLASS +#define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_CACHE_LINE +#define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_LATENCY +#define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_HEADER +#define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF0_2_BIST +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_ADAPTER_ID +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_CAP_PTR +#define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_MIN_GRANT +#define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_MAX_LATENCY +#define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_PMI_CAP +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_PCIE_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF0_2_DEVICE_CAP +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_2_LINK_CAP +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_LINK_CNTL +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF0_2_LINK_STATUS +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_2_LINK_CAP2 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF0_2_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF0_2_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF0_2_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_MASK +#define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_PENDING +#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_MSIX_TABLE +#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_2_MSIX_PBA +#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF0_2_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L +//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp +//BIF_CFG_DEV1_EPF1_2_VENDOR_ID +#define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_2_DEVICE_ID +#define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_2_COMMAND +#define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF1_2_STATUS +#define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_2_REVISION_ID +#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_SUB_CLASS +#define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_BASE_CLASS +#define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_CACHE_LINE +#define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_LATENCY +#define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_HEADER +#define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF1_2_BIST +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_ADAPTER_ID +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_CAP_PTR +#define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_MIN_GRANT +#define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_MAX_LATENCY +#define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_PMI_CAP +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_2_SBRN +#define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_FLADJ +#define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_PCIE_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF1_2_DEVICE_CAP +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_2_LINK_CAP +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_2_LINK_CNTL +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF1_2_LINK_STATUS +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_2_LINK_CAP2 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF1_2_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF1_2_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF1_2_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_MASK +#define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_PENDING +#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF1_2_MSIX_TABLE +#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_2_MSIX_PBA +#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF1_2_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_2_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp +//BIF_CFG_DEV1_EPF2_2_VENDOR_ID +#define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_2_DEVICE_ID +#define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_2_COMMAND +#define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV1_EPF2_2_STATUS +#define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_2_REVISION_ID +#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE +#define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_SUB_CLASS +#define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_BASE_CLASS +#define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_CACHE_LINE +#define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_LATENCY +#define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_HEADER +#define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV1_EPF2_2_BIST +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_ADAPTER_ID +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR +#define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_CAP_PTR +#define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL +//BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE +#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN +#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_MIN_GRANT +#define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_MAX_LATENCY +#define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_PMI_CAP +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_2_SBRN +#define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_FLADJ +#define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ_MASK 0x3FL +//BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD +#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL +#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_PCIE_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV1_EPF2_2_DEVICE_CAP +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_2_LINK_CAP +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_2_LINK_CNTL +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +//BIF_CFG_DEV1_EPF2_2_LINK_STATUS +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +//BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_2_LINK_CAP2 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L +//BIF_CFG_DEV1_EPF2_2_LINK_CNTL2 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV1_EPF2_2_LINK_STATUS2 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L +//BIF_CFG_DEV1_EPF2_2_SLOT_CAP2 +#define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2 +#define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2 +#define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_MASK +#define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_MASK_64 +#define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_PENDING +#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64 +#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV1_EPF2_2_MSIX_TABLE +#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_2_MSIX_PBA +#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV1_EPF2_2_SATA_CAP_0 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_2_SATA_CAP_1 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L +#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L +//BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +//BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L +//BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L +#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L +//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +//BIF_BX_PF1_SYSHUB_INDEX_OVLP +#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX_PF1_SYSHUB_DATA_OVLP +#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_PCIE_INDEX +#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF1_PCIE_DATA +#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_PCIE_INDEX2 +#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX_PF1_PCIE_DATA2 +#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX_PF1_SBIOS_SCRATCH_0 +#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_SBIOS_SCRATCH_1 +#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_SBIOS_SCRATCH_2 +#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_SBIOS_SCRATCH_3 +#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_0 +#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_1 +#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_2 +#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_3 +#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_4 +#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_5 +#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_6 +#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_7 +#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_8 +#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_9 +#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_10 +#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_11 +#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_12 +#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_13 +#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_14 +#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIOS_SCRATCH_15 +#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIF_RLC_INTR_CNTL +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF1_BIF_VCE_INTR_CNTL +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF1_BIF_UVD_INTR_CNTL +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec +//SYSHUB_MMREG_IND0_SYSHUB_INDEX +#define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX__SHIFT 0x0 +#define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL +//SYSHUB_MMREG_IND0_SYSHUB_DATA +#define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA__SHIFT 0x0 +#define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +//BIF_BX_PF1_BIF_MM_INDACCESS_CNTL +#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX_PF1_BUS_CNTL +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 +#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 +#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 +#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b +#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c +#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L +#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L +#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L +#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L +#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L +#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L +#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L +#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_SCRATCH0 +#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIF_SCRATCH1 +#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BX_RESET_EN +#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 +#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L +#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L +#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L +#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L +#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX_PF1_MM_CFGREGS_CNTL +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX_PF1_BX_RESET_CNTL +#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX_PF1_INTERRUPT_CNTL +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +//BIF_BX_PF1_INTERRUPT_CNTL2 +#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX_PF1_CLKREQB_PAD_CNTL +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L +#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L +//BIF_BX_PF1_BIF_DOORBELL_CNTL +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX_PF1_BIF_DOORBELL_INT_CNTL +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L +//BIF_BX_PF1_BIF_FB_EN +#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_BUSY_DELAY_CNTR +#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL +//BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL +//BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL +//BIF_BX_PF1_BACO_CNTL +#define BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 +#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L +#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX_PF1_BIF_BACO_EXIT_TIME0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF1_BIF_BACO_EXIT_TIMER1 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX_PF1_BIF_BACO_EXIT_TIMER2 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF1_BIF_BACO_EXIT_TIMER3 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF1_BIF_BACO_EXIT_TIMER4 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX_PF1_MEM_TYPE_CNTL +#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS +#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L +//BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_VDDGFX_FB_CMP +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L +#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L +//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL +//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L +//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL +//BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX_PF1_BIF_RB_CNTL +#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX_PF1_BIF_RB_BASE +#define BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX_PF1_BIF_RB_RPTR +#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_RB_WPTR +#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX_PF1_MAILBOX_INDEX +#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE +#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE +#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE +#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX_PF1_BIF_PERSTB_PAD_CNTL +#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX_PF1_BIF_PX_EN_PAD_CNTL +#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//GDC1_NGDC_SDP_PORT_CTRL +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//GDC1_NGDC_RESERVED_0 +#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NGDC_RESERVED_1 +#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK +#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 +#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL +//GDC1_BIF_SDMA0_DOORBELL_RANGE +#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC1_BIF_SDMA1_DOORBELL_RANGE +#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC1_BIF_IH_DOORBELL_RANGE +#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC1_BIF_MMSCH0_DOORBELL_RANGE +#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//GDC1_ATDMA_MISC_CNTL +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC1_BIF_DOORBELL_FENCE_CNTL +#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 +#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L +#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +//GDC1_GDC_PG_MISC_CNTL +#define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 +#define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//MM_INDEX +#define MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define MM_INDEX__MM_APER__SHIFT 0x1f +#define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define MM_INDEX__MM_APER_MASK 0x80000000L +//MM_DATA +#define MM_DATA__MM_DATA__SHIFT 0x0 +#define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//MM_INDEX_HI +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC +//SYSHUB_INDEX_OVLP +#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//SYSHUB_DATA_OVLP +#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//PCIE_INDEX +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//PCIE_DATA +#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//PCIE_INDEX2 +#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//PCIE_DATA2 +#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_0 +#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_1 +#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_2 +#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//SBIOS_SCRATCH_3 +#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 +#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_0 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_1 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_2 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_3 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_4 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_5 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_6 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_7 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_8 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_9 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_10 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_11 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_12 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_13 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_14 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIOS_SCRATCH_15 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_RLC_INTR_CNTL +#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 +#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L +#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_VCE_INTR_CNTL +#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 +#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L +#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L +//BIF_UVD_INTR_CNTL +#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 +#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L +#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L +//GFX_MMIOREG_CAM_ADDR0 +#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR0 +#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR1 +#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR1 +#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR2 +#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR2 +#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR3 +#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR3 +#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR4 +#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR4 +#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR5 +#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR5 +#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR6 +#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR6 +#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_ADDR7 +#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_REMAP_ADDR7 +#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//GFX_MMIOREG_CAM_CNTL +#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//GFX_MMIOREG_CAM_ZERO_CPL +#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//GFX_MMIOREG_CAM_ONE_CPL +#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec +//SYSHUB_INDEX +#define SYSHUB_INDEX__INDEX__SHIFT 0x0 +#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL +//SYSHUB_DATA +#define SYSHUB_DATA__DATA__SHIFT 0x0 +#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_DEV0_EPF0_STRAP0 +#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//EP_PCIE_SCRATCH +#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//EP_PCIE_CNTL +#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//EP_PCIE_INT_CNTL +#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//EP_PCIE_INT_STATUS +#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +//EP_PCIE_RX_CNTL2 +#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//EP_PCIE_BUS_CNTL +#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//EP_PCIE_CFG_CNTL +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +//EP_PCIE_TX_LTR_CNTL +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//EP_PCIE_F0_DPA_CAP +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//EP_PCIE_F0_DPA_CNTL +#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//EP_PCIE_PME_CONTROL +#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//EP_PCIEP_RESERVED +#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//EP_PCIE_TX_CNTL +#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//EP_PCIE_TX_REQUESTER_ID +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//EP_PCIE_ERR_CNTL +#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//EP_PCIE_RX_CNTL +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//EP_PCIE_LC_SPEED_CNTL +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//DN_PCIE_RESERVED +#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//DN_PCIE_SCRATCH +#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//DN_PCIE_CNTL +#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//DN_PCIE_CONFIG_CNTL +#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//DN_PCIE_RX_CNTL2 +#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//DN_PCIE_BUS_CNTL +#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//DN_PCIE_CFG_CNTL +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//PCIE_ERR_CNTL +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +//PCIE_RX_CNTL +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//PCIE_LC_SPEED_CNTL +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +//PCIE_LC_CNTL2 +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//PCIEP_STRAP_MISC +#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//LTR_MSG_INFO_FROM_EP +#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 +//RCC_ERR_LOG +#define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DOORBELL_APER_EN +#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_CONFIG_MEMSIZE +#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_CONFIG_RESERVED +#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_IOV_FUNC_IDENTIFIER +#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_ERR_INT_CNTL +#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_BACO_CNTL_MISC +#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_RESET_EN +#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_VDM_SUPPORT +#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_PEER_REG_RANGE0 +#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_PEER_REG_RANGE1 +#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_BUS_CNTL +#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_CONFIG_CNTL +#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_CONFIG_F0_BASE +#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_CONFIG_APER_SIZE +#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_CONFIG_REG_APER_SIZE +#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL +//RCC_XDMA_LO +#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_XDMA_HI +#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_FEATURES_CONTROL_MISC +#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L +#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L +#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L +#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_BUSNUM_CNTL1 +#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_BUSNUM_LIST0 +#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_BUSNUM_LIST1 +#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_BUSNUM_CNTL2 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_CAPTURE_HOST_BUSNUM +#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_HOST_BUSNUM +#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_PEER0_FB_OFFSET_HI +#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER0_FB_OFFSET_LO +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_PEER1_FB_OFFSET_HI +#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER1_FB_OFFSET_LO +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_PEER2_FB_OFFSET_HI +#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER2_FB_OFFSET_LO +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_PEER3_FB_OFFSET_HI +#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_PEER3_FB_OFFSET_LO +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_CMN_LINK_CNTL +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_EP_REQUESTERID_RESTORE +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_LTR_LSWITCH_CNTL +#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_MH_ARB_CNTL +#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 +//BIF_MM_INDACCESS_CNTL +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BUS_CNTL +#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 +#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 +#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 +#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 +#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 +#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b +#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c +#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L +#define BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L +#define BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L +#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L +#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L +#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L +#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L +#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L +#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_SCRATCH0 +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_SCRATCH1 +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BX_RESET_EN +#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L +#define BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L +#define BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L +#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//MM_CFGREGS_CNTL +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BX_RESET_CNTL +#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//INTERRUPT_CNTL +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +//INTERRUPT_CNTL2 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//CLKREQB_PAD_CNTL +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_FEATURES_CONTROL_MISC +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 +#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 +#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L +#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L +#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L +//BIF_DOORBELL_CNTL +#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_DOORBELL_INT_CNTL +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L +//BIF_FB_EN +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BUSY_DELAY_CNTR +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL +//BIF_MST_TRANS_PENDING_VF +#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL +//BIF_SLV_TRANS_PENDING_VF +#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL +//BACO_CNTL +#define BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 +#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L +#define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BACO_EXIT_TIME0 +#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER1 +#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19 +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L +#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BACO_EXIT_TIMER2 +#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER3 +#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BACO_EXIT_TIMER4 +#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//MEM_TYPE_CNTL +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//SMU_BIF_VDDGFX_PWR_STATUS +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L +//BIF_VDDGFX_GFX0_LOWER +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX0_UPPER +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_GFX1_LOWER +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX1_UPPER +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_GFX2_LOWER +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX2_UPPER +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_GFX3_LOWER +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX3_UPPER +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_GFX4_LOWER +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX4_UPPER +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_GFX5_LOWER +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_GFX5_UPPER +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_RSV1_LOWER +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_RSV1_UPPER +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_RSV2_LOWER +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_RSV2_UPPER +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_RSV3_LOWER +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_RSV3_UPPER +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_RSV4_LOWER +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L +//BIF_VDDGFX_RSV4_UPPER +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL +//BIF_VDDGFX_FB_CMP +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L +//BIF_DOORBELL_GBLAPER1_LOWER +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L +//BIF_DOORBELL_GBLAPER1_UPPER +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL +//BIF_DOORBELL_GBLAPER2_LOWER +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L +//BIF_DOORBELL_GBLAPER2_UPPER +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL +//REMAP_HDP_MEM_FLUSH_CNTL +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//REMAP_HDP_REG_FLUSH_CNTL +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_RB_CNTL +#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_RB_BASE +#define BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_RB_RPTR +#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_RB_WPTR +#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_RB_WPTR_ADDR_HI +#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_RB_WPTR_ADDR_LO +#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//MAILBOX_INDEX +#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_UVD_GPUIOV_CFG_SIZE +#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_VCE_GPUIOV_CFG_SIZE +#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_GFX_SDMA_GPUIOV_CFG_SIZE +#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_PERSTB_PAD_CNTL +#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_PX_EN_PAD_CNTL +#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL +//BIF_REFPADKIN_PAD_CNTL +#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_CLKREQB_PAD_CNTL +#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BME_STATUS +#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_ATOMIC_ERR_LOG +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//DOORBELL_SELFRING_GPA_APER_CNTL +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//HDP_REG_COHERENCY_FLUSH_CNTL +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//HDP_MEM_COHERENCY_FLUSH_CNTL +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//GPU_HDP_FLUSH_REQ +#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +//GPU_HDP_FLUSH_DONE +#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +//BIF_TRANS_PENDING +#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//MAILBOX_MSGBUF_TRN_DW0 +#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_TRN_DW1 +#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_TRN_DW2 +#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_TRN_DW3 +#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_RCV_DW0 +#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_RCV_DW1 +#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_RCV_DW2 +#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_MSGBUF_RCV_DW3 +#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//MAILBOX_CONTROL +#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//MAILBOX_INT_CNTL +#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_VMHV_MAILBOX +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +//NGDC_SDP_PORT_CTRL +#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL +//SHUB_REGS_IF_CTL +#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//NGDC_RESERVED_0 +#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//NGDC_RESERVED_1 +#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//NGDC_SDP_PORT_CTRL_SOCCLK +#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 +#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL +//BIF_SDMA0_DOORBELL_RANGE +#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//BIF_SDMA1_DOORBELL_RANGE +#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//BIF_IH_DOORBELL_RANGE +#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//BIF_MMSCH0_DOORBELL_RANGE +#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL +#define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L +//ATDMA_MISC_CNTL +#define ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//BIF_DOORBELL_FENCE_CNTL +#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 +#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L +//S2A_MISC_CNTL +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 +#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L +#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L +#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +//GDC_PG_MISC_CNTL +#define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0 +#define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 +//GFXMSIX_VECT0_ADDR_LO +#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//GFXMSIX_VECT0_ADDR_HI +#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//GFXMSIX_VECT0_MSG_DATA +#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//GFXMSIX_VECT0_CONTROL +#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//GFXMSIX_VECT1_ADDR_LO +#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//GFXMSIX_VECT1_ADDR_HI +#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//GFXMSIX_VECT1_MSG_DATA +#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//GFXMSIX_VECT1_CONTROL +#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//GFXMSIX_VECT2_ADDR_LO +#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//GFXMSIX_VECT2_ADDR_HI +#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//GFXMSIX_VECT2_MSG_DATA +#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//GFXMSIX_VECT2_CONTROL +#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//GFXMSIX_PBA +#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L + + +// addressBlock: syshub_mmreg_ind_syshubind +//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L +//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L +//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//SYSHUB_MMREG_IND_SYSHUB_CG_CNTL +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L +#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L +//SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L +#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L +//SYSHUB_MMREG_IND_SYSHUB_HP_TIMER +#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL +//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L +//SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET +#define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L +//SYSHUB_MMREG_IND_SYSHUB_SCRATCH +#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//SYSHUB_MMREG_IND_SYSHUB_CL_MASK +#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L +//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L +//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L +//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L +#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2 +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L +#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L +//SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS +#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD +#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h new file mode 100644 index 000000000000..bafcecbad451 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_1_DEFAULT_HEADER +#define _sdma0_4_1_DEFAULT_HEADER + + +// addressBlock: sdma0_sdma0dec +#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 +#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 +#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f +#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff +#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff +#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 +#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 +#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc66880 +#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 +#define mmSDMA0_POWER_CNTL_DEFAULT 0x4003c050 +#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 +#define mmSDMA0_CNTL_DEFAULT 0x00000002 +#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 +#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 +#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 +#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_PROGRAM_DEFAULT 0x00000000 +#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 +#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff +#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 +#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 +#define mmSDMA0_FREEZE_DEFAULT 0x00000000 +#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA_POWER_GATING_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 +#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 +#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define mmSDMA0_ID_DEFAULT 0x00000001 +#define mmSDMA0_VERSION_DEFAULT 0x00000401 +#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 +#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 +#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe +#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff +#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff +#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 +#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 +#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 +#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 +#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 +#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 +#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 +#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f +#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 +#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd +#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 +#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 +#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 +#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 +#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h new file mode 100644 index 000000000000..1544af6a1efc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_1_OFFSET_HEADER +#define _sdma0_4_1_OFFSET_HEADER + + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define mmSDMA0_UCODE_ADDR 0x0000 +#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA0_UCODE_DATA 0x0001 +#define mmSDMA0_UCODE_DATA_BASE_IDX 0 +#define mmSDMA0_VM_CNTL 0x0004 +#define mmSDMA0_VM_CNTL_BASE_IDX 0 +#define mmSDMA0_VM_CTX_LO 0x0005 +#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA0_VM_CTX_HI 0x0006 +#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA0_ACTIVE_FCN_ID 0x0007 +#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA0_VM_CTX_CNTL 0x0008 +#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA0_VIRT_RESET_REQ 0x0009 +#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE0 0x000f +#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE1 0x0010 +#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE2 0x0011 +#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE3 0x0012 +#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_MMHUB_CNTL 0x0013 +#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL 0x001a +#define mmSDMA0_POWER_CNTL_BASE_IDX 0 +#define mmSDMA0_CLK_CTRL 0x001b +#define mmSDMA0_CLK_CTRL_BASE_IDX 0 +#define mmSDMA0_CNTL 0x001c +#define mmSDMA0_CNTL_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS 0x001d +#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG 0x001e +#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH 0x0022 +#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA0_IB_OFFSET_FETCH 0x0023 +#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA0_PROGRAM 0x0024 +#define mmSDMA0_PROGRAM_BASE_IDX 0 +#define mmSDMA0_STATUS_REG 0x0025 +#define mmSDMA0_STATUS_REG_BASE_IDX 0 +#define mmSDMA0_STATUS1_REG 0x0026 +#define mmSDMA0_STATUS1_REG_BASE_IDX 0 +#define mmSDMA0_RD_BURST_CNTL 0x0027 +#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA0_UCODE_CHECKSUM 0x0029 +#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA0_F32_CNTL 0x002a +#define mmSDMA0_F32_CNTL_BASE_IDX 0 +#define mmSDMA0_FREEZE 0x002b +#define mmSDMA0_FREEZE_BASE_IDX 0 +#define mmSDMA0_PHASE0_QUANTUM 0x002c +#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA0_PHASE1_QUANTUM 0x002d +#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA_POWER_GATING 0x002e +#define mmSDMA_POWER_GATING_BASE_IDX 0 +#define mmSDMA_PGFSM_CONFIG 0x002f +#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define mmSDMA_PGFSM_WRITE 0x0030 +#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 +#define mmSDMA_PGFSM_READ 0x0031 +#define mmSDMA_PGFSM_READ_BASE_IDX 0 +#define mmSDMA0_EDC_CONFIG 0x0032 +#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA0_BA_THRESHOLD 0x0033 +#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA0_ID 0x0034 +#define mmSDMA0_ID_BASE_IDX 0 +#define mmSDMA0_VERSION 0x0035 +#define mmSDMA0_VERSION_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER 0x0036 +#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA0_STATUS2_REG 0x0038 +#define mmSDMA0_STATUS2_REG_BASE_IDX 0 +#define mmSDMA0_ATOMIC_CNTL 0x0039 +#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_LO 0x003a +#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_HI 0x003b +#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA0_UTCL1_CNTL 0x003c +#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA0_UTCL1_WATERMK 0x003d +#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_STATUS 0x003e +#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_STATUS 0x003f +#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV0 0x0040 +#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV1 0x0041 +#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV2 0x0042 +#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_TIMEOUT 0x0047 +#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA0_UTCL1_PAGE 0x0048 +#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL_IDLE 0x0049 +#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA0_RELAX_ORDERING_LUT 0x004a +#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS_2 0x004b +#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA0_STATUS3_REG 0x004c +#define mmSDMA0_STATUS3_REG_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_ERROR_LOG 0x0050 +#define mmSDMA0_ERROR_LOG_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG0 0x0051 +#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG1 0x0052 +#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG2 0x0053 +#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG3 0x0054 +#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA0_F32_COUNTER 0x0055 +#define mmSDMA0_F32_COUNTER_BASE_IDX 0 +#define mmSDMA0_UNBREAKABLE 0x0056 +#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA0_PERFMON_CNTL 0x0057 +#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA0_CRD_CNTL 0x005b +#define mmSDMA0_CRD_CNTL_BASE_IDX 0 +#define mmSDMA0_MMHUB_TRUSTLVL 0x005c +#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA0_ULV_CNTL 0x005e +#define mmSDMA0_ULV_CNTL_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA0_GFX_RB_CNTL 0x0080 +#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE 0x0081 +#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE_HI 0x0082 +#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR 0x0083 +#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR 0x0085 +#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_CNTL 0x008a +#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_IB_RPTR 0x008b +#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_IB_OFFSET 0x008c +#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_LO 0x008d +#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_HI 0x008e +#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SIZE 0x008f +#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_GFX_SKIP_CNTL 0x0090 +#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL 0x0092 +#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_STATUS 0x00a8 +#define mmSDMA0_GFX_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_GFX_WATERMARK 0x00aa +#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_GFX_PREEMPT 0x00b0 +#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA0_GFX_DUMMY_REG 0x00b1 +#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_CNTL 0x0140 +#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE 0x0141 +#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 +#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR 0x0143 +#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 +#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR 0x0145 +#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 +#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_CNTL 0x014a +#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_RPTR 0x014b +#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_OFFSET 0x014c +#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_LO 0x014d +#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_HI 0x014e +#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SIZE 0x014f +#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 +#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 +#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL 0x0152 +#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC0_STATUS 0x0168 +#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 +#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC0_WATERMARK 0x016a +#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b +#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c +#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d +#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f +#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC0_PREEMPT 0x0170 +#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC0_DUMMY_REG 0x0171 +#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 +#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 +#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 +#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 +#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 +#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 +#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 +#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 +#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 +#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 +#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 +#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_CNTL 0x01a0 +#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE 0x01a1 +#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 +#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR 0x01a3 +#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 +#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR 0x01a5 +#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 +#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_CNTL 0x01aa +#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_RPTR 0x01ab +#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_OFFSET 0x01ac +#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad +#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae +#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SIZE 0x01af +#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 +#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 +#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL 0x01b2 +#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC1_STATUS 0x01c8 +#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 +#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC1_WATERMARK 0x01ca +#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb +#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc +#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd +#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf +#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC1_PREEMPT 0x01d0 +#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 +#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 +#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 +#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 +#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 +#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 +#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 +#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 +#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 +#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 +#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 +#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 +#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h new file mode 100644 index 000000000000..1445bba8f41f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h @@ -0,0 +1,1658 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_1_SH_MASK_HEADER +#define _sdma0_4_1_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VM_CNTL +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_VM_CTX_LO +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_VM_CTX_HI +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_ACTIVE_FCN_ID +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA0_VM_CTX_CNTL +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA0_VIRT_RESET_REQ +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_CONTEXT_REG_TYPE0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA0_CONTEXT_REG_TYPE1 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA0_CONTEXT_REG_TYPE2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA0_CONTEXT_REG_TYPE3 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_PUB_REG_TYPE0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL +//SDMA0_MMHUB_CNTL +#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_UNBREAKABLE +#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA0_PERFMON_CNTL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA0_PERFCOUNTER0_RESULT +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_RESULT +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_MMHUB_TRUSTLVL +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L +//SDMA0_GPU_IOV_VIOLATION_LOG +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h new file mode 100644 index 000000000000..1a3c4864ae66 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _thm_10_0_DEFAULT_HEADER +#define _thm_10_0_DEFAULT_HEADER + + +// addressBlock: thm_thm_SmuThmDec +#define mmTHM_TCON_CUR_TMP_DEFAULT 0x00000000 +#define mmTHM_TCON_HTC_DEFAULT 0x00004000 +#define mmTHM_TCON_THERM_TRIP_DEFAULT 0x00000001 +#define mmTHM_CTF_DELAY_DEFAULT 0x00000000 +#define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT 0x000000f9 +#define mmTHM_THERMAL_INT_ENA_DEFAULT 0x00000000 +#define mmTHM_THERMAL_INT_CTRL_DEFAULT 0x0fff0078 +#define mmTHM_THERMAL_INT_STATUS_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL0_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL1_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL2_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL3_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL4_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL5_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL6_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL7_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL8_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL9_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL10_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL11_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL12_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL13_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL14_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIL15_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR0_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR1_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR2_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR3_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR4_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR5_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR6_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR7_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR8_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR9_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR10_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR11_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR12_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR13_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR14_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_RDIR15_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_INT_DATA_DEFAULT 0x00000000 +#define mmTHM_TMON0_CTRL_DEFAULT 0x00000100 +#define mmTHM_TMON0_CTRL2_DEFAULT 0x0fffffff +#define mmTHM_TMON0_DEBUG_DEFAULT 0x00000000 +#define mmTHM_DIE1_TEMP_DEFAULT 0x00000000 +#define mmTHM_DIE2_TEMP_DEFAULT 0x00000000 +#define mmTHM_DIE3_TEMP_DEFAULT 0x00000000 +#define mmTHM_SW_TEMP_DEFAULT 0x00000000 +#define mmCG_MULT_THERMAL_CTRL_DEFAULT 0x08400001 +#define mmCG_MULT_THERMAL_STATUS_DEFAULT 0x00000000 +#define mmCG_THERMAL_RANGE_DEFAULT 0x00000000 +#define mmTHM_TMON_CONFIG_DEFAULT 0xc0800005 +#define mmTHM_TMON_CONFIG2_DEFAULT 0x30c8680e +#define mmTHM_TMON0_COEFF_DEFAULT 0x00024068 +#define mmTHM_TCON_LOCAL0_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL1_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL2_DEFAULT 0x00000060 +#define mmTHM_TCON_LOCAL3_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL4_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL5_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL6_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL7_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL8_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL9_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL10_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL11_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL12_DEFAULT 0x00000000 +#define mmTHM_TCON_LOCAL13_DEFAULT 0x00000000 +#define mmTHM_PWRMGT_DEFAULT 0x00010000 +#define mmSMUSBI_SBIREGADDR_DEFAULT 0x00000000 +#define mmSMUSBI_SBIREGDATA_DEFAULT 0x00000000 +#define mmSMUSBI_ERRATA_STAT_REG_DEFAULT 0x00000000 +#define mmSMUSBI_SBICTRL_DEFAULT 0x00000002 +#define mmSMUSBI_CKNBIRESET_DEFAULT 0x00000000 +#define mmSMUSBI_TIMING_DEFAULT 0x001f001a +#define mmSMUSBI_HS_TIMING_DEFAULT 0x00050003 +#define mmSBTSI_REMOTE_TEMP_DEFAULT 0x00000000 +#define mmSBRMI_CONTROL_DEFAULT 0x00000000 +#define mmSBRMI_COMMAND_DEFAULT 0x00000000 +#define mmSBRMI_WRITE_DATA0_DEFAULT 0x00000000 +#define mmSBRMI_WRITE_DATA1_DEFAULT 0x00000000 +#define mmSBRMI_WRITE_DATA2_DEFAULT 0x00000000 +#define mmSBRMI_READ_DATA0_DEFAULT 0x00000000 +#define mmSBRMI_READ_DATA1_DEFAULT 0x00000000 +#define mmSBRMI_CORE_EN_NUMBER_DEFAULT 0x00000010 +#define mmSBRMI_CORE_EN_STATUS0_DEFAULT 0x00000000 +#define mmSBRMI_CORE_EN_STATUS1_DEFAULT 0x00000000 +#define mmSBRMI_APIC_STATUS0_DEFAULT 0x00000000 +#define mmSBRMI_APIC_STATUS1_DEFAULT 0x00000000 +#define mmSBRMI_MCE_STATUS0_DEFAULT 0x00000000 +#define mmSBRMI_MCE_STATUS1_DEFAULT 0x00000000 +#define mmSMBUS_CNTL0_DEFAULT 0x00030082 +#define mmSMBUS_CNTL1_DEFAULT 0x0000063f +#define mmSMBUS_BLKWR_CMD_CTRL0_DEFAULT 0x12110201 +#define mmSMBUS_BLKWR_CMD_CTRL1_DEFAULT 0x0003005a +#define mmSMBUS_BLKRD_CMD_CTRL0_DEFAULT 0x00001303 +#define mmSMBUS_BLKRD_CMD_CTRL1_DEFAULT 0x00000000 +#define mmSMBUS_TIMING_CNTL0_DEFAULT 0x028a4f5c +#define mmSMBUS_TIMING_CNTL1_DEFAULT 0x08036927 +#define mmSMBUS_TIMING_CNTL2_DEFAULT 0x0021e548 +#define mmSMBUS_TRIGGER_CNTL_DEFAULT 0x00000000 +#define mmSMBUS_UDID_CNTL0_DEFAULT 0x7fffffff +#define mmSMBUS_UDID_CNTL1_DEFAULT 0x00000000 +#define mmSMBUS_UDID_CNTL2_DEFAULT 0x00000043 +#define mmSMUSBI_SMBUS_DEFAULT 0x000001c0 +#define mmSMUSBI_ALERT_DEFAULT 0x000000f9 +#define mmTHM_TMON0_REMOTE_START_DEFAULT 0x00000000 +#define mmTHM_TMON0_REMOTE_END_DEFAULT 0x00000000 +#define mmTHM_TMON1_REMOTE_START_DEFAULT 0x00000000 +#define mmTHM_TMON1_REMOTE_END_DEFAULT 0x00000000 +#define mmTHM_TMON2_REMOTE_START_DEFAULT 0x00000000 +#define mmTHM_TMON2_REMOTE_END_DEFAULT 0x00000000 +#define mmTHM_TMON3_REMOTE_START_DEFAULT 0x00000000 +#define mmTHM_TMON3_REMOTE_END_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h new file mode 100644 index 000000000000..6af3e6fa2f23 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _thm_10_0_OFFSET_HEADER +#define _thm_10_0_OFFSET_HEADER + + + +// addressBlock: thm_thm_SmuThmDec +// base address: 0x59800 +#define mmTHM_TCON_CUR_TMP 0x0000 +#define mmTHM_TCON_CUR_TMP_BASE_IDX 0 +#define mmTHM_TCON_HTC 0x0001 +#define mmTHM_TCON_HTC_BASE_IDX 0 +#define mmTHM_TCON_THERM_TRIP 0x0002 +#define mmTHM_TCON_THERM_TRIP_BASE_IDX 0 +#define mmTHM_CTF_DELAY 0x0003 +#define mmTHM_CTF_DELAY_BASE_IDX 0 +#define mmTHM_GPIO_PROCHOT_CTRL 0x0004 +#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 +#define mmTHM_THERMAL_INT_ENA 0x000a +#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0 +#define mmTHM_THERMAL_INT_CTRL 0x000b +#define mmTHM_THERMAL_INT_CTRL_BASE_IDX 0 +#define mmTHM_THERMAL_INT_STATUS 0x000c +#define mmTHM_THERMAL_INT_STATUS_BASE_IDX 0 +#define mmTHM_TMON0_RDIL0_DATA 0x000d +#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL1_DATA 0x000e +#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL2_DATA 0x000f +#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL3_DATA 0x0010 +#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL4_DATA 0x0011 +#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL5_DATA 0x0012 +#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL6_DATA 0x0013 +#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL7_DATA 0x0014 +#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL8_DATA 0x0015 +#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL9_DATA 0x0016 +#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL10_DATA 0x0017 +#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL11_DATA 0x0018 +#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL12_DATA 0x0019 +#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL13_DATA 0x001a +#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL14_DATA 0x001b +#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIL15_DATA 0x001c +#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR0_DATA 0x001d +#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR1_DATA 0x001e +#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR2_DATA 0x001f +#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR3_DATA 0x0020 +#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR4_DATA 0x0021 +#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR5_DATA 0x0022 +#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR6_DATA 0x0023 +#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR7_DATA 0x0024 +#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR8_DATA 0x0025 +#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR9_DATA 0x0026 +#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR10_DATA 0x0027 +#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR11_DATA 0x0028 +#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR12_DATA 0x0029 +#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR13_DATA 0x002a +#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR14_DATA 0x002b +#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX 0 +#define mmTHM_TMON0_RDIR15_DATA 0x002c +#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX 0 +#define mmTHM_TMON0_INT_DATA 0x002d +#define mmTHM_TMON0_INT_DATA_BASE_IDX 0 +#define mmTHM_TMON0_CTRL 0x002e +#define mmTHM_TMON0_CTRL_BASE_IDX 0 +#define mmTHM_TMON0_CTRL2 0x002f +#define mmTHM_TMON0_CTRL2_BASE_IDX 0 +#define mmTHM_TMON0_DEBUG 0x0030 +#define mmTHM_TMON0_DEBUG_BASE_IDX 0 +#define mmTHM_DIE1_TEMP 0x0055 +#define mmTHM_DIE1_TEMP_BASE_IDX 0 +#define mmTHM_DIE2_TEMP 0x0056 +#define mmTHM_DIE2_TEMP_BASE_IDX 0 +#define mmTHM_DIE3_TEMP 0x0057 +#define mmTHM_DIE3_TEMP_BASE_IDX 0 +#define mmTHM_SW_TEMP 0x0058 +#define mmTHM_SW_TEMP_BASE_IDX 0 +#define mmCG_MULT_THERMAL_CTRL 0x0059 +#define mmCG_MULT_THERMAL_CTRL_BASE_IDX 0 +#define mmCG_MULT_THERMAL_STATUS 0x005a +#define mmCG_MULT_THERMAL_STATUS_BASE_IDX 0 +#define mmCG_THERMAL_RANGE 0x005b +#define mmCG_THERMAL_RANGE_BASE_IDX 0 +#define mmTHM_TMON_CONFIG 0x005c +#define mmTHM_TMON_CONFIG_BASE_IDX 0 +#define mmTHM_TMON_CONFIG2 0x005d +#define mmTHM_TMON_CONFIG2_BASE_IDX 0 +#define mmTHM_TMON0_COEFF 0x005e +#define mmTHM_TMON0_COEFF_BASE_IDX 0 +#define mmTHM_TCON_LOCAL0 0x006e +#define mmTHM_TCON_LOCAL0_BASE_IDX 0 +#define mmTHM_TCON_LOCAL1 0x006f +#define mmTHM_TCON_LOCAL1_BASE_IDX 0 +#define mmTHM_TCON_LOCAL2 0x0070 +#define mmTHM_TCON_LOCAL2_BASE_IDX 0 +#define mmTHM_TCON_LOCAL3 0x0071 +#define mmTHM_TCON_LOCAL3_BASE_IDX 0 +#define mmTHM_TCON_LOCAL4 0x0072 +#define mmTHM_TCON_LOCAL4_BASE_IDX 0 +#define mmTHM_TCON_LOCAL5 0x0073 +#define mmTHM_TCON_LOCAL5_BASE_IDX 0 +#define mmTHM_TCON_LOCAL6 0x0074 +#define mmTHM_TCON_LOCAL6_BASE_IDX 0 +#define mmTHM_TCON_LOCAL7 0x0075 +#define mmTHM_TCON_LOCAL7_BASE_IDX 0 +#define mmTHM_TCON_LOCAL8 0x0076 +#define mmTHM_TCON_LOCAL8_BASE_IDX 0 +#define mmTHM_TCON_LOCAL9 0x0077 +#define mmTHM_TCON_LOCAL9_BASE_IDX 0 +#define mmTHM_TCON_LOCAL10 0x0078 +#define mmTHM_TCON_LOCAL10_BASE_IDX 0 +#define mmTHM_TCON_LOCAL11 0x0079 +#define mmTHM_TCON_LOCAL11_BASE_IDX 0 +#define mmTHM_TCON_LOCAL12 0x007a +#define mmTHM_TCON_LOCAL12_BASE_IDX 0 +#define mmTHM_TCON_LOCAL13 0x007b +#define mmTHM_TCON_LOCAL13_BASE_IDX 0 +#define mmTHM_PWRMGT 0x007d +#define mmTHM_PWRMGT_BASE_IDX 0 +#define mmSMUSBI_SBIREGADDR 0x0080 +#define mmSMUSBI_SBIREGADDR_BASE_IDX 0 +#define mmSMUSBI_SBIREGDATA 0x0081 +#define mmSMUSBI_SBIREGDATA_BASE_IDX 0 +#define mmSMUSBI_ERRATA_STAT_REG 0x0085 +#define mmSMUSBI_ERRATA_STAT_REG_BASE_IDX 0 +#define mmSMUSBI_SBICTRL 0x0086 +#define mmSMUSBI_SBICTRL_BASE_IDX 0 +#define mmSMUSBI_CKNBIRESET 0x0087 +#define mmSMUSBI_CKNBIRESET_BASE_IDX 0 +#define mmSMUSBI_TIMING 0x0088 +#define mmSMUSBI_TIMING_BASE_IDX 0 +#define mmSMUSBI_HS_TIMING 0x0089 +#define mmSMUSBI_HS_TIMING_BASE_IDX 0 +#define mmSBTSI_REMOTE_TEMP 0x008a +#define mmSBTSI_REMOTE_TEMP_BASE_IDX 0 +#define mmSBRMI_CONTROL 0x008b +#define mmSBRMI_CONTROL_BASE_IDX 0 +#define mmSBRMI_COMMAND 0x008c +#define mmSBRMI_COMMAND_BASE_IDX 0 +#define mmSBRMI_WRITE_DATA0 0x008d +#define mmSBRMI_WRITE_DATA0_BASE_IDX 0 +#define mmSBRMI_WRITE_DATA1 0x008e +#define mmSBRMI_WRITE_DATA1_BASE_IDX 0 +#define mmSBRMI_WRITE_DATA2 0x008f +#define mmSBRMI_WRITE_DATA2_BASE_IDX 0 +#define mmSBRMI_READ_DATA0 0x0090 +#define mmSBRMI_READ_DATA0_BASE_IDX 0 +#define mmSBRMI_READ_DATA1 0x0091 +#define mmSBRMI_READ_DATA1_BASE_IDX 0 +#define mmSBRMI_CORE_EN_NUMBER 0x0092 +#define mmSBRMI_CORE_EN_NUMBER_BASE_IDX 0 +#define mmSBRMI_CORE_EN_STATUS0 0x0093 +#define mmSBRMI_CORE_EN_STATUS0_BASE_IDX 0 +#define mmSBRMI_CORE_EN_STATUS1 0x0094 +#define mmSBRMI_CORE_EN_STATUS1_BASE_IDX 0 +#define mmSBRMI_APIC_STATUS0 0x0095 +#define mmSBRMI_APIC_STATUS0_BASE_IDX 0 +#define mmSBRMI_APIC_STATUS1 0x0096 +#define mmSBRMI_APIC_STATUS1_BASE_IDX 0 +#define mmSBRMI_MCE_STATUS0 0x0097 +#define mmSBRMI_MCE_STATUS0_BASE_IDX 0 +#define mmSBRMI_MCE_STATUS1 0x0098 +#define mmSBRMI_MCE_STATUS1_BASE_IDX 0 +#define mmSMBUS_CNTL0 0x0099 +#define mmSMBUS_CNTL0_BASE_IDX 0 +#define mmSMBUS_CNTL1 0x009a +#define mmSMBUS_CNTL1_BASE_IDX 0 +#define mmSMBUS_BLKWR_CMD_CTRL0 0x009b +#define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 +#define mmSMBUS_BLKWR_CMD_CTRL1 0x009c +#define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 +#define mmSMBUS_BLKRD_CMD_CTRL0 0x009d +#define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 +#define mmSMBUS_BLKRD_CMD_CTRL1 0x009e +#define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 +#define mmSMBUS_TIMING_CNTL0 0x009f +#define mmSMBUS_TIMING_CNTL0_BASE_IDX 0 +#define mmSMBUS_TIMING_CNTL1 0x00a0 +#define mmSMBUS_TIMING_CNTL1_BASE_IDX 0 +#define mmSMBUS_TIMING_CNTL2 0x00a1 +#define mmSMBUS_TIMING_CNTL2_BASE_IDX 0 +#define mmSMBUS_TRIGGER_CNTL 0x00a2 +#define mmSMBUS_TRIGGER_CNTL_BASE_IDX 0 +#define mmSMBUS_UDID_CNTL0 0x00a3 +#define mmSMBUS_UDID_CNTL0_BASE_IDX 0 +#define mmSMBUS_UDID_CNTL1 0x00a4 +#define mmSMBUS_UDID_CNTL1_BASE_IDX 0 +#define mmSMBUS_UDID_CNTL2 0x00a5 +#define mmSMBUS_UDID_CNTL2_BASE_IDX 0 +#define mmSMUSBI_SMBUS 0x00a6 +#define mmSMUSBI_SMBUS_BASE_IDX 0 +#define mmSMUSBI_ALERT 0x00a7 +#define mmSMUSBI_ALERT_BASE_IDX 0 +#define mmTHM_TMON0_REMOTE_START 0x0100 +#define mmTHM_TMON0_REMOTE_START_BASE_IDX 0 +#define mmTHM_TMON0_REMOTE_END 0x013f +#define mmTHM_TMON0_REMOTE_END_BASE_IDX 0 +#define mmTHM_TMON1_REMOTE_START 0x0140 +#define mmTHM_TMON1_REMOTE_START_BASE_IDX 0 +#define mmTHM_TMON1_REMOTE_END 0x017f +#define mmTHM_TMON1_REMOTE_END_BASE_IDX 0 +#define mmTHM_TMON2_REMOTE_START 0x0180 +#define mmTHM_TMON2_REMOTE_START_BASE_IDX 0 +#define mmTHM_TMON2_REMOTE_END 0x01bf +#define mmTHM_TMON2_REMOTE_END_BASE_IDX 0 +#define mmTHM_TMON3_REMOTE_START 0x01c0 +#define mmTHM_TMON3_REMOTE_START_BASE_IDX 0 +#define mmTHM_TMON3_REMOTE_END 0x01ff +#define mmTHM_TMON3_REMOTE_END_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h new file mode 100644 index 000000000000..b8cadcf78da6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h @@ -0,0 +1,885 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _thm_10_0_SH_MASK_HEADER +#define _thm_10_0_SH_MASK_HEADER + + +// addressBlock: thm_thm_SmuThmDec +//THM_TCON_CUR_TMP +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L +#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L +//THM_TCON_HTC +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 +#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb +#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b +#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L +#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L +#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L +#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L +#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L +#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L +#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L +//THM_TCON_THERM_TRIP +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L +#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L +#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L +#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L +//THM_CTF_DELAY +#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 +#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL +//THM_GPIO_PROCHOT_CTRL +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L +//THM_THERMAL_INT_ENA +#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L +#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L +//THM_THERMAL_INT_CTRL +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b +#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c +#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L +#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L +#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L +#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L +#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L +//THM_THERMAL_INT_STATUS +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L +#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L +//THM_TMON0_RDIL0_DATA +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL1_DATA +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL2_DATA +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL3_DATA +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL4_DATA +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL5_DATA +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL6_DATA +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL7_DATA +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL8_DATA +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL9_DATA +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL10_DATA +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL11_DATA +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL12_DATA +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL13_DATA +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL14_DATA +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIL15_DATA +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR0_DATA +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR1_DATA +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR2_DATA +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR3_DATA +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR4_DATA +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR5_DATA +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR6_DATA +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR7_DATA +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR8_DATA +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR9_DATA +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR10_DATA +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR11_DATA +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR12_DATA +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR13_DATA +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR14_DATA +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_RDIR15_DATA +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_INT_DATA +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL +#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L +//THM_TMON0_CTRL +#define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0 +#define THM_TMON0_CTRL__BGADJ__SHIFT 0x1 +#define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9 +#define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa +#define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb +#define THM_TMON0_CTRL__DEBUG_MODE__SHIFT 0xc +#define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd +#define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L +#define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL +#define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L +#define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L +#define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L +#define THM_TMON0_CTRL__DEBUG_MODE_MASK 0x00001000L +#define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L +//THM_TMON0_CTRL2 +#define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0 +#define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10 +#define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL +#define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L +//THM_TMON0_DEBUG +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L +//THM_DIE1_TEMP +#define THM_DIE1_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE1_TEMP__VALID__SHIFT 0xb +#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE1_TEMP__VALID_MASK 0x00000800L +//THM_DIE2_TEMP +#define THM_DIE2_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE2_TEMP__VALID__SHIFT 0xb +#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE2_TEMP__VALID_MASK 0x00000800L +//THM_DIE3_TEMP +#define THM_DIE3_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE3_TEMP__VALID__SHIFT 0xb +#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE3_TEMP__VALID_MASK 0x00000800L +//THM_SW_TEMP +#define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 +#define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL +//CG_MULT_THERMAL_CTRL +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L +//CG_MULT_THERMAL_STATUS +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L +//CG_THERMAL_RANGE +#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 +#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 +#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL +#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L +//THM_TMON_CONFIG +#define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0 +#define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define THM_TMON_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 +#define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5 +#define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define THM_TMON_CONFIG__Z__SHIFT 0x15 +#define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L +#define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L +#define THM_TMON_CONFIG__RDI_INTERLEAVE_MASK 0x00000010L +#define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L +#define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L +#define THM_TMON_CONFIG__Z_MASK 0xFFE00000L +//THM_TMON_CONFIG2 +#define THM_TMON_CONFIG2__A__SHIFT 0x0 +#define THM_TMON_CONFIG2__B__SHIFT 0xc +#define THM_TMON_CONFIG2__C__SHIFT 0x12 +#define THM_TMON_CONFIG2__K__SHIFT 0x1d +#define THM_TMON_CONFIG2__A_MASK 0x00000FFFL +#define THM_TMON_CONFIG2__B_MASK 0x0003F000L +#define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L +#define THM_TMON_CONFIG2__K_MASK 0x20000000L +//THM_TMON0_COEFF +#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 +#define THM_TMON0_COEFF__D__SHIFT 0xb +#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL +#define THM_TMON0_COEFF__D_MASK 0x0003F800L +//THM_TCON_LOCAL0 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L +//THM_TCON_LOCAL1 +#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 +#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 +#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 +#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L +#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L +#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L +#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L +//THM_TCON_LOCAL2 +#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 +#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 +#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 +#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa +#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb +#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL +#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L +#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L +#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L +#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L +//THM_TCON_LOCAL3 +#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 +#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL +//THM_TCON_LOCAL4 +#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 +#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL +//THM_TCON_LOCAL5 +#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 +#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL +//THM_TCON_LOCAL6 +#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 +#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL +//THM_TCON_LOCAL7 +#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 +#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL +//THM_TCON_LOCAL8 +#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 +#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL +//THM_TCON_LOCAL9 +#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL +//THM_TCON_LOCAL10 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL +//THM_TCON_LOCAL11 +#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 +#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL +//THM_TCON_LOCAL12 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL +//THM_TCON_LOCAL13 +#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 +#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L +//THM_PWRMGT +#define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN__SHIFT 0x0 +#define THM_PWRMGT__SBAXI_CLK_GATE_EN__SHIFT 0x1 +#define THM_PWRMGT__SB_CLK_GATE_MAX_CNT__SHIFT 0x8 +#define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN_MASK 0x00000001L +#define THM_PWRMGT__SBAXI_CLK_GATE_EN_MASK 0x00000002L +#define THM_PWRMGT__SB_CLK_GATE_MAX_CNT_MASK 0x00FFFF00L +//SMUSBI_SBIREGADDR +#define SMUSBI_SBIREGADDR__SBI_REGADDR__SHIFT 0x0 +#define SMUSBI_SBIREGADDR__SBI_REGADDR_MASK 0x000007FFL +//SMUSBI_SBIREGDATA +#define SMUSBI_SBIREGDATA__SBI_REGDATA__SHIFT 0x0 +#define SMUSBI_SBIREGDATA__SBI_REGDATA_MASK 0xFFFFFFFFL +//SMUSBI_ERRATA_STAT_REG +#define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG__SHIFT 0x0 +#define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG_MASK 0xFFFFFFFFL +//SMUSBI_SBICTRL +#define SMUSBI_SBICTRL__CK_SPRSBIWRDONE__SHIFT 0x0 +#define SMUSBI_SBICTRL__NB_SBISELECT__SHIFT 0x1 +#define SMUSBI_SBICTRL__NB_SBIADDR__SHIFT 0x2 +#define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE__SHIFT 0x5 +#define SMUSBI_SBICTRL__CK_SPRSBIWRDONE_MASK 0x00000001L +#define SMUSBI_SBICTRL__NB_SBISELECT_MASK 0x00000002L +#define SMUSBI_SBICTRL__NB_SBIADDR_MASK 0x0000001CL +#define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE_MASK 0x00000020L +//SMUSBI_CKNBIRESET +#define SMUSBI_CKNBIRESET__CKNBIRESET__SHIFT 0x0 +#define SMUSBI_CKNBIRESET__CKNBIRESET_MASK 0x00000001L +//SMUSBI_TIMING +#define SMUSBI_TIMING__SETUP_TIME__SHIFT 0x0 +#define SMUSBI_TIMING__SETUP_TIME_OVERRIDE__SHIFT 0x8 +#define SMUSBI_TIMING__HOLD_TIME__SHIFT 0x10 +#define SMUSBI_TIMING__HOLD_TIME_OVERRIDE__SHIFT 0x18 +#define SMUSBI_TIMING__SETUP_TIME_MASK 0x0000003FL +#define SMUSBI_TIMING__SETUP_TIME_OVERRIDE_MASK 0x00000100L +#define SMUSBI_TIMING__HOLD_TIME_MASK 0x00FF0000L +#define SMUSBI_TIMING__HOLD_TIME_OVERRIDE_MASK 0x01000000L +//SMUSBI_HS_TIMING +#define SMUSBI_HS_TIMING__HS_SETUP_TIME__SHIFT 0x0 +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE__SHIFT 0x8 +#define SMUSBI_HS_TIMING__HS_HOLD_TIME__SHIFT 0x10 +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE__SHIFT 0x18 +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_MASK 0x0000003FL +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE_MASK 0x00000100L +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_MASK 0x00FF0000L +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE_MASK 0x01000000L +//SBTSI_REMOTE_TEMP +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L +//SBRMI_CONTROL +#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 +#define SBRMI_CONTROL__DPD__SHIFT 0x1 +#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 +#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L +#define SBRMI_CONTROL__DPD_MASK 0x00000002L +#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L +//SBRMI_COMMAND +#define SBRMI_COMMAND__Command__SHIFT 0x0 +#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 +#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 +#define SBRMI_COMMAND__CommandSent__SHIFT 0x18 +#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 +#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a +#define SBRMI_COMMAND__Status__SHIFT 0x1c +#define SBRMI_COMMAND__Command_MASK 0x000000FFL +#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L +#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L +#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L +#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L +#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L +#define SBRMI_COMMAND__Status_MASK 0xF0000000L +//SBRMI_WRITE_DATA0 +#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 +#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 +#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 +#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 +#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL +#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L +//SBRMI_WRITE_DATA1 +#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 +#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 +#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 +#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 +#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL +#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L +//SBRMI_WRITE_DATA2 +#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 +#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 +#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 +#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 +#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL +#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L +//SBRMI_READ_DATA0 +#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 +#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 +#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 +#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 +#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL +#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L +#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L +#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L +//SBRMI_READ_DATA1 +#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 +#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 +#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 +#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 +#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL +#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L +#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L +#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L +//SBRMI_CORE_EN_NUMBER +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL +//SBRMI_CORE_EN_STATUS0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL +//SBRMI_CORE_EN_STATUS1 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS0 +#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 +#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS1 +#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 +#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS0 +#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 +#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS1 +#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 +#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL +//SMBUS_CNTL0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 +#define SMBUS_CNTL0__THM_READY__SHIFT 0x14 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L +#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L +//SMBUS_CNTL1 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L +//SMBUS_BLKWR_CMD_CTRL0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L +//SMBUS_BLKWR_CMD_CTRL1 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL1 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L +//SMBUS_TIMING_CNTL0 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L +//SMBUS_TIMING_CNTL1 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L +//SMBUS_TIMING_CNTL2 +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L +//SMBUS_TRIGGER_CNTL +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L +//SMBUS_UDID_CNTL0 +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L +//SMBUS_UDID_CNTL1 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL +//SMBUS_UDID_CNTL2 +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 +#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 +#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 +#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 +#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 +#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L +#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL +#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L +#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L +#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L +#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L +//SMUSBI_SMBUS +#define SMUSBI_SMBUS__Spare0__SHIFT 0x0 +#define SMUSBI_SMBUS__Spare1__SHIFT 0x1 +#define SMUSBI_SMBUS__ResBiasEn__SHIFT 0x2 +#define SMUSBI_SMBUS__CompSel__SHIFT 0x3 +#define SMUSBI_SMBUS__NG__SHIFT 0x4 +#define SMUSBI_SMBUS__I2cRxSel__SHIFT 0x8 +#define SMUSBI_SMBUS__PdEn0__SHIFT 0xa +#define SMUSBI_SMBUS__PdEn1__SHIFT 0xb +#define SMUSBI_SMBUS__FallSlewSel__SHIFT 0xc +#define SMUSBI_SMBUS__Slewn__SHIFT 0xe +#define SMUSBI_SMBUS__SpikeRcEn__SHIFT 0xf +#define SMUSBI_SMBUS__SpikeRcSel__SHIFT 0x10 +#define SMUSBI_SMBUS__CSel0p9__SHIFT 0x11 +#define SMUSBI_SMBUS__CSel1p1__SHIFT 0x12 +#define SMUSBI_SMBUS__RSel0p9__SHIFT 0x13 +#define SMUSBI_SMBUS__RSel1p1__SHIFT 0x14 +#define SMUSBI_SMBUS__BiasCrtEn__SHIFT 0x15 +#define SMUSBI_SMBUS__DI2C0__SHIFT 0x16 +#define SMUSBI_SMBUS__DI2C1__SHIFT 0x17 +#define SMUSBI_SMBUS__DI2C0_OVERRIDE__SHIFT 0x18 +#define SMUSBI_SMBUS__DI2C1_OVERRIDE__SHIFT 0x19 +#define SMUSBI_SMBUS__Y0__SHIFT 0x1e +#define SMUSBI_SMBUS__Y1__SHIFT 0x1f +#define SMUSBI_SMBUS__Spare0_MASK 0x00000001L +#define SMUSBI_SMBUS__Spare1_MASK 0x00000002L +#define SMUSBI_SMBUS__ResBiasEn_MASK 0x00000004L +#define SMUSBI_SMBUS__CompSel_MASK 0x00000008L +#define SMUSBI_SMBUS__NG_MASK 0x000000F0L +#define SMUSBI_SMBUS__I2cRxSel_MASK 0x00000300L +#define SMUSBI_SMBUS__PdEn0_MASK 0x00000400L +#define SMUSBI_SMBUS__PdEn1_MASK 0x00000800L +#define SMUSBI_SMBUS__FallSlewSel_MASK 0x00003000L +#define SMUSBI_SMBUS__Slewn_MASK 0x00004000L +#define SMUSBI_SMBUS__SpikeRcEn_MASK 0x00008000L +#define SMUSBI_SMBUS__SpikeRcSel_MASK 0x00010000L +#define SMUSBI_SMBUS__CSel0p9_MASK 0x00020000L +#define SMUSBI_SMBUS__CSel1p1_MASK 0x00040000L +#define SMUSBI_SMBUS__RSel0p9_MASK 0x00080000L +#define SMUSBI_SMBUS__RSel1p1_MASK 0x00100000L +#define SMUSBI_SMBUS__BiasCrtEn_MASK 0x00200000L +#define SMUSBI_SMBUS__DI2C0_MASK 0x00400000L +#define SMUSBI_SMBUS__DI2C1_MASK 0x00800000L +#define SMUSBI_SMBUS__DI2C0_OVERRIDE_MASK 0x01000000L +#define SMUSBI_SMBUS__DI2C1_OVERRIDE_MASK 0x02000000L +#define SMUSBI_SMBUS__Y0_MASK 0x40000000L +#define SMUSBI_SMBUS__Y1_MASK 0x80000000L +//SMUSBI_ALERT +#define SMUSBI_ALERT__TXIMPSEL__SHIFT 0x0 +#define SMUSBI_ALERT__PD__SHIFT 0x1 +#define SMUSBI_ALERT__PU__SHIFT 0x2 +#define SMUSBI_ALERT__SCHMEN__SHIFT 0x3 +#define SMUSBI_ALERT__S0__SHIFT 0x4 +#define SMUSBI_ALERT__S1__SHIFT 0x5 +#define SMUSBI_ALERT__RXEN__SHIFT 0x6 +#define SMUSBI_ALERT__RXSEL0__SHIFT 0x7 +#define SMUSBI_ALERT__RXSEL1__SHIFT 0x8 +#define SMUSBI_ALERT__OE_OVERRIDE__SHIFT 0x10 +#define SMUSBI_ALERT__OE__SHIFT 0x11 +#define SMUSBI_ALERT__A_OVERRIDE__SHIFT 0x12 +#define SMUSBI_ALERT__A__SHIFT 0x13 +#define SMUSBI_ALERT__Y__SHIFT 0x1f +#define SMUSBI_ALERT__TXIMPSEL_MASK 0x00000001L +#define SMUSBI_ALERT__PD_MASK 0x00000002L +#define SMUSBI_ALERT__PU_MASK 0x00000004L +#define SMUSBI_ALERT__SCHMEN_MASK 0x00000008L +#define SMUSBI_ALERT__S0_MASK 0x00000010L +#define SMUSBI_ALERT__S1_MASK 0x00000020L +#define SMUSBI_ALERT__RXEN_MASK 0x00000040L +#define SMUSBI_ALERT__RXSEL0_MASK 0x00000080L +#define SMUSBI_ALERT__RXSEL1_MASK 0x00000100L +#define SMUSBI_ALERT__OE_OVERRIDE_MASK 0x00010000L +#define SMUSBI_ALERT__OE_MASK 0x00020000L +#define SMUSBI_ALERT__A_OVERRIDE_MASK 0x00040000L +#define SMUSBI_ALERT__A_MASK 0x00080000L +#define SMUSBI_ALERT__Y_MASK 0x80000000L +//THM_TMON0_REMOTE_START +#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON0_REMOTE_END +#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL +//THM_TMON1_REMOTE_START +#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON1_REMOTE_END +#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL +//THM_TMON2_REMOTE_START +#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON2_REMOTE_END +#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL +//THM_TMON3_REMOTE_START +#define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL +//THM_TMON3_REMOTE_END +#define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h new file mode 100644 index 000000000000..5793a10e3dc2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vcn_1_0_DEFAULT_HEADER +#define _vcn_1_0_DEFAULT_HEADER + + +// addressBlock: uvd_uvd_pg_dec +#define mmUVD_PGFSM_CONFIG_DEFAULT 0x00000000 +#define mmUVD_PGFSM_STATUS_DEFAULT 0x002aaaaa +#define mmUVD_POWER_STATUS_DEFAULT 0x00000801 +#define mmCC_UVD_HARVESTING_DEFAULT 0x00000000 +#define mmUVD_SCRATCH1_DEFAULT 0x00000000 +#define mmUVD_SCRATCH2_DEFAULT 0x00000000 +#define mmUVD_SCRATCH3_DEFAULT 0x00000000 +#define mmUVD_SCRATCH4_DEFAULT 0x00000000 +#define mmUVD_SCRATCH5_DEFAULT 0x00000000 +#define mmUVD_SCRATCH6_DEFAULT 0x00000000 +#define mmUVD_SCRATCH7_DEFAULT 0x00000000 +#define mmUVD_SCRATCH8_DEFAULT 0x00000000 +#define mmUVD_SCRATCH9_DEFAULT 0x00000000 +#define mmUVD_SCRATCH10_DEFAULT 0x00000000 +#define mmUVD_SCRATCH11_DEFAULT 0x00000000 +#define mmUVD_SCRATCH12_DEFAULT 0x00000000 +#define mmUVD_SCRATCH13_DEFAULT 0x00000000 +#define mmUVD_SCRATCH14_DEFAULT 0x00000000 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 + + +// addressBlock: uvd_uvdgendec +#define mmUVD_LCM_CGC_CNTRL_DEFAULT 0xa0f00000 + + +// addressBlock: uvd_uvdnpdec +#define mmUVD_JPEG_CNTL_DEFAULT 0x00000004 +#define mmUVD_JPEG_RB_BASE_DEFAULT 0x00000000 +#define mmUVD_JPEG_RB_WPTR_DEFAULT 0x00000000 +#define mmUVD_JPEG_RB_RPTR_DEFAULT 0x00000000 +#define mmUVD_JPEG_RB_SIZE_DEFAULT 0x00000000 +#define mmUVD_JPEG_UV_TILING_CTRL_DEFAULT 0x02104800 +#define mmUVD_JPEG_TILING_CTRL_DEFAULT 0x02104800 +#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_JPEG_GPCOM_CMD_DEFAULT 0x00000000 +#define mmUVD_JPEG_GPCOM_DATA0_DEFAULT 0x00000000 +#define mmUVD_JPEG_GPCOM_DATA1_DEFAULT 0x00000000 +#define mmUVD_JPEG_JRB_BASE_LO_DEFAULT 0x00000000 +#define mmUVD_JPEG_JRB_BASE_HI_DEFAULT 0x00000000 +#define mmUVD_JPEG_JRB_SIZE_DEFAULT 0x00000000 +#define mmUVD_JPEG_JRB_RPTR_DEFAULT 0x00000000 +#define mmUVD_JPEG_JRB_WPTR_DEFAULT 0x00000000 +#define mmUVD_JPEG_UV_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_SEMA_ADDR_LOW_DEFAULT 0x00000000 +#define mmUVD_SEMA_ADDR_HIGH_DEFAULT 0x00000000 +#define mmUVD_SEMA_CMD_DEFAULT 0x00000080 +#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000 +#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000 +#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000 +#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010 +#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000 +#define mmUVD_SUVD_CGC_STATUS_DEFAULT 0x00000000 +#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_NO_OP_DEFAULT 0x00000000 +#define mmUVD_JPEG_CNTL2_DEFAULT 0x00000000 +#define mmUVD_VERSION_DEFAULT 0x00010000 +#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH9_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH10_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH11_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH12_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH13_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH14_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH15_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH16_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH17_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH18_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH19_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH20_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH21_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH22_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH23_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000 +#define mmUVD_RB_SIZE2_DEFAULT 0x00000000 +#define mmUVD_RB_RPTR2_DEFAULT 0x00000000 +#define mmUVD_RB_WPTR2_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000 +#define mmUVD_RB_SIZE_DEFAULT 0x00000000 +#define mmUVD_RB_RPTR_DEFAULT 0x00000000 +#define mmUVD_RB_WPTR_DEFAULT 0x00000000 +#define mmUVD_RB_WPTR4_DEFAULT 0x00000000 +#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 + + +// addressBlock: uvd_uvddec +#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000 +#define mmUVD_LMI_JRBC_IB_VMID_DEFAULT 0x00000000 +#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000 +#define mmUVD_JRBC_RB_CNTL_DEFAULT 0x00000100 +#define mmUVD_JRBC_IB_SIZE_DEFAULT 0x00000000 +#define mmUVD_JRBC_LMI_SWAP_CNTL_DEFAULT 0x00000000 +#define mmUVD_JRBC_SOFT_RESET_DEFAULT 0x00000000 +#define mmUVD_JRBC_STATUS_DEFAULT 0x00000003 +#define mmUVD_RB_RPTR3_DEFAULT 0x00000000 +#define mmUVD_RB_WPTR3_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000 +#define mmUVD_RB_SIZE3_DEFAULT 0x00000000 +#define mmJPEG_CGC_GATE_DEFAULT 0x00300000 +#define mmUVD_CTX_INDEX_DEFAULT 0x00000000 +#define mmUVD_CTX_DATA_DEFAULT 0x00000000 +#define mmUVD_CGC_GATE_DEFAULT 0x000fffff +#define mmUVD_CGC_STATUS_DEFAULT 0x00000000 +#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d +#define mmUVD_GP_SCRATCH0_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH1_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH2_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH3_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH5_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH6_DEFAULT 0x00000000 +#define mmUVD_GP_SCRATCH7_DEFAULT 0x00000000 +#define mmUVD_LMI_VCPU_CACHE_VMID_DEFAULT 0x00000000 +#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000 +#define mmUVD_MASTINT_EN_DEFAULT 0x00000000 +#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d +#define mmUVD_LMI_CTRL_DEFAULT 0x00104340 +#define mmUVD_LMI_STATUS_DEFAULT 0x003fff7f +#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000 +#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000 +#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040 +#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000 +#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040 +#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000 +#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088 +#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000 +#define mmUVD_GPCOM_SYS_CMD_DEFAULT 0x00000000 +#define mmUVD_GPCOM_SYS_DATA0_DEFAULT 0x00000000 +#define mmUVD_GPCOM_SYS_DATA1_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 +#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 +#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000 +#define mmUVD_SOFT_RESET_DEFAULT 0x00000008 +#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000 +#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000 +#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000 +#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000 +#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 +#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101 +#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000 +#define mmUVD_STATUS_DEFAULT 0x00000000 +#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 +#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000 +#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000 +#define mmUVD_RBC_WPTR_POLL_CNTL_DEFAULT 0x00400100 +#define mmUVD_RBC_WPTR_POLL_ADDR_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_LO4_DEFAULT 0x00000000 +#define mmUVD_RB_BASE_HI4_DEFAULT 0x00000000 +#define mmUVD_RB_SIZE4_DEFAULT 0x00000000 +#define mmUVD_RB_RPTR4_DEFAULT 0x00000000 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h new file mode 100644 index 000000000000..18a32477ed1d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vcn_1_0_OFFSET_HEADER +#define _vcn_1_0_OFFSET_HEADER + + + +// addressBlock: uvd_uvd_pg_dec +// base address: 0x1fb00 +#define mmUVD_PGFSM_CONFIG 0x00c0 +#define mmUVD_PGFSM_CONFIG_BASE_IDX 1 +#define mmUVD_PGFSM_STATUS 0x00c1 +#define mmUVD_PGFSM_STATUS_BASE_IDX 1 +#define mmUVD_POWER_STATUS 0x00c4 +#define mmUVD_POWER_STATUS_BASE_IDX 1 +#define mmCC_UVD_HARVESTING 0x00c7 +#define mmCC_UVD_HARVESTING_BASE_IDX 1 +#define mmUVD_SCRATCH1 0x00d5 +#define mmUVD_SCRATCH1_BASE_IDX 1 +#define mmUVD_SCRATCH2 0x00d6 +#define mmUVD_SCRATCH2_BASE_IDX 1 +#define mmUVD_SCRATCH3 0x00d7 +#define mmUVD_SCRATCH3_BASE_IDX 1 +#define mmUVD_SCRATCH4 0x00d8 +#define mmUVD_SCRATCH4_BASE_IDX 1 +#define mmUVD_SCRATCH5 0x00d9 +#define mmUVD_SCRATCH5_BASE_IDX 1 +#define mmUVD_SCRATCH6 0x00da +#define mmUVD_SCRATCH6_BASE_IDX 1 +#define mmUVD_SCRATCH7 0x00db +#define mmUVD_SCRATCH7_BASE_IDX 1 +#define mmUVD_SCRATCH8 0x00dc +#define mmUVD_SCRATCH8_BASE_IDX 1 +#define mmUVD_SCRATCH9 0x00dd +#define mmUVD_SCRATCH9_BASE_IDX 1 +#define mmUVD_SCRATCH10 0x00de +#define mmUVD_SCRATCH10_BASE_IDX 1 +#define mmUVD_SCRATCH11 0x00df +#define mmUVD_SCRATCH11_BASE_IDX 1 +#define mmUVD_SCRATCH12 0x00e0 +#define mmUVD_SCRATCH12_BASE_IDX 1 +#define mmUVD_SCRATCH13 0x00e1 +#define mmUVD_SCRATCH13_BASE_IDX 1 +#define mmUVD_SCRATCH14 0x00e2 +#define mmUVD_SCRATCH14_BASE_IDX 1 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7 +#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 + + +// addressBlock: uvd_uvdgendec +// base address: 0x1fc00 +#define mmUVD_LCM_CGC_CNTRL 0x0123 +#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 + + +// addressBlock: uvd_uvdnpdec +// base address: 0x20000 +#define mmUVD_JPEG_CNTL 0x0200 +#define mmUVD_JPEG_CNTL_BASE_IDX 1 +#define mmUVD_JPEG_RB_BASE 0x0201 +#define mmUVD_JPEG_RB_BASE_BASE_IDX 1 +#define mmUVD_JPEG_RB_WPTR 0x0202 +#define mmUVD_JPEG_RB_WPTR_BASE_IDX 1 +#define mmUVD_JPEG_RB_RPTR 0x0203 +#define mmUVD_JPEG_RB_RPTR_BASE_IDX 1 +#define mmUVD_JPEG_RB_SIZE 0x0204 +#define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 +#define mmUVD_JPEG_ADDR_CONFIG 0x021f +#define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_JPEG_GPCOM_CMD 0x022c +#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 1 +#define mmUVD_JPEG_GPCOM_DATA0 0x022d +#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 +#define mmUVD_JPEG_GPCOM_DATA1 0x022e +#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 +#define mmUVD_JPEG_JRB_BASE_LO 0x022f +#define mmUVD_JPEG_JRB_BASE_LO_BASE_IDX 1 +#define mmUVD_JPEG_JRB_BASE_HI 0x0230 +#define mmUVD_JPEG_JRB_BASE_HI_BASE_IDX 1 +#define mmUVD_JPEG_JRB_SIZE 0x0232 +#define mmUVD_JPEG_JRB_SIZE_BASE_IDX 1 +#define mmUVD_JPEG_JRB_RPTR 0x0233 +#define mmUVD_JPEG_JRB_RPTR_BASE_IDX 1 +#define mmUVD_JPEG_JRB_WPTR 0x0234 +#define mmUVD_JPEG_JRB_WPTR_BASE_IDX 1 +#define mmUVD_JPEG_UV_ADDR_CONFIG 0x0238 +#define mmUVD_JPEG_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_SEMA_ADDR_LOW 0x03c0 +#define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 +#define mmUVD_SEMA_ADDR_HIGH 0x03c1 +#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 +#define mmUVD_SEMA_CMD 0x03c2 +#define mmUVD_SEMA_CMD_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_CMD 0x03c3 +#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_DATA0 0x03c4 +#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_DATA1 0x03c5 +#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2 +#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_UDEC_ADDR_CONFIG 0x03d3 +#define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4 +#define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 +#define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_SUVD_CGC_GATE 0x03e4 +#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 +#define mmUVD_SUVD_CGC_STATUS 0x03e5 +#define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 +#define mmUVD_SUVD_CGC_CTRL 0x03e6 +#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_NO_OP 0x03ff +#define mmUVD_NO_OP_BASE_IDX 1 +#define mmUVD_JPEG_CNTL2 0x0404 +#define mmUVD_JPEG_CNTL2_BASE_IDX 1 +#define mmUVD_VERSION 0x0409 +#define mmUVD_VERSION_BASE_IDX 1 +#define mmUVD_GP_SCRATCH8 0x040a +#define mmUVD_GP_SCRATCH8_BASE_IDX 1 +#define mmUVD_GP_SCRATCH9 0x040b +#define mmUVD_GP_SCRATCH9_BASE_IDX 1 +#define mmUVD_GP_SCRATCH10 0x040c +#define mmUVD_GP_SCRATCH10_BASE_IDX 1 +#define mmUVD_GP_SCRATCH11 0x040d +#define mmUVD_GP_SCRATCH11_BASE_IDX 1 +#define mmUVD_GP_SCRATCH12 0x040e +#define mmUVD_GP_SCRATCH12_BASE_IDX 1 +#define mmUVD_GP_SCRATCH13 0x040f +#define mmUVD_GP_SCRATCH13_BASE_IDX 1 +#define mmUVD_GP_SCRATCH14 0x0410 +#define mmUVD_GP_SCRATCH14_BASE_IDX 1 +#define mmUVD_GP_SCRATCH15 0x0411 +#define mmUVD_GP_SCRATCH15_BASE_IDX 1 +#define mmUVD_GP_SCRATCH16 0x0412 +#define mmUVD_GP_SCRATCH16_BASE_IDX 1 +#define mmUVD_GP_SCRATCH17 0x0413 +#define mmUVD_GP_SCRATCH17_BASE_IDX 1 +#define mmUVD_GP_SCRATCH18 0x0414 +#define mmUVD_GP_SCRATCH18_BASE_IDX 1 +#define mmUVD_GP_SCRATCH19 0x0415 +#define mmUVD_GP_SCRATCH19_BASE_IDX 1 +#define mmUVD_GP_SCRATCH20 0x0416 +#define mmUVD_GP_SCRATCH20_BASE_IDX 1 +#define mmUVD_GP_SCRATCH21 0x0417 +#define mmUVD_GP_SCRATCH21_BASE_IDX 1 +#define mmUVD_GP_SCRATCH22 0x0418 +#define mmUVD_GP_SCRATCH22_BASE_IDX 1 +#define mmUVD_GP_SCRATCH23 0x0419 +#define mmUVD_GP_SCRATCH23_BASE_IDX 1 +#define mmUVD_RB_BASE_LO2 0x0421 +#define mmUVD_RB_BASE_LO2_BASE_IDX 1 +#define mmUVD_RB_BASE_HI2 0x0422 +#define mmUVD_RB_BASE_HI2_BASE_IDX 1 +#define mmUVD_RB_SIZE2 0x0423 +#define mmUVD_RB_SIZE2_BASE_IDX 1 +#define mmUVD_RB_RPTR2 0x0424 +#define mmUVD_RB_RPTR2_BASE_IDX 1 +#define mmUVD_RB_WPTR2 0x0425 +#define mmUVD_RB_WPTR2_BASE_IDX 1 +#define mmUVD_RB_BASE_LO 0x0426 +#define mmUVD_RB_BASE_LO_BASE_IDX 1 +#define mmUVD_RB_BASE_HI 0x0427 +#define mmUVD_RB_BASE_HI_BASE_IDX 1 +#define mmUVD_RB_SIZE 0x0428 +#define mmUVD_RB_SIZE_BASE_IDX 1 +#define mmUVD_RB_RPTR 0x0429 +#define mmUVD_RB_RPTR_BASE_IDX 1 +#define mmUVD_RB_WPTR 0x042a +#define mmUVD_RB_WPTR_BASE_IDX 1 +#define mmUVD_RB_WPTR4 0x0456 +#define mmUVD_RB_WPTR4_BASE_IDX 1 +#define mmUVD_JRBC_RB_RPTR 0x0457 +#define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0468 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0469 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 + + +// addressBlock: uvd_uvddec +// base address: 0x20c00 +#define mmUVD_SEMA_CNTL 0x0500 +#define mmUVD_SEMA_CNTL_BASE_IDX 1 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0504 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0505 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0506 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_JRBC_IB_VMID 0x0507 +#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 +#define mmUVD_JRBC_RB_WPTR 0x0509 +#define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 +#define mmUVD_JRBC_RB_CNTL 0x050a +#define mmUVD_JRBC_RB_CNTL_BASE_IDX 1 +#define mmUVD_JRBC_IB_SIZE 0x050b +#define mmUVD_JRBC_IB_SIZE_BASE_IDX 1 +#define mmUVD_JRBC_LMI_SWAP_CNTL 0x050d +#define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX 1 +#define mmUVD_JRBC_SOFT_RESET 0x0519 +#define mmUVD_JRBC_SOFT_RESET_BASE_IDX 1 +#define mmUVD_JRBC_STATUS 0x051a +#define mmUVD_JRBC_STATUS_BASE_IDX 1 +#define mmUVD_RB_RPTR3 0x051b +#define mmUVD_RB_RPTR3_BASE_IDX 1 +#define mmUVD_RB_WPTR3 0x051c +#define mmUVD_RB_WPTR3_BASE_IDX 1 +#define mmUVD_RB_BASE_LO3 0x051d +#define mmUVD_RB_BASE_LO3_BASE_IDX 1 +#define mmUVD_RB_BASE_HI3 0x051e +#define mmUVD_RB_BASE_HI3_BASE_IDX 1 +#define mmUVD_RB_SIZE3 0x051f +#define mmUVD_RB_SIZE3_BASE_IDX 1 +#define mmJPEG_CGC_GATE 0x0526 +#define mmJPEG_CGC_GATE_BASE_IDX 1 +#define mmUVD_CTX_INDEX 0x0528 +#define mmUVD_CTX_INDEX_BASE_IDX 1 +#define mmUVD_CTX_DATA 0x0529 +#define mmUVD_CTX_DATA_BASE_IDX 1 +#define mmUVD_CGC_GATE 0x052a +#define mmUVD_CGC_GATE_BASE_IDX 1 +#define mmUVD_CGC_STATUS 0x052b +#define mmUVD_CGC_STATUS_BASE_IDX 1 +#define mmUVD_CGC_CTRL 0x052c +#define mmUVD_CGC_CTRL_BASE_IDX 1 +#define mmUVD_GP_SCRATCH0 0x0534 +#define mmUVD_GP_SCRATCH0_BASE_IDX 1 +#define mmUVD_GP_SCRATCH1 0x0535 +#define mmUVD_GP_SCRATCH1_BASE_IDX 1 +#define mmUVD_GP_SCRATCH2 0x0536 +#define mmUVD_GP_SCRATCH2_BASE_IDX 1 +#define mmUVD_GP_SCRATCH3 0x0537 +#define mmUVD_GP_SCRATCH3_BASE_IDX 1 +#define mmUVD_GP_SCRATCH4 0x0538 +#define mmUVD_GP_SCRATCH4_BASE_IDX 1 +#define mmUVD_GP_SCRATCH5 0x0539 +#define mmUVD_GP_SCRATCH5_BASE_IDX 1 +#define mmUVD_GP_SCRATCH6 0x053a +#define mmUVD_GP_SCRATCH6_BASE_IDX 1 +#define mmUVD_GP_SCRATCH7 0x053b +#define mmUVD_GP_SCRATCH7_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_VMID 0x053c +#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define mmUVD_LMI_CTRL2 0x053d +#define mmUVD_LMI_CTRL2_BASE_IDX 1 +#define mmUVD_MASTINT_EN 0x0540 +#define mmUVD_MASTINT_EN_BASE_IDX 1 +#define mmJPEG_CGC_CTRL 0x0565 +#define mmJPEG_CGC_CTRL_BASE_IDX 1 +#define mmUVD_LMI_CTRL 0x0566 +#define mmUVD_LMI_CTRL_BASE_IDX 1 +#define mmUVD_LMI_STATUS 0x0567 +#define mmUVD_LMI_STATUS_BASE_IDX 1 +#define mmUVD_LMI_VM_CTRL 0x0568 +#define mmUVD_LMI_VM_CTRL_BASE_IDX 1 +#define mmUVD_LMI_SWAP_CNTL 0x056d +#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXA0 0x0579 +#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXA1 0x057a +#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXB0 0x057b +#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXB1 0x057c +#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 +#define mmUVD_MPC_SET_MUX 0x057d +#define mmUVD_MPC_SET_MUX_BASE_IDX 1 +#define mmUVD_MPC_SET_ALU 0x057e +#define mmUVD_MPC_SET_ALU_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_CMD 0x057f +#define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_DATA0 0x0580 +#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_DATA1 0x0581 +#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET0 0x0582 +#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE0 0x0583 +#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET1 0x0584 +#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE1 0x0585 +#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET2 0x0586 +#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE2 0x0587 +#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 +#define mmUVD_VCPU_CNTL 0x0598 +#define mmUVD_VCPU_CNTL_BASE_IDX 1 +#define mmUVD_SOFT_RESET 0x05a0 +#define mmUVD_SOFT_RESET_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_VMID 0x05a1 +#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 +#define mmUVD_RBC_IB_SIZE 0x05a2 +#define mmUVD_RBC_IB_SIZE_BASE_IDX 1 +#define mmUVD_RBC_RB_RPTR 0x05a4 +#define mmUVD_RBC_RB_RPTR_BASE_IDX 1 +#define mmUVD_RBC_RB_WPTR 0x05a5 +#define mmUVD_RBC_RB_WPTR_BASE_IDX 1 +#define mmUVD_RBC_RB_WPTR_CNTL 0x05a6 +#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 +#define mmUVD_RBC_RB_CNTL 0x05a9 +#define mmUVD_RBC_RB_CNTL_BASE_IDX 1 +#define mmUVD_RBC_RB_RPTR_ADDR 0x05aa +#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 +#define mmUVD_STATUS 0x05af +#define mmUVD_STATUS_BASE_IDX 1 +#define mmUVD_SEMA_TIMEOUT_STATUS 0x05b0 +#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x05b1 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x05b3 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_CONTEXT_ID 0x05bd +#define mmUVD_CONTEXT_ID_BASE_IDX 1 +#define mmUVD_CONTEXT_ID2 0x05bf +#define mmUVD_CONTEXT_ID2_BASE_IDX 1 +#define mmUVD_RBC_WPTR_POLL_CNTL 0x05d8 +#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmUVD_RBC_WPTR_POLL_ADDR 0x05d9 +#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 +#define mmUVD_RB_BASE_LO4 0x05df +#define mmUVD_RB_BASE_LO4_BASE_IDX 1 +#define mmUVD_RB_BASE_HI4 0x05e0 +#define mmUVD_RB_BASE_HI4_BASE_IDX 1 +#define mmUVD_RB_SIZE4 0x05e1 +#define mmUVD_RB_SIZE4_BASE_IDX 1 +#define mmUVD_RB_RPTR4 0x05e2 +#define mmUVD_RB_RPTR4_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h new file mode 100644 index 000000000000..d6ba26922275 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h @@ -0,0 +1,1308 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vcn_1_0_SH_MASK_HEADER +#define _vcn_1_0_SH_MASK_HEADER + + +// addressBlock: uvd_uvd_pg_dec +//UVD_PGFSM_CONFIG +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L +//UVD_PGFSM_STATUS +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L +//UVD_POWER_STATUS +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 +#define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT 0xa +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L +#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L +#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L +#define UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK 0x00000400L +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L +//CC_UVD_HARVESTING +#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 +#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L +//UVD_SCRATCH1 +#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 +#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH2 +#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 +#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH3 +#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 +#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH4 +#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 +#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH5 +#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 +#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH6 +#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 +#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH7 +#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 +#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH8 +#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 +#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH9 +#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 +#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH10 +#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 +#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH11 +#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 +#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH12 +#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 +#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH13 +#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 +#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH14 +#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 +#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_DPG_VCPU_CACHE_OFFSET0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL + + +// addressBlock: uvd_uvdgendec +//UVD_LCM_CGC_CNTRL +#define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12 +#define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13 +#define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14 +#define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c +#define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L +#define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L +#define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L +#define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L + + +// addressBlock: uvd_uvdnpdec +//UVD_JPEG_CNTL +#define UVD_JPEG_CNTL__SOFT_RESET__SHIFT 0x0 +#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 +#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 +#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 +#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 +#define UVD_JPEG_CNTL__SOFT_RESET_MASK 0x00000001L +#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L +#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L +#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L +#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L +//UVD_JPEG_RB_BASE +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 +#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL +#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L +//UVD_JPEG_RB_WPTR +#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_RPTR +#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_SIZE +#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L +//UVD_JPEG_ADDR_CONFIG +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_JPEG_GPCOM_CMD +#define UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_JPEG_GPCOM_DATA0 +#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_GPCOM_DATA1 +#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_JRB_BASE_LO +#define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT 0x6 +#define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_JPEG_JRB_BASE_HI +#define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT 0x0 +#define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_JPEG_JRB_SIZE +#define UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT 0x4 +#define UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK 0x007FFFF0L +//UVD_JPEG_JRB_RPTR +#define UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT 0x4 +#define UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK 0x007FFFF0L +//UVD_JPEG_JRB_WPTR +#define UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT 0x4 +#define UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK 0x007FFFF0L +//UVD_JPEG_UV_ADDR_CONFIG +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_SEMA_ADDR_LOW +#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL +//UVD_SEMA_ADDR_HIGH +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL +//UVD_SEMA_CMD +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L +#define UVD_SEMA_CMD__MODE_MASK 0x00000040L +#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L +#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L +//UVD_GPCOM_VCPU_CMD +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_VCPU_DATA0 +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_VCPU_DATA1 +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_UDEC_DBW_UV_ADDR_CONFIG +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_UDEC_ADDR_CONFIG +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_UDEC_DB_ADDR_CONFIG +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_UDEC_DBW_ADDR_CONFIG +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//UVD_SUVD_CGC_GATE +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +//UVD_SUVD_CGC_STATUS +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf +#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 +#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 +#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L +#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L +#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L +#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L +#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L +//UVD_SUVD_CGC_CTRL +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_NO_OP +#define UVD_NO_OP__NO_OP__SHIFT 0x0 +#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL +//UVD_VERSION +#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 +#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 +#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL +#define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L +//UVD_GP_SCRATCH8 +#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH9 +#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH10 +#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH11 +#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH12 +#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH13 +#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH14 +#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH15 +#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH16 +#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH17 +#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH18 +#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH19 +#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH20 +#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH21 +#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH22 +#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH23 +#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL +//UVD_RB_BASE_LO2 +#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI2 +#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE2 +#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR2 +#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR2 +#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO +#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI +#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE +#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR +#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR +#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR4 +#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_RPTR +#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_HIGH +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_LOW +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_LOW +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_LOW +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_uvddec +//UVD_SEMA_CNTL +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L +//UVD_LMI_JRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_VMID +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +//UVD_JRBC_RB_WPTR +#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_CNTL +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC_IB_SIZE +#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_LMI_SWAP_CNTL +#define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +//UVD_JRBC_SOFT_RESET +#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT 0x10 +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK 0x00010000L +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC_STATUS +#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_RB_RPTR3 +#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR3 +#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO3 +#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI3 +#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE3 +#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L +//JPEG_CGC_GATE +#define JPEG_CGC_GATE__JPEG__SHIFT 0x14 +#define JPEG_CGC_GATE__JPEG2__SHIFT 0x15 +#define JPEG_CGC_GATE__JPEG_MASK 0x00100000L +#define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L +//UVD_CTX_INDEX +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL +//UVD_CTX_DATA +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_CGC_GATE +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__SCPU__SHIFT 0x13 +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__SCPU_MASK 0x00080000L +//UVD_CGC_STATUS +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d +#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L +#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000L +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L +//UVD_CGC_CTRL +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L +//UVD_GP_SCRATCH0 +#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH1 +#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH2 +#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH3 +#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH4 +#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH5 +#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH6 +#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH7 +#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_VMID +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_LMI_CTRL2 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +//UVD_MASTINT_EN +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//JPEG_CGC_CTRL +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL +#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L +#define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L +//UVD_LMI_CTRL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__RFU__SHIFT 0x1b +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L +//UVD_LMI_SWAP_CNTL +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L +#define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L +//UVD_MPC_SET_MUXA0 +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXA1 +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L +//UVD_MPC_SET_MUXB0 +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXB1 +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L +//UVD_MPC_SET_MUX +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L +#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L +#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L +//UVD_MPC_SET_ALU +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L +#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L +//UVD_GPCOM_SYS_CMD +#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_SYS_DATA0 +#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_DATA1 +#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_VCPU_CACHE_OFFSET0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET1 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE1 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET2 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE2 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL +//UVD_VCPU_CNTL +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +//UVD_SOFT_RESET +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L +//UVD_LMI_RBC_IB_VMID +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL +//UVD_RBC_IB_SIZE +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_RBC_RB_RPTR +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_WPTR +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_WPTR_CNTL +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL +//UVD_RBC_WPTR_STATUS +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L +//UVD_RBC_RB_CNTL +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L +//UVD_RBC_RB_RPTR_ADDR +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL +//UVD_STATUS +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_STATUS__AVP_BUSY__SHIFT 0x8 +#define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 +#define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb +#define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc +#define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd +#define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe +#define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf +#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 +#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL +#define UVD_STATUS__AVP_BUSY_MASK 0x00000100L +#define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L +#define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L +#define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L +#define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L +#define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L +#define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L +#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L +#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L +//UVD_SEMA_TIMEOUT_STATUS +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L +//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_CONTEXT_ID +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID2 +#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 +#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL +//UVD_RBC_WPTR_POLL_CNTL +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//UVD_RBC_WPTR_POLL_ADDR +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL +//UVD_RB_BASE_LO4 +#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI4 +#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE4 +#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR4 +#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L + + +#endif diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index d38687516d60..0021a1c63356 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1206,10 +1206,10 @@ struct atom_asic_profiling_info_v4_1 uint32_t gb_vdroop_table_ckson_a1; uint32_t gb_vdroop_table_ckson_a2; uint32_t avfsgb_fuse_table_cksoff_m1; - uint16_t avfsgb_fuse_table_cksoff_m2; + uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t avfsgb_fuse_table_cksoff_b; uint32_t avfsgb_fuse_table_ckson_m1; - uint16_t avfsgb_fuse_table_ckson_m2; + uint32_t avfsgb_fuse_table_ckson_m2; uint32_t avfsgb_fuse_table_ckson_b; uint16_t max_voltage_0_25mv; uint8_t enable_gb_vdroop_table_cksoff; @@ -1220,16 +1220,16 @@ struct atom_asic_profiling_info_v4_1 uint8_t enable_apply_avfs_cksoff_voltage; uint8_t reserved; uint32_t dispclk2gfxclk_a; - uint16_t dispclk2gfxclk_b; + uint32_t dispclk2gfxclk_b; uint32_t dispclk2gfxclk_c; uint32_t pixclk2gfxclk_a; - uint16_t pixclk2gfxclk_b; + uint32_t pixclk2gfxclk_b; uint32_t pixclk2gfxclk_c; uint32_t dcefclk2gfxclk_a; - uint16_t dcefclk2gfxclk_b; + uint32_t dcefclk2gfxclk_b; uint32_t dcefclk2gfxclk_c; uint32_t phyclk2gfxclk_a; - uint16_t phyclk2gfxclk_b; + uint32_t phyclk2gfxclk_b; uint32_t phyclk2gfxclk_c; }; diff --git a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h new file mode 100644 index 000000000000..ac9fa3a9bd07 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h @@ -0,0 +1,1134 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __IRQSRCS_DCN_1_0_H__ +#define __IRQSRCS_DCN_1_0_H__ + + +#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 + +#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 + +#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 + +#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 + +#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 + +#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 + +#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 + +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 + +#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 + +#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 + +#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 + +#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 + +#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 + +#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 + +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 + +#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 + +#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 + +#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_SCP_INT 14 + +#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 + +#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 + +#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 + +#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 + +#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 + +#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 + +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 + +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 + +#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 + +#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 + +#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_HPD1_INT 0 + +#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_HPD2_INT 1 + +#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_HPD3_INT 2 + +#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_HPD4_INT 3 + +#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_HPD5_INT 4 + +#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_HPD6_INT 5 + +#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 + +#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 + +#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 + +#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 + +#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 + +#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 + +#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 + +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 + +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 + +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 + +#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 + +#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 + +#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 + +#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 + +#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 + +#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 + +#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 + +#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 + +#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 + +#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 + +#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 + +#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 + +#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 + +#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 + +#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 + +#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 + +#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 + +#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 + +#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 + +#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 + +#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 + +#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 + +#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 + +#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 + +#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 + +#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__VGA_CRT_INT 12 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 + +#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 + +#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 + +#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 + +#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 + +#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 + +#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 + +#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 + +#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 + +#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 + +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 + +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 + +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 + +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 + +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 + +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 + +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 + +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 + +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 + +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 + +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 + +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 + +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 + +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 + +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 + +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 + +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 + +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 + +#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 + +#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 + +#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 + +#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 + +#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 + +#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 + +#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 + +#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 + +#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 + +#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 + +#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 + +#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 + +#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 + +#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 + +#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 + +#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 + +#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 + +#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 + +#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 + +#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 + +#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 + +#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 + +#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 + +#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 + +#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 + +#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 + +#define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VBLANK 0 + +#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VLINE1 1 + +#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VLINE2 2 + +#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VBLANK 3 + +#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VLINE1 4 + +#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VLINE2 5 + +#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 + +#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 + +#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 + +#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 + +#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 + +#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 + +#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 + +#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 + +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VLINE2 14 + +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VLINE2 14 + +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VLINE2 14 + +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse +#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse + +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 + +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 + +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 + +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 + +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 + +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 + +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 + +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 + +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 + +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 + +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 + +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 + +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 + +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 + +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 + +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 + +#define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse + +#define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse + +#define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse + + +#endif // __IRQSRCS_DCN_1_0_H__ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index a09d9f352871..91ef1484b3bb 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -29,10 +29,12 @@ #define KGD_KFD_INTERFACE_H_INCLUDED #include <linux/types.h> +#include <linux/bitmap.h> struct pci_dev; -#define KFD_INTERFACE_VERSION 1 +#define KFD_INTERFACE_VERSION 2 +#define KGD_MAX_QUEUES 128 struct kfd_dev; struct kgd_dev; @@ -61,11 +63,17 @@ struct kgd2kfd_shared_resources { /* Bit n == 1 means VMID n is available for KFD. */ unsigned int compute_vmid_bitmap; - /* Compute pipes are counted starting from MEC0/pipe0 as 0. */ - unsigned int first_compute_pipe; + /* number of mec available from the hardware */ + uint32_t num_mec; - /* Number of MEC pipes available for KFD. */ - unsigned int compute_pipe_count; + /* number of pipes per mec */ + uint32_t num_pipe_per_mec; + + /* number of queues per pipe */ + uint32_t num_queue_per_pipe; + + /* Bit n == 1 means Queue n is available for KFD */ + DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES); /* Base address of doorbell aperture. */ phys_addr_t doorbell_physical_address; diff --git a/drivers/gpu/drm/amd/include/pptable.h b/drivers/gpu/drm/amd/include/pptable.h index ee6978b30b77..0b6a057e0a4c 100644 --- a/drivers/gpu/drm/amd/include/pptable.h +++ b/drivers/gpu/drm/amd/include/pptable.h @@ -61,13 +61,17 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER #define ATOM_PP_THERMALCONTROLLER_LM96163 17 #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 #define ATOM_PP_THERMALCONTROLLER_KAVERI 19 +#define ATOM_PP_THERMALCONTROLLER_ICELAND 20 +#define ATOM_PP_THERMALCONTROLLER_TONGA 21 +#define ATOM_PP_THERMALCONTROLLER_FIJI 22 +#define ATOM_PP_THERMALCONTROLLER_POLARIS10 23 +#define ATOM_PP_THERMALCONTROLLER_VEGA10 24 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. // We probably should reserve the bit 0x80 for this use. // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). // The driver can pick the correct internal controller based on the ASIC. - #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller @@ -104,6 +108,21 @@ typedef struct _ATOM_PPLIB_FANTABLE3 USHORT usFanOutputSensitivity; } ATOM_PPLIB_FANTABLE3; +typedef struct _ATOM_PPLIB_FANTABLE4 +{ + ATOM_PPLIB_FANTABLE3 basicTable3; + USHORT usFanRPMMax; +} ATOM_PPLIB_FANTABLE4; + +typedef struct _ATOM_PPLIB_FANTABLE5 +{ + ATOM_PPLIB_FANTABLE4 basicTable4; + USHORT usFanCurrentLow; + USHORT usFanCurrentHigh; + USHORT usFanRPMLow; + USHORT usFanRPMHigh; +} ATOM_PPLIB_FANTABLE5; + typedef struct _ATOM_PPLIB_EXTENDEDHEADER { USHORT usSize; @@ -119,6 +138,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER USHORT usPowerTuneTableOffset; /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ USHORT usSclkVddgfxTableOffset; + USHORT usVQBudgetingTableOffset; /* points to the vqBudgetingTable; */ } ATOM_PPLIB_EXTENDEDHEADER; //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps @@ -147,8 +167,9 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 #define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000 -#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000 -#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000 +#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000 +#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000 +#define ATOM_PP_PLATFORM_CAP_VRHOT_POLARITY_HIGH 0x08000000 typedef struct _ATOM_PPLIB_POWERPLAYTABLE { @@ -427,6 +448,15 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ ULONG rsv2[2]; }ATOM_PPLIB_SUMO_CLOCK_INFO; +typedef struct _ATOM_PPLIB_KV_CLOCK_INFO { + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + UCHAR vddcIndex; + USHORT tdpLimit; + USHORT rsv1; + ULONG rsv2[2]; +} ATOM_PPLIB_KV_CLOCK_INFO; + typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { UCHAR index; UCHAR rsv[3]; @@ -697,6 +727,27 @@ typedef struct _ATOM_PPLIB_PPM_Table ULONG ulTjmax; } ATOM_PPLIB_PPM_Table; +#define VQ_DisplayConfig_NoneAWD 1 +#define VQ_DisplayConfig_AWD 2 + +typedef struct ATOM_PPLIB_VQ_Budgeting_Record{ + ULONG ulDeviceID; + ULONG ulSustainableSOCPowerLimitLow; /* in mW */ + ULONG ulSustainableSOCPowerLimitHigh; /* in mW */ + + ULONG ulDClk; + ULONG ulEClk; + ULONG ulDispSclk; + UCHAR ucDispConfig; + +} ATOM_PPLIB_VQ_Budgeting_Record; + +typedef struct ATOM_PPLIB_VQ_Budgeting_Table { + UCHAR revid; + UCHAR numEntries; + ATOM_PPLIB_VQ_Budgeting_Record entries[1]; +} ATOM_PPLIB_VQ_Budgeting_Table; + #pragma pack() #endif diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h index b68f8efcdeae..ca93b5160ba6 100644 --- a/drivers/gpu/drm/amd/include/vi_structs.h +++ b/drivers/gpu/drm/amd/include/vi_structs.h @@ -195,6 +195,274 @@ struct vi_mqd { uint32_t compute_wave_restore_addr_lo; uint32_t compute_wave_restore_addr_hi; uint32_t compute_wave_restore_control; + uint32_t reserved9; + uint32_t reserved10; + uint32_t reserved11; + uint32_t reserved12; + uint32_t reserved13; + uint32_t reserved14; + uint32_t reserved15; + uint32_t reserved16; + uint32_t reserved17; + uint32_t reserved18; + uint32_t reserved19; + uint32_t reserved20; + uint32_t reserved21; + uint32_t reserved22; + uint32_t reserved23; + uint32_t reserved24; + uint32_t reserved25; + uint32_t reserved26; + uint32_t reserved27; + uint32_t reserved28; + uint32_t reserved29; + uint32_t reserved30; + uint32_t reserved31; + uint32_t reserved32; + uint32_t reserved33; + uint32_t reserved34; + uint32_t compute_user_data_0; + uint32_t compute_user_data_1; + uint32_t compute_user_data_2; + uint32_t compute_user_data_3; + uint32_t compute_user_data_4; + uint32_t compute_user_data_5; + uint32_t compute_user_data_6; + uint32_t compute_user_data_7; + uint32_t compute_user_data_8; + uint32_t compute_user_data_9; + uint32_t compute_user_data_10; + uint32_t compute_user_data_11; + uint32_t compute_user_data_12; + uint32_t compute_user_data_13; + uint32_t compute_user_data_14; + uint32_t compute_user_data_15; + uint32_t cp_compute_csinvoc_count_lo; + uint32_t cp_compute_csinvoc_count_hi; + uint32_t reserved35; + uint32_t reserved36; + uint32_t reserved37; + uint32_t cp_mqd_query_time_lo; + uint32_t cp_mqd_query_time_hi; + uint32_t cp_mqd_connect_start_time_lo; + uint32_t cp_mqd_connect_start_time_hi; + uint32_t cp_mqd_connect_end_time_lo; + uint32_t cp_mqd_connect_end_time_hi; + uint32_t cp_mqd_connect_end_wf_count; + uint32_t cp_mqd_connect_end_pq_rptr; + uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr; + uint32_t cp_mqd_connect_end_ib_rptr; + uint32_t reserved38; + uint32_t reserved39; + uint32_t cp_mqd_save_start_time_lo; + uint32_t cp_mqd_save_start_time_hi; + uint32_t cp_mqd_save_end_time_lo; + uint32_t cp_mqd_save_end_time_hi; + uint32_t cp_mqd_restore_start_time_lo; + uint32_t cp_mqd_restore_start_time_hi; + uint32_t cp_mqd_restore_end_time_lo; + uint32_t cp_mqd_restore_end_time_hi; + uint32_t disable_queue; + uint32_t reserved41; + uint32_t gds_cs_ctxsw_cnt0; + uint32_t gds_cs_ctxsw_cnt1; + uint32_t gds_cs_ctxsw_cnt2; + uint32_t gds_cs_ctxsw_cnt3; + uint32_t reserved42; + uint32_t reserved43; + uint32_t cp_pq_exe_status_lo; + uint32_t cp_pq_exe_status_hi; + uint32_t cp_packet_id_lo; + uint32_t cp_packet_id_hi; + uint32_t cp_packet_exe_status_lo; + uint32_t cp_packet_exe_status_hi; + uint32_t gds_save_base_addr_lo; + uint32_t gds_save_base_addr_hi; + uint32_t gds_save_mask_lo; + uint32_t gds_save_mask_hi; + uint32_t ctx_save_base_addr_lo; + uint32_t ctx_save_base_addr_hi; + uint32_t dynamic_cu_mask_addr_lo; + uint32_t dynamic_cu_mask_addr_hi; + uint32_t cp_mqd_base_addr_lo; + uint32_t cp_mqd_base_addr_hi; + uint32_t cp_hqd_active; + uint32_t cp_hqd_vmid; + uint32_t cp_hqd_persistent_state; + uint32_t cp_hqd_pipe_priority; + uint32_t cp_hqd_queue_priority; + uint32_t cp_hqd_quantum; + uint32_t cp_hqd_pq_base_lo; + uint32_t cp_hqd_pq_base_hi; + uint32_t cp_hqd_pq_rptr; + uint32_t cp_hqd_pq_rptr_report_addr_lo; + uint32_t cp_hqd_pq_rptr_report_addr_hi; + uint32_t cp_hqd_pq_wptr_poll_addr_lo; + uint32_t cp_hqd_pq_wptr_poll_addr_hi; + uint32_t cp_hqd_pq_doorbell_control; + uint32_t cp_hqd_pq_wptr; + uint32_t cp_hqd_pq_control; + uint32_t cp_hqd_ib_base_addr_lo; + uint32_t cp_hqd_ib_base_addr_hi; + uint32_t cp_hqd_ib_rptr; + uint32_t cp_hqd_ib_control; + uint32_t cp_hqd_iq_timer; + uint32_t cp_hqd_iq_rptr; + uint32_t cp_hqd_dequeue_request; + uint32_t cp_hqd_dma_offload; + uint32_t cp_hqd_sema_cmd; + uint32_t cp_hqd_msg_type; + uint32_t cp_hqd_atomic0_preop_lo; + uint32_t cp_hqd_atomic0_preop_hi; + uint32_t cp_hqd_atomic1_preop_lo; + uint32_t cp_hqd_atomic1_preop_hi; + uint32_t cp_hqd_hq_status0; + uint32_t cp_hqd_hq_control0; + uint32_t cp_mqd_control; + uint32_t cp_hqd_hq_status1; + uint32_t cp_hqd_hq_control1; + uint32_t cp_hqd_eop_base_addr_lo; + uint32_t cp_hqd_eop_base_addr_hi; + uint32_t cp_hqd_eop_control; + uint32_t cp_hqd_eop_rptr; + uint32_t cp_hqd_eop_wptr; + uint32_t cp_hqd_eop_done_events; + uint32_t cp_hqd_ctx_save_base_addr_lo; + uint32_t cp_hqd_ctx_save_base_addr_hi; + uint32_t cp_hqd_ctx_save_control; + uint32_t cp_hqd_cntl_stack_offset; + uint32_t cp_hqd_cntl_stack_size; + uint32_t cp_hqd_wg_state_offset; + uint32_t cp_hqd_ctx_save_size; + uint32_t cp_hqd_gds_resource_state; + uint32_t cp_hqd_error; + uint32_t cp_hqd_eop_wptr_mem; + uint32_t cp_hqd_eop_dones; + uint32_t reserved46; + uint32_t reserved47; + uint32_t reserved48; + uint32_t reserved49; + uint32_t reserved50; + uint32_t reserved51; + uint32_t reserved52; + uint32_t reserved53; + uint32_t reserved54; + uint32_t reserved55; + uint32_t iqtimer_pkt_header; + uint32_t iqtimer_pkt_dw0; + uint32_t iqtimer_pkt_dw1; + uint32_t iqtimer_pkt_dw2; + uint32_t iqtimer_pkt_dw3; + uint32_t iqtimer_pkt_dw4; + uint32_t iqtimer_pkt_dw5; + uint32_t iqtimer_pkt_dw6; + uint32_t iqtimer_pkt_dw7; + uint32_t iqtimer_pkt_dw8; + uint32_t iqtimer_pkt_dw9; + uint32_t iqtimer_pkt_dw10; + uint32_t iqtimer_pkt_dw11; + uint32_t iqtimer_pkt_dw12; + uint32_t iqtimer_pkt_dw13; + uint32_t iqtimer_pkt_dw14; + uint32_t iqtimer_pkt_dw15; + uint32_t iqtimer_pkt_dw16; + uint32_t iqtimer_pkt_dw17; + uint32_t iqtimer_pkt_dw18; + uint32_t iqtimer_pkt_dw19; + uint32_t iqtimer_pkt_dw20; + uint32_t iqtimer_pkt_dw21; + uint32_t iqtimer_pkt_dw22; + uint32_t iqtimer_pkt_dw23; + uint32_t iqtimer_pkt_dw24; + uint32_t iqtimer_pkt_dw25; + uint32_t iqtimer_pkt_dw26; + uint32_t iqtimer_pkt_dw27; + uint32_t iqtimer_pkt_dw28; + uint32_t iqtimer_pkt_dw29; + uint32_t iqtimer_pkt_dw30; + uint32_t iqtimer_pkt_dw31; + uint32_t reserved56; + uint32_t reserved57; + uint32_t reserved58; + uint32_t set_resources_header; + uint32_t set_resources_dw1; + uint32_t set_resources_dw2; + uint32_t set_resources_dw3; + uint32_t set_resources_dw4; + uint32_t set_resources_dw5; + uint32_t set_resources_dw6; + uint32_t set_resources_dw7; + uint32_t reserved59; + uint32_t reserved60; + uint32_t reserved61; + uint32_t reserved62; + uint32_t reserved63; + uint32_t reserved64; + uint32_t reserved65; + uint32_t reserved66; + uint32_t reserved67; + uint32_t reserved68; + uint32_t reserved69; + uint32_t reserved70; + uint32_t reserved71; + uint32_t reserved72; + uint32_t reserved73; + uint32_t reserved74; + uint32_t reserved75; + uint32_t reserved76; + uint32_t reserved77; + uint32_t reserved78; + uint32_t reserved_t[256]; +}; + +struct vi_mqd_allocation { + struct vi_mqd mqd; + uint32_t wptr_poll_mem; + uint32_t rptr_report_mem; + uint32_t dyamic_cu_mask; + uint32_t dyamic_rb_mask; +}; + +struct cz_mqd { + uint32_t header; + uint32_t compute_dispatch_initiator; + uint32_t compute_dim_x; + uint32_t compute_dim_y; + uint32_t compute_dim_z; + uint32_t compute_start_x; + uint32_t compute_start_y; + uint32_t compute_start_z; + uint32_t compute_num_thread_x; + uint32_t compute_num_thread_y; + uint32_t compute_num_thread_z; + uint32_t compute_pipelinestat_enable; + uint32_t compute_perfcount_enable; + uint32_t compute_pgm_lo; + uint32_t compute_pgm_hi; + uint32_t compute_tba_lo; + uint32_t compute_tba_hi; + uint32_t compute_tma_lo; + uint32_t compute_tma_hi; + uint32_t compute_pgm_rsrc1; + uint32_t compute_pgm_rsrc2; + uint32_t compute_vmid; + uint32_t compute_resource_limits; + uint32_t compute_static_thread_mgmt_se0; + uint32_t compute_static_thread_mgmt_se1; + uint32_t compute_tmpring_size; + uint32_t compute_static_thread_mgmt_se2; + uint32_t compute_static_thread_mgmt_se3; + uint32_t compute_restart_x; + uint32_t compute_restart_y; + uint32_t compute_restart_z; + uint32_t compute_thread_trace_enable; + uint32_t compute_misc_reserved; + uint32_t compute_dispatch_id; + uint32_t compute_threadgroup_id; + uint32_t compute_relaunch; + uint32_t compute_wave_restore_addr_lo; + uint32_t compute_wave_restore_addr_hi; + uint32_t compute_wave_restore_control; uint32_t reserved_39; uint32_t reserved_40; uint32_t reserved_41; diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 043e6ebab575..4e132b936e3d 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -1,5 +1,5 @@ -subdir-ccflags-y += -Iinclude/drm \ +subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/powerplay/inc/ \ -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c index 781e53dcf128..3e3ca03bd344 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c @@ -42,8 +42,8 @@ static int pem_init(struct pp_eventmgr *eventmgr) /* Call initialization event */ result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data); - if (0 != result) - return result; + /* if (0 != result) + return result; */ /* Register interrupt callback functions */ result = pem_register_interrupts(eventmgr); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 27db2b77824f..f0277c16c2bf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -9,8 +9,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ smu7_clockpowergating.o \ vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ - vega10_thermal.o - + vega10_thermal.o pp_overdriver.o rv_hwmgr.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 7aa5ca815a3a..0b74da3dca8b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -1224,6 +1224,12 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); + + if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + } + kfree(hwmgr->backend); hwmgr->backend = NULL; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index ff4ae3de6bb6..d025653c7823 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -22,10 +22,10 @@ */ #include "pp_debug.h" -#include "linux/delay.h" -#include <linux/types.h> +#include <linux/delay.h> #include <linux/kernel.h> #include <linux/slab.h> +#include <linux/types.h> #include <drm/amdgpu_drm.h> #include "cgs_common.h" #include "power_state.h" @@ -115,6 +115,15 @@ int hwmgr_early_init(struct pp_instance *handle) return -EINVAL; } break; + case AMDGPU_FAMILY_RV: + switch (hwmgr->chip_id) { + case CHIP_RAVEN: + rv_init_function_pointers(hwmgr); + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c index f5e8fda964f7..f6b4dd96c0ec 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c @@ -21,8 +21,8 @@ * */ +#include <linux/delay.h> #include <linux/errno.h> -#include "linux/delay.h" #include "hwmgr.h" #include "amd_acpi.h" #include "pp_acpi.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c new file mode 100644 index 000000000000..d09f25485844 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c @@ -0,0 +1,1276 @@ +#include "pp_overdriver.h" +#include <linux/errno.h> + +struct phm_fuses_default vega10_fuses_default[] = { + {"0000001000010011111010101001010011011110000011100100100101100100",0x00003C96,0xFFFFE226,0x00000656,0x00002203,0xFFFFF201,0x000003FF,0x00002203,0xFFFFF201,0x000003FF}, + {"0000001000010011111010101001010011011110000010100001100010000100",0x00003CC5,0xFFFFE23A,0x0000064E,0x00002258,0xFFFFF1F7,0x000003FC,0x00002258,0xFFFFF1F7,0x000003FC}, + {"0000001000010011111010101001010011011110000011100011000110100100",0x00003CAF,0xFFFFE36E,0x00000602,0x00001E98,0xFFFFF569,0x00000357,0x00001E98,0xFFFFF569,0x00000357}, + {"0000001000010011111010101001010011011110001011000001000101000100",0x0000391A,0xFFFFE548,0x000005C9,0x00001B98,0xFFFFF707,0x00000324,0x00001B98,0xFFFFF707,0x00000324}, + {"0000001000010011111010101001010011011110001011000001100011000100",0x00003821,0xFFFFE674,0x00000597,0x00002196,0xFFFFF361,0x000003C0,0x00002196,0xFFFFF361,0x000003C0}, + {"0000001000010011111010101001010011011110001001100011100010000100",0x000044A2,0xFFFFDCB7,0x00000738,0x0000325C,0xFFFFE6A7,0x000005E6,0x0000325C,0xFFFFE6A7,0x000005E6}, + {"0000001000010011111010101001010011011110000010000010100100100100",0x00004057,0xFFFFE1CF,0x0000063C,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD}, + {"0000001000010011111010101001010011011110001010000100100100100100",0x00003FD0,0xFFFFDF0F,0x000006E5,0x0000267C,0xFFFFEE2D,0x000004AB,0x0000267C,0xFFFFEE2D,0x000004AB}, + {"0000001000010011111010101001010011011110001010000000100100000100",0x00003F13,0xFFFFE010,0x000006AD,0x000020E7,0xFFFFF266,0x000003EC,0x000020E7,0xFFFFF266,0x000003EC}, + {"0000001000010011111010101001010011011110000010000010000001000100",0x00004088,0xFFFFDFAB,0x000006B6,0x0000252B,0xFFFFEFDB,0x00000458,0x0000252B,0xFFFFEFDB,0x00000458}, + {"0000001000010011111010101001010011011110001010000011100010000100",0x00003EF6,0xFFFFE017,0x000006AA,0x00001F67,0xFFFFF369,0x000003BE,0x00001F67,0xFFFFF369,0x000003BE}, + {"0000001000010011111010101001010011011110001011000010000110000100",0x00003CDD,0xFFFFE2A7,0x0000063C,0x000026C6,0xFFFFEF38,0x00000478,0x000026C6,0xFFFFEF38,0x00000478}, + {"0000001000010011111010101001010011011110000100000101000100100100",0x00003FA8,0xFFFFDF02,0x000006F0,0x000027FE,0xFFFFECF6,0x000004EA,0x000027FE,0xFFFFECF6,0x000004EA}, + {"0000001000010011111010101001010011011110001001100011100011000100",0x00004670,0xFFFFDC40,0x00000742,0x00003A7A,0xFFFFE1A7,0x000006B6,0x00003A7A,0xFFFFE1A7,0x000006B6}, + {"0000001000010011111010101001010011011110001011000011000000100100",0x00003CDC,0xFFFFE18C,0x00000683,0x00002A69,0xFFFFEBE7,0x00000515,0x00002A69,0xFFFFEBE7,0x00000515}, + {"0000001000010011111010101001010011011110000011100011100011000100",0x00003CEC,0xFFFFE38E,0x00000601,0x00002752,0xFFFFEFA7,0x00000453,0x00002752,0xFFFFEFA7,0x00000453}, + {"0000001000010011111010101001010011011110001011000001000100100100",0x000037D0,0xFFFFE634,0x000005A7,0x00001CD2,0xFFFFF644,0x00000348,0x00001CD2,0xFFFFF644,0x00000348}, + {"0000001000010011111010101001010011011110001010000011100101100100",0x00003DF5,0xFFFFE0A5,0x00000698,0x00001FD5,0xFFFFF30E,0x000003D1,0x00001FD5,0xFFFFF30E,0x000003D1}, + {"0000001000010011111010101001010011011110000010000010100011000100",0x00004201,0xFFFFE03E,0x00000688,0x00003206,0xFFFFE852,0x0000058A,0x00003206,0xFFFFE852,0x0000058A}, + {"0000001000010011111010101001010011011110001011000001100001100100",0x00003BED,0xFFFFE2F5,0x00000638,0x0000270D,0xFFFFEED0,0x0000048E,0x0000270D,0xFFFFEED0,0x0000048E}, + {"0000001000010011111010101001010011011110000010100001100100000100",0x00003E82,0xFFFFE1BE,0x00000654,0x000025FB,0xFFFFEFFA,0x00000448,0x000025FB,0xFFFFEFFA,0x00000448}, + {"0000001000010011111010101001010011011110001011000100000011000100",0x00003962,0xFFFFE4B9,0x000005EF,0x00002385,0xFFFFF156,0x00000423,0x00002385,0xFFFFF156,0x00000423}, + {"0000001000010011111010101001010011011110001011000000100101000100",0x00003D88,0xFFFFE21A,0x00000655,0x0000295A,0xFFFFED68,0x000004C4,0x0000295A,0xFFFFED68,0x000004C4}, + {"0000001000010011111010101001010011011110001011000001000100000100",0x00003AA4,0xFFFFE4A3,0x000005E0,0x000022EF,0xFFFFF250,0x000003EB,0x000022EF,0xFFFFF250,0x000003EB}, + {"0000001000010011111010101001010011011110000011100010100110100100",0x00003D97,0xFFFFE30D,0x0000060D,0x0000205D,0xFFFFF45D,0x00000380,0x0000205D,0xFFFFF45D,0x00000380}, + {"0000001000010011111010101001010011011110001011000100000010100100",0x000039B6,0xFFFFE446,0x00000605,0x00002325,0xFFFFF16C,0x0000041F,0x00002325,0xFFFFF16C,0x0000041F}, + {"0000001000010011111010101001010011011110001001100011100100000100",0x0000457E,0xFFFFDCF6,0x00000722,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E}, + {"0000001000010011111010101001010011011110000010100001100100100100",0x00003FB8,0xFFFFE101,0x00000670,0x00002787,0xFFFFEEF5,0x00000471,0x00002787,0xFFFFEEF5,0x00000471}, + {"0000001000010011111010101001010011011110000011100011100010100100",0x00003BB2,0xFFFFE430,0x000005EA,0x000024A5,0xFFFFF162,0x00000409,0x000024A5,0xFFFFF162,0x00000409}, + {"0000001000010011111010101001010011011110000010000010000101000100",0x00003EC5,0xFFFFE1BD,0x0000064F,0x000022F0,0xFFFFF227,0x000003E8,0x000022F0,0xFFFFF227,0x000003E8}, + {"0000001000010011111010101001010011011110001011000011000101100100",0x000038A7,0xFFFFE59F,0x000005C1,0x000021CC,0xFFFFF2DF,0x000003D9,0x000021CC,0xFFFFF2DF,0x000003D9}, + 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{"0000001000010011111100001111111010011001001010000100000010000100",0x00002A00,0xFFFFF02E,0x00000424,0x00001E21,0xFFFFF61D,0x0000036C,0x00001E21,0xFFFFF61D,0x0000036C}, + {"0000001000010011111100001111111010011001001010100100100010100100",0x000029CF,0xFFFFEF53,0x00000457,0x00001B11,0xFFFFF772,0x0000033D,0x00001B11,0xFFFFF772,0x0000033D}, + {"0000001000010011111100001111111010011001000110100011000010100100",0x000032A1,0xFFFFEA63,0x000004FB,0x00001F83,0xFFFFF516,0x0000037E,0x00001F83,0xFFFFF516,0x0000037E}, + {"0000001000010011111100001111111010011001001011100010000011000100",0x0000305C,0xFFFFEC14,0x000004B5,0x00001D0B,0xFFFFF6ED,0x00000332,0x00001D0B,0xFFFFF6ED,0x00000332}, + {"0000001000010011111100001111111010011001001011000001000001100100",0x00003467,0xFFFFE8D5,0x00000543,0x0000243F,0xFFFFF190,0x00000418,0x0000243F,0xFFFFF190,0x00000418}, + {"0000001000010011111100001111111010011001001010100010000001100100",0x00002796,0xFFFFF133,0x00000409,0x00001903,0xFFFFF91C,0x000002FC,0x00001903,0xFFFFF91C,0x000002FC}, + {"0000001000010011111100001111111010011001001100000010000101100100",0x000031F6,0xFFFFEAB7,0x000004F5,0x000022B9,0xFFFFF2D0,0x000003E6,0x000022B9,0xFFFFF2D0,0x000003E6}, + {"0000001000010011111100001111111010011001001011100101000100000100",0x00003196,0xFFFFEA76,0x00000503,0x00001CC5,0xFFFFF67D,0x0000034A,0x00001CC5,0xFFFFF67D,0x0000034A}, + {"0000001000010011111100001111111010011001001100100001000101000100",0x00002F9E,0xFFFFEAD9,0x00000505,0x000017C1,0xFFFFF93D,0x000002DF,0x000017C1,0xFFFFF93D,0x000002DF}, + {"0000001000010011111100001111111010011001001011100010000100100100",0x00002FBC,0xFFFFEC75,0x000004A8,0x00001D6D,0xFFFFF6AC,0x0000033D,0x00001D6D,0xFFFFF6AC,0x0000033D}, + {"0000001000010011111100001111111010011001001011000011100010100100",0x00003541,0xFFFFE921,0x00000524,0x00002662,0xFFFFF0CB,0x0000042B,0x00002662,0xFFFFF0CB,0x0000042B}, + {"0000001000010011111100001111111010011001001010100010000110100100",0x00002953,0xFFFFEF76,0x00000459,0x00001C05,0xFFFFF6A0,0x00000368,0x00001C05,0xFFFFF6A0,0x00000368}, + {"0000001000010011111100001111111010011001001011000100100100100100",0x000034BC,0xFFFFE8DD,0x00000536,0x0000210E,0xFFFFF3F4,0x000003A8,0x0000210E,0xFFFFF3F4,0x000003A8}, + {"0000001000010011111100001111111010011001001011000010100110100100",0x000034BE,0xFFFFE916,0x0000052F,0x000024A1,0xFFFFF1A6,0x00000410,0x000024A1,0xFFFFF1A6,0x00000410}, + {"0000001000010011111100001111111010011001001100000100100101100100",0x000037B5,0xFFFFE7A9,0x0000055B,0x000028A1,0xFFFFEF51,0x00000467,0x000028A1,0xFFFFEF51,0x00000467}, + {"0000001000010011111100001111111010011001001100000001000100000100",0x00002FC5,0xFFFFEBBE,0x000004D1,0x00001BA5,0xFFFFF757,0x00000328,0x00001BA5,0xFFFFF757,0x00000328}, + {"0000001000010011111100001111111010011001001100000100000010100100",0x000033CB,0xFFFFE944,0x0000052B,0x00001FBE,0xFFFFF4B1,0x0000038C,0x00001FBE,0xFFFFF4B1,0x0000038C}, + {"0000001000010011111100001111111010011001001100000001100001000100",0x000030AE,0xFFFFEBA0,0x000004D3,0x00002268,0xFFFFF316,0x000003DD,0x00002268,0xFFFFF316,0x000003DD}, + {"0000001000010011111100001111111010011001001011000010000010100100",0x00002F90,0xFFFFEC5A,0x000004B0,0x00001C3A,0xFFFFF752,0x00000323,0x00001C3A,0xFFFFF752,0x00000323}, + {"0000001000010011111100001111111010011001001011100011100011100100",0x00003113,0xFFFFEB91,0x000004C8,0x00001E3C,0xFFFFF623,0x0000034E,0x00001E3C,0xFFFFF623,0x0000034E}, + {"0000001000010011111100001111111010011001001100100011100110000100",0x0000330B,0xFFFFE94B,0x00000539,0x000020E7,0xFFFFF37E,0x000003CD,0x000020E7,0xFFFFF37E,0x000003CD}, + {"0000001000010011111100001111111010011001001011100010100001100100",0x000031D1,0xFFFFEACB,0x000004ED,0x00001E82,0xFFFFF5B2,0x00000365,0x00001E82,0xFFFFF5B2,0x00000365}, + {"0000001000010011111100001111111010011001001010100011100110000100",0x00002CD5,0xFFFFEDC1,0x0000048D,0x000020F8,0xFFFFF3C1,0x000003D1,0x000020F8,0xFFFFF3C1,0x000003D1}, + { NULL ,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000} +}; + +int pp_override_get_default_fuse_value(uint64_t key, + struct phm_fuses_default list[], + struct phm_fuses_default *result) +{ + uint32_t i; + uint64_t temp_serial_numer; + uint32_t bit; + const char *temp; + + for (i = 0; list[i].key != NULL; i++) { + temp = list[i].key; + temp_serial_numer = 0; + do { + bit = *temp=='1'? 1 : 0; + temp_serial_numer = (temp_serial_numer <<1 ) | bit; + temp++; + } while (*temp); + + if (key == temp_serial_numer) { + result->key = list[i].key; + result->VFT2_m1 = list[i].VFT2_m1; + result->VFT2_m2 = list[i].VFT2_m2; + result->VFT2_b = list[i].VFT2_b; + result->VFT1_m1 = list[i].VFT1_m1; + result->VFT1_m2 = list[i].VFT1_m2; + result->VFT1_b = list[i].VFT1_b; + result->VFT0_m1 = list[i].VFT0_m1; + result->VFT0_m2 = list[i].VFT0_m2; + result->VFT0_b = list[i].VFT0_b; + return 0; + } + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h new file mode 100644 index 000000000000..6e8f7a2119c1 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h @@ -0,0 +1,48 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PP_OVERDRIVER_H_ +#define _PP_OVERDRIVER_H_ + +#include <linux/types.h> +#include <linux/kernel.h> + +struct phm_fuses_default { + const char *key; + uint32_t VFT2_m1; + uint32_t VFT2_m2; + uint32_t VFT2_b; + uint32_t VFT1_m1; + uint32_t VFT1_m2; + uint32_t VFT1_b; + uint32_t VFT0_m1; + uint32_t VFT0_m2; + uint32_t VFT0_b; +}; + +extern struct phm_fuses_default vega10_fuses_default[]; +extern int pp_override_get_default_fuse_value(uint64_t key, + struct phm_fuses_default list[], + struct phm_fuses_default *result); + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c index 56023114ad6f..720d5006ff62 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c @@ -315,13 +315,13 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, param->ulGbFuseTableCksoffM1 = le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1); param->ulGbFuseTableCksoffM2 = - le16_to_cpu(profile->avfsgb_fuse_table_cksoff_m2); + le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m2); param->ulGbFuseTableCksoffB = le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b); param->ulGbFuseTableCksonM1 = le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1); param->ulGbFuseTableCksonM2 = - le16_to_cpu(profile->avfsgb_fuse_table_ckson_m2); + le32_to_cpu(profile->avfsgb_fuse_table_ckson_m2); param->ulGbFuseTableCksonB = le32_to_cpu(profile->avfsgb_fuse_table_ckson_b); @@ -335,25 +335,25 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, param->ulDispclk2GfxclkM1 = le32_to_cpu(profile->dispclk2gfxclk_a); param->ulDispclk2GfxclkM2 = - le16_to_cpu(profile->dispclk2gfxclk_b); + le32_to_cpu(profile->dispclk2gfxclk_b); param->ulDispclk2GfxclkB = le32_to_cpu(profile->dispclk2gfxclk_c); param->ulDcefclk2GfxclkM1 = le32_to_cpu(profile->dcefclk2gfxclk_a); param->ulDcefclk2GfxclkM2 = - le16_to_cpu(profile->dcefclk2gfxclk_b); + le32_to_cpu(profile->dcefclk2gfxclk_b); param->ulDcefclk2GfxclkB = le32_to_cpu(profile->dcefclk2gfxclk_c); param->ulPixelclk2GfxclkM1 = le32_to_cpu(profile->pixclk2gfxclk_a); param->ulPixelclk2GfxclkM2 = - le16_to_cpu(profile->pixclk2gfxclk_b); + le32_to_cpu(profile->pixclk2gfxclk_b); param->ulPixelclk2GfxclkB = le32_to_cpu(profile->pixclk2gfxclk_c); param->ulPhyclk2GfxclkM1 = le32_to_cpu(profile->phyclk2gfxclk_a); param->ulPhyclk2GfxclkM2 = - le16_to_cpu(profile->phyclk2gfxclk_b); + le32_to_cpu(profile->phyclk2gfxclk_b); param->ulPhyclk2GfxclkB = le32_to_cpu(profile->phyclk2gfxclk_c); @@ -388,11 +388,33 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, return 0; } +int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency) +{ + struct atom_get_smu_clock_info_parameters_v3_1 parameters; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + uint32_t ix; + + parameters.clk_id = id; + parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + + ix = GetIndexIntoMasterCmdTable(getsmuclockinfo); + if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, ¶meters)) { + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters; + *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000; + } else { + pr_info("Error execute_table getsmuclockinfo!"); + return -1; + } + + return 0; +} + int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, struct pp_atomfwctrl_bios_boot_up_values *boot_values) { struct atom_firmware_info_v3_1 *info = NULL; uint16_t ix; + uint32_t frequency = 0; ix = GetIndexIntoMasterDataTable(firmwareinfo); info = (struct atom_firmware_info_v3_1 *) @@ -407,11 +429,18 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, boot_values->ulRevision = info->firmware_revision; boot_values->ulGfxClk = info->bootup_sclk_in10khz; boot_values->ulUClk = info->bootup_mclk_in10khz; - boot_values->ulSocClk = 0; boot_values->usVddc = info->bootup_vddc_mv; boot_values->usVddci = info->bootup_vddci_mv; boot_values->usMvddc = info->bootup_mvddc_mv; boot_values->usVddGfx = info->bootup_vddgfx_mv; + boot_values->ulSocClk = 0; + boot_values->ulDCEFClk = 0; + + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency)) + boot_values->ulSocClk = frequency; + + if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency)) + boot_values->ulDCEFClk = frequency; return 0; } \ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h index 43a6711e3c06..81908b5cfd5f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h @@ -26,6 +26,8 @@ #include "hwmgr.h" +typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; + #define GetIndexIntoMasterCmdTable(FieldName) \ (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) #define GetIndexIntoMasterDataTable(FieldName) \ @@ -125,6 +127,7 @@ struct pp_atomfwctrl_bios_boot_up_values { uint32_t ulGfxClk; uint32_t ulUClk; uint32_t ulSocClk; + uint32_t ulDCEFClk; uint16_t usVddc; uint16_t usVddci; uint16_t usMvddc; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index ed6c934927fb..2716721e5453 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -1015,6 +1015,10 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; hwmgr->platform_descriptor.minOverdriveVDDC = 0; hwmgr->platform_descriptor.maxOverdriveVDDC = 0; + hwmgr->platform_descriptor.overdriveVDDCStep = 0; + + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; /* We assume here that fw_info is unchanged if this call fails.*/ fw_info = cgs_atom_get_data_table(hwmgr->device, @@ -1559,6 +1563,9 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) int result; const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + hwmgr->need_pp_table_upload = true; powerplay_table = get_powerplay_table(hwmgr); @@ -1605,6 +1612,9 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) { + if (hwmgr->chip_id == CHIP_RAVEN) + return 0; + if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) { kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c new file mode 100644 index 000000000000..4c7f430b36eb --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -0,0 +1,1059 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "pp_debug.h" +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include "atom-types.h" +#include "atombios.h" +#include "processpptables.h" +#include "cgs_common.h" +#include "smumgr.h" +#include "hwmgr.h" +#include "hardwaremanager.h" +#include "rv_ppsmc.h" +#include "rv_hwmgr.h" +#include "power_state.h" +#include "rv_smumgr.h" +#include "pp_soc15.h" + +#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip +#define SCLK_MIN_DIV_INTV_SHIFT 12 +#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz +#define SMC_RAM_END 0x40000 + +static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic; +int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, + struct pp_display_clock_request *clock_req); + +struct phm_vq_budgeting_record rv_vqtable[] = { + /* _TBD + * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */ + { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 }, +}; + +static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps) +{ + if (PhwRaven_Magic != hw_ps->magic) + return NULL; + + return (struct rv_power_state *)hw_ps; +} + +static const struct rv_power_state *cast_const_rv_ps( + const struct pp_hw_power_state *hw_ps) +{ + if (PhwRaven_Magic != hw_ps->magic) + return NULL; + + return (struct rv_power_state *)hw_ps; +} + +static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr) +{ + uint32_t table_size, i; + struct phm_vq_budgeting_table *ptable; + uint32_t num_entries = ARRAY_SIZE(rv_vqtable); + + if (hwmgr->dyn_state.vq_budgeting_table != NULL) + return 0; + + table_size = sizeof(struct phm_vq_budgeting_table) + + sizeof(struct phm_vq_budgeting_record) * (num_entries - 1); + + ptable = kzalloc(table_size, GFP_KERNEL); + if (NULL == ptable) + return -ENOMEM; + + ptable->numEntries = (uint8_t) num_entries; + + for (i = 0; i < ptable->numEntries; i++) { + ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs; + ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow; + ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh; + ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow; + ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh; + ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig; + ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk; + ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk; + ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk; + ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs; + } + + hwmgr->dyn_state.vq_budgeting_table = ptable; + + return 0; +} + +static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend); + struct cgs_system_info sys_info = {0}; + int result; + + rv_hwmgr->ddi_power_gating_disabled = 0; + rv_hwmgr->bapm_enabled = 1; + rv_hwmgr->dce_slow_sclk_threshold = 30000; + rv_hwmgr->disable_driver_thermal_policy = 1; + rv_hwmgr->thermal_auto_throttling_treshold = 0; + rv_hwmgr->is_nb_dpm_enabled = 1; + rv_hwmgr->dpm_flags = 1; + rv_hwmgr->disable_smu_acp_s3_handshake = 1; + rv_hwmgr->disable_notify_smu_vpu_recovery = 0; + rv_hwmgr->gfx_off_controled_by_driver = false; + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicM3Arbiter); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDDynamicPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_VCEPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SamuPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ACP); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_GFXDynamicMGPowerGating); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification); + + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableVoltageIsland); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DynamicUVDState); + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (!result) { + if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_GFXDynamicMGPowerGating); + } + + return 0; +} + +static int rv_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, + struct phm_clock_and_voltage_limits *table) +{ + return 0; +} + +static int rv_init_dynamic_state_adjustment_rule_settings( + struct pp_hwmgr *hwmgr) +{ + uint32_t table_size = + sizeof(struct phm_clock_voltage_dependency_table) + + (7 * sizeof(struct phm_clock_voltage_dependency_record)); + + struct phm_clock_voltage_dependency_table *table_clk_vlt = + kzalloc(table_size, GFP_KERNEL); + + if (NULL == table_clk_vlt) { + pr_err("Can not allocate memory!\n"); + return -ENOMEM; + } + + table_clk_vlt->count = 8; + table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; + table_clk_vlt->entries[0].v = 0; + table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; + table_clk_vlt->entries[1].v = 1; + table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; + table_clk_vlt->entries[2].v = 2; + table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; + table_clk_vlt->entries[3].v = 3; + table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; + table_clk_vlt->entries[4].v = 4; + table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; + table_clk_vlt->entries[5].v = 5; + table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; + table_clk_vlt->entries[6].v = 6; + table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; + table_clk_vlt->entries[7].v = 7; + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; + + return 0; +} + +static int rv_get_system_info_data(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)hwmgr->backend; + + rv_data->sys_info.htc_hyst_lmt = 5; + rv_data->sys_info.htc_tmp_lmt = 203; + + if (rv_data->thermal_auto_throttling_treshold == 0) + rv_data->thermal_auto_throttling_treshold = 203; + + rv_construct_max_power_limits_table (hwmgr, + &hwmgr->dyn_state.max_clock_voltage_on_ac); + + rv_init_dynamic_state_adjustment_rule_settings(hwmgr); + + return 0; +} + +static int rv_construct_boot_state(struct pp_hwmgr *hwmgr) +{ + return 0; +} + +static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct PP_Clocks clocks = {0}; + struct pp_display_clock_request clock_req; + + clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; + clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; + clock_req.clock_type = amd_pp_dcf_clock; + clock_req.clock_freq_in_khz = clocks.dcefClock * 10; + + if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0) + clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq; + + PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req), + "Attempt to set DCF Clock Failed!", return -EINVAL); + + if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + clocks.dcefClockInSR / 100); + /* + if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) { + if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq), + } + } */ + + if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && + ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetHardMinSocclkByFreq, + hwmgr->gfx_arbiter.sclk_hard_min / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); + } + + if ((hwmgr->gfx_arbiter.gfxclk != 0) && + (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinVideoGfxclkFreq, + hwmgr->gfx_arbiter.gfxclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq); + } + + if ((hwmgr->gfx_arbiter.fclk != 0) && + (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinVideoFclkFreq, + hwmgr->gfx_arbiter.fclk / 100); + rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq); + } + + return 0; +} + +static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + uint32_t num_of_active_displays = 0; + struct cgs_display_info info = {0}; + + cgs_get_active_displays_info(hwmgr->device, &info); + num_of_active_displays = info.display_count; + + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetDisplayCount, + num_of_active_displays); + return 0; +} + +static const struct phm_master_table_item rv_set_power_state_list[] = { + { NULL, rv_tf_set_clock_limit }, + { NULL, rv_tf_set_num_active_display }, + { } +}; + +static const struct phm_master_table_header rv_set_power_state_master = { + 0, + PHM_MasterTableFlag_None, + rv_set_power_state_list +}; + +static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + rv_data->vcn_power_gated = true; + rv_data->isp_tileA_power_gated = true; + rv_data->isp_tileB_power_gated = true; + + return 0; +} + +static const struct phm_master_table_item rv_setup_asic_list[] = { + { .tableFunction = rv_tf_init_power_gate_state }, + { } +}; + +static const struct phm_master_table_header rv_setup_asic_master = { + 0, + PHM_MasterTableFlag_None, + rv_setup_asic_list +}; + +static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + rv_data->separation_time = 0; + rv_data->cc6_disable = false; + rv_data->pstate_disable = false; + rv_data->cc6_setting_changed = false; + + return 0; +} + +static const struct phm_master_table_item rv_power_down_asic_list[] = { + { .tableFunction = rv_tf_reset_cc6_data }, + { } +}; + +static const struct phm_master_table_header rv_power_down_asic_master = { + 0, + PHM_MasterTableFlag_None, + rv_power_down_asic_list +}; + + +static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + if (rv_data->gfx_off_controled_by_driver) + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_DisableGfxOff); + + return 0; +} + +static const struct phm_master_table_item rv_disable_dpm_list[] = { + {NULL, rv_tf_disable_gfx_off}, + { }, +}; + + +static const struct phm_master_table_header rv_disable_dpm_master = { + 0, + PHM_MasterTableFlag_None, + rv_disable_dpm_list +}; + +static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr, + void *input, void *output, + void *storage, int result) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + if (rv_data->gfx_off_controled_by_driver) + smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_EnableGfxOff); + + return 0; +} + +static const struct phm_master_table_item rv_enable_dpm_list[] = { + {NULL, rv_tf_enable_gfx_off}, + { }, +}; + +static const struct phm_master_table_header rv_enable_dpm_master = { + 0, + PHM_MasterTableFlag_None, + rv_enable_dpm_list +}; + +static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *prequest_ps, + const struct pp_power_state *pcurrent_ps) +{ + return 0; +} + +/* temporary hardcoded clock voltage breakdown tables */ +DpmClock_t VddDcfClk[]= { + { 300, 2600}, + { 600, 3200}, + { 600, 3600}, +}; + +DpmClock_t VddSocClk[]= { + { 478, 2600}, + { 722, 3200}, + { 722, 3600}, +}; + +DpmClock_t VddFClk[]= { + { 400, 2600}, + {1200, 3200}, + {1200, 3600}, +}; + +DpmClock_t VddDispClk[]= { + { 435, 2600}, + { 661, 3200}, + {1086, 3600}, +}; + +DpmClock_t VddDppClk[]= { + { 435, 2600}, + { 661, 3200}, + { 661, 3600}, +}; + +DpmClock_t VddPhyClk[]= { + { 540, 2600}, + { 810, 3200}, + { 810, 3600}, +}; + +static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, + struct rv_voltage_dependency_table **pptable, + uint32_t num_entry, DpmClock_t *pclk_dependency_table) +{ + uint32_t table_size, i; + struct rv_voltage_dependency_table *ptable; + + table_size = sizeof(uint32_t) + sizeof(struct rv_voltage_dependency_table) * num_entry; + ptable = kzalloc(table_size, GFP_KERNEL); + + if (NULL == ptable) + return -ENOMEM; + + ptable->count = num_entry; + + for (i = 0; i < ptable->count; i++) { + ptable->entries[i].clk = pclk_dependency_table->Freq * 100; + ptable->entries[i].vol = pclk_dependency_table->Vol; + pclk_dependency_table++; + } + + *pptable = ptable; + + return 0; +} + + +static int rv_populate_clock_table(struct pp_hwmgr *hwmgr) +{ + int result; + + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + DpmClocks_t *table = &(rv_data->clock_table); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + + result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE); + + PP_ASSERT_WITH_CODE((0 == result), + "Attempt to copy clock table from smc failed", + return result); + + if (0 == result && table->DcefClocks[0].Freq != 0) { + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, + NUM_DCEFCLK_DPM_LEVELS, + &rv_data->clock_table.DcefClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, + NUM_SOCCLK_DPM_LEVELS, + &rv_data->clock_table.SocClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, + NUM_FCLK_DPM_LEVELS, + &rv_data->clock_table.FClocks[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, + NUM_MEMCLK_DPM_LEVELS, + &rv_data->clock_table.MemClocks[0]); + } else { + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, + ARRAY_SIZE(VddDcfClk), + &VddDcfClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, + ARRAY_SIZE(VddSocClk), + &VddSocClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, + ARRAY_SIZE(VddFClk), + &VddFClk[0]); + } + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, + ARRAY_SIZE(VddDispClk), + &VddDispClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, + ARRAY_SIZE(VddDppClk), &VddDppClk[0]); + rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, + ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]); + + return 0; +} + +static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +{ + int result = 0; + struct rv_hwmgr *data; + + data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + hwmgr->backend = data; + + result = rv_initialize_dpm_defaults(hwmgr); + if (result != 0) { + pr_err("rv_initialize_dpm_defaults failed\n"); + return result; + } + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerPlaySupport); + + rv_populate_clock_table(hwmgr); + + result = rv_get_system_info_data(hwmgr); + if (result != 0) { + pr_err("rv_get_system_info_data failed\n"); + return result; + } + + rv_construct_boot_state(hwmgr); + + result = phm_construct_table(hwmgr, &rv_setup_asic_master, + &(hwmgr->setup_asic)); + if (result != 0) { + pr_err("Fail to construct setup ASIC\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_power_down_asic_master, + &(hwmgr->power_down_asic)); + if (result != 0) { + pr_err("Fail to construct power down ASIC\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_set_power_state_master, + &(hwmgr->set_power_state)); + if (result != 0) { + pr_err("Fail to construct set_power_state\n"); + return result; + } + + result = phm_construct_table(hwmgr, &rv_disable_dpm_master, + &(hwmgr->disable_dynamic_state_management)); + if (result != 0) { + pr_err("Fail to disable_dynamic_state\n"); + return result; + } + result = phm_construct_table(hwmgr, &rv_enable_dpm_master, + &(hwmgr->enable_dynamic_state_management)); + if (result != 0) { + pr_err("Fail to enable_dynamic_state\n"); + return result; + } + + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = + RAVEN_MAX_HARDWARE_POWERLEVELS; + + hwmgr->platform_descriptor.hardwarePerformanceLevels = + RAVEN_MAX_HARDWARE_POWERLEVELS; + + hwmgr->platform_descriptor.vbiosInterruptId = 0; + + hwmgr->platform_descriptor.clockStep.engineClock = 500; + + hwmgr->platform_descriptor.clockStep.memoryClock = 500; + + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + + rv_init_vq_budget_table(hwmgr); + + return result; +} + +static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + + phm_destroy_table(hwmgr, &(hwmgr->set_power_state)); + phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management)); + phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); + phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); + phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); + + if (pinfo->vdd_dep_on_dcefclk) { + kfree(pinfo->vdd_dep_on_dcefclk); + pinfo->vdd_dep_on_dcefclk = NULL; + } + if (pinfo->vdd_dep_on_socclk) { + kfree(pinfo->vdd_dep_on_socclk); + pinfo->vdd_dep_on_socclk = NULL; + } + if (pinfo->vdd_dep_on_fclk) { + kfree(pinfo->vdd_dep_on_fclk); + pinfo->vdd_dep_on_fclk = NULL; + } + if (pinfo->vdd_dep_on_dispclk) { + kfree(pinfo->vdd_dep_on_dispclk); + pinfo->vdd_dep_on_dispclk = NULL; + } + if (pinfo->vdd_dep_on_dppclk) { + kfree(pinfo->vdd_dep_on_dppclk); + pinfo->vdd_dep_on_dppclk = NULL; + } + if (pinfo->vdd_dep_on_phyclk) { + kfree(pinfo->vdd_dep_on_phyclk); + pinfo->vdd_dep_on_phyclk = NULL; + } + + if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + } + + if (NULL != hwmgr->dyn_state.vq_budgeting_table) { + kfree(hwmgr->dyn_state.vq_budgeting_table); + hwmgr->dyn_state.vq_budgeting_table = NULL; + } + + kfree(hwmgr->backend); + hwmgr->backend = NULL; + + return 0; +} + +static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level level) +{ + return 0; +} + +static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +{ + return 0; +} + +static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +{ + return 0; +} + +static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps) +{ + return 0; +} + +static int rv_dpm_get_pp_table_entry_callback( + struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps, + unsigned int index, + const void *clock_info) +{ + struct rv_power_state *rv_ps = cast_rv_ps(hw_ps); + + const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info; + + struct phm_clock_voltage_dependency_table *table = + hwmgr->dyn_state.vddc_dependency_on_sclk; + uint8_t clock_info_index = rv_clock_info->index; + + if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) + clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); + + rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk; + rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v; + + rv_ps->level = index + 1; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + rv_ps->levels[index].ds_divider_index = 5; + rv_ps->levels[index].ss_divider_index = 5; + } + + return 0; +} + +static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) +{ + int result; + unsigned long ret = 0; + + result = pp_tables_get_num_of_entries(hwmgr, &ret); + + return result ? 0 : ret; +} + +static int rv_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, + unsigned long entry, struct pp_power_state *ps) +{ + int result; + struct rv_power_state *rv_ps; + + ps->hardware.magic = PhwRaven_Magic; + + rv_ps = cast_rv_ps(&(ps->hardware)); + + result = pp_tables_get_entry(hwmgr, entry, ps, + rv_dpm_get_pp_table_entry_callback); + + rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; + rv_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; + + return result; +} + +static int rv_get_power_state_size(struct pp_hwmgr *hwmgr) +{ + return sizeof(struct rv_power_state); +} + +static int rv_set_cpu_power_state(struct pp_hwmgr *hwmgr) +{ + return 0; +} + + +static int rv_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, + bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) +{ + return 0; +} + +static int rv_get_dal_power_level(struct pp_hwmgr *hwmgr, + struct amd_pp_simple_clock_info *info) +{ + return -EINVAL; +} + +static int rv_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, uint32_t mask) +{ + return 0; +} + +static int rv_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) +{ + return 0; +} + +static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, + PHM_PerformanceLevelDesignation designation, uint32_t index, + PHM_PerformanceLevel *level) +{ + const struct rv_power_state *ps; + struct rv_hwmgr *data; + uint32_t level_index; + uint32_t i; + uint32_t vol_dep_record_index = 0; + + if (level == NULL || hwmgr == NULL || state == NULL) + return -EINVAL; + + data = (struct rv_hwmgr *)(hwmgr->backend); + ps = cast_const_rv_ps(state); + + level_index = index > ps->level - 1 ? ps->level - 1 : index; + level->coreClock = ps->levels[level_index].engine_clock; + + if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { + for (i = 1; i < ps->level; i++) { + if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) { + level->coreClock = ps->levels[i].engine_clock; + break; + } + } + } + + if (level_index == 0) { + vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1; + level->memory_clock = + data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk; + } else + level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; + + level->nonLocalMemoryFreq = 0; + level->nonLocalMemoryWidth = 0; + + return 0; +} + +static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) +{ + const struct rv_power_state *ps = cast_const_rv_ps(state); + + clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); + clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); + + return 0; +} + +#define MEM_FREQ_LOW_LATENCY 25000 +#define MEM_FREQ_HIGH_LATENCY 80000 +#define MEM_LATENCY_HIGH 245 +#define MEM_LATENCY_LOW 35 +#define MEM_LATENCY_ERR 0xFFFF + + +static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr, + uint32_t clock) +{ + if (clock >= MEM_FREQ_LOW_LATENCY && + clock < MEM_FREQ_HIGH_LATENCY) + return MEM_LATENCY_HIGH; + else if (clock >= MEM_FREQ_HIGH_LATENCY) + return MEM_LATENCY_LOW; + else + return MEM_LATENCY_ERR; +} + +static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_latency *clocks) +{ + uint32_t i; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + struct rv_voltage_dependency_table *pclk_vol_table; + bool latency_required = false; + + if (pinfo == NULL) + return -EINVAL; + + switch (type) { + case amd_pp_mem_clock: + pclk_vol_table = pinfo->vdd_dep_on_mclk; + latency_required = true; + break; + case amd_pp_f_clock: + pclk_vol_table = pinfo->vdd_dep_on_fclk; + latency_required = true; + break; + case amd_pp_dcf_clock: + pclk_vol_table = pinfo->vdd_dep_on_dcefclk; + break; + case amd_pp_disp_clock: + pclk_vol_table = pinfo->vdd_dep_on_dispclk; + break; + case amd_pp_phy_clock: + pclk_vol_table = pinfo->vdd_dep_on_phyclk; + break; + case amd_pp_dpp_clock: + pclk_vol_table = pinfo->vdd_dep_on_dppclk; + default: + return -EINVAL; + } + + if (pclk_vol_table == NULL || pclk_vol_table->count == 0) + return -EINVAL; + + clocks->num_levels = 0; + for (i = 0; i < pclk_vol_table->count; i++) { + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk; + clocks->data[i].latency_in_us = latency_required ? + rv_get_mem_latency(hwmgr, + pclk_vol_table->entries[i].clk) : + 0; + clocks->num_levels++; + } + + return 0; +} + +static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_voltage *clocks) +{ + uint32_t i; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); + struct rv_voltage_dependency_table *pclk_vol_table = NULL; + + if (pinfo == NULL) + return -EINVAL; + + switch (type) { + case amd_pp_mem_clock: + pclk_vol_table = pinfo->vdd_dep_on_mclk; + break; + case amd_pp_f_clock: + pclk_vol_table = pinfo->vdd_dep_on_fclk; + break; + case amd_pp_dcf_clock: + pclk_vol_table = pinfo->vdd_dep_on_dcefclk; + break; + case amd_pp_soc_clock: + pclk_vol_table = pinfo->vdd_dep_on_socclk; + break; + default: + return -EINVAL; + } + + if (pclk_vol_table == NULL || pclk_vol_table->count == 0) + return -EINVAL; + + clocks->num_levels = 0; + for (i = 0; i < pclk_vol_table->count; i++) { + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk; + clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol; + clocks->num_levels++; + } + + return 0; +} + +int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, + struct pp_display_clock_request *clock_req) +{ + int result = 0; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + enum amd_pp_clock_type clk_type = clock_req->clock_type; + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; + PPSMC_Msg msg; + + switch (clk_type) { + case amd_pp_dcf_clock: + if (clk_freq == rv_data->dcf_actual_hard_min_freq) + return 0; + msg = PPSMC_MSG_SetHardMinDcefclkByFreq; + rv_data->dcf_actual_hard_min_freq = clk_freq; + break; + case amd_pp_soc_clock: + msg = PPSMC_MSG_SetHardMinSocclkByFreq; + break; + case amd_pp_f_clock: + if (clk_freq == rv_data->f_actual_hard_min_freq) + return 0; + rv_data->f_actual_hard_min_freq = clk_freq; + msg = PPSMC_MSG_SetHardMinFclkByFreq; + break; + default: + pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); + return -EINVAL; + } + + result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, + clk_freq); + + return result; +} + +static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) +{ + return -EINVAL; +} + +static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr) +{ + uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0, + mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP); + uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset); + int cur_temp = + (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; + + if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) + cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + else + cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return cur_temp; +} + +static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx, + void *value, int *size) +{ + switch (idx) { + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = rv_thermal_get_temperature(hwmgr); + return 0; + default: + return -EINVAL; + } +} + +static const struct pp_hwmgr_func rv_hwmgr_funcs = { + .backend_init = rv_hwmgr_backend_init, + .backend_fini = rv_hwmgr_backend_fini, + .asic_setup = NULL, + .apply_state_adjust_rules = rv_apply_state_adjust_rules, + .force_dpm_level = rv_dpm_force_dpm_level, + .get_power_state_size = rv_get_power_state_size, + .powerdown_uvd = NULL, + .powergate_uvd = NULL, + .powergate_vce = NULL, + .get_mclk = rv_dpm_get_mclk, + .get_sclk = rv_dpm_get_sclk, + .patch_boot_state = rv_dpm_patch_boot_state, + .get_pp_table_entry = rv_dpm_get_pp_table_entry, + .get_num_of_pp_table_entries = rv_dpm_get_num_of_pp_table_entries, + .set_cpu_power_state = rv_set_cpu_power_state, + .store_cc6_data = rv_store_cc6_data, + .force_clock_level = rv_force_clock_level, + .print_clock_levels = rv_print_clock_levels, + .get_dal_power_level = rv_get_dal_power_level, + .get_performance_level = rv_get_performance_level, + .get_current_shallow_sleep_clocks = rv_get_current_shallow_sleep_clocks, + .get_clock_by_type_with_latency = rv_get_clock_by_type_with_latency, + .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage, + .get_max_high_clocks = rv_get_max_high_clocks, + .read_sensor = rv_read_sensor, +}; + +int rv_init_function_pointers(struct pp_hwmgr *hwmgr) +{ + hwmgr->hwmgr_func = &rv_hwmgr_funcs; + hwmgr->pptable_func = &pptable_funcs; + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h new file mode 100644 index 000000000000..afb852295a15 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h @@ -0,0 +1,301 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_HWMGR_H +#define RAVEN_HWMGR_H + +#include "hwmgr.h" +#include "rv_inc.h" +#include "smu10_driver_if.h" +#include "rv_ppsmc.h" + + +#define RAVEN_MAX_HARDWARE_POWERLEVELS 8 +#define PHMRAVEN_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15 + +#define DPMFlags_SCLK_Enabled 0x00000001 +#define DPMFlags_UVD_Enabled 0x00000002 +#define DPMFlags_VCE_Enabled 0x00000004 +#define DPMFlags_ACP_Enabled 0x00000008 +#define DPMFlags_ForceHighestValid 0x40000000 + +/* Do not change the following, it is also defined in SMU8.h */ +#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 +#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 +#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000 +#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000 + +#define SMU_PHYID_SHIFT 8 + +#define RAVEN_PCIE_POWERGATING_TARGET_GFX 0 +#define RAVEN_PCIE_POWERGATING_TARGET_DDI 1 +#define RAVEN_PCIE_POWERGATING_TARGET_PLLCASCADE 2 +#define RAVEN_PCIE_POWERGATING_TARGET_PHY 3 + +enum VQ_TYPE { + CLOCK_TYPE_DCLK = 0L, + CLOCK_TYPE_ECLK, + CLOCK_TYPE_SCLK, + CLOCK_TYPE_CCLK, + VQ_GFX_CU +}; + +#define SUSTAINABLE_SCLK_MASK 0x00ffffff +#define SUSTAINABLE_SCLK_SHIFT 0 +#define SUSTAINABLE_CU_MASK 0xff000000 +#define SUSTAINABLE_CU_SHIFT 24 + +struct rv_dpm_entry { + uint32_t soft_min_clk; + uint32_t hard_min_clk; + uint32_t soft_max_clk; + uint32_t hard_max_clk; +}; + +struct rv_power_level { + uint32_t engine_clock; + uint8_t vddc_index; + uint8_t ds_divider_index; + uint8_t ss_divider_index; + uint8_t allow_gnb_slow; + uint8_t force_nbp_state; + uint8_t display_wm; + uint8_t vce_wm; + uint8_t num_simd_to_powerdown; + uint8_t hysteresis_up; + uint8_t rsv[3]; +}; + +/*used for the nbpsFlags field in rv_power state*/ +#define RAVEN_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0) +#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1) +#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2) + +#define RAVEN_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0) + +struct rv_uvd_clocks { + uint32_t vclk; + uint32_t dclk; + uint32_t vclk_low_divider; + uint32_t vclk_high_divider; + uint32_t dclk_low_divider; + uint32_t dclk_high_divider; +}; + +struct pp_disable_nbpslo_flags { + union { + struct { + uint32_t entry : 1; + uint32_t display : 1; + uint32_t driver: 1; + uint32_t vce : 1; + uint32_t uvd : 1; + uint32_t acp : 1; + uint32_t reserved: 26; + } bits; + uint32_t u32All; + }; +}; + + +enum rv_pstate_previous_action { + DO_NOTHING = 1, + FORCE_HIGH, + CANCEL_FORCE_HIGH +}; + +struct rv_power_state { + unsigned int magic; + uint32_t level; + struct rv_uvd_clocks uvd_clocks; + uint32_t evclk; + uint32_t ecclk; + uint32_t samclk; + uint32_t acpclk; + bool need_dfs_bypass; + + uint32_t nbps_flags; + uint32_t bapm_flags; + uint8_t dpm0_pg_nbps_low; + uint8_t dpm0_pg_nbps_high; + uint8_t dpm_x_nbps_low; + uint8_t dpm_x_nbps_high; + + enum rv_pstate_previous_action action; + + struct rv_power_level levels[RAVEN_MAX_HARDWARE_POWERLEVELS]; + struct pp_disable_nbpslo_flags nbpslo_flags; +}; + +#define RAVEN_NUM_NBPSTATES 4 +#define RAVEN_NUM_NBPMEMORYCLOCK 2 + + +struct rv_display_phy_info_entry { + uint8_t phy_present; + uint8_t active_lane_mapping; + uint8_t display_config_type; + uint8_t active_num_of_lanes; +}; + +#define RAVEN_MAX_DISPLAYPHY_IDS 10 + +struct rv_display_phy_info { + bool display_phy_access_initialized; + struct rv_display_phy_info_entry entries[RAVEN_MAX_DISPLAYPHY_IDS]; +}; + +#define MAX_DISPLAY_CLOCK_LEVEL 8 + +struct rv_system_info{ + uint8_t htc_tmp_lmt; + uint8_t htc_hyst_lmt; +}; + +#define MAX_REGULAR_DPM_NUMBER 8 + +struct rv_mclk_latency_entries { + uint32_t frequency; + uint32_t latency; +}; + +struct rv_mclk_latency_table { + uint32_t count; + struct rv_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; +}; + +struct rv_clock_voltage_dependency_record { + uint32_t clk; + uint32_t vol; +}; + + +struct rv_voltage_dependency_table { + uint32_t count; + struct rv_clock_voltage_dependency_record entries[1]; +}; + +struct rv_clock_voltage_information { + struct rv_voltage_dependency_table *vdd_dep_on_dcefclk; + struct rv_voltage_dependency_table *vdd_dep_on_socclk; + struct rv_voltage_dependency_table *vdd_dep_on_fclk; + struct rv_voltage_dependency_table *vdd_dep_on_mclk; + struct rv_voltage_dependency_table *vdd_dep_on_dispclk; + struct rv_voltage_dependency_table *vdd_dep_on_dppclk; + struct rv_voltage_dependency_table *vdd_dep_on_phyclk; +}; + +struct rv_hwmgr { + uint32_t disable_driver_thermal_policy; + uint32_t thermal_auto_throttling_treshold; + struct rv_system_info sys_info; + struct rv_mclk_latency_table mclk_latency_table; + + uint32_t ddi_power_gating_disabled; + + struct rv_display_phy_info_entry display_phy_info; + uint32_t dce_slow_sclk_threshold; + + bool disp_clk_bypass; + bool disp_clk_bypass_pending; + uint32_t bapm_enabled; + + bool video_start; + bool battery_state; + + uint32_t is_nb_dpm_enabled; + uint32_t is_voltage_island_enabled; + uint32_t disable_smu_acp_s3_handshake; + uint32_t disable_notify_smu_vpu_recovery; + bool in_vpu_recovery; + bool pg_acp_init; + uint8_t disp_config; + + /* PowerTune */ + uint32_t power_containment_features; + bool cac_enabled; + bool disable_uvd_power_tune_feature; + bool enable_bapm_feature; + bool enable_tdc_limit_feature; + + + /* SMC SRAM Address of firmware header tables */ + uint32_t sram_end; + uint32_t dpm_table_start; + uint32_t soft_regs_start; + + /* start of SMU7_Fusion_DpmTable */ + + uint8_t uvd_level_count; + uint8_t vce_level_count; + uint8_t acp_level_count; + uint8_t samu_level_count; + + uint32_t fps_high_threshold; + uint32_t fps_low_threshold; + + uint32_t dpm_flags; + struct rv_dpm_entry sclk_dpm; + struct rv_dpm_entry uvd_dpm; + struct rv_dpm_entry vce_dpm; + struct rv_dpm_entry acp_dpm; + bool acp_power_up_no_dsp; + + uint32_t max_sclk_level; + uint32_t num_of_clk_entries; + + /* CPU Power State */ + uint32_t separation_time; + bool cc6_disable; + bool pstate_disable; + bool cc6_setting_changed; + + uint32_t ulTotalActiveCUs; + + bool isp_tileA_power_gated; + bool isp_tileB_power_gated; + uint32_t isp_actual_hard_min_freq; + uint32_t soc_actual_hard_min_freq; + uint32_t dcf_actual_hard_min_freq; + + uint32_t f_actual_hard_min_freq; + uint32_t fabric_actual_soft_min_freq; + uint32_t gfx_actual_soft_min_freq; + + bool vcn_power_gated; + bool vcn_dpg_mode; + + bool gfx_off_controled_by_driver; + Watermarks_t water_marks_table; + struct rv_clock_voltage_information clock_vol_info; + DpmClocks_t clock_table; + + uint32_t active_process_mask; + bool need_min_deep_sleep_dcefclk; /* disabled by default */ +}; + +struct pp_hwmgr; + +int rv_init_function_pointers(struct pp_hwmgr *hwmgr); + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h new file mode 100644 index 000000000000..9a0149370d26 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -0,0 +1,43 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_INC_H +#define RAVEN_INC_H + + +#include "asic_reg/raven1/MP/mp_10_0_default.h" +#include "asic_reg/raven1/MP/mp_10_0_offset.h" +#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h" + +#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" +#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" + +#include "asic_reg/raven1/THM/thm_10_0_default.h" +#include "asic_reg/raven1/THM/thm_10_0_offset.h" +#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" + + +#define ixDDI_PHY_GEN_STATUS 0x3FCE8 + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 102eb6d029fa..1f01020ce3a9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -21,11 +21,11 @@ * */ #include "pp_debug.h" +#include <linux/delay.h> +#include <linux/fb.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/fb.h> #include <asm/div64.h> -#include "linux/delay.h" #include "pp_acpi.h" #include "ppatomctrl.h" #include "atombios.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 2614af2f553f..d6f097f44b6c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -20,10 +20,11 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ + +#include <linux/delay.h> +#include <linux/fb.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/fb.h> -#include "linux/delay.h" #include "hwmgr.h" #include "amd_powerplay.h" @@ -47,7 +48,7 @@ #include "amd_pcie_helpers.h" #include "cgs_linux.h" #include "ppinterrupt.h" - +#include "pp_overdriver.h" #define VOLTAGE_SCALE 4 #define VOLTAGE_VID_OFFSET_SCALE1 625 @@ -124,7 +125,13 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) } data->registry_data.clock_stretcher_support = - hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? false : true; + hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; + + data->registry_data.ulv_support = + hwmgr->feature_mask & PP_ULV_MASK ? true : false; + + data->registry_data.sclk_deep_sleep_support = + hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; data->registry_data.disable_water_mark = 0; @@ -349,6 +356,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->smu_features[GNLD_DS_GFXCLK].supported = true; data->smu_features[GNLD_DS_SOCCLK].supported = true; data->smu_features[GNLD_DS_LCLK].supported = true; + data->smu_features[GNLD_DS_DCEFCLK].supported = true; } if (data->registry_data.enable_pkg_pwr_tracking_feature) @@ -1161,7 +1169,7 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) "Incorrect number of PCIE States from VBIOS!", return -1); - for (i = 0; i < NUM_LINK_LEVELS - 1; i++) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { if (data->registry_data.pcieSpeedOverride) pcie_table->pcie_gen[i] = data->registry_data.pcieSpeedOverride; @@ -1170,12 +1178,11 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) bios_pcie_table->entries[i].gen_speed; if (data->registry_data.pcieLaneOverride) - pcie_table->pcie_lane[i] = - data->registry_data.pcieLaneOverride; + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + data->registry_data.pcieLaneOverride); else - pcie_table->pcie_lane[i] = - bios_pcie_table->entries[i].lane_width; - + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + bios_pcie_table->entries[i].lane_width); if (data->registry_data.pcieClockOverride) pcie_table->lclk[i] = data->registry_data.pcieClockOverride; @@ -1506,7 +1513,9 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; + uint32_t gfx_max_clock = + hwmgr->platform_descriptor.overdriveLimit.engineClock; + uint32_t i = 0; if (data->apply_overdrive_next_settings_mask & DPMTABLE_OD_UPDATE_VDDC) @@ -1517,14 +1526,18 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, "Invalid SOC_VDD-GFX_CLK Dependency Table!", return -EINVAL); - for (i = 0; i < dep_on_sclk->count; i++) { - if (dep_on_sclk->entries[i].clk == gfx_clock) - break; + if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) + gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; + else { + for (i = 0; i < dep_on_sclk->count; i++) { + if (dep_on_sclk->entries[i].clk == gfx_clock) + break; + } + PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, + "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", + return -EINVAL); } - PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, - "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", - return -EINVAL); PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, gfx_clock, ÷rs), @@ -1535,11 +1548,7 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, current_gfxclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EngineSpreadSpectrumSupport)) - current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; - else - current_gfxclk_level->SsOn = 0; + current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; current_gfxclk_level->SsFbMult = cpu_to_le32(dividers.ulPll_ss_fbsmult); current_gfxclk_level->SsSlewFrac = @@ -1692,7 +1701,9 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk = table_info->vdd_dep_on_mclk; struct pp_atomfwctrl_clock_dividers_soc15 dividers; - uint32_t i; + uint32_t mem_max_clock = + hwmgr->platform_descriptor.overdriveLimit.memoryClock; + uint32_t i = 0; if (data->apply_overdrive_next_settings_mask & DPMTABLE_OD_UPDATE_VDDC) @@ -1703,15 +1714,18 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, "Invalid SOC_VDD-UCLK Dependency Table!", return -EINVAL); - for (i = 0; i < dep_on_mclk->count; i++) { - if (dep_on_mclk->entries[i].clk == mem_clock) - break; + if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) + mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; + else { + for (i = 0; i < dep_on_mclk->count; i++) { + if (dep_on_mclk->entries[i].clk == mem_clock) + break; + } + PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, + "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", + return -EINVAL); } - PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, - "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", - return -EINVAL); - PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), "Failed to get UCLK settings from VBIOS!", @@ -2095,7 +2109,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) pp_table->AvfsGbCksOn.m1 = cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); pp_table->AvfsGbCksOn.m2 = - cpu_to_le16(avfs_params.ulGbFuseTableCksonM2); + cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); pp_table->AvfsGbCksOn.b = cpu_to_le32(avfs_params.ulGbFuseTableCksonB); pp_table->AvfsGbCksOn.m1_shift = 24; @@ -2107,7 +2121,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) pp_table->AvfsGbCksOff.m1 = cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); pp_table->AvfsGbCksOff.m2 = - cpu_to_le16(avfs_params.ulGbFuseTableCksoffM2); + cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); pp_table->AvfsGbCksOff.b = cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); pp_table->AvfsGbCksOff.m1_shift = 24; @@ -2286,6 +2300,73 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) return 0; } +static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) +{ + int result = 0; + + uint64_t serial_number = 0; + uint32_t top32, bottom32; + struct phm_fuses_default fuse; + + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32); + vega10_read_arg_from_smc(hwmgr->smumgr, &top32); + + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32); + vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32); + + serial_number = ((uint64_t)bottom32 << 32) | top32; + + if (pp_override_get_default_fuse_value(serial_number, vega10_fuses_default, &fuse) == 0) { + avfs_fuse_table->VFT0_b = fuse.VFT0_b; + avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; + avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; + avfs_fuse_table->VFT1_b = fuse.VFT1_b; + avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; + avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; + avfs_fuse_table->VFT2_b = fuse.VFT2_b; + avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; + avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; + result = vega10_copy_table_to_smc(hwmgr->smumgr, + (uint8_t *)avfs_fuse_table, AVFSFUSETABLE); + PP_ASSERT_WITH_CODE(!result, + "Failed to upload FuseOVerride!", + ); + } + + return result; +} + +static int vega10_save_default_power_profile(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); + uint32_t min_level; + + hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; + hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; + + /* Optimize compute power profile: Use only highest + * 2 power levels (if more than 2 are available) + */ + if (dpm_table->count > 2) + min_level = dpm_table->count - 2; + else if (dpm_table->count == 2) + min_level = 1; + else + min_level = 0; + + hwmgr->default_compute_power_profile.min_sclk = + dpm_table->dpm_levels[min_level].value; + + hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; + hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; + + return 0; +} + /** * Initializes the SMC table and uploads it * @@ -2382,6 +2463,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; + data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; if (0 != boot_up_values.usVddc) { smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFloorSocVoltage, @@ -2390,6 +2472,9 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) } else { data->vbios_boot_state.bsoc_vddc_lock = false; } + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); } result = vega10_populate_avfs_parameters(hwmgr); @@ -2411,6 +2496,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) pp_table->GfxActivityAverageAlpha = (uint8_t) (data->gfx_activity_average_alpha); + vega10_populate_and_upload_avfs_fuse_override(hwmgr); + result = vega10_copy_table_to_smc(hwmgr->smumgr, (uint8_t *)pp_table, PPTABLE); PP_ASSERT_WITH_CODE(!result, @@ -2420,6 +2507,8 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", return result); + vega10_save_default_power_profile(hwmgr); + return 0; } @@ -2509,6 +2598,22 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) return 0; } +static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + + if (data->registry_data.ulv_support) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_ULV].smu_feature_bitmap), + "disable ULV Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_ULV].enabled = false; + } + + return 0; +} + static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = @@ -2518,26 +2623,74 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + return -EINVAL); data->smu_features[GNLD_DS_GFXCLK].enabled = true; } if (data->smu_features[GNLD_DS_SOCCLK].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + "Attempt to Enable DS_SOCCLK Feature Failed!", + return -EINVAL); data->smu_features[GNLD_DS_SOCCLK].enabled = true; } if (data->smu_features[GNLD_DS_LCLK].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), - "Attempt to Enable DS_GFXCLK Feature Failed!", - return -1); + "Attempt to Enable DS_LCLK Feature Failed!", + return -EINVAL); data->smu_features[GNLD_DS_LCLK].enabled = true; } + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), + "Attempt to Enable DS_DCEFCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_DCEFCLK].enabled = true; + } + + return 0; +} + +static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + + if (data->smu_features[GNLD_DS_GFXCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), + "Attempt to disable DS_GFXCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_GFXCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_SOCCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), + "Attempt to disable DS_ Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_SOCCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_LCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), + "Attempt to disable DS_LCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_LCLK].enabled = false; + } + + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), + "Attempt to disable DS_DCEFCLK Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_DS_DCEFCLK].enabled = false; + } + return 0; } @@ -2550,9 +2703,9 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, - true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), - "Attempt to Enable LED DPM feature Failed!", return -EINVAL); - data->smu_features[GNLD_LED_DISPLAY].enabled = true; + false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), + "Attempt to disable LED DPM feature failed!", return -EINVAL); + data->smu_features[GNLD_LED_DISPLAY].enabled = false; } for (i = 0; i < GNLD_DPM_MAX; i++) { @@ -2676,11 +2829,6 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to enable VR hot feature!", result = tmp_result); - tmp_result = vega10_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable ULV!", - result = tmp_result); - tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to enable deep sleep master switch!", @@ -2700,6 +2848,11 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to power control set level!", result = tmp_result); + tmp_result = vega10_enable_ulv(hwmgr); + PP_ASSERT_WITH_CODE(!tmp_result, + "Failed to enable ULV!", + result = tmp_result); + return result; } @@ -2712,6 +2865,7 @@ static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, void *state, struct pp_power_state *power_state, void *pp_table, uint32_t classification_flag) { + ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; struct vega10_power_state *vega10_power_state = cast_phw_vega10_power_state(&(power_state->hardware)); struct vega10_performance_level *performance_level; @@ -2788,11 +2942,16 @@ static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, performance_level = &(vega10_power_state->performance_levels [vega10_power_state->performance_level_count++]); - performance_level->soc_clock = socclk_dep_table->entries - [state_entry->ucSocClockIndexHigh].ulClk; - performance_level->gfx_clock = gfxclk_dep_table->entries + [state_entry->ucSocClockIndexHigh].ulClk; + if (gfxclk_dep_table->ucRevId == 0) { + performance_level->gfx_clock = gfxclk_dep_table->entries [state_entry->ucGfxClockIndexHigh].ulClk; + } else if (gfxclk_dep_table->ucRevId == 1) { + patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; + performance_level->gfx_clock = patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; + } + performance_level->mem_clock = mclk_dep_table->entries [state_entry->ucMemClockIndexHigh].ulMemClk; return 0; @@ -2886,7 +3045,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; - /* minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; */ + minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { @@ -2978,11 +3137,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, vega10_ps->performance_levels[0].gfx_clock = sclk; vega10_ps->performance_levels[0].mem_clock = mclk; - vega10_ps->performance_levels[1].gfx_clock = - (vega10_ps->performance_levels[1].gfx_clock >= - vega10_ps->performance_levels[0].gfx_clock) ? - vega10_ps->performance_levels[1].gfx_clock : - vega10_ps->performance_levels[0].gfx_clock; + if (vega10_ps->performance_levels[1].gfx_clock < + vega10_ps->performance_levels[0].gfx_clock) + vega10_ps->performance_levels[0].gfx_clock = + vega10_ps->performance_levels[1].gfx_clock; if (disable_mclk_switching) { /* Set Mclk the max of level 0 and level 1 */ @@ -3005,8 +3163,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, } else { if (vega10_ps->performance_levels[1].mem_clock < vega10_ps->performance_levels[0].mem_clock) - vega10_ps->performance_levels[1].mem_clock = - vega10_ps->performance_levels[0].mem_clock; + vega10_ps->performance_levels[0].mem_clock = + vega10_ps->performance_levels[1].mem_clock; } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -3197,7 +3355,6 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( dpm_table-> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1]. value = sclk; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -3320,7 +3477,6 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( return result); } } - return result; } @@ -3673,6 +3829,23 @@ static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) [vega10_ps->performance_level_count-1].mem_clock; } +static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, + struct pp_gpu_power *query) +{ + uint32_t value; + + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PPSMC_MSG_GetCurrPkgPwr), + "Failed to get current package power!", + return -EINVAL); + + vega10_read_arg_from_smc(hwmgr->smumgr, &value); + /* power value is an integer */ + query->average_gpu_power = value << 8; + + return 0; +} + static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { @@ -3718,6 +3891,14 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; *size = 4; break; + case AMDGPU_PP_SENSOR_GPU_POWER: + if (*size < sizeof(struct pp_gpu_power)) + ret = -EINVAL; + else { + *size = sizeof(struct pp_gpu_power); + ret = vega10_get_gpu_power(hwmgr, (struct pp_gpu_power *)value); + } + break; default: ret = -EINVAL; break; @@ -3738,7 +3919,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, { int result = 0; enum amd_pp_clock_type clk_type = clock_req->clock_type; - uint32_t clk_freq = clock_req->clock_freq_in_khz / 100; + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; DSPCLK_e clk_select = 0; uint32_t clk_request = 0; @@ -3771,6 +3952,26 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, return result; } +static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, + uint32_t frequency) +{ + uint8_t count; + uint8_t i; + + if (mclk_table == NULL || mclk_table->count == 0) + return 0; + + count = (uint8_t)(mclk_table->count); + + for(i = 0; i < count; i++) { + if(mclk_table->entries[i].clk >= frequency) + return i; + } + + return i-1; +} + static int vega10_notify_smc_display_config_after_ps_adjustment( struct pp_hwmgr *hwmgr) { @@ -3778,6 +3979,10 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( (struct vega10_hwmgr *)(hwmgr->backend); struct vega10_single_dpm_table *dpm_table = &data->dpm_table.dcef_table; + struct phm_ppt_v2_information *table_info = + (struct phm_ppt_v2_information *)hwmgr->pptable; + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; + uint32_t idx; uint32_t num_active_disps = 0; struct cgs_display_info info = {0}; struct PP_Clocks min_clocks = {0}; @@ -3797,6 +4002,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; + min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; for (i = 0; i < dpm_table->count; i++) { if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) @@ -3809,12 +4015,20 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, - min_clocks.dcefClockInSR), + min_clocks.dcefClockInSR /100), "Attempt to set divider for DCEFCLK Failed!",); - } else + } else { pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); - } else + } + } else { pr_info("Cannot find requested DCEFCLK!"); + } + + if (min_clocks.memoryClock != 0) { + idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); + data->dpm_table.mem_table.dpm_state.soft_min_level= idx; + } return 0; } @@ -4219,11 +4433,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, if (mask & (1 << i)) break; } - - for (i = 0; i < 32; i++) { - if (mask & (1 << i)) - break; - } data->smc_state_table.mem_boot_level = i; for (i = 31; i >= 0; i--) { @@ -4466,6 +4675,14 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((tmp_result == 0), "Failed to stop DPM!", result = tmp_result); + tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable deep sleep!", result = tmp_result); + + tmp_result = vega10_disable_ulv(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable ulv!", result = tmp_result); + return result; } @@ -4483,6 +4700,170 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) return result; } +static void vega10_find_min_clock_index(struct pp_hwmgr *hwmgr, + uint32_t *sclk_idx, uint32_t *mclk_idx, + uint32_t min_sclk, uint32_t min_mclk) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_dpm_table *dpm_table = &(data->dpm_table); + uint32_t i; + + for (i = 0; i < dpm_table->gfx_table.count; i++) { + if (dpm_table->gfx_table.dpm_levels[i].enabled && + dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { + *sclk_idx = i; + break; + } + } + + for (i = 0; i < dpm_table->mem_table.count; i++) { + if (dpm_table->mem_table.dpm_levels[i].enabled && + dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { + *mclk_idx = i; + break; + } + } +} + +static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + uint32_t sclk_idx = ~0, mclk_idx = ~0; + + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) + return -EINVAL; + + vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx, + request->min_sclk, request->min_mclk); + + if (sclk_idx != ~0) { + if (!data->registry_data.sclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + !smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinGfxclkByIndex, + sclk_idx), + "Failed to set soft min sclk index!", + return -EINVAL); + } + + if (mclk_idx != ~0) { + if (!data->registry_data.mclk_dpm_key_disabled) + PP_ASSERT_WITH_CODE( + !smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinUclkByIndex, + mclk_idx), + "Failed to set soft min mclk index!", + return -EINVAL); + } + + return 0; +} + +static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); + struct vega10_single_dpm_table *golden_sclk_table = + &(data->golden_dpm_table.gfx_table); + int value; + + value = (sclk_table->dpm_levels[sclk_table->count - 1].value - + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value) * + 100 / + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value; + + return value; +} + +static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *golden_sclk_table = + &(data->golden_dpm_table.gfx_table); + struct pp_power_state *ps; + struct vega10_power_state *vega10_ps; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + vega10_ps = cast_phw_vega10_power_state(&ps->hardware); + + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock = + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value * + value / 100 + + golden_sclk_table->dpm_levels + [golden_sclk_table->count - 1].value; + + if (vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock > + hwmgr->platform_descriptor.overdriveLimit.engineClock) + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].gfx_clock = + hwmgr->platform_descriptor.overdriveLimit.engineClock; + + return 0; +} + +static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); + struct vega10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mem_table); + int value; + + value = (mclk_table->dpm_levels + [mclk_table->count - 1].value - + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value; + + return value; +} + +static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + struct vega10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mem_table); + struct pp_power_state *ps; + struct vega10_power_state *vega10_ps; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + vega10_ps = cast_phw_vega10_power_state(&ps->hardware); + + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock = + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels + [golden_mclk_table->count - 1].value; + + if (vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock > + hwmgr->platform_descriptor.overdriveLimit.memoryClock) + vega10_ps->performance_levels + [vega10_ps->performance_level_count - 1].mem_clock = + hwmgr->platform_descriptor.overdriveLimit.memoryClock; + + return 0; +} static const struct pp_hwmgr_func vega10_hwmgr_funcs = { .backend_init = vega10_hwmgr_backend_init, @@ -4531,6 +4912,12 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { vega10_check_smc_update_required_for_display_configuration, .power_off_asic = vega10_power_off_asic, .disable_smc_firmware_ctf = vega10_thermal_disable_alert, + .set_power_profile_state = vega10_set_power_profile_state, + .get_sclk_od = vega10_get_sclk_od, + .set_sclk_od = vega10_set_sclk_od, + .get_mclk_od = vega10_get_mclk_od, + .set_mclk_od = vega10_set_mclk_od, + .avfs_control = vega10_avfs_enable, }; int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h index 1912e086c0cf..6e5c5b99593b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h @@ -185,6 +185,7 @@ struct vega10_vbios_boot_state { uint32_t gfx_clock; uint32_t mem_clock; uint32_t soc_clock; + uint32_t dcef_clock; }; #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 @@ -210,6 +211,7 @@ struct vega10_smc_state_table { PPTable_t pp_table; Watermarks_t water_marks_table; AvfsTable_t avfs_table; + AvfsFuseOverride_t avfs_fuse_override_table; }; struct vega10_mclk_latency_entries { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h index 6a907c93fd9c..b3e63003a789 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h @@ -144,6 +144,15 @@ typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record { USHORT usAVFSOffset; /* AVFS Voltage offset */ } ATOM_Vega10_GFXCLK_Dependency_Record; +typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record_V2 { + ULONG ulClk; + UCHAR ucVddInd; + USHORT usCKSVOffsetandDisable; + USHORT usAVFSOffset; + UCHAR ucACGEnable; + UCHAR ucReserved[3]; +} ATOM_Vega10_GFXCLK_Dependency_Record_V2; + typedef struct _ATOM_Vega10_MCLK_Dependency_Record { ULONG ulMemClk; /* Clock Frequency */ UCHAR ucVddInd; /* SOC_VDD index */ @@ -355,6 +364,37 @@ typedef struct _ATOM_Vega10_PowerTune_Table_V2 USHORT usTemperatureLimitTedge; } ATOM_Vega10_PowerTune_Table_V2; +typedef struct _ATOM_Vega10_PowerTune_Table_V3 +{ + UCHAR ucRevId; + USHORT usSocketPowerLimit; + USHORT usBatteryPowerLimit; + USHORT usSmallPowerLimit; + USHORT usTdcLimit; + USHORT usEdcLimit; + USHORT usSoftwareShutdownTemp; + USHORT usTemperatureLimitHotSpot; + USHORT usTemperatureLimitLiquid1; + USHORT usTemperatureLimitLiquid2; + USHORT usTemperatureLimitHBM; + USHORT usTemperatureLimitVrSoc; + USHORT usTemperatureLimitVrMem; + USHORT usTemperatureLimitPlx; + USHORT usLoadLineResistance; + UCHAR ucLiquid1_I2C_address; + UCHAR ucLiquid2_I2C_address; + UCHAR ucLiquid_I2C_Line; + UCHAR ucVr_I2C_address; + UCHAR ucVr_I2C_Line; + UCHAR ucPlx_I2C_address; + UCHAR ucPlx_I2C_Line; + USHORT usTemperatureLimitTedge; + USHORT usBoostStartTemperature; + USHORT usBoostStopTemperature; + ULONG ulBoostClock; + ULONG Reserved[2]; +} ATOM_Vega10_PowerTune_Table_V3; + typedef struct _ATOM_Vega10_Hard_Limit_Record { ULONG ulSOCCLKLimit; ULONG ulGFXCLKLimit; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c index 00e95511e19a..1623644ea49a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c @@ -54,6 +54,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) &size, &frev, &crev); hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ + hwmgr->soft_pp_table_size = size; } return table_address; @@ -210,10 +211,8 @@ static int init_thermal_controller( fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL; hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); - hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = le16_to_cpu(fan_table_v2->usFanOutputSensitivity); hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = @@ -366,6 +365,7 @@ static int get_tdp_table( uint8_t sda; const ATOM_Vega10_PowerTune_Table *power_tune_table; const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2; + const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3; table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); @@ -408,7 +408,7 @@ static int get_tdp_table( tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance); - } else { + } else if (table->ucRevId == 6) { power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table; tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit); tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit); @@ -454,6 +454,47 @@ static int get_tdp_table( hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table_v2->usLoadLineResistance); + } else { + power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table; + tdp_table->usMaximumPowerDeliveryLimit = power_tune_table_v3->usSocketPowerLimit; + tdp_table->usTDC = power_tune_table_v3->usTdcLimit; + tdp_table->usEDCLimit = power_tune_table_v3->usEdcLimit; + tdp_table->usSoftwareShutdownTemp = power_tune_table_v3->usSoftwareShutdownTemp; + tdp_table->usTemperatureLimitTedge = power_tune_table_v3->usTemperatureLimitTedge; + tdp_table->usTemperatureLimitHotspot = power_tune_table_v3->usTemperatureLimitHotSpot; + tdp_table->usTemperatureLimitLiquid1 = power_tune_table_v3->usTemperatureLimitLiquid1; + tdp_table->usTemperatureLimitLiquid2 = power_tune_table_v3->usTemperatureLimitLiquid2; + tdp_table->usTemperatureLimitHBM = power_tune_table_v3->usTemperatureLimitHBM; + tdp_table->usTemperatureLimitVrVddc = power_tune_table_v3->usTemperatureLimitVrSoc; + tdp_table->usTemperatureLimitVrMvdd = power_tune_table_v3->usTemperatureLimitVrMem; + tdp_table->usTemperatureLimitPlx = power_tune_table_v3->usTemperatureLimitPlx; + tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address; + tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address; + tdp_table->usBoostStartTemperature = power_tune_table_v3->usBoostStartTemperature; + tdp_table->usBoostStopTemperature = power_tune_table_v3->usBoostStopTemperature; + tdp_table->ulBoostClock = power_tune_table_v3->ulBoostClock; + + get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda); + + tdp_table->ucLiquid_I2C_Line = scl; + tdp_table->ucLiquid_I2C_LineSDA = sda; + + tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address; + + get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda); + + tdp_table->ucVr_I2C_Line = scl; + tdp_table->ucVr_I2C_LineSDA = sda; + + tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address; + + get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda); + + tdp_table->ucPlx_I2C_Line = scl; + tdp_table->ucPlx_I2C_LineSDA = sda; + + hwmgr->platform_descriptor.LoadLineSlope = + le16_to_cpu(power_tune_table_v3->usLoadLineResistance); } *info_tdp_table = tdp_table; @@ -544,6 +585,7 @@ static int get_gfxclk_voltage_dependency_table( uint32_t table_size, i; struct phm_ppt_v1_clock_voltage_dependency_table *clk_table; + ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2; PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), "Invalid PowerPlay Table!", return -1); @@ -560,18 +602,41 @@ static int get_gfxclk_voltage_dependency_table( clk_table->count = clk_dep_table->ucNumEntries; - for (i = 0; i < clk_table->count; i++) { - clk_table->entries[i].vddInd = + if (clk_dep_table->ucRevId == 0) { + for (i = 0; i < clk_table->count; i++) { + clk_table->entries[i].vddInd = clk_dep_table->entries[i].ucVddInd; - clk_table->entries[i].clk = + clk_table->entries[i].clk = le32_to_cpu(clk_dep_table->entries[i].ulClk); - clk_table->entries[i].cks_enable = - (((clk_dep_table->entries[i].usCKSVOffsetandDisable & 0x80) + clk_table->entries[i].cks_enable = + (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000) >> 15) == 0) ? 1 : 0; - clk_table->entries[i].cks_voffset = - (clk_dep_table->entries[i].usCKSVOffsetandDisable & 0x7F); - clk_table->entries[i].sclk_offset = - clk_dep_table->entries[i].usAVFSOffset; + clk_table->entries[i].cks_voffset = + le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F; + clk_table->entries[i].sclk_offset = + le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset); + } + } else if (clk_dep_table->ucRevId == 1) { + patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries; + for (i = 0; i < clk_table->count; i++) { + clk_table->entries[i].vddInd = + patom_record_v2->ucVddInd; + clk_table->entries[i].clk = + le32_to_cpu(patom_record_v2->ulClk); + clk_table->entries[i].cks_enable = + (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000) + >> 15) == 0) ? 1 : 0; + clk_table->entries[i].cks_voffset = + le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F; + clk_table->entries[i].sclk_offset = + le16_to_cpu(patom_record_v2->usAVFSOffset); + patom_record_v2++; + } + } else { + kfree(clk_table); + PP_ASSERT_WITH_CODE(false, + "Unsupported GFXClockDependencyTable Revision!", + return -EINVAL); } *pp_vega10_clk_dep_table = clk_table; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c index 83e40fe51b62..e7ab8eb8a0cf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c @@ -439,9 +439,6 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, cgs_write_register(hwmgr->device, reg, val); - reg = soc15_get_register_offset(THM_HWID, 0, - mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC); - return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 4e39f35bb745..07e9c0b5915d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -273,7 +273,10 @@ enum amd_pp_clock_type { amd_pp_dcef_clock, amd_pp_soc_clock, amd_pp_pixel_clock, - amd_pp_phy_clock + amd_pp_phy_clock, + amd_pp_dcf_clock, + amd_pp_dpp_clock, + amd_pp_f_clock = amd_pp_dcef_clock, }; #define MAX_NUM_CLOCKS 16 diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 805b9df452a3..47e57bd2c36f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -99,7 +99,8 @@ enum PHM_BackEnd_Magic { PHM_CIslands_Magic = 0x38AC78B0, PHM_Kv_Magic = 0xDCBBABC0, PHM_VIslands_Magic = 0x20130307, - PHM_Cz_Magic = 0x67DCBA25 + PHM_Cz_Magic = 0x67DCBA25, + PHM_Rv_Magic = 0x20161121 }; @@ -136,11 +137,14 @@ struct phm_vce_arbiter { struct phm_gfx_arbiter { uint32_t sclk; + uint32_t sclk_hard_min; uint32_t mclk; uint32_t sclk_over_drive; uint32_t mclk_over_drive; uint32_t sclk_threshold; uint32_t num_cus; + uint32_t gfxclk; + uint32_t fclk; }; /* Entries in the master tables */ @@ -488,6 +492,9 @@ struct phm_tdp_table { uint8_t ucVr_I2C_LineSDA; uint8_t ucPlx_I2C_LineSDA; uint32_t usBoostPowerLimit; + uint16_t usBoostStartTemperature; + uint16_t usBoostStopTemperature; + uint32_t ulBoostClock; }; struct phm_ppm_table { @@ -624,7 +631,7 @@ struct phm_dynamic_state_info { uint32_t vddc_vddci_delta; uint32_t min_vddc_for_pcie_gen2; struct phm_cac_leakage_table *cac_leakage_table; - struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; + struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; struct phm_vce_clock_voltage_dependency_table *vce_clock_voltage_dependency_table; @@ -637,8 +644,8 @@ struct phm_dynamic_state_info { struct phm_ppm_table *ppm_parameter_table; struct phm_cac_tdp_table *cac_dtp_table; - struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; - struct phm_vq_budgeting_table *vq_budgeting_table; + struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; + struct phm_vq_budgeting_table *vq_budgeting_table; }; struct pp_fan_info { @@ -822,6 +829,7 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); +extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr); extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t id, uint16_t *voltage); diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h new file mode 100644 index 000000000000..e0e106f1b23a --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h @@ -0,0 +1,77 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef RAVEN_PP_SMC_H +#define RAVEN_PP_SMC_H + +#pragma pack(push, 1) + +#define PPSMC_Result_OK 0x1 +#define PPSMC_Result_Failed 0xFF +#define PPSMC_Result_UnknownCmd 0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_PowerUpGfx 0x6 +#define PPSMC_MSG_EnableGfxOff 0x7 +#define PPSMC_MSG_DisableGfxOff 0x8 +#define PPSMC_MSG_PowerDownIspByTile 0x9 +#define PPSMC_MSG_PowerUpIspByTile 0xA +#define PPSMC_MSG_PowerDownVcn 0xB +#define PPSMC_MSG_PowerUpVcn 0xC +#define PPSMC_MSG_PowerDownSdma 0xD +#define PPSMC_MSG_PowerUpSdma 0xE +#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF +#define PPSMC_MSG_SetHardMinVcn 0x10 +#define PPSMC_MSG_SetMinDisplayClock 0x11 +#define PPSMC_MSG_SetHardMinFclkByFreq 0x12 +#define PPSMC_MSG_SetAllowFclkSwitch 0x13 +#define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14 +#define PPSMC_MSG_ActiveProcessNotify 0x15 +#define PPSMC_MSG_SetCustomPolicy 0x16 +#define PPSMC_MSG_SetVideoFps 0x17 +#define PPSMC_MSG_SetDisplayCount 0x18 +#define PPSMC_MSG_QueryPowerLimit 0x19 +#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A +#define PPSMC_MSG_SetDriverDramAddrLow 0x1B +#define PPSMC_MSG_TransferTableSmu2Dram 0x1C +#define PPSMC_MSG_TransferTableDram2Smu 0x1D +#define PPSMC_MSG_ControlGfxRM 0x1E +#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F +#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20 +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21 +#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22 +#define PPSMC_MSG_SetMinVideoFclkFreq 0x23 +#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x24 +#define PPSMC_Message_Count 0x25 + +typedef uint16_t PPSMC_Result; +typedef int PPSMC_Msg; + + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10.h b/drivers/gpu/drm/amd/powerplay/inc/smu10.h new file mode 100644 index 000000000000..9e837a5014c5 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu10.h @@ -0,0 +1,188 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU10_H +#define SMU10_H + +#pragma pack(push, 1) + +#define ENABLE_DEBUG_FEATURES + +/* Feature Control Defines */ +#define FEATURE_CCLK_CONTROLLER_BIT 0 +#define FEATURE_FAN_CONTROLLER_BIT 1 +#define FEATURE_DATA_CALCULATION_BIT 2 +#define FEATURE_PPT_BIT 3 +#define FEATURE_TDC_BIT 4 +#define FEATURE_THERMAL_BIT 5 +#define FEATURE_FIT_BIT 6 +#define FEATURE_EDC_BIT 7 +#define FEATURE_PLL_POWER_DOWN_BIT 8 +#define FEATURE_ULV_BIT 9 +#define FEATURE_VDDOFF_BIT 10 +#define FEATURE_VCN_DPM_BIT 11 +#define FEATURE_ACP_DPM_BIT 12 +#define FEATURE_ISP_DPM_BIT 13 +#define FEATURE_FCLK_DPM_BIT 14 +#define FEATURE_SOCCLK_DPM_BIT 15 +#define FEATURE_MP0CLK_DPM_BIT 16 +#define FEATURE_LCLK_DPM_BIT 17 +#define FEATURE_SHUBCLK_DPM_BIT 18 +#define FEATURE_DCEFCLK_DPM_BIT 19 +#define FEATURE_GFX_DPM_BIT 20 +#define FEATURE_DS_GFXCLK_BIT 21 +#define FEATURE_DS_SOCCLK_BIT 22 +#define FEATURE_DS_LCLK_BIT 23 +#define FEATURE_DS_DCEFCLK_BIT 24 +#define FEATURE_DS_SHUBCLK_BIT 25 +#define FEATURE_RM_BIT 26 +#define FEATURE_S0i2_BIT 27 +#define FEATURE_WHISPER_MODE_BIT 28 +#define FEATURE_DS_FCLK_BIT 29 +#define FEATURE_DS_SMNCLK_BIT 30 +#define FEATURE_DS_MP1CLK_BIT 31 +#define FEATURE_DS_MP0CLK_BIT 32 +#define FEATURE_MGCG_BIT 33 +#define FEATURE_DS_FUSE_SRAM_BIT 34 +#define FEATURE_GFX_CKS 35 +#define FEATURE_PSI0_BIT 36 +#define FEATURE_PROCHOT_BIT 37 +#define FEATURE_CPUOFF_BIT 38 +#define FEATURE_STAPM_BIT 39 +#define FEATURE_CORE_CSTATES_BIT 40 +#define FEATURE_SPARE_41_BIT 41 +#define FEATURE_SPARE_42_BIT 42 +#define FEATURE_SPARE_43_BIT 43 +#define FEATURE_SPARE_44_BIT 44 +#define FEATURE_SPARE_45_BIT 45 +#define FEATURE_SPARE_46_BIT 46 +#define FEATURE_SPARE_47_BIT 47 +#define FEATURE_SPARE_48_BIT 48 +#define FEATURE_SPARE_49_BIT 49 +#define FEATURE_SPARE_50_BIT 50 +#define FEATURE_SPARE_51_BIT 51 +#define FEATURE_SPARE_52_BIT 52 +#define FEATURE_SPARE_53_BIT 53 +#define FEATURE_SPARE_54_BIT 54 +#define FEATURE_SPARE_55_BIT 55 +#define FEATURE_SPARE_56_BIT 56 +#define FEATURE_SPARE_57_BIT 57 +#define FEATURE_SPARE_58_BIT 58 +#define FEATURE_SPARE_59_BIT 59 +#define FEATURE_SPARE_60_BIT 60 +#define FEATURE_SPARE_61_BIT 61 +#define FEATURE_SPARE_62_BIT 62 +#define FEATURE_SPARE_63_BIT 63 + +#define NUM_FEATURES 64 + +#define FEATURE_CCLK_CONTROLLER_MASK (1 << FEATURE_CCLK_CONTROLLER_BIT) +#define FEATURE_FAN_CONTROLLER_MASK (1 << FEATURE_FAN_CONTROLLER_BIT) +#define FEATURE_DATA_CALCULATION_MASK (1 << FEATURE_DATA_CALCULATION_BIT) +#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT) +#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT) +#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT) +#define FEATURE_FIT_MASK (1 << FEATURE_FIT_BIT) +#define FEATURE_EDC_MASK (1 << FEATURE_EDC_BIT) +#define FEATURE_PLL_POWER_DOWN_MASK (1 << FEATURE_PLL_POWER_DOWN_BIT) +#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT) +#define FEATURE_VDDOFF_MASK (1 << FEATURE_VDDOFF_BIT) +#define FEATURE_VCN_DPM_MASK (1 << FEATURE_VCN_DPM_BIT) +#define FEATURE_ACP_DPM_MASK (1 << FEATURE_ACP_DPM_BIT) +#define FEATURE_ISP_DPM_MASK (1 << FEATURE_ISP_DPM_BIT) +#define FEATURE_FCLK_DPM_MASK (1 << FEATURE_FCLK_DPM_BIT) +#define FEATURE_SOCCLK_DPM_MASK (1 << FEATURE_SOCCLK_DPM_BIT) +#define FEATURE_MP0CLK_DPM_MASK (1 << FEATURE_MP0CLK_DPM_BIT) +#define FEATURE_LCLK_DPM_MASK (1 << FEATURE_LCLK_DPM_BIT) +#define FEATURE_SHUBCLK_DPM_MASK (1 << FEATURE_SHUBCLK_DPM_BIT) +#define FEATURE_DCEFCLK_DPM_MASK (1 << FEATURE_DCEFCLK_DPM_BIT) +#define FEATURE_GFX_DPM_MASK (1 << FEATURE_GFX_DPM_BIT) +#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT) +#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT) +#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT) +#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT) +#define FEATURE_DS_SHUBCLK_MASK (1 << FEATURE_DS_SHUBCLK_BIT) +#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT) +#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT) +#define FEATURE_DS_SMNCLK_MASK (1 << FEATURE_DS_SMNCLK_BIT) +#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT) +#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT) +#define FEATURE_MGCG_MASK (1 << FEATURE_MGCG_BIT) +#define FEATURE_DS_FUSE_SRAM_MASK (1 << FEATURE_DS_FUSE_SRAM_BIT) +#define FEATURE_PSI0_MASK (1 << FEATURE_PSI0_BIT) +#define FEATURE_STAPM_MASK (1 << FEATURE_STAPM_BIT) +#define FEATURE_PROCHOT_MASK (1 << FEATURE_PROCHOT_BIT) +#define FEATURE_CPUOFF_MASK (1 << FEATURE_CPUOFF_BIT) +#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT) + +/* Workload bits */ +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 +#define WORKLOAD_PPLIB_VIDEO_BIT 2 +#define WORKLOAD_PPLIB_VR_BIT 3 +#define WORKLOAD_PPLIB_COMPUTE_BIT 4 +#define WORKLOAD_PPLIB_CUSTOM_BIT 5 +#define WORKLOAD_PPLIB_COUNT 6 + +typedef struct { + /* MP1_EXT_SCRATCH0 */ + uint32_t CurrLevel_ACP : 4; + uint32_t CurrLevel_ISP : 4; + uint32_t CurrLevel_VCN : 4; + uint32_t CurrLevel_LCLK : 4; + uint32_t CurrLevel_MP0CLK : 4; + uint32_t CurrLevel_FCLK : 4; + uint32_t CurrLevel_SOCCLK : 4; + uint32_t CurrLevel_DCEFCLK : 4; + /* MP1_EXT_SCRATCH1 */ + uint32_t TargLevel_ACP : 4; + uint32_t TargLevel_ISP : 4; + uint32_t TargLevel_VCN : 4; + uint32_t TargLevel_LCLK : 4; + uint32_t TargLevel_MP0CLK : 4; + uint32_t TargLevel_FCLK : 4; + uint32_t TargLevel_SOCCLK : 4; + uint32_t TargLevel_DCEFCLK : 4; + /* MP1_EXT_SCRATCH2 */ + uint32_t CurrLevel_SHUBCLK : 4; + uint32_t TargLevel_SHUBCLK : 4; + uint32_t InUlv : 1; + uint32_t InS0i2 : 1; + uint32_t InWhisperMode : 1; + uint32_t Reserved : 21; + /* MP1_EXT_SCRATCH3-4 */ + uint32_t Reserved2[2]; + /* MP1_EXT_SCRATCH5 */ + uint32_t FeatureStatus[NUM_FEATURES / 32]; +} FwStatus_t; + +#define TABLE_BIOS_IF 0 /* Called by BIOS */ +#define TABLE_WATERMARKS 1 /* Called by Driver */ +#define TABLE_CUSTOM_DPM 2 /* Called by Driver */ +#define TABLE_PMSTATUSLOG 3 /* Called by Tools for Agm logging */ +#define TABLE_DPMCLOCKS 4 /* Called by Driver */ +#define TABLE_MOMENTARY_PM 5 /* Called by Tools */ +#define TABLE_COUNT 6 + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h new file mode 100644 index 000000000000..dea8fe93da63 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h @@ -0,0 +1,116 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU10_DRIVER_IF_H +#define SMU10_DRIVER_IF_H + +#define SMU10_DRIVER_IF_VERSION 0x6 + +#define NUM_DSPCLK_LEVELS 8 + +typedef struct { + int32_t value; + uint32_t numFractionalBits; +} FloatInIntFormat_t; + +typedef enum { + DSPCLK_DCEFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; + uint16_t Vid; +} DisplayClockTable_t; + + +typedef struct { + uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ + uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t Padding[3]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + uint32_t MmHubPadding[7]; +} Watermarks_t; + +typedef enum { + CUSTOM_DPM_SETTING_GFXCLK, + CUSTOM_DPM_SETTING_CCLK, + CUSTOM_DPM_SETTING_FCLK_CCX, + CUSTOM_DPM_SETTING_FCLK_GFX, + CUSTOM_DPM_SETTING_FCLK_STALLS, + CUSTOM_DPM_SETTING_LCLK, + CUSTOM_DPM_SETTING_COUNT, +} CUSTOM_DPM_SETTING_e; + +typedef struct { + uint8_t ActiveHystLimit; + uint8_t IdleHystLimit; + uint8_t FPS; + uint8_t MinActiveFreqType; + FloatInIntFormat_t MinActiveFreq; + FloatInIntFormat_t PD_Data_limit; + FloatInIntFormat_t PD_Data_time_constant; + FloatInIntFormat_t PD_Data_error_coeff; + FloatInIntFormat_t PD_Data_error_rate_coeff; +} DpmActivityMonitorCoeffExt_t; + +typedef struct { + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; +} CustomDpmSettings_t; + +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_DCEFCLK_DPM_LEVELS 4 +#define NUM_FCLK_DPM_LEVELS 4 +#define NUM_MEMCLK_DPM_LEVELS 4 + +typedef struct { + uint32_t Freq; /* In MHz */ + uint32_t Vol; /* Millivolts with 2 fractional bits */ +} DpmClock_t; + +typedef struct { + DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS]; + DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS]; + DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS]; +} DpmClocks_t; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h index d43f98a910b0..532186b6f941 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h @@ -30,7 +30,7 @@ * SMU TEAM: Always increment the interface version if * any structure is changed in this file */ -#define SMU9_DRIVER_IF_VERSION 0xD +#define SMU9_DRIVER_IF_VERSION 0xE #define PPTABLE_V10_SMU_VERSION 1 @@ -380,25 +380,25 @@ typedef struct { uint8_t AvfsVersion; uint8_t Padding[2]; - uint32_t VFT0_m1; /* Q16.16 */ - uint32_t VFT0_m2; /* Q16.16 */ - uint32_t VFT0_b; /* Q16.16 */ + int32_t VFT0_m1; /* Q8.24 */ + int32_t VFT0_m2; /* Q12.12 */ + int32_t VFT0_b; /* Q32 */ - uint32_t VFT1_m1; /* Q16.16 */ - uint32_t VFT1_m2; /* Q16.16 */ - uint32_t VFT1_b; /* Q16.16 */ + int32_t VFT1_m1; /* Q8.16 */ + int32_t VFT1_m2; /* Q12.12 */ + int32_t VFT1_b; /* Q32 */ - uint32_t VFT2_m1; /* Q16.16 */ - uint32_t VFT2_m2; /* Q16.16 */ - uint32_t VFT2_b; /* Q16.16 */ + int32_t VFT2_m1; /* Q8.16 */ + int32_t VFT2_m2; /* Q12.12 */ + int32_t VFT2_b; /* Q32 */ - uint32_t AvfsGb0_m1; /* Q16.16 */ - uint32_t AvfsGb0_m2; /* Q16.16 */ - uint32_t AvfsGb0_b; /* Q16.16 */ + int32_t AvfsGb0_m1; /* Q8.16 */ + int32_t AvfsGb0_m2; /* Q12.12 */ + int32_t AvfsGb0_b; /* Q32 */ - uint32_t AcBtcGb_m1; /* Q16.16 */ - uint32_t AcBtcGb_m2; /* Q16.16 */ - uint32_t AcBtcGb_b; /* Q16.16 */ + int32_t AcBtcGb_m1; /* Q8.24 */ + int32_t AcBtcGb_m2; /* Q12.12 */ + int32_t AcBtcGb_b; /* Q32 */ uint32_t AvfsTempCold; uint32_t AvfsTempMid; @@ -406,9 +406,9 @@ typedef struct { uint32_t InversionVoltage; /* in mV with 2 fractional bits */ - uint32_t P2V_m1; /* Q16.16 */ - uint32_t P2V_m2; /* Q16.16 */ - uint32_t P2V_b; /* Q16.16 */ + int32_t P2V_m1; /* Q8.24 */ + int32_t P2V_m2; /* Q12.12 */ + int32_t P2V_b; /* Q32 */ uint32_t P2VCharzFreq; /* in 10KHz units */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h index 37f41217b8a0..976e942ec694 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h @@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs; extern const struct pp_smumgr_func fiji_smu_funcs; extern const struct pp_smumgr_func polaris10_smu_funcs; extern const struct pp_smumgr_func vega10_smu_funcs; +extern const struct pp_smumgr_func rv_smu_funcs; enum AVFS_BTC_STATUS { AVFS_BTC_BOOT = 0, diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h index 254974d3d371..b4af9e85dfa5 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h @@ -124,7 +124,8 @@ typedef uint16_t PPSMC_Result; #define PPSMC_MSG_NumOfDisplays 0x56 #define PPSMC_MSG_ReadSerialNumTop32 0x58 #define PPSMC_MSG_ReadSerialNumBottom32 0x59 -#define PPSMC_Message_Count 0x5A +#define PPSMC_MSG_GetCurrPkgPwr 0x61 +#define PPSMC_Message_Count 0x62 typedef int PPSMC_Msg; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 68b01b594e11..1703bbefbfd5 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -4,7 +4,7 @@ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \ polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \ - smu7_smumgr.o iceland_smc.o vega10_smumgr.o + smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c index 1f6744a443d4..652aaa43e95c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c @@ -20,11 +20,13 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include <linux/types.h> + +#include <linux/delay.h> +#include <linux/gfp.h> #include <linux/kernel.h> #include <linux/slab.h> -#include <linux/gfp.h> -#include "linux/delay.h" +#include <linux/types.h> + #include "cgs_common.h" #include "smu/smu_8_0_d.h" #include "smu/smu_8_0_sh_mask.h" @@ -70,7 +72,7 @@ static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr, result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); if (result != 0) { - pr_err("cz_send_msg_to_smc_async failed\n"); + pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg); return result; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c new file mode 100644 index 000000000000..ce0a30388ea1 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c @@ -0,0 +1,398 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "smumgr.h" +#include "rv_inc.h" +#include "pp_soc15.h" +#include "rv_smumgr.h" +#include "ppatomctrl.h" +#include "rv_ppsmc.h" +#include "smu10_driver_if.h" +#include "smu10.h" +#include "ppatomctrl.h" +#include "pp_debug.h" +#include "smu_ucode_xfer_vi.h" +#include "smu7_smumgr.h" + +#define VOLTAGE_SCALE 4 + +#define BUFFER_SIZE 80000 +#define MAX_STRING_SIZE 15 +#define BUFFER_SIZETWO 131072 + +#define MP0_Public 0x03800000 +#define MP0_SRAM 0x03900000 +#define MP1_Public 0x03b00000 +#define MP1_SRAM 0x03c00004 + +#define smnMP1_FIRMWARE_FLAGS 0x3010028 + + +bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) +{ + uint32_t mp1_fw_flags, reg; + + reg = soc15_get_register_offset(NBIF_HWID, 0, + mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); + + cgs_write_register(smumgr->device, reg, + (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); + + reg = soc15_get_register_offset(NBIF_HWID, 0, + mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); + + mp1_fw_flags = cgs_read_register(smumgr->device, reg); + + if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) + return true; + + return false; +} + +static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr) +{ + uint32_t reg; + + if (!rv_is_smc_ram_running(smumgr)) + return -EINVAL; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + + smum_wait_for_register_unequal(smumgr, reg, + 0, MP1_C2PMSG_90__CONTENT_MASK); + + return cgs_read_register(smumgr->device, reg); +} + +int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, + uint16_t msg) +{ + uint32_t reg; + + if (!rv_is_smc_ram_running(smumgr)) + return -EINVAL; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); + cgs_write_register(smumgr->device, reg, msg); + + return 0; +} + +int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) +{ + uint32_t reg; + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); + + *arg = cgs_read_register(smumgr->device, reg); + + return 0; +} + +int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +{ + uint32_t reg; + + rv_wait_for_response(smumgr); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + cgs_write_register(smumgr->device, reg, 0); + + rv_send_msg_to_smc_without_waiting(smumgr, msg); + + if (rv_wait_for_response(smumgr) == 0) + printk("Failed to send Message %x.\n", msg); + + return 0; +} + + +int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, + uint16_t msg, uint32_t parameter) +{ + uint32_t reg; + + rv_wait_for_response(smumgr); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); + cgs_write_register(smumgr->device, reg, 0); + + reg = soc15_get_register_offset(MP1_HWID, 0, + mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); + cgs_write_register(smumgr->device, reg, parameter); + + rv_send_msg_to_smc_without_waiting(smumgr, msg); + + + if (rv_wait_for_response(smumgr) == 0) + printk("Failed to send Message %x.\n", msg); + + return 0; +} + +int rv_copy_table_from_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, + "Invalid SMU Table version!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrHigh, + priv->smu_tables.entry[table_id].table_addr_high) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrLow, + priv->smu_tables.entry[table_id].table_addr_low) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_TransferTableSmu2Dram, + priv->smu_tables.entry[table_id].table_id) == 0, + "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", + return -EINVAL;); + + memcpy(table, priv->smu_tables.entry[table_id].table, + priv->smu_tables.entry[table_id].size); + + return 0; +} + +int rv_copy_table_to_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, + "Invalid SMU Table ID!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, + "Invalid SMU Table version!", return -EINVAL;); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL;); + + memcpy(priv->smu_tables.entry[table_id].table, table, + priv->smu_tables.entry[table_id].size); + + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrHigh, + priv->smu_tables.entry[table_id].table_addr_high) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SetDriverDramAddrLow, + priv->smu_tables.entry[table_id].table_addr_low) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL;); + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_TransferTableDram2Smu, + priv->smu_tables.entry[table_id].table_id) == 0, + "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", + return -EINVAL;); + + return 0; +} + +static int rv_verify_smc_interface(struct pp_smumgr *smumgr) +{ + uint32_t smc_driver_if_version; + + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_GetDriverIfVersion), + "Attempt to get SMC IF Version Number Failed!", + return -EINVAL); + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr, + &smc_driver_if_version), + "Attempt to read SMC IF Version Number Failed!", + return -EINVAL); + + if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) + return -EINVAL; + + return 0; +} + +/* sdma is disabled by default in vbios, need to re-enable in driver */ +static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_PowerUpSdma), + "Attempt to power up sdma Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PPSMC_MSG_PowerDownSdma), + "Attempt to power down sdma Failed!", + return -EINVAL); + + return 0; +} + +/* vcn is disabled by default in vbios, need to re-enable in driver */ +static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_PowerUpVcn, 0), + "Attempt to power up vcn Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) +{ + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_PowerDownVcn, 0), + "Attempt to power down vcn Failed!", + return -EINVAL); + + return 0; +} + +static int rv_smu_fini(struct pp_smumgr *smumgr) +{ + struct rv_smumgr *priv = + (struct rv_smumgr *)(smumgr->backend); + + if (priv) { + rv_smc_disable_sdma(smumgr); + rv_smc_disable_vcn(smumgr); + cgs_free_gpu_mem(smumgr->device, + priv->smu_tables.entry[WMTABLE].handle); + cgs_free_gpu_mem(smumgr->device, + priv->smu_tables.entry[CLOCKTABLE].handle); + kfree(smumgr->backend); + smumgr->backend = NULL; + } + + return 0; +} + +static int rv_start_smu(struct pp_smumgr *smumgr) +{ + if (rv_verify_smc_interface(smumgr)) + return -EINVAL; + if (rv_smc_enable_sdma(smumgr)) + return -EINVAL; + if (rv_smc_enable_vcn(smumgr)) + return -EINVAL; + + return 0; +} + +static int rv_smu_init(struct pp_smumgr *smumgr) +{ + struct rv_smumgr *priv; + uint64_t mc_addr; + void *kaddr = NULL; + unsigned long handle; + + priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + smumgr->backend = priv; + + /* allocate space for watermarks table */ + smu_allocate_memory(smumgr->device, + sizeof(Watermarks_t), + CGS_GPU_MEM_TYPE__GART_CACHEABLE, + PAGE_SIZE, + &mc_addr, + &kaddr, + &handle); + + PP_ASSERT_WITH_CODE(kaddr, + "[rv_smu_init] Out of memory for wmtable.", + kfree(smumgr->backend); + smumgr->backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[WMTABLE].version = 0x01; + priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t); + priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS; + priv->smu_tables.entry[WMTABLE].table_addr_high = + smu_upper_32_bits(mc_addr); + priv->smu_tables.entry[WMTABLE].table_addr_low = + smu_lower_32_bits(mc_addr); + priv->smu_tables.entry[WMTABLE].table = kaddr; + priv->smu_tables.entry[WMTABLE].handle = handle; + + /* allocate space for watermarks table */ + smu_allocate_memory(smumgr->device, + sizeof(DpmClocks_t), + CGS_GPU_MEM_TYPE__GART_CACHEABLE, + PAGE_SIZE, + &mc_addr, + &kaddr, + &handle); + + PP_ASSERT_WITH_CODE(kaddr, + "[rv_smu_init] Out of memory for CLOCKTABLE.", + cgs_free_gpu_mem(smumgr->device, + (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); + kfree(smumgr->backend); + smumgr->backend = NULL; + return -EINVAL); + + priv->smu_tables.entry[CLOCKTABLE].version = 0x01; + priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t); + priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS; + priv->smu_tables.entry[CLOCKTABLE].table_addr_high = + smu_upper_32_bits(mc_addr); + priv->smu_tables.entry[CLOCKTABLE].table_addr_low = + smu_lower_32_bits(mc_addr); + priv->smu_tables.entry[CLOCKTABLE].table = kaddr; + priv->smu_tables.entry[CLOCKTABLE].handle = handle; + + return 0; +} + +const struct pp_smumgr_func rv_smu_funcs = { + .smu_init = &rv_smu_init, + .smu_fini = &rv_smu_fini, + .start_smu = &rv_start_smu, + .request_smu_load_specific_fw = NULL, + .send_msg_to_smc = &rv_send_msg_to_smc, + .send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, +}; + + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h new file mode 100644 index 000000000000..262c8ded87c0 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h @@ -0,0 +1,62 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef PP_RAVEN_SMUMANAGER_H +#define PP_RAVEN_SMUMANAGER_H + +#include "rv_ppsmc.h" +#include "smu10_driver_if.h" + +enum SMU_TABLE_ID { + WMTABLE = 0, + CLOCKTABLE, + MAX_SMU_TABLE, +}; + +struct smu_table_entry { + uint32_t version; + uint32_t size; + uint32_t table_id; + uint32_t table_addr_high; + uint32_t table_addr_low; + uint8_t *table; + uint32_t handle; +}; + +struct smu_table_array { + struct smu_table_entry entry[MAX_SMU_TABLE]; +}; + +struct rv_smumgr { + struct smu_table_array smu_tables; +}; + +int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); +bool rv_is_smc_ram_running(struct pp_smumgr *smumgr); +int rv_copy_table_from_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id); +int rv_copy_table_to_smc(struct pp_smumgr *smumgr, + uint8_t *table, int16_t table_id); + + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index c0d75766bbc8..bcc61ffd13cb 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -20,15 +20,16 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include <linux/types.h> + +#include <linux/delay.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> +#include <linux/types.h> #include <drm/amdgpu_drm.h> #include "pp_instance.h" #include "smumgr.h" #include "cgs_common.h" -#include "linux/delay.h" MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin"); @@ -95,6 +96,15 @@ int smum_early_init(struct pp_instance *handle) return -EINVAL; } break; + case AMDGPU_FAMILY_RV: + switch (smumgr->chip_id) { + case CHIP_RAVEN: + smumgr->smumgr_funcs = &rv_smu_funcs; + break; + default: + return -EINVAL; + } + break; default: kfree(smumgr); return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 115f0e4b1603..269678443862 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -500,7 +500,6 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) smu_lower_32_bits(mc_addr); priv->smu_tables.entry[TOOLSTABLE].table = kaddr; priv->smu_tables.entry[TOOLSTABLE].handle = handle; - vega10_set_tools_address(smumgr); } } @@ -569,6 +568,9 @@ static int vega10_start_smu(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr), "Failed to verify SMC interface!", return -EINVAL); + + vega10_set_tools_address(smumgr); + return 0; } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index fea96a765cf1..38cea6fb25a8 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -409,9 +409,18 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) &s_job->s_fence->cb)) { dma_fence_put(s_job->s_fence->parent); s_job->s_fence->parent = NULL; + atomic_dec(&sched->hw_rq_count); } } - atomic_set(&sched->hw_rq_count, 0); + spin_unlock(&sched->job_list_lock); +} + +void amd_sched_job_kickout(struct amd_sched_job *s_job) +{ + struct amd_gpu_scheduler *sched = s_job->sched; + + spin_lock(&sched->job_list_lock); + list_del_init(&s_job->node); spin_unlock(&sched->job_list_lock); } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 924d4a5899e1..f9d8f28efd16 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -81,6 +81,7 @@ struct amd_sched_job { struct list_head node; struct delayed_work work_tdr; uint64_t id; + atomic_t karma; }; extern const struct dma_fence_ops amd_sched_fence_ops_scheduled; @@ -96,6 +97,11 @@ static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f) return NULL; } +static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int threshold) +{ + return (s_job && atomic_inc_return(&s_job->karma) > threshold); +} + /** * Define the backend operations called by the scheduler, * these functions should be implemented in driver side @@ -160,4 +166,5 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched); void amd_sched_job_recovery(struct amd_gpu_scheduler *sched); bool amd_sched_dependency_optimized(struct dma_fence* fence, struct amd_sched_entity *entity); +void amd_sched_job_kickout(struct amd_sched_job *s_job); #endif |